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signals.txt
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{sim:/tb/clk {-format Logic -height 17}} {sim:/tb/reset {-format Logic -height 17}} {{Program Counter} {-format Default -height 17 -divider -label {Program Counter}}} {sim:/tb/r1/PC/PC_In {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/PC/PC_Out {-autoscale 1 -format Literal -height 17 -radix unsigned}} {{Instruction Parser} {-format Default -height 17 -divider -label {Instruction Parser}}} {sim:/tb/r1/IP/opcode {-autoscale 1 -format Literal -height 17}} {sim:/tb/r1/IP/rd {-autoscale 1 -format Literal -height 17}} {sim:/tb/r1/IP/funct3 {-autoscale 1 -format Literal -height 17}} {sim:/tb/r1/IP/rs1 {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/IP/rs2 {-autoscale 1 -format Literal -height 17 -radix unsigned}} {{Register File} {-format Default -height 17 -divider -label {Register File}}} {sim:/tb/r1/rg/WriteData {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/rg/RS1 {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/rg/RS2 {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/rg/RD {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/rg/RegWrite {-format Logic -height 17}} {sim:/tb/r1/rg/ReadData1 {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/rg/ReadData2 {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/rg/registers {-format Literal -height 17 -radix unsigned}} {{Immediate Data Gen} {-format Default -height 17 -divider -label {Immediate Data Gen}}} {sim:/tb/r1/IDG/instruction {-autoscale 1 -format Literal -height 17}} {sim:/tb/r1/IDG/imm_data {-autoscale 1 -format Literal -height 17 -radix unsigned}} {{Mux 2} {-format Default -height 17 -divider -label {Mux 2}}} {sim:/tb/r1/mux2/a {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/mux2/b {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/mux2/sel {-format Logic -height 17}} {sim:/tb/r1/mux2/F {-autoscale 1 -format Literal -height 17 -radix unsigned}} {ALU {-format Default -height 17 -divider -label ALU}} {sim:/tb/r1/ALU/a {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/ALU/b {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/ALU/ALUOp {-autoscale 1 -format Literal -height 17}} {sim:/tb/r1/ALU/Result {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/ALU/Zero {-format Logic -height 17}} {{Data Memory} {-format Default -height 17 -divider -label {Data Memory}}} {sim:/tb/r1/DM/Mem_Addr {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/DM/Write_Data {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/DM/MemWrite {-format Logic -height 17}} {sim:/tb/r1/DM/MemRead {-format Logic -height 17}} {sim:/tb/r1/DM/Read_Data {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/DM/Data_Memory {-format Literal -height 17 -radix unsigned}} {sim:/tb/r1/IP/funct7 {-autoscale 1 -format Literal -height 17}} {{Control Unit} {-format Default -height 17 -divider -label {Control Unit}}} {sim:/tb/r1/CU/Opcode {-autoscale 1 -format Literal -height 17}} {sim:/tb/r1/CU/Branch {-format Logic -height 17}} {sim:/tb/r1/CU/MemRead {-format Logic -height 17}} {sim:/tb/r1/CU/MemtoReg {-format Logic -height 17}} {sim:/tb/r1/CU/MemWrite {-format Logic -height 17}} {sim:/tb/r1/CU/ALUSrc {-format Logic -height 17}} {sim:/tb/r1/CU/RegWrite {-format Logic -height 17}} {sim:/tb/r1/CU/ALUOp {-autoscale 1 -format Literal -height 17}} {{Mux 1} {-format Default -height 17 -divider -label {Mux 1}}} {sim:/tb/r1/mux1/a {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/mux1/b {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/mux1/sel {-format Logic -height 17}} {sim:/tb/r1/mux1/F {-autoscale 1 -format Literal -height 17 -radix unsigned}} {{Adder 2} {-format Default -height 17 -divider -label {Adder 2}}} {sim:/tb/r1/adder2/a {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/adder2/b {-autoscale 1 -format Literal -height 17 -radix unsigned}} {sim:/tb/r1/adder2/out {-autoscale 1 -format Literal -height 17 -radix unsigned}}