From 2d6308ec2c2245d46bbaaacb0a58ed3814eb755d Mon Sep 17 00:00:00 2001 From: Brett Nicholas <7547222+bigbrett@users.noreply.github.com> Date: Fri, 5 Jul 2024 14:54:22 -0600 Subject: [PATCH] - Infineon TC3xx support - fix (existing) unused variable compiler warnings - documentation updates - add multi-sector erase option --- .github/workflows/test-configs.yml | 2 +- .../workflows/test-powerfail-simulator.yml | 48 + .gitignore | 9 + IDE/AURIX/Configurations/placeholder.txt | 1 + IDE/AURIX/README.md | 188 ++ IDE/AURIX/SDK/placeholder.txt | 1 + IDE/AURIX/test-app/.cproject | 611 ++++++ IDE/AURIX/test-app/.project | 62 + .../test-app/.settings/language.settings.xml | 41 + IDE/AURIX/test-app/Cpu0_Main.c | 83 + IDE/AURIX/test-app/Cpu1_Main.c | 42 + IDE/AURIX/test-app/Cpu2_Main.c | 42 + IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl | 1772 ++++++++++++++++ IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl | 918 +++++++++ IDE/AURIX/wolfBoot-tc3xx/.cproject | 778 +++++++ IDE/AURIX/wolfBoot-tc3xx/.project | 90 + .../.settings/language.settings.xml | 41 + IDE/AURIX/wolfBoot-tc3xx/Cpu0_Main.c | 47 + IDE/AURIX/wolfBoot-tc3xx/Cpu1_Main.c | 42 + IDE/AURIX/wolfBoot-tc3xx/Cpu2_Main.c | 42 + .../wolfBoot-tc3xx/Lcf_Gnuc_Tricore_Tc.lsl | 1781 +++++++++++++++++ .../wolfBoot-tc3xx/Lcf_Tasking_Tricore_Tc.lsl | 918 +++++++++ docs/HAL.md | 32 +- docs/compile.md | 17 + docs/firmware_image.md | 17 +- hal/aurix_tc3xx.c | 511 +++++ options.mk | 4 + src/image.c | 1 - src/libwolfboot.c | 2 + src/update_flash.c | 38 +- tools/config.mk | 1 + tools/scripts/tc3xx/gen-tc3xx-keys.sh | 5 + .../tc3xx/gen-tc3xx-signed-test-apps-debug.sh | 6 + .../gen-tc3xx-signed-test-apps-release.sh | 6 + tools/scripts/tc3xx/gen-tc3xx-target.sh | 29 + .../scripts/tc3xx/wolfBoot-loadAll-debug.cmm | 31 + .../tc3xx/wolfBoot-loadAll-release.cmm | 31 + 37 files changed, 8266 insertions(+), 24 deletions(-) create mode 100644 IDE/AURIX/Configurations/placeholder.txt create mode 100644 IDE/AURIX/README.md create mode 100644 IDE/AURIX/SDK/placeholder.txt create mode 100644 IDE/AURIX/test-app/.cproject create mode 100644 IDE/AURIX/test-app/.project create mode 100644 IDE/AURIX/test-app/.settings/language.settings.xml create mode 100644 IDE/AURIX/test-app/Cpu0_Main.c create mode 100644 IDE/AURIX/test-app/Cpu1_Main.c create mode 100644 IDE/AURIX/test-app/Cpu2_Main.c create mode 100644 IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl create mode 100644 IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl create mode 100644 IDE/AURIX/wolfBoot-tc3xx/.cproject create mode 100644 IDE/AURIX/wolfBoot-tc3xx/.project create mode 100644 IDE/AURIX/wolfBoot-tc3xx/.settings/language.settings.xml create mode 100644 IDE/AURIX/wolfBoot-tc3xx/Cpu0_Main.c create mode 100644 IDE/AURIX/wolfBoot-tc3xx/Cpu1_Main.c create mode 100644 IDE/AURIX/wolfBoot-tc3xx/Cpu2_Main.c create mode 100644 IDE/AURIX/wolfBoot-tc3xx/Lcf_Gnuc_Tricore_Tc.lsl create mode 100644 IDE/AURIX/wolfBoot-tc3xx/Lcf_Tasking_Tricore_Tc.lsl create mode 100644 hal/aurix_tc3xx.c create mode 100644 tools/scripts/tc3xx/gen-tc3xx-keys.sh create mode 100644 tools/scripts/tc3xx/gen-tc3xx-signed-test-apps-debug.sh create mode 100644 tools/scripts/tc3xx/gen-tc3xx-signed-test-apps-release.sh create mode 100644 tools/scripts/tc3xx/gen-tc3xx-target.sh create mode 100644 tools/scripts/tc3xx/wolfBoot-loadAll-debug.cmm create mode 100644 tools/scripts/tc3xx/wolfBoot-loadAll-release.cmm diff --git a/.github/workflows/test-configs.yml b/.github/workflows/test-configs.yml index eee92bd74..1df9275be 100644 --- a/.github/workflows/test-configs.yml +++ b/.github/workflows/test-configs.yml @@ -175,7 +175,7 @@ jobs: config-file: ./config/examples/sim.config make-args: SPMATHALL=1 WOLFBOOT_SMALL_STACK=1 - sim_spmathall_bigsack_test: + sim_spmathall_bigstack_test: uses: ./.github/workflows/test-build.yml with: arch: host diff --git a/.github/workflows/test-powerfail-simulator.yml b/.github/workflows/test-powerfail-simulator.yml index b6e927a9b..7d2f11e05 100644 --- a/.github/workflows/test-powerfail-simulator.yml +++ b/.github/workflows/test-powerfail-simulator.yml @@ -571,3 +571,51 @@ jobs: - name: Run update test with DISABLE_BACKUP and powefail run: | tools/scripts/sim-update-powerfail-resume-nobackup.sh + + + # TEST with FLASH_MULTI_SECTOR_ERASE + - name: make clean + run: | + make distclean + + - name: Select config + run: | + cp config/examples/sim.config .config + + - name: Build tools + run: | + make -C tools/keytools && make -C tools/bin-assemble + + - name: Build wolfboot.elf (FLASH_MULTI_SECTOR_ERASE=1) + run: | + make clean && make test-sim-internal-flash-with-update FLASH_MULTI_SECTOR_ERASE=1 + + - name: Run sunny day update test (FLASH_MULTI_SECTOR_ERASE=1) + run: | + tools/scripts/sim-sunnyday-update.sh + + - name: Rebuild wolfboot.elf (FLASH_MULTI_SECTOR_ERASE=1) + run: | + make clean && make test-sim-internal-flash-with-update FLASH_MULTI_SECTOR_ERASE=1 + + - name: Run update-revert test (FLASH_MULTI_SECTOR_ERASE=1) + run: | + tools/scripts/sim-update-fallback.sh + + - name: Rebuild wolfboot.elf (FLASH_MULTI_SECTOR_ERASE=1) + run: | + make clean && make test-sim-internal-flash-with-update FLASH_MULTI_SECTOR_ERASE=1 + + - name: Run update-revert test with power failures (FLASH_MULTI_SECTOR_ERASE=1) + run: | + tools/scripts/sim-update-powerfail-resume.sh + + - name: Rebuild wolfboot.elf (FLASH_MULTI_SECTOR_ERASE=1) + run: | + make clean && make test-sim-internal-flash-with-update FLASH_MULTI_SECTOR_ERASE=1 + + - name: Run emergency fallback test (FLASH_MULTI_SECTOR_ERASE=1) + run: | + tools/scripts/sim-update-emergency-fallback.sh + + diff --git a/.gitignore b/.gitignore index cb828f3f5..e18b8a452 100644 --- a/.gitignore +++ b/.gitignore @@ -200,6 +200,15 @@ IDE/Renesas/e2studio/RZN2L/wolfboot/.cache/* IDE/Renesas/e2studio/RZN2L/flash_app/.cache/* IDE/Release/e2studio/RZN2L/app_RZ/.cache/* +# IDE AURIX generated +IDE/AURIX/*/TriCore* (GCC)/* +IDE/AURIX/*/TriCore* (TASKING)/* +IDE/AURIX/*/.settings/* +IDE/AURIX/*/.ads/* +IDE/AURIX/SDK/* +!IDE/AURIX/SDK/placeholder.txt +IDE/AURIX/Configurations/* +!IDE/AURIX/Configurations/placeholder.txt tpm_seal_key.key diff --git a/IDE/AURIX/Configurations/placeholder.txt b/IDE/AURIX/Configurations/placeholder.txt new file mode 100644 index 000000000..8d8b1372f --- /dev/null +++ b/IDE/AURIX/Configurations/placeholder.txt @@ -0,0 +1 @@ +Extract AURIX template configuration here diff --git a/IDE/AURIX/README.md b/IDE/AURIX/README.md new file mode 100644 index 000000000..881c62df5 --- /dev/null +++ b/IDE/AURIX/README.md @@ -0,0 +1,188 @@ +# Overview + +This example demonstrates using wolfBoot on the Infineon AURIX TC3xx family of microcontrollers. The example is based on the TC375 Lite-Kit V2, but should be easily adaptable to other TC3xx devices. This README assumes basic familiarity with the TC375 SoC, the AURIX IDE, and Lauterbach Trace32 debugger. + +The example contains two projects: `wolfBoot-tc3xx` and `test-app`. The `wolfBoot-tc3xx` project contains the wolfBoot bootloader, and the `test-app` project contains a simple firmware application that will be loaded and executed by wolfBoot. The `test-app` project is a simple blinky application that blinks LED2 on the TC375 Lite-Kit V2 once per second when running the base image, and rapidly (~3x/sec) when running the update image. The test app determines if it is a base or update image by inspecting the firmware version (obtained through the wolfBoot API). The firmware version is set in the image header by the wolfBoot keytools when signing the test app binaries. The same test app binary is used for both the base and update images, with the only difference being the firmware version set by the keytools. + +## Important notes + +- In the TC375 UCBs, BMDHx.STAD must point to the wolfBoot entrypoint `0xA000_0000`. This is the default value of the TC375 and so need not be changed unless it has already been modified or you wish to rearrange the memory map. +- Because TC3xx PFLASH ECC prevents reading from erased flash, the `EXT_FLASH` option is used to redirect flash reads to the `ext_flash_read()` HAL API, where the flash pages requested to be read can be blank-checked by hardware before reading. +- TC3xx PFLASH is write-once (`NVM_FLASH_WRITEONCE`), however wolfBoot `NVM_FLASH_WRITEONCE` does not support `EXT_FLASH`. Therefore the write-once functionality is re-implemented in the `HAL` layer. +- This demo app is only compatible with the GCC toolchain build configurations shipped with the AURIX IDE. The TASKING compiler build configurations are not yet supported. + +## Flash Partitioning + +The TC3xx AURIX port of wolfBoot places all images in PFLASH, and uses both PFLASH0 and PFLASH1 banks. The wolfBoot executable code and the image swap sector are located in PFLASH0, with the remainder available for use. PFLASH1 is divided in half, with the first half holding the BOOT partition and the second half holding the UPDATE partition. User firmware images are directly executed in place from the BOOT partition in PFLASH1, and so must be linked to execute within this address space, with an offset of `IMAGE_HEADER_SIZE` to account for the wolfBoot image header. + +``` ++==========+ +| PFLASH0 | ++==========+ <-- 0x8000_0000 +| wolfBoot | 128K ++----------+ <-- 0x8002_0000 +| SWAP | 16K ++----------+ <-- 0x8002_4000 +| Unused | ~2.86M ++----------+ <-- 0x8030_0000 + ++==========+ +| PFLASH1 | ++==========+ <-- 0x8030_0000 +| BOOT | 1.5M ++----------+ <-- 0x8048_0000 +| UPDATE | 1.5M ++----------+ <-- 0x8060_0000 +``` + +Please refer to the [wolfBoot](wolfBoot-tc3xx/Lcf_Gnu_Tricore_Tc.lsl) and [test-app](test-app/Lcf_Gnu_Tricore_Tc.lsl) linker scripts for the exact memory configuration. + + +## Building and running the wolfBoot demo + +### Prerequisites + +- A Windows 10 computer with the Infineon AURIX IDE installed +- A WSL2 distro (tested on Ubuntu 22.04) with the `build-essential` package installed (`sudo apt install build-essential`) +- A TC375 AURIX Lite-Kit V2 + +### Clone wolfBoot + +1. Clone the wolfBoot repository and initialize the repository submodules (`git submodule update --init`) + +### Build wolfBoot keytools and generate keys + +1. Open a WSL2 terminal and navigate to the top level `wolfBoot` directory +2. Compile the keytools by running `make keytools` +3. Use the helper script to generate a new signing key pair using RSA 4096 + 1. Navigate to `wolfBoot/tools/scripts/tc3xx` + 2. Run `./gen-tc3xx-keys.sh`. This generates the signing private key `wolfBoot/priv.der` and adds the public key to the wolfBoot keystore (see [keygen](https://github.com/wolfSSL/wolfBoot/blob/aurix-tc3xx-support/docs/Signing.md) for more information). If you already have generated a key, you will be prompted to overwrite it. + +``` +$ ./gen-tc3xx-keys.sh ++ cd ../../../ ++ ./tools/keytools/keygen -g priv.der --rsa4096 +Keytype: RSA4096 +Generating key (type: RSA4096) +RSA public key len: 550 bytes +Associated key file: priv.der +Partition ids mask: ffffffff +Key type : RSA4096 +Public key slot: 0 +Done. +``` + +### Install the Infineon TC3xx SDK into the wolfBoot project + +Because of repository size constraints and differing licenses, the required Infineon low level drivers ("iLLD") and auto-generated SDK configuration code that are usually included in AURIX projects are not included in this demo app. It is therefore required to locate them in your AURIX install and extract them to the location that the wolfBoot AURIX projects expect them to be at. The remainder of these instructions will use variables to reference the following three paths: + +- `$AURIX_INSTALL`: The AURIX IDE installation location. This is usually `C:\Infineon\AURIX-Studio-`. +- `$SDK_ARCHIVE`: The zip archive of the iLLD SDK. This is usually at `$AURIX_INSTALL\build_system\bundled-artefacts-repo\project-initializer\tricore-tc3xx\\iLLDs\Full_Set\iLLD___TC37A.zip` +- `$SDK_CONFIG`: The directory containing the iLLD SDK configuration for the specific chip. This is usually at `$AURIX_INSTALL\build_system\bundled-artefacts-repo\project-initializer\tricore-tc3xx\\ProjectTemplates\TC37A\TriCore\Configurations` + +Perform the following two steps to add the iLLD SDK drivers to the wolfBoot project: + +1. Extract the iLLD package for the TC375TP from `$SDK_ARCHIVE` into the `wolfBoot/IDE/AURIX/SDK` directory. The contents of the `wolfBoot/IDE/AURIX/SDK` directory should now be: + +``` +wolfBoot/IDE/AURIX/SDK +├── Infra/ +├── Service/ +├── iLLD/ +└── placeholder.txt +``` + +2. Copy the SDK configuration sources from `$SDK_CONFIG` into the `wolfBoot/IDE/AURIX/Configurations` directory. The contents of the `wolfBoot/IDE/AURIX/Configurations` directory should now be: + +``` +wolfBoot/IDE/AURIX/Configurations/ +├── Debug +├── Ifx_Cfg.h +├── Ifx_Cfg_Ssw.c +├── Ifx_Cfg_Ssw.h +├── Ifx_Cfg_SswBmhd.c +└── placeholder.txt +``` + +### Build wolfBoot +1. Generate the 'target.h` header file for the tc375 flash configuration + 1. Open a WSL terminal and navigate to `wolfBoot/tools/scripts/tc3xx` + 2. Run `./gen-tc3xx-target.sh` +2. Open the AURIX IDE and create a new workspace directory, if you do not already have a workspace you wish to use +3. Import the wolfBoot project + 1. Click "File" -> Open Projects From File System" + 2. Click "Directory" to select an import source, and choose the wolfBoot/IDE/AURIX/wolfBoot-tc3xx directory in the system file explorer + 3. Click "Finish" to import the project +4. Build the wolfBoot Project + 1. Right-click the wolfBoot-tc3xx project and choose "Set active project" + 2. Right-click the wolfBoot-tc3xx project, and from the "Build Configurations" -> "Set Active" menu, select either the "TriCore Debug (GCC)" or "TriCore Release (GCC)" build configuration + 3. Click the hammer icon to build the active project. This will compile wolfBoot. +5. Import the test-app project using the same procedure as in step (3), except using `wolfBoot/IDE/AURIX/test-app` as the directory +6. Build the test-app project using the same procedure as in step (4), except choosing the `test-app` eclipse project. Note that the build process contains a custom post-build step that converts the application `elf` file into a `.bin` file using `tricore-elf-objcopy`, which can then be signed by the wolfBoot key tools in the following step +7. Sign the generated test-app binary using the wolfBoot keytools + 1. Open a WSL terminal and navigate to `wolfBoot/tools/scripts/tc3xx` + 2. Run `./gen-tc3xx-signed-test-apps-debug.sh` or `gen-tc3xx-signed-test-apps-release.sh` to sign either the debug or release build, respectively. This creates the signed image files `test-app_v1_signed.bin` and `test-app_v2_signed.bin` in the test-app output build directory. The v1 image is the initial image that will be loaded to the `BOOT` partition, and the v2 image is the update image that will be loaded to the `UPDATE` partition. + +``` +$ ./gen-tc3xx-signed-test-apps-release.sh ++ ../../keytools/sign --rsa4096 --sha256 '../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin' ../../../priv.der 1 +wolfBoot KeyTools (Compiled C version) +wolfBoot version 2010000 +Update type: Firmware +Input image: ../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin +Selected cipher: RSA4096 +Selected hash : SHA256 +Public key: ../../../priv.der +Output image: ../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app_v1_signed.bin +Target partition id : 1 +Found RSA512 key +image header size calculated at runtime (1024 bytes) +Calculating SHA256 digest... +Signing the digest... +Output image(s) successfully created. ++ ../../keytools/sign --rsa4096 --sha256 '../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin' ../../../priv.der 2 +wolfBoot KeyTools (Compiled C version) +wolfBoot version 2010000 +Update type: Firmware +Input image: ../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin +Selected cipher: RSA4096 +Selected hash : SHA256 +Public key: ../../../priv.der +Output image: ../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app_v2_signed.bin +Target partition id : 1 +Found RSA512 key +image header size calculated at runtime (1024 bytes) +Calculating SHA256 digest... +Signing the digest... +Output image(s) successfully created. +``` + +### Load and run the wolfBoot demo + +1. Load wolfBoot and the firmware application images to the tc3xx device using Trace32 and a Lauterbach probe + 1. Ensure the Lauterbach probe is connected to the debug port of the tc375 LiteKit + 2. Open Trace32 Power View for Tricore + 3. Open the SYStem menu and click "DETECT" to detect the tc375 device. Click "CONTINUE" in the pop-up window, and then choose "Set TC375xx" when the device is detected + 4. Click "File" -> "ChangeDir and Run Script" and choose the `wolfBoot/tools/scripts/tc3xx/wolfBoot-loadAll-$BUILD.cmm` script, where $BUILD should be either "debug" or "release" depending on your build type in (4) and (6). + +wolfBoot and the demo applications are now loaded into flash, and core0 will be halted at the wolfBoot entry point (`core0_main()`). + +2. Run the application by clicking "Go" to release the core. This will run wolfBoot which will eventually boot into the application in the `BOOT` partition. You should see LED2 on the board blink once per second. + +3. Reset the application to trigger the firmware update. Click "System Down", "System Up", then "Go" to reset the tc3xx. If the device halts again at `core0_main`, click "Go" one more time to release the core. You should see LED2 turn on for ~5sec while wolfBoot swaps the images between `UPDATE` and `BOOT` partitions, then you should see LED2 blink rapidly (~3x/sec) indicating that the firmware update was successful and the new image has booted. Subsequent resets should continue to boot into to the new image. + +To rerun the demo, simply rerun the loader script in Trace32 and repeat the above steps + + +## Troubleshooting + +### WSL "bad interpreter" error + +When running a shell script in WSL, you may see the following error: + +``` +$ ./gen-tc3xx-target.sh: +/bin/bash^M: bad interpreter: No such file or directory +``` + +This occurs because your local git repository is configured with the default `core.autocrlf true` configuration, meaning that git is checking out files with Windows-style CRLF line endings which the bash interpreter cannot handle. To fix this, you need to either configure git to not checkout windows line endings for shell scripts ([GitHub docs](https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings#about-line-endings)), or you can run the `dos2unix` (`sudo apt install dos2unix`) utility on the script before running it. diff --git a/IDE/AURIX/SDK/placeholder.txt b/IDE/AURIX/SDK/placeholder.txt new file mode 100644 index 000000000..2f2a0124a --- /dev/null +++ b/IDE/AURIX/SDK/placeholder.txt @@ -0,0 +1 @@ +Extract SDK here diff --git a/IDE/AURIX/test-app/.cproject b/IDE/AURIX/test-app/.cproject new file mode 100644 index 000000000..a07fde14f --- /dev/null +++ b/IDE/AURIX/test-app/.cproject @@ -0,0 +1,611 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/IDE/AURIX/test-app/.project b/IDE/AURIX/test-app/.project new file mode 100644 index 000000000..075e71273 --- /dev/null +++ b/IDE/AURIX/test-app/.project @@ -0,0 +1,62 @@ + + + test-app + + + wolfBoot-tc3xx + + + + com.infineon.aurix.buildsystem.builders.booster + full,incremental, + + + + + com.infineon.aurix.buildsystem.builders.autodiscovery + full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.infineon.aurix.buildsystem.aurixnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Configurations + 2 + SDK_CONFIGURATION_DIR + + + Libraries + 2 + SDK_DIR + + + + + SDK_CONFIGURATION_DIR + $%7BPARENT-1-PROJECT_LOC%7D/Configurations + + + SDK_DIR + $%7BPARENT-1-PROJECT_LOC%7D/SDK + + + diff --git a/IDE/AURIX/test-app/.settings/language.settings.xml b/IDE/AURIX/test-app/.settings/language.settings.xml new file mode 100644 index 000000000..8a8ec65a1 --- /dev/null +++ b/IDE/AURIX/test-app/.settings/language.settings.xml @@ -0,0 +1,41 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/IDE/AURIX/test-app/Cpu0_Main.c b/IDE/AURIX/test-app/Cpu0_Main.c new file mode 100644 index 000000000..c96c0bc3f --- /dev/null +++ b/IDE/AURIX/test-app/Cpu0_Main.c @@ -0,0 +1,83 @@ +/* Cpu0_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "Bsp.h" +#include "IfxCpu.h" +#include "IfxPort.h" +#include "IfxScuWdt.h" +#include "Ifx_Types.h" +#include "wolfboot/wolfboot.h" + +IFX_ALIGN(4) IfxCpu_syncEvent g_cpuSyncEvent = 0; + + +#define LED &MODULE_P00, 6 /* LED: Port, Pin definition */ +#define BLINK_TIME_BASE 500 /* Wait time constant in milliseconds */ +#define BLINK_TIME_UPDATE 100 /* Wait time constant in milliseconds */ + +#define BASE_FW_VERSION 1 + +/* This function initializes the port pin which drives the LED */ +static void initLED(void) +{ + /* Initialization of the LED used in this example */ + IfxPort_setPinModeOutput(LED, + IfxPort_OutputMode_pushPull, + IfxPort_OutputIdx_general); + + /* Switch OFF the LED (low-level active) */ + IfxPort_setPinLow(LED); +} + +void core0_main(void) +{ + size_t blinkTime; + + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!! + * Enable the watchdogs and service them periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + initLED(); + + if (wolfBoot_current_firmware_version() <= BASE_FW_VERSION) { + /* We are booting into the base firmware, so stage the update and set + * the LED to blink slow */ + wolfBoot_update_trigger(); + blinkTime = BLINK_TIME_BASE; + } + else { + /* we are booting into the updated firmware so acknowledge the update + * (to prevent rollback) and set the LED to blink fast */ + wolfBoot_success(); + blinkTime = BLINK_TIME_UPDATE; + } + + while (1) { + IfxPort_togglePin(LED); + waitTime(IfxStm_getTicksFromMilliseconds(BSP_DEFAULT_TIMER, blinkTime)); + } +} diff --git a/IDE/AURIX/test-app/Cpu1_Main.c b/IDE/AURIX/test-app/Cpu1_Main.c new file mode 100644 index 000000000..4a353f526 --- /dev/null +++ b/IDE/AURIX/test-app/Cpu1_Main.c @@ -0,0 +1,42 @@ +/* Cpu1_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "Ifx_Types.h" +#include "IfxCpu.h" +#include "IfxScuWdt.h" + +extern IfxCpu_syncEvent g_cpuSyncEvent; + +void core1_main(void) +{ + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG1 IS DISABLED HERE!! + * Enable the watchdog and service it periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + while(1) + { + } +} diff --git a/IDE/AURIX/test-app/Cpu2_Main.c b/IDE/AURIX/test-app/Cpu2_Main.c new file mode 100644 index 000000000..09d82c438 --- /dev/null +++ b/IDE/AURIX/test-app/Cpu2_Main.c @@ -0,0 +1,42 @@ +/* Cpu2_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "Ifx_Types.h" +#include "IfxCpu.h" +#include "IfxScuWdt.h" + +extern IfxCpu_syncEvent g_cpuSyncEvent; + +void core2_main(void) +{ + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG2 IS DISABLED HERE!! + * Enable the watchdog and service it periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + while(1) + { + } +} diff --git a/IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl b/IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl new file mode 100644 index 000000000..caa67fad3 --- /dev/null +++ b/IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl @@ -0,0 +1,1772 @@ +/* Lcf_Gnuc_Tricore_Tc.lsl + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH(tricore) +ENTRY(_START) + +__TRICORE_DERIVATE_MEMORY_MAP__ = 0x380; + +LCF_CSA0_SIZE = 8k; +LCF_USTACK0_SIZE = 2k; +LCF_ISTACK0_SIZE = 1k; + +LCF_CSA1_SIZE = 8k; +LCF_USTACK1_SIZE = 2k; +LCF_ISTACK1_SIZE = 1k; + +LCF_CSA2_SIZE = 8k; +LCF_USTACK2_SIZE = 2k; +LCF_ISTACK2_SIZE = 1k; + +LCF_HEAP_SIZE = 4k; + +LCF_DSPR2_START = 0x50000000; +LCF_DSPR2_SIZE = 96k; + +LCF_DSPR1_START = 0x60000000; +LCF_DSPR1_SIZE = 240k; + +LCF_DSPR0_START = 0x70000000; +LCF_DSPR0_SIZE = 240k; + +LCF_CSA2_OFFSET = (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE); +LCF_ISTACK2_OFFSET = (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE); +LCF_USTACK2_OFFSET = (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE); + +LCF_CSA1_OFFSET = (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE); +LCF_ISTACK1_OFFSET = (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE); +LCF_USTACK1_OFFSET = (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE); + +LCF_CSA0_OFFSET = (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE); +LCF_ISTACK0_OFFSET = (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE); +LCF_USTACK0_OFFSET = (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE); + +LCF_HEAP0_OFFSET = (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE); +LCF_HEAP1_OFFSET = (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE); +LCF_HEAP2_OFFSET = (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE); + + +LCF_STARTPTR_CPU0 = 0x80300400; +LCF_STARTPTR_CPU1 = 0x80300420; +LCF_STARTPTR_CPU2 = 0x80300440; + +LCF_STARTPTR_NC_CPU0 = 0xA0300400; +LCF_STARTPTR_NC_CPU1 = 0xA0300420; +LCF_STARTPTR_NC_CPU2 = 0xA0300440; + +/* TODO LCF_TRAPVEC_SIZE */ +LCF_TRAPVEC0_START = 0x80300500; +LCF_TRAPVEC1_START = 0x80300600; +LCF_TRAPVEC2_START = 0x80300700; + +LCF_INTVEC0_START = 0x80300800; +LCF_INTVEC1_START = 0x80302800; +LCF_INTVEC2_START = 0x80304800; + +__INTTAB_CPU0 = LCF_INTVEC0_START; +__INTTAB_CPU1 = LCF_INTVEC1_START; +__INTTAB_CPU2 = LCF_INTVEC2_START; + + + +RESET = LCF_STARTPTR_NC_CPU0; + +MEMORY +{ + dsram2_local (w!xp): org = 0xd0000000, len = 96K + dsram2 (w!xp): org = 0x50000000, len = 96K + psram2 (w!xp): org = 0x50100000, len = 64K + + dsram1_local (w!xp): org = 0xd0000000, len = 240K + dsram1 (w!xp): org = 0x60000000, len = 240K + psram1 (w!xp): org = 0x60100000, len = 64K + + dsram0_local (w!xp): org = 0xd0000000, len = 240K + dsram0 (w!xp): org = 0x70000000, len = 240K + psram0 (w!xp): org = 0x70100000, len = 64K + + psram_local (w!xp): org = 0xc0000000, len = 64K + + /* Majority of pfls0 is reserved for wolfBoot, swap and HSM */ + pfls0 (rx!p): org = 0x80000000, len = 3M + + /* placeholder for wolfBoot image header */ + pfls1_hdr (rx!p): org = 0x80300000, len = 1024 + + /* pfls1 is the remainder of the wolfBoot BOOT partition. Everything goes here */ + pfls1 (rx!p): org = 0x80300400, len = 0x17FC00 /* 1.5MiB - 1024B*/ + + /* reserved for wolfBoot UPDATE partition */ + pfls1_update (rx!p): org = 0x80480000, len = 0x180000 /* 1.5MiB */ + + dfls0 (rx!p): org = 0xaf000000, len = 256K + + ucb (rx!p): org = 0xaf400000, len = 24K + + cpu0_dlmu (w!xp): org = 0x90000000, len = 64K + + cpu1_dlmu (w!xp): org = 0x90010000, len = 64K + + cpu2_dlmu (w!xp): org = 0x90020000, len = 64K +} + +/* map local memory address to a global address */ +REGION_MAP( CPU0 , ORIGIN(dsram0_local), LENGTH(dsram0_local), ORIGIN(dsram0)) +REGION_MAP( CPU1 , ORIGIN(dsram1_local), LENGTH(dsram1_local), ORIGIN(dsram1)) +REGION_MAP( CPU2 , ORIGIN(dsram2_local), LENGTH(dsram2_local), ORIGIN(dsram2)) + + +/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ +/* +REGION_ALIAS( default_ram , dsram0) +REGION_ALIAS( default_rom , pfls1) +*/ + +/* +REGION_ALIAS( default_ram , dsram1) +REGION_ALIAS( default_rom , pfls1) +*/ +/* +REGION_ALIAS( default_ram , dsram2) +*/ + +REGION_ALIAS( default_ram , dsram0) +REGION_ALIAS( default_rom , pfls1) + +/*Sections located at absolute fixed address*/ + /*Fixed memory Allocations for stack memory and CSA*/ + CORE_ID = CPU2; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR2_START + LCF_USTACK2_OFFSET): + { PROVIDE(__USTACK2_END = .); . = . + LCF_USTACK2_SIZE; PROVIDE(__USTACK2 = .); } + + CORE_SEC(.istack) (LCF_DSPR2_START + LCF_ISTACK2_OFFSET): + { PROVIDE(__ISTACK2_END = .); . = . + LCF_ISTACK2_SIZE; PROVIDE(__ISTACK2 = .); } + + CORE_SEC(.csa) (LCF_DSPR2_START + LCF_CSA2_OFFSET): + { PROVIDE(__CSA2 = .); . = . + LCF_CSA2_SIZE; PROVIDE(__CSA2_END = .); } + } + + CORE_ID = CPU1; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR1_START + LCF_USTACK1_OFFSET): + { PROVIDE(__USTACK1_END = .); . = . + LCF_USTACK1_SIZE; PROVIDE(__USTACK1 = .); } + + CORE_SEC(.istack) (LCF_DSPR1_START + LCF_ISTACK1_OFFSET): + { PROVIDE(__ISTACK1_END = .); . = . + LCF_ISTACK1_SIZE; PROVIDE(__ISTACK1 = .); } + + CORE_SEC(.csa) (LCF_DSPR1_START + LCF_CSA1_OFFSET): + { PROVIDE(__CSA1 = .); . = . + LCF_CSA1_SIZE; PROVIDE(__CSA1_END = .); } + } + + CORE_ID = CPU0; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR0_START + LCF_USTACK0_OFFSET): + { PROVIDE(__USTACK0_END = .); . = . + LCF_USTACK0_SIZE; PROVIDE(__USTACK0 = .); } + + CORE_SEC(.istack) (LCF_DSPR0_START + LCF_ISTACK0_OFFSET): + { PROVIDE(__ISTACK0_END = .); . = . + LCF_ISTACK0_SIZE; PROVIDE(__ISTACK0 = .); } + + CORE_SEC(.csa) (LCF_DSPR0_START + LCF_CSA0_OFFSET): + { PROVIDE(__CSA0 = .); . = . + LCF_CSA0_SIZE; PROVIDE(__CSA0_END = .); } + } + + /*Fixed memory Allocations for _START*/ + CORE_ID = GLOBAL ; + SECTIONS + { + .start_tc0 (LCF_STARTPTR_CPU0) : FLAGS(rxl) { KEEP (*(.start)); } > pfls1 + PROVIDE(__START0 = LCF_STARTPTR_NC_CPU0); + .start_tc1 (LCF_STARTPTR_CPU1) : FLAGS(rxl) { KEEP (*(.start_cpu1)); } > pfls1 + PROVIDE(__START1 = LCF_STARTPTR_NC_CPU1); + .start_tc2 (LCF_STARTPTR_CPU2) : FLAGS(rxl) { KEEP (*(.start_cpu2)); } > pfls1 + PROVIDE(__START2 = LCF_STARTPTR_NC_CPU2); + + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); /* Not used */ + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 0); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 0); + } + + /*Fixed memory Allocations for Trap Vector Table*/ + CORE_ID = GLOBAL; + SECTIONS + { + .traptab_tc0 (LCF_TRAPVEC0_START) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU0 = .); + KEEP (*(.traptab_cpu0)); + PROVIDE(__TRAPTAB_CPU0_END = .); + } > pfls1 + + .traptab_tc1 (__TRAPTAB_CPU0_END) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU1 = .); + KEEP (*(.traptab_cpu1)); + PROVIDE(__TRAPTAB_CPU1_END = .); + } > pfls1 + + .traptab_tc2 (__TRAPTAB_CPU1_END) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU2 = .); + KEEP (*(.traptab_cpu2)); + PROVIDE(__TRAPTAB_CPU2_END = .); + } > pfls1 + } + + /*Fixed memory Allocations for Interrupt Vector Table*/ + SECTIONS + { + /*CPU0 Interrupt Vector Table*/ + .inttab_tc0_000 (__INTTAB_CPU0 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_0 )); } + .inttab_tc0_001 (__INTTAB_CPU0 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_1 )); } + .inttab_tc0_002 (__INTTAB_CPU0 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_2 )); } + .inttab_tc0_003 (__INTTAB_CPU0 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_3 )); } + .inttab_tc0_004 (__INTTAB_CPU0 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_4 )); } + .inttab_tc0_005 (__INTTAB_CPU0 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_5 )); } + .inttab_tc0_006 (__INTTAB_CPU0 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_6 )); } + .inttab_tc0_007 (__INTTAB_CPU0 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_7 )); } + .inttab_tc0_008 (__INTTAB_CPU0 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_8 )); } + .inttab_tc0_009 (__INTTAB_CPU0 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_9 )); } + .inttab_tc0_00A (__INTTAB_CPU0 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_10 )); } + .inttab_tc0_00B (__INTTAB_CPU0 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_11 )); } + .inttab_tc0_00C (__INTTAB_CPU0 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_12 )); } + .inttab_tc0_00D (__INTTAB_CPU0 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_13 )); } + .inttab_tc0_00E (__INTTAB_CPU0 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_14 )); } + .inttab_tc0_00F (__INTTAB_CPU0 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_15 )); } + .inttab_tc0_010 (__INTTAB_CPU0 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_16 )); } + .inttab_tc0_011 (__INTTAB_CPU0 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_17 )); } + .inttab_tc0_012 (__INTTAB_CPU0 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_18 )); } + .inttab_tc0_013 (__INTTAB_CPU0 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_19 )); } + .inttab_tc0_014 (__INTTAB_CPU0 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_20 )); } + .inttab_tc0_015 (__INTTAB_CPU0 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_21 )); } + .inttab_tc0_016 (__INTTAB_CPU0 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_22 )); } + .inttab_tc0_017 (__INTTAB_CPU0 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_23 )); } + .inttab_tc0_018 (__INTTAB_CPU0 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_24 )); } + .inttab_tc0_019 (__INTTAB_CPU0 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_25 )); } + .inttab_tc0_01A (__INTTAB_CPU0 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_26 )); } + .inttab_tc0_01B (__INTTAB_CPU0 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_27 )); } + .inttab_tc0_01C (__INTTAB_CPU0 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_28 )); } + .inttab_tc0_01D (__INTTAB_CPU0 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_29 )); } + .inttab_tc0_01E (__INTTAB_CPU0 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_30 )); } + .inttab_tc0_01F (__INTTAB_CPU0 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_31 )); } + .inttab_tc0_020 (__INTTAB_CPU0 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_32 )); } + .inttab_tc0_021 (__INTTAB_CPU0 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_33 )); } + .inttab_tc0_022 (__INTTAB_CPU0 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_34 )); } + .inttab_tc0_023 (__INTTAB_CPU0 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_35 )); } + .inttab_tc0_024 (__INTTAB_CPU0 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_36 )); } + .inttab_tc0_025 (__INTTAB_CPU0 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_37 )); } + .inttab_tc0_026 (__INTTAB_CPU0 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_38 )); } + .inttab_tc0_027 (__INTTAB_CPU0 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_39 )); } + .inttab_tc0_028 (__INTTAB_CPU0 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_40 )); } + .inttab_tc0_029 (__INTTAB_CPU0 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_41 )); } + .inttab_tc0_02A (__INTTAB_CPU0 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_42 )); } + .inttab_tc0_02B (__INTTAB_CPU0 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_43 )); } + .inttab_tc0_02C (__INTTAB_CPU0 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_44 )); } + .inttab_tc0_02D (__INTTAB_CPU0 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_45 )); } + .inttab_tc0_02E (__INTTAB_CPU0 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_46 )); } + .inttab_tc0_02F (__INTTAB_CPU0 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_47 )); } + .inttab_tc0_030 (__INTTAB_CPU0 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_48 )); } + .inttab_tc0_031 (__INTTAB_CPU0 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_49 )); } + .inttab_tc0_032 (__INTTAB_CPU0 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_50 )); } + .inttab_tc0_033 (__INTTAB_CPU0 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_51 )); } + .inttab_tc0_034 (__INTTAB_CPU0 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_52 )); } + .inttab_tc0_035 (__INTTAB_CPU0 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_53 )); } + .inttab_tc0_036 (__INTTAB_CPU0 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_54 )); } + .inttab_tc0_037 (__INTTAB_CPU0 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_55 )); } + .inttab_tc0_038 (__INTTAB_CPU0 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_56 )); } + .inttab_tc0_039 (__INTTAB_CPU0 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_57 )); } + .inttab_tc0_03A (__INTTAB_CPU0 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_58 )); } + .inttab_tc0_03B (__INTTAB_CPU0 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_59 )); } + .inttab_tc0_03C (__INTTAB_CPU0 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_60 )); } + .inttab_tc0_03D (__INTTAB_CPU0 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_61 )); } + .inttab_tc0_03E (__INTTAB_CPU0 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_62 )); } + .inttab_tc0_03F (__INTTAB_CPU0 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_63 )); } + .inttab_tc0_040 (__INTTAB_CPU0 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_64 )); } + .inttab_tc0_041 (__INTTAB_CPU0 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_65 )); } + .inttab_tc0_042 (__INTTAB_CPU0 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_66 )); } + .inttab_tc0_043 (__INTTAB_CPU0 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_67 )); } + .inttab_tc0_044 (__INTTAB_CPU0 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_68 )); } + .inttab_tc0_045 (__INTTAB_CPU0 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_69 )); } + .inttab_tc0_046 (__INTTAB_CPU0 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_70 )); } + .inttab_tc0_047 (__INTTAB_CPU0 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_71 )); } + .inttab_tc0_048 (__INTTAB_CPU0 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_72 )); } + .inttab_tc0_049 (__INTTAB_CPU0 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_73 )); } + .inttab_tc0_04A (__INTTAB_CPU0 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_74 )); } + .inttab_tc0_04B (__INTTAB_CPU0 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_75 )); } + .inttab_tc0_04C (__INTTAB_CPU0 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_76 )); } + .inttab_tc0_04D (__INTTAB_CPU0 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_77 )); } + .inttab_tc0_04E (__INTTAB_CPU0 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_78 )); } + .inttab_tc0_04F (__INTTAB_CPU0 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_79 )); } + .inttab_tc0_050 (__INTTAB_CPU0 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_80 )); } + .inttab_tc0_051 (__INTTAB_CPU0 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_81 )); } + .inttab_tc0_052 (__INTTAB_CPU0 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_82 )); } + .inttab_tc0_053 (__INTTAB_CPU0 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_83 )); } + .inttab_tc0_054 (__INTTAB_CPU0 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_84 )); } + .inttab_tc0_055 (__INTTAB_CPU0 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_85 )); } + .inttab_tc0_056 (__INTTAB_CPU0 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_86 )); } + .inttab_tc0_057 (__INTTAB_CPU0 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_87 )); } + .inttab_tc0_058 (__INTTAB_CPU0 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_88 )); } + .inttab_tc0_059 (__INTTAB_CPU0 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_89 )); } + .inttab_tc0_05A (__INTTAB_CPU0 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_90 )); } + .inttab_tc0_05B (__INTTAB_CPU0 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_91 )); } + .inttab_tc0_05C (__INTTAB_CPU0 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_92 )); } + .inttab_tc0_05D (__INTTAB_CPU0 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_93 )); } + .inttab_tc0_05E (__INTTAB_CPU0 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_94 )); } + .inttab_tc0_05F (__INTTAB_CPU0 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_95 )); } + .inttab_tc0_060 (__INTTAB_CPU0 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_96 )); } + .inttab_tc0_061 (__INTTAB_CPU0 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_97 )); } + .inttab_tc0_062 (__INTTAB_CPU0 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_98 )); } + .inttab_tc0_063 (__INTTAB_CPU0 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_99 )); } + .inttab_tc0_064 (__INTTAB_CPU0 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_100)); } + .inttab_tc0_065 (__INTTAB_CPU0 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_101)); } + .inttab_tc0_066 (__INTTAB_CPU0 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_102)); } + .inttab_tc0_067 (__INTTAB_CPU0 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_103)); } + .inttab_tc0_068 (__INTTAB_CPU0 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_104)); } + .inttab_tc0_069 (__INTTAB_CPU0 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_105)); } + .inttab_tc0_06A (__INTTAB_CPU0 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_106)); } + .inttab_tc0_06B (__INTTAB_CPU0 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_107)); } + .inttab_tc0_06C (__INTTAB_CPU0 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_108)); } + .inttab_tc0_06D (__INTTAB_CPU0 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_109)); } + .inttab_tc0_06E (__INTTAB_CPU0 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_110)); } + .inttab_tc0_06F (__INTTAB_CPU0 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_111)); } + .inttab_tc0_070 (__INTTAB_CPU0 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_112)); } + .inttab_tc0_071 (__INTTAB_CPU0 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_113)); } + .inttab_tc0_072 (__INTTAB_CPU0 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_114)); } + .inttab_tc0_073 (__INTTAB_CPU0 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_115)); } + .inttab_tc0_074 (__INTTAB_CPU0 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_116)); } + .inttab_tc0_075 (__INTTAB_CPU0 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_117)); } + .inttab_tc0_076 (__INTTAB_CPU0 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_118)); } + .inttab_tc0_077 (__INTTAB_CPU0 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_119)); } + .inttab_tc0_078 (__INTTAB_CPU0 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_120)); } + .inttab_tc0_079 (__INTTAB_CPU0 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_121)); } + .inttab_tc0_07A (__INTTAB_CPU0 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_122)); } + .inttab_tc0_07B (__INTTAB_CPU0 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_123)); } + .inttab_tc0_07C (__INTTAB_CPU0 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_124)); } + .inttab_tc0_07D (__INTTAB_CPU0 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_125)); } + .inttab_tc0_07E (__INTTAB_CPU0 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_126)); } + .inttab_tc0_07F (__INTTAB_CPU0 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_127)); } + .inttab_tc0_080 (__INTTAB_CPU0 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_128)); } + .inttab_tc0_081 (__INTTAB_CPU0 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_129)); } + .inttab_tc0_082 (__INTTAB_CPU0 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_130)); } + .inttab_tc0_083 (__INTTAB_CPU0 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_131)); } + .inttab_tc0_084 (__INTTAB_CPU0 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_132)); } + .inttab_tc0_085 (__INTTAB_CPU0 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_133)); } + .inttab_tc0_086 (__INTTAB_CPU0 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_134)); } + .inttab_tc0_087 (__INTTAB_CPU0 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_135)); } + .inttab_tc0_088 (__INTTAB_CPU0 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_136)); } + .inttab_tc0_089 (__INTTAB_CPU0 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_137)); } + .inttab_tc0_08A (__INTTAB_CPU0 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_138)); } + .inttab_tc0_08B (__INTTAB_CPU0 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_139)); } + .inttab_tc0_08C (__INTTAB_CPU0 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_140)); } + .inttab_tc0_08D (__INTTAB_CPU0 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_141)); } + .inttab_tc0_08E (__INTTAB_CPU0 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_142)); } + .inttab_tc0_08F (__INTTAB_CPU0 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_143)); } + .inttab_tc0_090 (__INTTAB_CPU0 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_144)); } + .inttab_tc0_091 (__INTTAB_CPU0 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_145)); } + .inttab_tc0_092 (__INTTAB_CPU0 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_146)); } + .inttab_tc0_093 (__INTTAB_CPU0 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_147)); } + .inttab_tc0_094 (__INTTAB_CPU0 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_148)); } + .inttab_tc0_095 (__INTTAB_CPU0 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_149)); } + .inttab_tc0_096 (__INTTAB_CPU0 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_150)); } + .inttab_tc0_097 (__INTTAB_CPU0 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_151)); } + .inttab_tc0_098 (__INTTAB_CPU0 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_152)); } + .inttab_tc0_099 (__INTTAB_CPU0 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_153)); } + .inttab_tc0_09A (__INTTAB_CPU0 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_154)); } + .inttab_tc0_09B (__INTTAB_CPU0 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_155)); } + .inttab_tc0_09C (__INTTAB_CPU0 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_156)); } + .inttab_tc0_09D (__INTTAB_CPU0 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_157)); } + .inttab_tc0_09E (__INTTAB_CPU0 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_158)); } + .inttab_tc0_09F (__INTTAB_CPU0 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_159)); } + .inttab_tc0_0A0 (__INTTAB_CPU0 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_160)); } + .inttab_tc0_0A1 (__INTTAB_CPU0 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_161)); } + .inttab_tc0_0A2 (__INTTAB_CPU0 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_162)); } + .inttab_tc0_0A3 (__INTTAB_CPU0 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_163)); } + .inttab_tc0_0A4 (__INTTAB_CPU0 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_164)); } + .inttab_tc0_0A5 (__INTTAB_CPU0 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_165)); } + .inttab_tc0_0A6 (__INTTAB_CPU0 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_166)); } + .inttab_tc0_0A7 (__INTTAB_CPU0 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_167)); } + .inttab_tc0_0A8 (__INTTAB_CPU0 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_168)); } + .inttab_tc0_0A9 (__INTTAB_CPU0 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_169)); } + .inttab_tc0_0AA (__INTTAB_CPU0 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_170)); } + .inttab_tc0_0AB (__INTTAB_CPU0 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_171)); } + .inttab_tc0_0AC (__INTTAB_CPU0 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_172)); } + .inttab_tc0_0AD (__INTTAB_CPU0 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_173)); } + .inttab_tc0_0AE (__INTTAB_CPU0 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_174)); } + .inttab_tc0_0AF (__INTTAB_CPU0 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_175)); } + .inttab_tc0_0B0 (__INTTAB_CPU0 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_176)); } + .inttab_tc0_0B1 (__INTTAB_CPU0 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_177)); } + .inttab_tc0_0B2 (__INTTAB_CPU0 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_178)); } + .inttab_tc0_0B3 (__INTTAB_CPU0 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_179)); } + .inttab_tc0_0B4 (__INTTAB_CPU0 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_180)); } + .inttab_tc0_0B5 (__INTTAB_CPU0 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_181)); } + .inttab_tc0_0B6 (__INTTAB_CPU0 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_182)); } + .inttab_tc0_0B7 (__INTTAB_CPU0 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_183)); } + .inttab_tc0_0B8 (__INTTAB_CPU0 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_184)); } + .inttab_tc0_0B9 (__INTTAB_CPU0 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_185)); } + .inttab_tc0_0BA (__INTTAB_CPU0 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_186)); } + .inttab_tc0_0BB (__INTTAB_CPU0 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_187)); } + .inttab_tc0_0BC (__INTTAB_CPU0 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_188)); } + .inttab_tc0_0BD (__INTTAB_CPU0 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_189)); } + .inttab_tc0_0BE (__INTTAB_CPU0 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_190)); } + .inttab_tc0_0BF (__INTTAB_CPU0 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_191)); } + .inttab_tc0_0C0 (__INTTAB_CPU0 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_192)); } + .inttab_tc0_0C1 (__INTTAB_CPU0 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_193)); } + .inttab_tc0_0C2 (__INTTAB_CPU0 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_194)); } + .inttab_tc0_0C3 (__INTTAB_CPU0 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_195)); } + .inttab_tc0_0C4 (__INTTAB_CPU0 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_196)); } + .inttab_tc0_0C5 (__INTTAB_CPU0 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_197)); } + .inttab_tc0_0C6 (__INTTAB_CPU0 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_198)); } + .inttab_tc0_0C7 (__INTTAB_CPU0 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_199)); } + .inttab_tc0_0C8 (__INTTAB_CPU0 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_200)); } + .inttab_tc0_0C9 (__INTTAB_CPU0 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_201)); } + .inttab_tc0_0CA (__INTTAB_CPU0 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_202)); } + .inttab_tc0_0CB (__INTTAB_CPU0 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_203)); } + .inttab_tc0_0CC (__INTTAB_CPU0 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_204)); } + .inttab_tc0_0CD (__INTTAB_CPU0 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_205)); } + .inttab_tc0_0CE (__INTTAB_CPU0 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_206)); } + .inttab_tc0_0CF (__INTTAB_CPU0 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_207)); } + .inttab_tc0_0D0 (__INTTAB_CPU0 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_208)); } + .inttab_tc0_0D1 (__INTTAB_CPU0 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_209)); } + .inttab_tc0_0D2 (__INTTAB_CPU0 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_210)); } + .inttab_tc0_0D3 (__INTTAB_CPU0 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_211)); } + .inttab_tc0_0D4 (__INTTAB_CPU0 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_212)); } + .inttab_tc0_0D5 (__INTTAB_CPU0 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_213)); } + .inttab_tc0_0D6 (__INTTAB_CPU0 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_214)); } + .inttab_tc0_0D7 (__INTTAB_CPU0 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_215)); } + .inttab_tc0_0D8 (__INTTAB_CPU0 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_216)); } + .inttab_tc0_0D9 (__INTTAB_CPU0 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_217)); } + .inttab_tc0_0DA (__INTTAB_CPU0 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_218)); } + .inttab_tc0_0DB (__INTTAB_CPU0 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_219)); } + .inttab_tc0_0DC (__INTTAB_CPU0 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_220)); } + .inttab_tc0_0DD (__INTTAB_CPU0 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_221)); } + .inttab_tc0_0DE (__INTTAB_CPU0 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_222)); } + .inttab_tc0_0DF (__INTTAB_CPU0 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_223)); } + .inttab_tc0_0E0 (__INTTAB_CPU0 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_224)); } + .inttab_tc0_0E1 (__INTTAB_CPU0 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_225)); } + .inttab_tc0_0E2 (__INTTAB_CPU0 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_226)); } + .inttab_tc0_0E3 (__INTTAB_CPU0 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_227)); } + .inttab_tc0_0E4 (__INTTAB_CPU0 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_228)); } + .inttab_tc0_0E5 (__INTTAB_CPU0 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_229)); } + .inttab_tc0_0E6 (__INTTAB_CPU0 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_230)); } + .inttab_tc0_0E7 (__INTTAB_CPU0 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_231)); } + .inttab_tc0_0E8 (__INTTAB_CPU0 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_232)); } + .inttab_tc0_0E9 (__INTTAB_CPU0 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_233)); } + .inttab_tc0_0EA (__INTTAB_CPU0 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_234)); } + .inttab_tc0_0EB (__INTTAB_CPU0 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_235)); } + .inttab_tc0_0EC (__INTTAB_CPU0 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_236)); } + .inttab_tc0_0ED (__INTTAB_CPU0 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_237)); } + .inttab_tc0_0EE (__INTTAB_CPU0 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_238)); } + .inttab_tc0_0EF (__INTTAB_CPU0 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_239)); } + .inttab_tc0_0F0 (__INTTAB_CPU0 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_240)); } + .inttab_tc0_0F1 (__INTTAB_CPU0 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_241)); } + .inttab_tc0_0F2 (__INTTAB_CPU0 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_242)); } + .inttab_tc0_0F3 (__INTTAB_CPU0 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_243)); } + .inttab_tc0_0F4 (__INTTAB_CPU0 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_244)); } + .inttab_tc0_0F5 (__INTTAB_CPU0 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_245)); } + .inttab_tc0_0F6 (__INTTAB_CPU0 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_246)); } + .inttab_tc0_0F7 (__INTTAB_CPU0 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_247)); } + .inttab_tc0_0F8 (__INTTAB_CPU0 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_248)); } + .inttab_tc0_0F9 (__INTTAB_CPU0 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_249)); } + .inttab_tc0_0FA (__INTTAB_CPU0 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_250)); } + .inttab_tc0_0FB (__INTTAB_CPU0 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_251)); } + .inttab_tc0_0FC (__INTTAB_CPU0 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_252)); } + .inttab_tc0_0FD (__INTTAB_CPU0 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_253)); } + .inttab_tc0_0FE (__INTTAB_CPU0 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_254)); } + .inttab_tc0_0FF (__INTTAB_CPU0 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_255)); } + } + SECTIONS + { + /*CPU1 Interrupt Vector Table*/ + .inttab_tc1_000 (__INTTAB_CPU1 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_0 )); } + .inttab_tc1_001 (__INTTAB_CPU1 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_1 )); } + .inttab_tc1_002 (__INTTAB_CPU1 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_2 )); } + .inttab_tc1_003 (__INTTAB_CPU1 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_3 )); } + .inttab_tc1_004 (__INTTAB_CPU1 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_4 )); } + .inttab_tc1_005 (__INTTAB_CPU1 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_5 )); } + .inttab_tc1_006 (__INTTAB_CPU1 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_6 )); } + .inttab_tc1_007 (__INTTAB_CPU1 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_7 )); } + .inttab_tc1_008 (__INTTAB_CPU1 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_8 )); } + .inttab_tc1_009 (__INTTAB_CPU1 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_9 )); } + .inttab_tc1_00A (__INTTAB_CPU1 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_10 )); } + .inttab_tc1_00B (__INTTAB_CPU1 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_11 )); } + .inttab_tc1_00C (__INTTAB_CPU1 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_12 )); } + .inttab_tc1_00D (__INTTAB_CPU1 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_13 )); } + .inttab_tc1_00E (__INTTAB_CPU1 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_14 )); } + .inttab_tc1_00F (__INTTAB_CPU1 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_15 )); } + .inttab_tc1_010 (__INTTAB_CPU1 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_16 )); } + .inttab_tc1_011 (__INTTAB_CPU1 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_17 )); } + .inttab_tc1_012 (__INTTAB_CPU1 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_18 )); } + .inttab_tc1_013 (__INTTAB_CPU1 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_19 )); } + .inttab_tc1_014 (__INTTAB_CPU1 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_20 )); } + .inttab_tc1_015 (__INTTAB_CPU1 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_21 )); } + .inttab_tc1_016 (__INTTAB_CPU1 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_22 )); } + .inttab_tc1_017 (__INTTAB_CPU1 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_23 )); } + .inttab_tc1_018 (__INTTAB_CPU1 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_24 )); } + .inttab_tc1_019 (__INTTAB_CPU1 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_25 )); } + .inttab_tc1_01A (__INTTAB_CPU1 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_26 )); } + .inttab_tc1_01B (__INTTAB_CPU1 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_27 )); } + .inttab_tc1_01C (__INTTAB_CPU1 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_28 )); } + .inttab_tc1_01D (__INTTAB_CPU1 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_29 )); } + .inttab_tc1_01E (__INTTAB_CPU1 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_30 )); } + .inttab_tc1_01F (__INTTAB_CPU1 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_31 )); } + .inttab_tc1_020 (__INTTAB_CPU1 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_32 )); } + .inttab_tc1_021 (__INTTAB_CPU1 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_33 )); } + .inttab_tc1_022 (__INTTAB_CPU1 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_34 )); } + .inttab_tc1_023 (__INTTAB_CPU1 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_35 )); } + .inttab_tc1_024 (__INTTAB_CPU1 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_36 )); } + .inttab_tc1_025 (__INTTAB_CPU1 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_37 )); } + .inttab_tc1_026 (__INTTAB_CPU1 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_38 )); } + .inttab_tc1_027 (__INTTAB_CPU1 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_39 )); } + .inttab_tc1_028 (__INTTAB_CPU1 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_40 )); } + .inttab_tc1_029 (__INTTAB_CPU1 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_41 )); } + .inttab_tc1_02A (__INTTAB_CPU1 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_42 )); } + .inttab_tc1_02B (__INTTAB_CPU1 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_43 )); } + .inttab_tc1_02C (__INTTAB_CPU1 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_44 )); } + .inttab_tc1_02D (__INTTAB_CPU1 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_45 )); } + .inttab_tc1_02E (__INTTAB_CPU1 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_46 )); } + .inttab_tc1_02F (__INTTAB_CPU1 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_47 )); } + .inttab_tc1_030 (__INTTAB_CPU1 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_48 )); } + .inttab_tc1_031 (__INTTAB_CPU1 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_49 )); } + .inttab_tc1_032 (__INTTAB_CPU1 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_50 )); } + .inttab_tc1_033 (__INTTAB_CPU1 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_51 )); } + .inttab_tc1_034 (__INTTAB_CPU1 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_52 )); } + .inttab_tc1_035 (__INTTAB_CPU1 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_53 )); } + .inttab_tc1_036 (__INTTAB_CPU1 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_54 )); } + .inttab_tc1_037 (__INTTAB_CPU1 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_55 )); } + .inttab_tc1_038 (__INTTAB_CPU1 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_56 )); } + .inttab_tc1_039 (__INTTAB_CPU1 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_57 )); } + .inttab_tc1_03A (__INTTAB_CPU1 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_58 )); } + .inttab_tc1_03B (__INTTAB_CPU1 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_59 )); } + .inttab_tc1_03C (__INTTAB_CPU1 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_60 )); } + .inttab_tc1_03D (__INTTAB_CPU1 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_61 )); } + .inttab_tc1_03E (__INTTAB_CPU1 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_62 )); } + .inttab_tc1_03F (__INTTAB_CPU1 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_63 )); } + .inttab_tc1_040 (__INTTAB_CPU1 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_64 )); } + .inttab_tc1_041 (__INTTAB_CPU1 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_65 )); } + .inttab_tc1_042 (__INTTAB_CPU1 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_66 )); } + .inttab_tc1_043 (__INTTAB_CPU1 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_67 )); } + .inttab_tc1_044 (__INTTAB_CPU1 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_68 )); } + .inttab_tc1_045 (__INTTAB_CPU1 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_69 )); } + .inttab_tc1_046 (__INTTAB_CPU1 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_70 )); } + .inttab_tc1_047 (__INTTAB_CPU1 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_71 )); } + .inttab_tc1_048 (__INTTAB_CPU1 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_72 )); } + .inttab_tc1_049 (__INTTAB_CPU1 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_73 )); } + .inttab_tc1_04A (__INTTAB_CPU1 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_74 )); } + .inttab_tc1_04B (__INTTAB_CPU1 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_75 )); } + .inttab_tc1_04C (__INTTAB_CPU1 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_76 )); } + .inttab_tc1_04D (__INTTAB_CPU1 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_77 )); } + .inttab_tc1_04E (__INTTAB_CPU1 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_78 )); } + .inttab_tc1_04F (__INTTAB_CPU1 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_79 )); } + .inttab_tc1_050 (__INTTAB_CPU1 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_80 )); } + .inttab_tc1_051 (__INTTAB_CPU1 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_81 )); } + .inttab_tc1_052 (__INTTAB_CPU1 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_82 )); } + .inttab_tc1_053 (__INTTAB_CPU1 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_83 )); } + .inttab_tc1_054 (__INTTAB_CPU1 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_84 )); } + .inttab_tc1_055 (__INTTAB_CPU1 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_85 )); } + .inttab_tc1_056 (__INTTAB_CPU1 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_86 )); } + .inttab_tc1_057 (__INTTAB_CPU1 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_87 )); } + .inttab_tc1_058 (__INTTAB_CPU1 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_88 )); } + .inttab_tc1_059 (__INTTAB_CPU1 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_89 )); } + .inttab_tc1_05A (__INTTAB_CPU1 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_90 )); } + .inttab_tc1_05B (__INTTAB_CPU1 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_91 )); } + .inttab_tc1_05C (__INTTAB_CPU1 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_92 )); } + .inttab_tc1_05D (__INTTAB_CPU1 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_93 )); } + .inttab_tc1_05E (__INTTAB_CPU1 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_94 )); } + .inttab_tc1_05F (__INTTAB_CPU1 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_95 )); } + .inttab_tc1_060 (__INTTAB_CPU1 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_96 )); } + .inttab_tc1_061 (__INTTAB_CPU1 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_97 )); } + .inttab_tc1_062 (__INTTAB_CPU1 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_98 )); } + .inttab_tc1_063 (__INTTAB_CPU1 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_99 )); } + .inttab_tc1_064 (__INTTAB_CPU1 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_100)); } + .inttab_tc1_065 (__INTTAB_CPU1 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_101)); } + .inttab_tc1_066 (__INTTAB_CPU1 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_102)); } + .inttab_tc1_067 (__INTTAB_CPU1 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_103)); } + .inttab_tc1_068 (__INTTAB_CPU1 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_104)); } + .inttab_tc1_069 (__INTTAB_CPU1 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_105)); } + .inttab_tc1_06A (__INTTAB_CPU1 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_106)); } + .inttab_tc1_06B (__INTTAB_CPU1 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_107)); } + .inttab_tc1_06C (__INTTAB_CPU1 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_108)); } + .inttab_tc1_06D (__INTTAB_CPU1 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_109)); } + .inttab_tc1_06E (__INTTAB_CPU1 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_110)); } + .inttab_tc1_06F (__INTTAB_CPU1 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_111)); } + .inttab_tc1_070 (__INTTAB_CPU1 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_112)); } + .inttab_tc1_071 (__INTTAB_CPU1 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_113)); } + .inttab_tc1_072 (__INTTAB_CPU1 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_114)); } + .inttab_tc1_073 (__INTTAB_CPU1 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_115)); } + .inttab_tc1_074 (__INTTAB_CPU1 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_116)); } + .inttab_tc1_075 (__INTTAB_CPU1 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_117)); } + .inttab_tc1_076 (__INTTAB_CPU1 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_118)); } + .inttab_tc1_077 (__INTTAB_CPU1 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_119)); } + .inttab_tc1_078 (__INTTAB_CPU1 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_120)); } + .inttab_tc1_079 (__INTTAB_CPU1 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_121)); } + .inttab_tc1_07A (__INTTAB_CPU1 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_122)); } + .inttab_tc1_07B (__INTTAB_CPU1 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_123)); } + .inttab_tc1_07C (__INTTAB_CPU1 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_124)); } + .inttab_tc1_07D (__INTTAB_CPU1 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_125)); } + .inttab_tc1_07E (__INTTAB_CPU1 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_126)); } + .inttab_tc1_07F (__INTTAB_CPU1 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_127)); } + .inttab_tc1_080 (__INTTAB_CPU1 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_128)); } + .inttab_tc1_081 (__INTTAB_CPU1 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_129)); } + .inttab_tc1_082 (__INTTAB_CPU1 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_130)); } + .inttab_tc1_083 (__INTTAB_CPU1 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_131)); } + .inttab_tc1_084 (__INTTAB_CPU1 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_132)); } + .inttab_tc1_085 (__INTTAB_CPU1 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_133)); } + .inttab_tc1_086 (__INTTAB_CPU1 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_134)); } + .inttab_tc1_087 (__INTTAB_CPU1 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_135)); } + .inttab_tc1_088 (__INTTAB_CPU1 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_136)); } + .inttab_tc1_089 (__INTTAB_CPU1 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_137)); } + .inttab_tc1_08A (__INTTAB_CPU1 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_138)); } + .inttab_tc1_08B (__INTTAB_CPU1 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_139)); } + .inttab_tc1_08C (__INTTAB_CPU1 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_140)); } + .inttab_tc1_08D (__INTTAB_CPU1 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_141)); } + .inttab_tc1_08E (__INTTAB_CPU1 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_142)); } + .inttab_tc1_08F (__INTTAB_CPU1 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_143)); } + .inttab_tc1_090 (__INTTAB_CPU1 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_144)); } + .inttab_tc1_091 (__INTTAB_CPU1 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_145)); } + .inttab_tc1_092 (__INTTAB_CPU1 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_146)); } + .inttab_tc1_093 (__INTTAB_CPU1 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_147)); } + .inttab_tc1_094 (__INTTAB_CPU1 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_148)); } + .inttab_tc1_095 (__INTTAB_CPU1 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_149)); } + .inttab_tc1_096 (__INTTAB_CPU1 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_150)); } + .inttab_tc1_097 (__INTTAB_CPU1 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_151)); } + .inttab_tc1_098 (__INTTAB_CPU1 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_152)); } + .inttab_tc1_099 (__INTTAB_CPU1 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_153)); } + .inttab_tc1_09A (__INTTAB_CPU1 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_154)); } + .inttab_tc1_09B (__INTTAB_CPU1 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_155)); } + .inttab_tc1_09C (__INTTAB_CPU1 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_156)); } + .inttab_tc1_09D (__INTTAB_CPU1 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_157)); } + .inttab_tc1_09E (__INTTAB_CPU1 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_158)); } + .inttab_tc1_09F (__INTTAB_CPU1 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_159)); } + .inttab_tc1_0A0 (__INTTAB_CPU1 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_160)); } + .inttab_tc1_0A1 (__INTTAB_CPU1 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_161)); } + .inttab_tc1_0A2 (__INTTAB_CPU1 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_162)); } + .inttab_tc1_0A3 (__INTTAB_CPU1 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_163)); } + .inttab_tc1_0A4 (__INTTAB_CPU1 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_164)); } + .inttab_tc1_0A5 (__INTTAB_CPU1 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_165)); } + .inttab_tc1_0A6 (__INTTAB_CPU1 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_166)); } + .inttab_tc1_0A7 (__INTTAB_CPU1 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_167)); } + .inttab_tc1_0A8 (__INTTAB_CPU1 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_168)); } + .inttab_tc1_0A9 (__INTTAB_CPU1 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_169)); } + .inttab_tc1_0AA (__INTTAB_CPU1 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_170)); } + .inttab_tc1_0AB (__INTTAB_CPU1 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_171)); } + .inttab_tc1_0AC (__INTTAB_CPU1 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_172)); } + .inttab_tc1_0AD (__INTTAB_CPU1 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_173)); } + .inttab_tc1_0AE (__INTTAB_CPU1 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_174)); } + .inttab_tc1_0AF (__INTTAB_CPU1 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_175)); } + .inttab_tc1_0B0 (__INTTAB_CPU1 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_176)); } + .inttab_tc1_0B1 (__INTTAB_CPU1 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_177)); } + .inttab_tc1_0B2 (__INTTAB_CPU1 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_178)); } + .inttab_tc1_0B3 (__INTTAB_CPU1 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_179)); } + .inttab_tc1_0B4 (__INTTAB_CPU1 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_180)); } + .inttab_tc1_0B5 (__INTTAB_CPU1 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_181)); } + .inttab_tc1_0B6 (__INTTAB_CPU1 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_182)); } + .inttab_tc1_0B7 (__INTTAB_CPU1 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_183)); } + .inttab_tc1_0B8 (__INTTAB_CPU1 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_184)); } + .inttab_tc1_0B9 (__INTTAB_CPU1 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_185)); } + .inttab_tc1_0BA (__INTTAB_CPU1 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_186)); } + .inttab_tc1_0BB (__INTTAB_CPU1 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_187)); } + .inttab_tc1_0BC (__INTTAB_CPU1 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_188)); } + .inttab_tc1_0BD (__INTTAB_CPU1 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_189)); } + .inttab_tc1_0BE (__INTTAB_CPU1 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_190)); } + .inttab_tc1_0BF (__INTTAB_CPU1 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_191)); } + .inttab_tc1_0C0 (__INTTAB_CPU1 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_192)); } + .inttab_tc1_0C1 (__INTTAB_CPU1 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_193)); } + .inttab_tc1_0C2 (__INTTAB_CPU1 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_194)); } + .inttab_tc1_0C3 (__INTTAB_CPU1 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_195)); } + .inttab_tc1_0C4 (__INTTAB_CPU1 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_196)); } + .inttab_tc1_0C5 (__INTTAB_CPU1 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_197)); } + .inttab_tc1_0C6 (__INTTAB_CPU1 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_198)); } + .inttab_tc1_0C7 (__INTTAB_CPU1 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_199)); } + .inttab_tc1_0C8 (__INTTAB_CPU1 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_200)); } + .inttab_tc1_0C9 (__INTTAB_CPU1 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_201)); } + .inttab_tc1_0CA (__INTTAB_CPU1 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_202)); } + .inttab_tc1_0CB (__INTTAB_CPU1 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_203)); } + .inttab_tc1_0CC (__INTTAB_CPU1 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_204)); } + .inttab_tc1_0CD (__INTTAB_CPU1 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_205)); } + .inttab_tc1_0CE (__INTTAB_CPU1 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_206)); } + .inttab_tc1_0CF (__INTTAB_CPU1 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_207)); } + .inttab_tc1_0D0 (__INTTAB_CPU1 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_208)); } + .inttab_tc1_0D1 (__INTTAB_CPU1 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_209)); } + .inttab_tc1_0D2 (__INTTAB_CPU1 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_210)); } + .inttab_tc1_0D3 (__INTTAB_CPU1 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_211)); } + .inttab_tc1_0D4 (__INTTAB_CPU1 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_212)); } + .inttab_tc1_0D5 (__INTTAB_CPU1 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_213)); } + .inttab_tc1_0D6 (__INTTAB_CPU1 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_214)); } + .inttab_tc1_0D7 (__INTTAB_CPU1 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_215)); } + .inttab_tc1_0D8 (__INTTAB_CPU1 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_216)); } + .inttab_tc1_0D9 (__INTTAB_CPU1 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_217)); } + .inttab_tc1_0DA (__INTTAB_CPU1 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_218)); } + .inttab_tc1_0DB (__INTTAB_CPU1 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_219)); } + .inttab_tc1_0DC (__INTTAB_CPU1 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_220)); } + .inttab_tc1_0DD (__INTTAB_CPU1 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_221)); } + .inttab_tc1_0DE (__INTTAB_CPU1 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_222)); } + .inttab_tc1_0DF (__INTTAB_CPU1 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_223)); } + .inttab_tc1_0E0 (__INTTAB_CPU1 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_224)); } + .inttab_tc1_0E1 (__INTTAB_CPU1 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_225)); } + .inttab_tc1_0E2 (__INTTAB_CPU1 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_226)); } + .inttab_tc1_0E3 (__INTTAB_CPU1 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_227)); } + .inttab_tc1_0E4 (__INTTAB_CPU1 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_228)); } + .inttab_tc1_0E5 (__INTTAB_CPU1 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_229)); } + .inttab_tc1_0E6 (__INTTAB_CPU1 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_230)); } + .inttab_tc1_0E7 (__INTTAB_CPU1 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_231)); } + .inttab_tc1_0E8 (__INTTAB_CPU1 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_232)); } + .inttab_tc1_0E9 (__INTTAB_CPU1 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_233)); } + .inttab_tc1_0EA (__INTTAB_CPU1 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_234)); } + .inttab_tc1_0EB (__INTTAB_CPU1 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_235)); } + .inttab_tc1_0EC (__INTTAB_CPU1 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_236)); } + .inttab_tc1_0ED (__INTTAB_CPU1 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_237)); } + .inttab_tc1_0EE (__INTTAB_CPU1 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_238)); } + .inttab_tc1_0EF (__INTTAB_CPU1 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_239)); } + .inttab_tc1_0F0 (__INTTAB_CPU1 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_240)); } + .inttab_tc1_0F1 (__INTTAB_CPU1 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_241)); } + .inttab_tc1_0F2 (__INTTAB_CPU1 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_242)); } + .inttab_tc1_0F3 (__INTTAB_CPU1 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_243)); } + .inttab_tc1_0F4 (__INTTAB_CPU1 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_244)); } + .inttab_tc1_0F5 (__INTTAB_CPU1 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_245)); } + .inttab_tc1_0F6 (__INTTAB_CPU1 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_246)); } + .inttab_tc1_0F7 (__INTTAB_CPU1 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_247)); } + .inttab_tc1_0F8 (__INTTAB_CPU1 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_248)); } + .inttab_tc1_0F9 (__INTTAB_CPU1 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_249)); } + .inttab_tc1_0FA (__INTTAB_CPU1 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_250)); } + .inttab_tc1_0FB (__INTTAB_CPU1 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_251)); } + .inttab_tc1_0FC (__INTTAB_CPU1 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_252)); } + .inttab_tc1_0FD (__INTTAB_CPU1 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_253)); } + .inttab_tc1_0FE (__INTTAB_CPU1 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_254)); } + .inttab_tc1_0FF (__INTTAB_CPU1 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_255)); } + } + SECTIONS + { + /*CPU2 Interrupt Vector Table*/ + .inttab_tc2_000 (__INTTAB_CPU2 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_0 )); } + .inttab_tc2_001 (__INTTAB_CPU2 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_1 )); } + .inttab_tc2_002 (__INTTAB_CPU2 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_2 )); } + .inttab_tc2_003 (__INTTAB_CPU2 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_3 )); } + .inttab_tc2_004 (__INTTAB_CPU2 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_4 )); } + .inttab_tc2_005 (__INTTAB_CPU2 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_5 )); } + .inttab_tc2_006 (__INTTAB_CPU2 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_6 )); } + .inttab_tc2_007 (__INTTAB_CPU2 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_7 )); } + .inttab_tc2_008 (__INTTAB_CPU2 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_8 )); } + .inttab_tc2_009 (__INTTAB_CPU2 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_9 )); } + .inttab_tc2_00A (__INTTAB_CPU2 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_10 )); } + .inttab_tc2_00B (__INTTAB_CPU2 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_11 )); } + .inttab_tc2_00C (__INTTAB_CPU2 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_12 )); } + .inttab_tc2_00D (__INTTAB_CPU2 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_13 )); } + .inttab_tc2_00E (__INTTAB_CPU2 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_14 )); } + .inttab_tc2_00F (__INTTAB_CPU2 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_15 )); } + .inttab_tc2_010 (__INTTAB_CPU2 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_16 )); } + .inttab_tc2_011 (__INTTAB_CPU2 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_17 )); } + .inttab_tc2_012 (__INTTAB_CPU2 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_18 )); } + .inttab_tc2_013 (__INTTAB_CPU2 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_19 )); } + .inttab_tc2_014 (__INTTAB_CPU2 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_20 )); } + .inttab_tc2_015 (__INTTAB_CPU2 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_21 )); } + .inttab_tc2_016 (__INTTAB_CPU2 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_22 )); } + .inttab_tc2_017 (__INTTAB_CPU2 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_23 )); } + .inttab_tc2_018 (__INTTAB_CPU2 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_24 )); } + .inttab_tc2_019 (__INTTAB_CPU2 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_25 )); } + .inttab_tc2_01A (__INTTAB_CPU2 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_26 )); } + .inttab_tc2_01B (__INTTAB_CPU2 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_27 )); } + .inttab_tc2_01C (__INTTAB_CPU2 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_28 )); } + .inttab_tc2_01D (__INTTAB_CPU2 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_29 )); } + .inttab_tc2_01E (__INTTAB_CPU2 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_30 )); } + .inttab_tc2_01F (__INTTAB_CPU2 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_31 )); } + .inttab_tc2_020 (__INTTAB_CPU2 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_32 )); } + .inttab_tc2_021 (__INTTAB_CPU2 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_33 )); } + .inttab_tc2_022 (__INTTAB_CPU2 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_34 )); } + .inttab_tc2_023 (__INTTAB_CPU2 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_35 )); } + .inttab_tc2_024 (__INTTAB_CPU2 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_36 )); } + .inttab_tc2_025 (__INTTAB_CPU2 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_37 )); } + .inttab_tc2_026 (__INTTAB_CPU2 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_38 )); } + .inttab_tc2_027 (__INTTAB_CPU2 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_39 )); } + .inttab_tc2_028 (__INTTAB_CPU2 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_40 )); } + .inttab_tc2_029 (__INTTAB_CPU2 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_41 )); } + .inttab_tc2_02A (__INTTAB_CPU2 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_42 )); } + .inttab_tc2_02B (__INTTAB_CPU2 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_43 )); } + .inttab_tc2_02C (__INTTAB_CPU2 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_44 )); } + .inttab_tc2_02D (__INTTAB_CPU2 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_45 )); } + .inttab_tc2_02E (__INTTAB_CPU2 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_46 )); } + .inttab_tc2_02F (__INTTAB_CPU2 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_47 )); } + .inttab_tc2_030 (__INTTAB_CPU2 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_48 )); } + .inttab_tc2_031 (__INTTAB_CPU2 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_49 )); } + .inttab_tc2_032 (__INTTAB_CPU2 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_50 )); } + .inttab_tc2_033 (__INTTAB_CPU2 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_51 )); } + .inttab_tc2_034 (__INTTAB_CPU2 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_52 )); } + .inttab_tc2_035 (__INTTAB_CPU2 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_53 )); } + .inttab_tc2_036 (__INTTAB_CPU2 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_54 )); } + .inttab_tc2_037 (__INTTAB_CPU2 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_55 )); } + .inttab_tc2_038 (__INTTAB_CPU2 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_56 )); } + .inttab_tc2_039 (__INTTAB_CPU2 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_57 )); } + .inttab_tc2_03A (__INTTAB_CPU2 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_58 )); } + .inttab_tc2_03B (__INTTAB_CPU2 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_59 )); } + .inttab_tc2_03C (__INTTAB_CPU2 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_60 )); } + .inttab_tc2_03D (__INTTAB_CPU2 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_61 )); } + .inttab_tc2_03E (__INTTAB_CPU2 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_62 )); } + .inttab_tc2_03F (__INTTAB_CPU2 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_63 )); } + .inttab_tc2_040 (__INTTAB_CPU2 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_64 )); } + .inttab_tc2_041 (__INTTAB_CPU2 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_65 )); } + .inttab_tc2_042 (__INTTAB_CPU2 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_66 )); } + .inttab_tc2_043 (__INTTAB_CPU2 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_67 )); } + .inttab_tc2_044 (__INTTAB_CPU2 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_68 )); } + .inttab_tc2_045 (__INTTAB_CPU2 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_69 )); } + .inttab_tc2_046 (__INTTAB_CPU2 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_70 )); } + .inttab_tc2_047 (__INTTAB_CPU2 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_71 )); } + .inttab_tc2_048 (__INTTAB_CPU2 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_72 )); } + .inttab_tc2_049 (__INTTAB_CPU2 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_73 )); } + .inttab_tc2_04A (__INTTAB_CPU2 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_74 )); } + .inttab_tc2_04B (__INTTAB_CPU2 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_75 )); } + .inttab_tc2_04C (__INTTAB_CPU2 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_76 )); } + .inttab_tc2_04D (__INTTAB_CPU2 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_77 )); } + .inttab_tc2_04E (__INTTAB_CPU2 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_78 )); } + .inttab_tc2_04F (__INTTAB_CPU2 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_79 )); } + .inttab_tc2_050 (__INTTAB_CPU2 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_80 )); } + .inttab_tc2_051 (__INTTAB_CPU2 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_81 )); } + .inttab_tc2_052 (__INTTAB_CPU2 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_82 )); } + .inttab_tc2_053 (__INTTAB_CPU2 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_83 )); } + .inttab_tc2_054 (__INTTAB_CPU2 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_84 )); } + .inttab_tc2_055 (__INTTAB_CPU2 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_85 )); } + .inttab_tc2_056 (__INTTAB_CPU2 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_86 )); } + .inttab_tc2_057 (__INTTAB_CPU2 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_87 )); } + .inttab_tc2_058 (__INTTAB_CPU2 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_88 )); } + .inttab_tc2_059 (__INTTAB_CPU2 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_89 )); } + .inttab_tc2_05A (__INTTAB_CPU2 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_90 )); } + .inttab_tc2_05B (__INTTAB_CPU2 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_91 )); } + .inttab_tc2_05C (__INTTAB_CPU2 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_92 )); } + .inttab_tc2_05D (__INTTAB_CPU2 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_93 )); } + .inttab_tc2_05E (__INTTAB_CPU2 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_94 )); } + .inttab_tc2_05F (__INTTAB_CPU2 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_95 )); } + .inttab_tc2_060 (__INTTAB_CPU2 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_96 )); } + .inttab_tc2_061 (__INTTAB_CPU2 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_97 )); } + .inttab_tc2_062 (__INTTAB_CPU2 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_98 )); } + .inttab_tc2_063 (__INTTAB_CPU2 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_99 )); } + .inttab_tc2_064 (__INTTAB_CPU2 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_100)); } + .inttab_tc2_065 (__INTTAB_CPU2 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_101)); } + .inttab_tc2_066 (__INTTAB_CPU2 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_102)); } + .inttab_tc2_067 (__INTTAB_CPU2 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_103)); } + .inttab_tc2_068 (__INTTAB_CPU2 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_104)); } + .inttab_tc2_069 (__INTTAB_CPU2 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_105)); } + .inttab_tc2_06A (__INTTAB_CPU2 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_106)); } + .inttab_tc2_06B (__INTTAB_CPU2 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_107)); } + .inttab_tc2_06C (__INTTAB_CPU2 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_108)); } + .inttab_tc2_06D (__INTTAB_CPU2 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_109)); } + .inttab_tc2_06E (__INTTAB_CPU2 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_110)); } + .inttab_tc2_06F (__INTTAB_CPU2 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_111)); } + .inttab_tc2_070 (__INTTAB_CPU2 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_112)); } + .inttab_tc2_071 (__INTTAB_CPU2 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_113)); } + .inttab_tc2_072 (__INTTAB_CPU2 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_114)); } + .inttab_tc2_073 (__INTTAB_CPU2 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_115)); } + .inttab_tc2_074 (__INTTAB_CPU2 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_116)); } + .inttab_tc2_075 (__INTTAB_CPU2 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_117)); } + .inttab_tc2_076 (__INTTAB_CPU2 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_118)); } + .inttab_tc2_077 (__INTTAB_CPU2 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_119)); } + .inttab_tc2_078 (__INTTAB_CPU2 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_120)); } + .inttab_tc2_079 (__INTTAB_CPU2 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_121)); } + .inttab_tc2_07A (__INTTAB_CPU2 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_122)); } + .inttab_tc2_07B (__INTTAB_CPU2 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_123)); } + .inttab_tc2_07C (__INTTAB_CPU2 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_124)); } + .inttab_tc2_07D (__INTTAB_CPU2 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_125)); } + .inttab_tc2_07E (__INTTAB_CPU2 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_126)); } + .inttab_tc2_07F (__INTTAB_CPU2 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_127)); } + .inttab_tc2_080 (__INTTAB_CPU2 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_128)); } + .inttab_tc2_081 (__INTTAB_CPU2 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_129)); } + .inttab_tc2_082 (__INTTAB_CPU2 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_130)); } + .inttab_tc2_083 (__INTTAB_CPU2 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_131)); } + .inttab_tc2_084 (__INTTAB_CPU2 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_132)); } + .inttab_tc2_085 (__INTTAB_CPU2 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_133)); } + .inttab_tc2_086 (__INTTAB_CPU2 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_134)); } + .inttab_tc2_087 (__INTTAB_CPU2 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_135)); } + .inttab_tc2_088 (__INTTAB_CPU2 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_136)); } + .inttab_tc2_089 (__INTTAB_CPU2 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_137)); } + .inttab_tc2_08A (__INTTAB_CPU2 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_138)); } + .inttab_tc2_08B (__INTTAB_CPU2 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_139)); } + .inttab_tc2_08C (__INTTAB_CPU2 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_140)); } + .inttab_tc2_08D (__INTTAB_CPU2 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_141)); } + .inttab_tc2_08E (__INTTAB_CPU2 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_142)); } + .inttab_tc2_08F (__INTTAB_CPU2 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_143)); } + .inttab_tc2_090 (__INTTAB_CPU2 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_144)); } + .inttab_tc2_091 (__INTTAB_CPU2 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_145)); } + .inttab_tc2_092 (__INTTAB_CPU2 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_146)); } + .inttab_tc2_093 (__INTTAB_CPU2 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_147)); } + .inttab_tc2_094 (__INTTAB_CPU2 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_148)); } + .inttab_tc2_095 (__INTTAB_CPU2 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_149)); } + .inttab_tc2_096 (__INTTAB_CPU2 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_150)); } + .inttab_tc2_097 (__INTTAB_CPU2 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_151)); } + .inttab_tc2_098 (__INTTAB_CPU2 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_152)); } + .inttab_tc2_099 (__INTTAB_CPU2 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_153)); } + .inttab_tc2_09A (__INTTAB_CPU2 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_154)); } + .inttab_tc2_09B (__INTTAB_CPU2 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_155)); } + .inttab_tc2_09C (__INTTAB_CPU2 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_156)); } + .inttab_tc2_09D (__INTTAB_CPU2 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_157)); } + .inttab_tc2_09E (__INTTAB_CPU2 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_158)); } + .inttab_tc2_09F (__INTTAB_CPU2 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_159)); } + .inttab_tc2_0A0 (__INTTAB_CPU2 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_160)); } + .inttab_tc2_0A1 (__INTTAB_CPU2 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_161)); } + .inttab_tc2_0A2 (__INTTAB_CPU2 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_162)); } + .inttab_tc2_0A3 (__INTTAB_CPU2 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_163)); } + .inttab_tc2_0A4 (__INTTAB_CPU2 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_164)); } + .inttab_tc2_0A5 (__INTTAB_CPU2 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_165)); } + .inttab_tc2_0A6 (__INTTAB_CPU2 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_166)); } + .inttab_tc2_0A7 (__INTTAB_CPU2 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_167)); } + .inttab_tc2_0A8 (__INTTAB_CPU2 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_168)); } + .inttab_tc2_0A9 (__INTTAB_CPU2 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_169)); } + .inttab_tc2_0AA (__INTTAB_CPU2 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_170)); } + .inttab_tc2_0AB (__INTTAB_CPU2 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_171)); } + .inttab_tc2_0AC (__INTTAB_CPU2 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_172)); } + .inttab_tc2_0AD (__INTTAB_CPU2 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_173)); } + .inttab_tc2_0AE (__INTTAB_CPU2 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_174)); } + .inttab_tc2_0AF (__INTTAB_CPU2 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_175)); } + .inttab_tc2_0B0 (__INTTAB_CPU2 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_176)); } + .inttab_tc2_0B1 (__INTTAB_CPU2 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_177)); } + .inttab_tc2_0B2 (__INTTAB_CPU2 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_178)); } + .inttab_tc2_0B3 (__INTTAB_CPU2 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_179)); } + .inttab_tc2_0B4 (__INTTAB_CPU2 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_180)); } + .inttab_tc2_0B5 (__INTTAB_CPU2 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_181)); } + .inttab_tc2_0B6 (__INTTAB_CPU2 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_182)); } + .inttab_tc2_0B7 (__INTTAB_CPU2 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_183)); } + .inttab_tc2_0B8 (__INTTAB_CPU2 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_184)); } + .inttab_tc2_0B9 (__INTTAB_CPU2 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_185)); } + .inttab_tc2_0BA (__INTTAB_CPU2 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_186)); } + .inttab_tc2_0BB (__INTTAB_CPU2 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_187)); } + .inttab_tc2_0BC (__INTTAB_CPU2 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_188)); } + .inttab_tc2_0BD (__INTTAB_CPU2 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_189)); } + .inttab_tc2_0BE (__INTTAB_CPU2 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_190)); } + .inttab_tc2_0BF (__INTTAB_CPU2 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_191)); } + .inttab_tc2_0C0 (__INTTAB_CPU2 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_192)); } + .inttab_tc2_0C1 (__INTTAB_CPU2 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_193)); } + .inttab_tc2_0C2 (__INTTAB_CPU2 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_194)); } + .inttab_tc2_0C3 (__INTTAB_CPU2 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_195)); } + .inttab_tc2_0C4 (__INTTAB_CPU2 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_196)); } + .inttab_tc2_0C5 (__INTTAB_CPU2 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_197)); } + .inttab_tc2_0C6 (__INTTAB_CPU2 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_198)); } + .inttab_tc2_0C7 (__INTTAB_CPU2 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_199)); } + .inttab_tc2_0C8 (__INTTAB_CPU2 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_200)); } + .inttab_tc2_0C9 (__INTTAB_CPU2 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_201)); } + .inttab_tc2_0CA (__INTTAB_CPU2 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_202)); } + .inttab_tc2_0CB (__INTTAB_CPU2 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_203)); } + .inttab_tc2_0CC (__INTTAB_CPU2 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_204)); } + .inttab_tc2_0CD (__INTTAB_CPU2 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_205)); } + .inttab_tc2_0CE (__INTTAB_CPU2 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_206)); } + .inttab_tc2_0CF (__INTTAB_CPU2 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_207)); } + .inttab_tc2_0D0 (__INTTAB_CPU2 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_208)); } + .inttab_tc2_0D1 (__INTTAB_CPU2 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_209)); } + .inttab_tc2_0D2 (__INTTAB_CPU2 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_210)); } + .inttab_tc2_0D3 (__INTTAB_CPU2 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_211)); } + .inttab_tc2_0D4 (__INTTAB_CPU2 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_212)); } + .inttab_tc2_0D5 (__INTTAB_CPU2 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_213)); } + .inttab_tc2_0D6 (__INTTAB_CPU2 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_214)); } + .inttab_tc2_0D7 (__INTTAB_CPU2 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_215)); } + .inttab_tc2_0D8 (__INTTAB_CPU2 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_216)); } + .inttab_tc2_0D9 (__INTTAB_CPU2 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_217)); } + .inttab_tc2_0DA (__INTTAB_CPU2 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_218)); } + .inttab_tc2_0DB (__INTTAB_CPU2 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_219)); } + .inttab_tc2_0DC (__INTTAB_CPU2 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_220)); } + .inttab_tc2_0DD (__INTTAB_CPU2 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_221)); } + .inttab_tc2_0DE (__INTTAB_CPU2 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_222)); } + .inttab_tc2_0DF (__INTTAB_CPU2 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_223)); } + .inttab_tc2_0E0 (__INTTAB_CPU2 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_224)); } + .inttab_tc2_0E1 (__INTTAB_CPU2 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_225)); } + .inttab_tc2_0E2 (__INTTAB_CPU2 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_226)); } + .inttab_tc2_0E3 (__INTTAB_CPU2 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_227)); } + .inttab_tc2_0E4 (__INTTAB_CPU2 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_228)); } + .inttab_tc2_0E5 (__INTTAB_CPU2 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_229)); } + .inttab_tc2_0E6 (__INTTAB_CPU2 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_230)); } + .inttab_tc2_0E7 (__INTTAB_CPU2 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_231)); } + .inttab_tc2_0E8 (__INTTAB_CPU2 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_232)); } + .inttab_tc2_0E9 (__INTTAB_CPU2 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_233)); } + .inttab_tc2_0EA (__INTTAB_CPU2 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_234)); } + .inttab_tc2_0EB (__INTTAB_CPU2 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_235)); } + .inttab_tc2_0EC (__INTTAB_CPU2 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_236)); } + .inttab_tc2_0ED (__INTTAB_CPU2 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_237)); } + .inttab_tc2_0EE (__INTTAB_CPU2 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_238)); } + .inttab_tc2_0EF (__INTTAB_CPU2 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_239)); } + .inttab_tc2_0F0 (__INTTAB_CPU2 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_240)); } + .inttab_tc2_0F1 (__INTTAB_CPU2 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_241)); } + .inttab_tc2_0F2 (__INTTAB_CPU2 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_242)); } + .inttab_tc2_0F3 (__INTTAB_CPU2 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_243)); } + .inttab_tc2_0F4 (__INTTAB_CPU2 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_244)); } + .inttab_tc2_0F5 (__INTTAB_CPU2 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_245)); } + .inttab_tc2_0F6 (__INTTAB_CPU2 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_246)); } + .inttab_tc2_0F7 (__INTTAB_CPU2 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_247)); } + .inttab_tc2_0F8 (__INTTAB_CPU2 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_248)); } + .inttab_tc2_0F9 (__INTTAB_CPU2 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_249)); } + .inttab_tc2_0FA (__INTTAB_CPU2 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_250)); } + .inttab_tc2_0FB (__INTTAB_CPU2 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_251)); } + .inttab_tc2_0FC (__INTTAB_CPU2 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_252)); } + .inttab_tc2_0FD (__INTTAB_CPU2 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_253)); } + .inttab_tc2_0FE (__INTTAB_CPU2 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_254)); } + .inttab_tc2_0FF (__INTTAB_CPU2 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_255)); } + } + + /*Fixed memory Allocations for BMHD*/ + CORE_ID = GLOBAL; + SECTIONS + { + .bmhd_0_org (0xaf400000) : FLAGS(arl) { KEEP (*(.bmhd_0_orig)); } > ucb + .bmhd_1_org (0xaf400200) : FLAGS(arl) { KEEP (*(.bmhd_1_orig)); } > ucb + .bmhd_2_org (0xaf400400) : FLAGS(arl) { KEEP (*(.bmhd_2_orig)); } > ucb + .bmhd_3_org (0xaf400600) : FLAGS(arl) { KEEP (*(.bmhd_3_orig)); } > ucb + .ucb_reserved (0xaf400800) : FLAGS(arl) { } > ucb + .bmhd_0_copy (0xaf401000) : FLAGS(arl) { KEEP (*(.bmhd_0_copy)); } > ucb + .bmhd_1_copy (0xaf401200) : FLAGS(arl) { KEEP (*(.bmhd_1_copy)); } > ucb + .bmhd_2_copy (0xaf401400) : FLAGS(arl) { KEEP (*(.bmhd_2_copy)); } > ucb + .bmhd_3_copy (0xaf401600) : FLAGS(arl) { KEEP (*(.bmhd_3_copy)); } > ucb + } + + /*Near Abbsolute Addressable Data Sections*/ + /*Near Absolute Data, selectable with patterns and user defined sections*/ + CORE_ID = CPU2; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR2_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc2.* (.zdata) + *Cpu2_Main.* (.zdata) + *(.zdata_cpu2) + *(.zdata_cpu2.*) + . = ALIGN(2); + } > dsram2 AT> pfls1 + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc2.* (.zbss) + *Cpu2_Main.* (.zbss) + *(.zbss_cpu2) + *(.zbss_cpu2.*) + } > dsram2 + } + CORE_ID = CPU1; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR1_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc1.* (.zdata) + *Cpu1_Main.* (.zdata) + *(.zdata_cpu1) + *(.zdata_cpu1.*) + . = ALIGN(2); + } > dsram1 AT> pfls1 + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc1.* (.zbss) + *Cpu1_Main.* (.zbss) + *(.zbss_cpu1) + *(.zbss_cpu1.*) + } > dsram1 + } + CORE_ID = CPU0; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR0_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc0.* (.zdata) + *Cpu0_Main.* (.zdata) + *(.zdata_cpu0) + *(.zdata_cpu0.*) + . = ALIGN(2); + } > dsram0 AT> pfls1 + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc0.* (.zbss) + *Cpu0_Main.* (.zbss) + *(.zbss_cpu0) + *(.zbss_cpu0.*) + } > dsram0 + } + + /*Near Absolute Data, selectable by toolchain*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zdata_powerOn) : FLAGS(awzl) + { + *(.zdata.dsprPowerOnInit.cpu0.32bit) + *(.zdata.dsprPowerOnInit.cpu0.16bit) + *(.zdata.dsprPowerOnInit.cpu0.8bit) + . = ALIGN(2); + } > default_ram AT> pfls1 + + CORE_SEC(.zdata) : FLAGS(awzl) + { + *(.zdata.dsprInit.cpu0.32bit) + *(.zdata.dsprInit.cpu0.16bit) + *(.zdata.dsprInit.cpu0.8bit) + *(.zdata) + *(.zdata.*) + *(.gnu.linkonce.z.*) + . = ALIGN(2); + } > default_ram AT> pfls1 + + CORE_SEC(.zbss_powerOn) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprPowerOnClear.cpu0.32bit) + *(.zbss.dsprPowerOnClear.cpu0.16bit) + *(.zbss.dsprPowerOnClear.cpu0.8bit) + } > default_ram + + CORE_SEC(.zbss_noClear) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprNoInit.cpu0.32bit) + *(.zbss.dsprNoInit.cpu0.16bit) + *(.zbss.dsprNoInit.cpu0.8bit) + } > default_ram + + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprClearOnInit.cpu0.32bit) + *(.zbss.dsprClearOnInit.cpu0.16bit) + *(.zbss.dsprClearOnInit.cpu0.8bit) + *(.zbss) + *(.zbss.*) + *(.bbss) + *(.bbss.*) + *(.gnu.linkonce.zb.*) + } > default_ram + } + + CORE_ID = GLOBAL; + SECTIONS + { + /*Cpu0_dlmu also is the segment start, all the near lmu data shll be located here*/ + CORE_SEC(.lmuzdata) : FLAGS(awzl) + { + *(.zlmudata) + *(.zlmudata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls1 + + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) + { + *(.zlmubss) + *(.zlmubss.*) + } > cpu0_dlmu + } + + /*Near Absolute Const, selectable with patterns and user defined sections*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zrodata) : FLAGS(arzl) + { + *Ifx_Ssw_Tc?.* (.zrodata) + *Cpu?_Main.* (.zrodata) + *(.zrodata_cpu?) + } > pfls1 + } + + /*Near Absolute Const, selectable by toolchain*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zrodata) : FLAGS(arzl) + { + *(.zrodata.const.cpu0.32bit) + *(.zrodata.const.cpu0.16bit) + *(.zrodata.const.cpu0.8bit) + *(.zrodata.config.cpu0.32bit) + *(.zrodata.config.cpu0.16bit) + *(.zrodata.config.cpu0.8bit) + *(.zrodata) + *(.zrodata.*) + } > pfls1 + } + +/*Relative A0/A1/A8/A9 Addressable Sections*/ +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A0 Addressable Data, selectable with patterns and user defined sections*/ + /*Note: A0 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A0 Addressable Data, selectable by toolchain*/ + CORE_SEC(.sdata) : FLAGS(awsl) + { + *(.sdata) + *(.sdata.*) + . = ALIGN(2); + } > default_ram AT> pfls1 + CORE_SEC(.sbss) (NOLOAD): FLAGS(aws) + { + *(.sbss) + *(.sbss.*) + } > default_ram + _SMALL_DATA_ = SIZEOF(CORE_SEC(.sdata)) ? ADDR(CORE_SEC(.sdata)) : (ADDR(CORE_SEC(.sdata)) & 0xF0000000) + 32k ; + __A0_MEM = _SMALL_DATA_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A1 Addressable Const, selectable with patterns and user defined sections*/ + /*Note: A1 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A1 Addressable Const, selectable by toolchain*/ + CORE_SEC(.sdata2) : FLAGS(arsl) + { + *(.srodata) + *(.srodata.*) + } > default_rom + _SMALL_DATA2_ = SIZEOF(CORE_SEC(.sdata2)) ? ADDR(CORE_SEC(.sdata2)) : (ADDR(CORE_SEC(.sdata2)) & 0xF0000000) + 32k ; + __A1_MEM = _SMALL_DATA2_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata3) : FLAGS(arsl) + { + *(.rodata_a8) + *(.rodata_a8.*) + } > default_rom + + _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; + __A8_MEM = _SMALL_DATA3_; +} + +/*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ +/*Far Data Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU2 ; +SECTIONS +{ + /*DSRAM2 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc2.* (.data) + *Cpu2_Main.* (.data) + *(.data_cpu2) + *(.data_cpu2.*) + . = ALIGN(2); + } > dsram2 AT> pfls1 + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc2.* (.bss) + *Cpu2_Main.* (.bss) + *(.bss_cpu2) + *(.bss_cpu2.*) + } > dsram2 + + /*DLMU2 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu2) + *(.lmudata_cpu2.*) + . = ALIGN(2); + } > cpu2_dlmu AT> pfls1 + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu2) + *(.lmubss_cpu2.*) + } > cpu2_dlmu +} +CORE_ID = CPU1 ; +SECTIONS +{ + /*DSRAM1 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc1.* (.data) + *Cpu1_Main.* (.data) + *(.data_cpu1) + *(.data_cpu1.*) + . = ALIGN(2); + } > dsram1 AT> pfls1 + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc1.* (.bss) + *Cpu1_Main.* (.bss) + *(.bss_cpu1) + *(.bss_cpu1.*) + } > dsram1 + + /*DLMU1 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu1) + *(.lmudata_cpu1.*) + . = ALIGN(2); + } > cpu1_dlmu AT> pfls1 + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu1) + *(.lmubss_cpu1.*) + } > cpu1_dlmu +} +CORE_ID = CPU0 ; +SECTIONS +{ + /*DSRAM0 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc0.* (.data) + *Cpu0_Main.* (.data) + *(.data_cpu0) + *(.data_cpu0.*) + . = ALIGN(2); + } > dsram0 AT> pfls1 + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc0.* (.bss) + *Cpu0_Main.* (.bss) + *(.bss_cpu0) + *(.bss_cpu0.*) + } > dsram0 + + /*DLMU0 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu0) + *(.lmudata_cpu0.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls1 + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu0) + *(.lmubss_cpu0.*) + } > cpu0_dlmu +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata4) : + { + *(.a9sdata) + *(.a9sdata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls1 + + CORE_SEC(.sbss4) : + { + *(.a9sbss) + *(.a9sbss.*) + } > cpu0_dlmu + + _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; + __A9_MEM = _SMALL_DATA4_; +} + +/*Far Data Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.bss_noClear) (NOLOAD) : FLAGS(aw) + { + *(.bss.farDsprNoInit.cpu0.32bit) + *(.bss.farDsprNoInit.cpu0.16bit) + *(.bss.farDsprNoInit.cpu0.8bit) + } > default_ram + + CORE_SEC(.data) : FLAGS(awl) + { + *(.data.farDsprInit.cpu0.32bit) + *(.data.farDsprInit.cpu0.16bit) + *(.data.farDsprInit.cpu0.8bit) + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(2); + } > default_ram AT> pfls1 + + CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) + { + *(.bss.farDsprClearOnInit.cpu0.32bit) + *(.bss.farDsprClearOnInit.cpu0.16bit) + *(.bss.farDsprClearOnInit.cpu0.8bit) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + } > default_ram + + .heap : FLAGS(aw) + { + . = ALIGN(4); + __HEAP = .; + . += LCF_HEAP_SIZE; + __HEAP_END = .; + } > default_ram + + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata) + *(.lmudata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls1 + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss) + *(.lmubss.*) + } > cpu0_dlmu +} +/*Far Const Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU0; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc0.* (.rodata) + *Cpu0_Main.* (.rodata) + *(.rodata_cpu0) + *(.rodata_cpu0.*) + } > pfls1 +} + +CORE_ID = CPU1; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc1.* (.rodata) + *Cpu1_Main.* (.rodata) + *(.rodata_cpu1) + *(.rodata_cpu1.*) + } > pfls1 +} + +CORE_ID = CPU2; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc2.* (.rodata) + *Cpu2_Main.* (.rodata) + *(.rodata_cpu2) + *(.rodata_cpu2.*) + } > pfls1 +} + +/*Far Const Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *(.rodata.farConst.cpu0.32bit) + *(.rodata.farConst.cpu0.16bit) + *(.rodata.farConst.cpu0.8bit) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + /* + * Create the clear and copy tables that tell the startup code + * which memory areas to clear and to copy, respectively. + */ + . = ALIGN(4) ; + PROVIDE(__clear_table = .); + LONG(0 + ADDR(.CPU2.zbss)); LONG(SIZEOF(.CPU2.zbss)); + LONG(0 + ADDR(.CPU2.bss)); LONG(SIZEOF(.CPU2.bss)); + LONG(0 + ADDR(.CPU2.lmubss)); LONG(SIZEOF(.CPU2.lmubss)); + LONG(0 + ADDR(.CPU1.zbss)); LONG(SIZEOF(.CPU1.zbss)); + LONG(0 + ADDR(.CPU1.bss)); LONG(SIZEOF(.CPU1.bss)); + LONG(0 + ADDR(.CPU1.lmubss)); LONG(SIZEOF(.CPU1.lmubss)); + LONG(0 + ADDR(.CPU0.zbss)); LONG(SIZEOF(.CPU0.zbss)); + LONG(0 + ADDR(.CPU0.bss)); LONG(SIZEOF(.CPU0.bss)); + LONG(0 + ADDR(.CPU0.lmubss)); LONG(SIZEOF(.CPU0.lmubss)); + LONG(0 + ADDR(.zbss)); LONG(SIZEOF(.zbss)); + LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss)); + LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); + LONG(0 + ADDR(.lmubss)); LONG(SIZEOF(.lmubss)); + LONG(0 + ADDR(.sbss4)); LONG(SIZEOF(.sbss4)); + LONG(-1); LONG(-1); + PROVIDE(__clear_table_powerOn = .); + LONG(0 + ADDR(.zbss_powerOn)); LONG(SIZEOF(.zbss_powerOn)); + LONG(-1); LONG(-1); + PROVIDE(__copy_table = .); + LONG(LOADADDR(.CPU2.zdata)); LONG(0 + ADDR(.CPU2.zdata)); LONG(SIZEOF(.CPU2.zdata)); + LONG(LOADADDR(.CPU2.data)); LONG(0 + ADDR(.CPU2.data)); LONG(SIZEOF(.CPU2.data)); + LONG(LOADADDR(.CPU2.lmudata)); LONG(0 + ADDR(.CPU2.lmudata)); LONG(SIZEOF(.CPU2.lmudata)); + LONG(LOADADDR(.CPU1.zdata)); LONG(0 + ADDR(.CPU1.zdata)); LONG(SIZEOF(.CPU1.zdata)); + LONG(LOADADDR(.CPU1.data)); LONG(0 + ADDR(.CPU1.data)); LONG(SIZEOF(.CPU1.data)); + LONG(LOADADDR(.CPU1.lmudata)); LONG(0 + ADDR(.CPU1.lmudata)); LONG(SIZEOF(.CPU1.lmudata)); + LONG(LOADADDR(.CPU0.zdata)); LONG(0 + ADDR(.CPU0.zdata)); LONG(SIZEOF(.CPU0.zdata)); + LONG(LOADADDR(.CPU0.data)); LONG(0 + ADDR(.CPU0.data)); LONG(SIZEOF(.CPU0.data)); + LONG(LOADADDR(.CPU0.lmudata)); LONG(0 + ADDR(.CPU0.lmudata)); LONG(SIZEOF(.CPU0.lmudata)); + LONG(LOADADDR(.zdata)); LONG(0 + ADDR(.zdata)); LONG(SIZEOF(.zdata)); + LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata)); + LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); + LONG(LOADADDR(.lmudata)); LONG(0 + ADDR(.lmudata)); LONG(SIZEOF(.lmudata)); + LONG(LOADADDR(.sdata4)); LONG(0 + ADDR(.sdata4)); LONG(SIZEOF(.sdata4)); + LONG(LOADADDR(.CPU0.psram_text)); LONG(0 + ADDR(.CPU0.psram_text)); LONG(SIZEOF(.CPU0.psram_text)); + LONG(LOADADDR(.CPU1.psram_text)); LONG(0 + ADDR(.CPU1.psram_text)); LONG(SIZEOF(.CPU1.psram_text)); + LONG(LOADADDR(.CPU2.psram_text)); LONG(0 + ADDR(.CPU2.psram_text)); LONG(SIZEOF(.CPU2.psram_text)); + LONG(-1); LONG(-1); LONG(-1); + PROVIDE(__copy_table_powerOn = .) ; + LONG(LOADADDR(.zdata_powerOn)); LONG(0 + ADDR(.zdata_powerOn)); LONG(SIZEOF(.zdata_powerOn)); + LONG(-1); LONG(-1); LONG(-1); + . = ALIGN(8); + } > default_rom +} + +/*Code selections*/ +/*Code Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU0; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc0.*(.text) + *Cpu0_Main.*(.text) + *Ifx_Ssw_Tc0.*(.text.*) + *Cpu0_Main.*(.text.*) + *(.text_cpu0) + *(.text_cpu0.*) + } > pfls1 + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + .init : + { + PROVIDE(__init_start = .); + KEEP(*(.init)) + KEEP(*(.init*)) + PROVIDE(__init_end = .); + . = ALIGN(8); + + } > pfls1 + + .fini : + { + PROVIDE(__fini_start = .); + KEEP(*(.fini)) + KEEP(*(.fini*)) + PROVIDE(__fini_end = .); + . = ALIGN(8); + } > pfls1 + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu0) + *(.psram_text_cpu0.*) + *(.cpu0_psram) + *(.cpu0_psram.*) + *(.ramcode) /* wolfBoot RAM function section, for RAM_CODE=1 */ + *(.ramcode.*) /* future proof subsection matching for wolfBoot RAM function section, for RAM_CODE=1 */ + . = ALIGN(2); + } > psram0 AT> pfls1 +} + +CORE_ID = CPU1; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc1.*(.text) + *Cpu1_Main.*(.text) + *Ifx_Ssw_Tc1.*(.text.*) + *Cpu1_Main.*(.text.*) + *(.text_cpu1) + *(.text_cpu1.*) + } > pfls1 + + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu1) + *(.psram_text_cpu1.*) + *(.cpu1_psram) + *(.cpu1_psram.*) + . = ALIGN(2); + } > psram1 AT> pfls1 +} + +CORE_ID = CPU2; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc2.*(.text) + *Cpu2_Main.*(.text) + *Ifx_Ssw_Tc2.*(.text.*) + *Cpu2_Main.*(.text.*) + *(.text_cpu2) + *(.text_cpu2.*) + } > pfls1 + + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu2) + *(.psram_text_cpu2.*) + *(.cpu2_psram) + *(.cpu2_psram.*) + . = ALIGN(2); + } > psram2 AT> pfls1 +} + +/*Code Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + *(.text.fast.pfls.cpu0) + *(.text.slow.pfls.cpu0) + *(.text.5ms.pfls.cpu0) + *(.text.10ms.pfls.cpu0) + *(.text.callout.pfls.cpu0) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ + . = ALIGN(4); + } > default_rom + + /* + * C++ exception handling tables. NOTE: gcc emits .eh_frame + * sections when compiling C sources with debugging enabled (-g). + * If you can be sure that your final application consists + * exclusively of C objects (i.e., no C++ objects), you may use + * the -R option of the "strip" and "objcopy" utilities to remove + * the .eh_frame section from the executable. + */ + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > default_rom + + .eh_frame : + { + __EH_FRAME_BEGIN__ = . ; + KEEP (*(.eh_frame)) + __EH_FRAME_END__ = . ; + . = ALIGN(8); + } > default_rom + + .gcc_except_table : + { + __GCC_EXCEPT_TABLE_BEGIN__ = . ; + KEEP (*(.gcc_except_table)) + __GCC_EXCEPT_TABLE_END__ = . ; + . = ALIGN(8); + } > default_rom + + /* + * Constructors and destructors. + */ + .ctors : FLAGS(ar) + { + __CTOR_LIST__ = . ; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __CTOR_END__ = . ; + . = ALIGN(8); + } > default_rom + .dtors : FLAGS(ar) + { + __DTOR_LIST__ = . ; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ distructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* + * Code executed before calling main extra section for C++ distructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __DTOR_END__ = . ; + . = ALIGN(8); + } > default_rom + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the + * beginning of the section, so we begin them at 0. + */ + /* + * DWARF 1 + */ + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* + * GNU DWARF 1 extensions + */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* + * DWARF 1.1 and DWARF 2 + */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* + * DWARF 2 + */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_ranges 0 : { *(.debug_ranges) } + /* + * SGI/MIPS DWARF 2 extensions + */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* + * Optional sections that may only appear when relocating. + */ + /* + * Optional sections that may appear regardless of relocating. + */ + .version_info 0 : { *(.version_info) } + .boffs 0 : { KEEP (*(.boffs)) } +} + diff --git a/IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl b/IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl new file mode 100644 index 000000000..da9305ff4 --- /dev/null +++ b/IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl @@ -0,0 +1,918 @@ +/* Lcf_Tasking_Tricore_Tc.lsl + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#define LCF_CSA0_SIZE 8k +#define LCF_USTACK0_SIZE 2k +#define LCF_ISTACK0_SIZE 1k + +#define LCF_CSA1_SIZE 8k +#define LCF_USTACK1_SIZE 2k +#define LCF_ISTACK1_SIZE 1k + +#define LCF_CSA2_SIZE 8k +#define LCF_USTACK2_SIZE 2k +#define LCF_ISTACK2_SIZE 1k + +#define LCF_HEAP_SIZE 4k + +#define LCF_CPU0 0 +#define LCF_CPU1 1 +#define LCF_CPU2 2 + +/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ +#define LCF_DEFAULT_HOST LCF_CPU0 +/*#define LCF_DEFAULT_HOST LCF_CPU1*/ +/*#define LCF_DEFAULT_HOST LCF_CPU2*/ + +#define LCF_DSPR2_START 0x50000000 +#define LCF_DSPR2_SIZE 96k + +#define LCF_DSPR1_START 0x60000000 +#define LCF_DSPR1_SIZE 240k + +#define LCF_DSPR0_START 0x70000000 +#define LCF_DSPR0_SIZE 240k + +#define LCF_CSA2_OFFSET (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE) +#define LCF_ISTACK2_OFFSET (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE) +#define LCF_USTACK2_OFFSET (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE) + +#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE) +#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE) +#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE) + +#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE) +#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE) +#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE) + +#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP2_OFFSET (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE) + +#define LCF_INTVEC0_START 0x802FE000 +#define LCF_INTVEC1_START 0x805FC000 +#define LCF_INTVEC2_START 0x805FE000 + +#define LCF_TRAPVEC0_START 0x80000100 +#define LCF_TRAPVEC1_START 0x80300000 +#define LCF_TRAPVEC2_START 0x80300100 + +#define LCF_STARTPTR_CPU0 0x80000000 +#define LCF_STARTPTR_CPU1 0x80300200 +#define LCF_STARTPTR_CPU2 0x80300220 + +#define LCF_STARTPTR_NC_CPU0 0xA0000000 +#define LCF_STARTPTR_NC_CPU1 0xA0300200 +#define LCF_STARTPTR_NC_CPU2 0xA0300220 + +#define INTTAB0 (LCF_INTVEC0_START) +#define INTTAB1 (LCF_INTVEC1_START) +#define INTTAB2 (LCF_INTVEC2_START) +#define TRAPTAB0 (LCF_TRAPVEC0_START) +#define TRAPTAB1 (LCF_TRAPVEC1_START) +#define TRAPTAB2 (LCF_TRAPVEC2_START) + +#define RESET LCF_STARTPTR_NC_CPU0 + +#include "tc1v1_6_2.lsl" + +// Specify a multi-core processor environment (mpe) + +processor mpe +{ + derivative = tc37; +} + +derivative tc37 +{ + core tc0 + { + architecture = TC1V1.6.2; + space_id_offset = 100; // add 100 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc1 // core 1 TC16E + { + architecture = TC1V1.6.2; + space_id_offset = 200; // add 200 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc2 // core 2 TC16P + { + architecture = TC1V1.6.2; + space_id_offset = 300; // add 300 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core vtc + { + architecture = TC1V1.6.2; + import tc0; // add all address spaces of core tc0 to core vtc for linking and locating + import tc1; // tc1 + import tc2; // tc2 + } + + bus sri + { + mau = 8; + width = 32; + + // map shared addresses one-to-one to real cores and virtual cores + map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc2:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + } + + memory dsram2 // Data Scratch Pad Ram + { + mau = 8; + size = 96k; + type = ram; + map (dest=bus:tc2:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); + map (dest=bus:sri, dest_offset=0x50000000, size=96k); + } + + memory psram2 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc2:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x50100000, size=64k); + } + + memory dsram1 // Data Scratch Pad Ram + { + mau = 8; + size = 240k; + type = ram; + map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); + map (dest=bus:sri, dest_offset=0x60000000, size=240k); + } + + memory psram1 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x60100000, size=64k); + } + + memory dsram0 // Data Scratch Pad Ram + { + mau = 8; + size = 240k; + type = ram; + map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); + map (dest=bus:sri, dest_offset=0x70000000, size=240k); + } + + memory psram0 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x70100000, size=64k); + } + + memory pfls0 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80000000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=3M); + } + + memory pfls1 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80300000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0300000, reserved, size=3M); + } + + memory dfls0 + { + mau = 8; + size = 256K; + type = reserved nvram; + map (dest=bus:sri, dest_offset=0xaf000000, size=256K); + } + + memory ucb + { + mau = 8; + size = 24k; + type = rom; + map (dest=bus:sri, dest_offset=0xaf400000, reserved, size=24k); + } + + memory cpu0_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90000000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=64k); + } + + memory cpu1_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90010000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0010000, reserved, size=64k); + } + + memory cpu2_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90020000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0020000, reserved, size=64k); + } + +#if (__VERSION__ >= 6003) + section_setup :vtc:linear + { + heap "heap" (min_size = (1k), fixed, align = 8); + } +#endif + + section_setup :vtc:linear + { + start_address + ( + symbol = "_START" + ); + } + + section_setup :vtc:linear + { + stack "ustack_tc0" (min_size = 1k, fixed, align = 8); + stack "istack_tc0" (min_size = 1k, fixed, align = 8); + stack "ustack_tc1" (min_size = 1k, fixed, align = 8); + stack "istack_tc1" (min_size = 1k, fixed, align = 8); + stack "ustack_tc2" (min_size = 1k, fixed, align = 8); + stack "istack_tc2" (min_size = 1k, fixed, align = 8); + } + + /*Section setup for the copy table*/ + section_setup :vtc:linear + { + copytable + ( + align = 4, + dest = linear, + table + { + symbol = "_lc_ub_table_tc0"; + space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa; + }, + table + { + symbol = "_lc_ub_table_tc1"; + space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa; + }, + table + { + symbol = "_lc_ub_table_tc2"; + space = :tc2:linear, :tc2:abs24, :tc2:abs18, :tc2:csa; + } + ); + } + + /*Sections located at absolute fixed address*/ + + section_layout :vtc:linear + { + /*Fixed memory Allocations for stack memory and CSA*/ + group (ordered) + { + group ustack2(align = 8, run_addr = mem:dsram2[LCF_USTACK2_OFFSET]) + { + stack "ustack_tc2" (size = LCF_USTACK2_SIZE); + } + "__USTACK2":= sizeof(group:ustack2) > 0 ? "_lc_ue_ustack_tc2" : 0; + "__USTACK2_END"="_lc_gb_ustack2"; + + group istack2(align = 8, run_addr = mem:dsram2[LCF_ISTACK2_OFFSET]) + { + stack "istack_tc2" (size = LCF_ISTACK2_SIZE); + } + "__ISTACK2":= sizeof(group:istack2) > 0 ? "_lc_ue_istack_tc2" : 0; + "__ISTACK2_END"="_lc_gb_istack2"; + + group (align = 64, attributes=rw, run_addr=mem:dsram2[LCF_CSA2_OFFSET]) + reserved "csa_tc2" (size = LCF_CSA2_SIZE); + "__CSA2":= "_lc_ub_csa_tc2"; + "__CSA2_END":= "_lc_ue_csa_tc2"; + } + group (ordered) + { + group ustack1(align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET]) + { + stack "ustack_tc1" (size = LCF_USTACK1_SIZE); + } + "__USTACK1":= sizeof(group:ustack1) > 0 ? "_lc_ue_ustack_tc1" : 0; + "__USTACK1_END"="_lc_gb_ustack1"; + + group istack1(align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET]) + { + stack "istack_tc1" (size = LCF_ISTACK1_SIZE); + } + "__ISTACK1":= sizeof(group:istack1) > 0 ? "_lc_ue_istack_tc1" : 0; + "__ISTACK1_END"="_lc_gb_istack1"; + + group (align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET]) + reserved "csa_tc1" (size = LCF_CSA1_SIZE); + "__CSA1":= "_lc_ub_csa_tc1"; + "__CSA1_END":= "_lc_ue_csa_tc1"; + } + group (ordered) + { + group ustack0(align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET]) + { + stack "ustack_tc0" (size = LCF_USTACK0_SIZE); + } + "__USTACK0":= sizeof(group:ustack0) > 0 ? "_lc_ue_ustack_tc0" : 0; + "__USTACK0_END"="_lc_gb_ustack0"; + + group istack0(align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET]) + { + stack "istack_tc0" (size = LCF_ISTACK0_SIZE); + } + "__ISTACK0":= sizeof(group:istack0) > 0 ? "_lc_ue_istack_tc0" : 0; + "__ISTACK0_END"="_lc_gb_istack0"; + + group (align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET]) + reserved "csa_tc0" (size = LCF_CSA0_SIZE); + "__CSA0":= "_lc_ub_csa_tc0"; + "__CSA0_END":= "_lc_ue_csa_tc0"; + } + + /*Fixed memory Allocations for _START*/ + group (ordered) + { + group reset (run_addr=RESET) + { + section "reset" ( size = 0x20, fill = 0x0800, attributes = r ) + { + select ".text.start"; + } + } + group interface_const (run_addr=mem:pfls0[0x0020]) + { + select "*.interface_const"; + } + "__IF_CONST" := addressof(group:interface_const); + "__START0" := LCF_STARTPTR_NC_CPU0; + "__START1" := LCF_STARTPTR_NC_CPU1; + "__START2" := LCF_STARTPTR_NC_CPU2; + } + + /*Fixed memory Allocations for Trap Vector Table*/ + group (ordered) + { + group trapvec_tc0 (align = 8, run_addr=LCF_TRAPVEC0_START) + { + section "trapvec_tc0" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu0*)"; + } + } + group trapvec_tc1 (align = 8, run_addr=LCF_TRAPVEC1_START) + { + section "trapvec_tc1" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu1*)"; + } + } + group trapvec_tc2 (align = 8, run_addr=LCF_TRAPVEC2_START) + { + section "trapvec_tc2" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu2*)"; + } + } + "__TRAPTAB_CPU0" := TRAPTAB0; + "__TRAPTAB_CPU1" := TRAPTAB1; + "__TRAPTAB_CPU2" := TRAPTAB2; + } + + /*Fixed memory Allocations for Start up code*/ + group (ordered) + { + group start_tc0 (run_addr=LCF_STARTPTR_NC_CPU0) + { + select "(.text.start_cpu0*)"; + } + group start_tc1 (run_addr=LCF_STARTPTR_NC_CPU1) + { + section "start_tc1" (size=0x20, attributes=rx, fill=0) + { + select "(.text.start_cpu1*)"; + } + } + group start_tc2 (run_addr=LCF_STARTPTR_NC_CPU2) + { + select "(.text.start_cpu2*)"; + } + "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 0; + "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 0; + } + + /*Fixed memory Allocations for Interrupt Vector Table*/ + group (ordered) + { + group int_tab_tc0 (ordered) + { +# include "inttab0.lsl" + } + group int_tab_tc1 (ordered) + { +# include "inttab1.lsl" + } + group int_tab_tc2 (ordered) + { +# include "inttab2.lsl" + } + "_lc_u_int_tab" = (LCF_INTVEC0_START); + "__INTTAB_CPU0" = (LCF_INTVEC0_START); + "__INTTAB_CPU1" = (LCF_INTVEC1_START); + "__INTTAB_CPU2" = (LCF_INTVEC2_START); + } + + /*Fixed memory Allocations for BMHD*/ + group (ordered) + { + group bmh_0_orig (run_addr=mem:ucb[0x0000]) + { + select ".rodata.bmhd_0_orig"; + } + group bmh_1_orig (run_addr=mem:ucb[0x0200]) + { + select ".rodata.bmhd_1_orig"; + } + group bmh_2_orig (run_addr=mem:ucb[0x0400]) + { + select ".rodata.bmhd_2_orig"; + } + group bmh_3_orig (run_addr=mem:ucb[0x0600]) + { + select ".rodata.bmhd_3_orig"; + } + group bmh_blank (run_addr=mem:ucb[0x0800]) + { + } + group bmh_0_copy (run_addr=mem:ucb[0x1000]) + { + select ".rodata.bmhd_0_copy"; + } + group bmh_1_copy (run_addr=mem:ucb[0x1200]) + { + select ".rodata.bmhd_1_copy"; + } + group bmh_2_copy (run_addr=mem:ucb[0x1400]) + { + select ".rodata.bmhd_2_copy"; + } + group bmh_3_copy (run_addr=mem:ucb[0x1600]) + { + select ".rodata.bmhd_3_copy"; + } + } + } + + /*Near Abbsolute Addressable Data Sections*/ + section_layout :vtc:abs18 + { + /*Near Absolute Data, selectable with patterns and user defined sections*/ + group + { + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) + { + select "(.zdata.zdata_cpu2|.zdata.zdata_cpu2.*)"; + select "(.zbss.zbss_cpu2|.zbss.zbss_cpu2.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) + { + select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1.*)"; + select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) + { + select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0.*)"; + select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0.*)"; + } + + group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) + { + select "(.zdata.zlmudata|.zdata.zlmudata.*)"; + select "(.zbss.zlmubss|.zbss.zlmubss.*)"; + } + } + + /*Near Absolute Data, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + group zdata_mcal(attributes=rw) + { + select ".zdata.dsprInit.cpu0.32bit"; + select ".zdata.dsprInit.cpu0.16bit"; + select ".zdata.dsprInit.cpu0.8bit"; + } + + group zdata_powerOn(attributes=rw) + { + select ".zdata.dsprPowerOnInit.cpu0.32bit"; + select ".zdata.dsprPowerOnInit.cpu0.16bit"; + select ".zdata.dsprPowerOnInit.cpu0.8bit"; + } + + group zbss_mcal(attributes=rw) + { + select ".zbss.dsprClearOnInit.cpu0.32bit"; + select ".zbss.dsprClearOnInit.cpu0.16bit"; + select ".zbss.dsprClearOnInit.cpu0.8bit"; + } + + group zbss_noClear(attributes=rw) + { + select ".zbss.dsprNoInit.cpu0.32bit"; + select ".zbss.dsprNoInit.cpu0.16bit"; + select ".zbss.dsprNoInit.cpu0.8bit"; + } + + group zbss_powerOn(attributes=rw) + { + select ".zbss.dsprPowerOnClear.cpu0.32bit"; + select ".zbss.dsprPowerOnClear.cpu0.16bit"; + select ".zbss.dsprPowerOnClear.cpu0.8bit"; + } + + group zdata(attributes=rw) + { + select "(.zdata|.zdata.*)"; + select "(.zbss|.zbss.*)"; + } + } + + /*Near Absolute Const, selectable with patterns and user defined sections*/ + group + { + group (ordered, align = 4, contiguous, run_addr=mem:pfls0) + { + select ".zrodata.Ifx_Ssw_Tc0.*"; + select ".zrodata.Ifx_Ssw_Tc1.*"; + select ".zrodata.Ifx_Ssw_Tc2.*"; + select ".zrodata.Cpu0_Main.*"; + select ".zrodata.Cpu1_Main.*"; + select ".zrodata.Cpu2_Main.*"; + + /*Near Absolute Const, selectable by toolchain*/ + select ".zrodata.const.cpu0.32bit"; + select ".zrodata.const.cpu0.16bit"; + select ".zrodata.const.cpu0.8bit"; + select ".zrodata.config.cpu0.32bit"; + select ".zrodata.config.cpu0.16bit"; + select ".zrodata.config.cpu0.8bit"; + select "(.zrodata|.zrodata.*)"; + } + } + } + + /*Relative A0/A1/A8/A9 Addressable Sections*/ + section_layout :vtc:linear + { + /*Relative A0 Addressable Data, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + select "(.data_a0.sdata|.data_a0.sdata.*)"; + select "(.bss_a0.sbss|.bss_a0.sbss.*)"; + } + "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; + "__A0_MEM" = "_SMALL_DATA_"; + + /*Relative A1 Addressable Const, selectable by toolchain*/ + /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a1 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a1 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a1 (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select "(.rodata_a1.srodata|.rodata_a1.srodata.*)"; + select "(.ldata|.ldata.*)"; + } + "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; + "__A1_MEM" = "_LITERAL_DATA_"; + + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + group a9 (ordered, align = 4, run_addr=mem:cpu0_dlmu) + { + select "(.data_a9.a9sdata|.data_a9.a9sdata.*)"; + select "(.bss_a9.a9sbss|.bss_a9.a9sbss.*)"; + } + "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; + "__A9_MEM" = "_A9_DATA_"; + + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a8 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a8 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a8 (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select "(.rodata_a8.a8srodata|.rodata_a8.a8srodata.*)"; + } + "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; + "__A8_MEM" = "_A8_DATA_"; + } + + /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ + section_layout :vtc:linear + { + /*Far Data Sections, selectable with patterns and user defined sections*/ + group + { + /*DSRAM sections*/ + group + { + group (ordered, attributes=rw, run_addr=mem:dsram2) + { + select ".data.Ifx_Ssw_Tc2.*"; + select ".data.Cpu2_Main.*"; + select "(.data.data_cpu2|.data.data_cpu2.*)"; + select ".bss.Ifx_Ssw_Tc2.*"; + select ".bss.Cpu2_Main.*"; + select "(.bss.bss_cpu2|.bss.bss_cpu2.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram1) + { + select ".data.Ifx_Ssw_Tc1.*"; + select ".data.Cpu1_Main.*"; + select "(.data.data_cpu1|.data.data_cpu1.*)"; + select ".bss.Ifx_Ssw_Tc1.*"; + select ".bss.Cpu1_Main.*"; + select "(.bss.bss_cpu1|.bss.bss_cpu1.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram0) + { + select ".data.Ifx_Ssw_Tc0.*"; + select ".data.Cpu0_Main.*"; + select "(.data.data_cpu0|.data.data_cpu0.*)"; + select ".bss.Ifx_Ssw_Tc0.*"; + select ".bss.Cpu0_Main.*"; + select "(.bss.bss_cpu0|.bss.bss_cpu0.*)"; + } + } + + /*LMU Data sections*/ + group + { + group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) + { + select "(.data.lmudata_cpu0|.data.lmudata_cpu0.*)"; + select "(.bss.lmubss_cpu0|.bss.lmubss_cpu0.*)"; + select "(.data.lmudata|.data.lmudata.*)"; + select "(.bss.lmubss|.bss.lmubss.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu1_dlmu) + { + select "(.data.lmudata_cpu1|.data.lmudata_cpu1.*)"; + select "(.bss.lmubss_cpu1|.bss.lmubss_cpu1.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu2_dlmu) + { + select "(.data.lmudata_cpu2|.data.lmudata_cpu2.*)"; + select "(.bss.lmubss_cpu2|.bss.lmubss_cpu2.*)"; + } + } + } + + /*Far Data Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + group data_mcal(attributes=rw) + { + select ".data.farDsprInit.cpu0.32bit"; + select ".data.farDsprInit.cpu0.16bit"; + select ".data.farDsprInit.cpu0.8bit"; + } + + group bss_mcal(attributes=rw) + { + select ".bss.farDsprClearOnInit.cpu0.32bit"; + select ".bss.farDsprClearOnInit.cpu0.16bit"; + select ".bss.farDsprClearOnInit.cpu0.8bit"; + } + + group bss_noInit(attributes=rw) + { + select ".bss.farDsprNoInit.cpu0.32bit"; + select ".bss.farDsprNoInit.cpu0.16bit"; + select ".bss.farDsprNoInit.cpu0.8bit"; + } + + group data(attributes=rw) + { + select "(.data|.data.*)"; + select "(.bss|.bss.*)"; + } + } + + /*Heap allocation*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, align = 4, run_addr = mem:dsram2[LCF_HEAP2_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET]) +# endif + { + heap "heap" (size = LCF_HEAP_SIZE); + } + + /*Far Const Sections, selectable with patterns and user defined sections*/ + group + { + group (ordered, align = 4, run_addr=mem:pfls0) + { + select ".rodata.Ifx_Ssw_Tc0.*"; + select ".rodata.Cpu0_Main.*"; + select "(.rodata.rodata_cpu0|.rodata.rodata_cpu0.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".rodata.Cpu1_Main.*"; + select ".rodata.Ifx_Ssw_Tc1.*"; + select "(.rodata.rodata_cpu1|.rodata.rodata_cpu1.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".rodata.Ifx_Ssw_Tc2.*"; + select ".rodata.Cpu2_Main.*"; + select "(.rodata.rodata_cpu2|.rodata.rodata_cpu2.*)"; + } + } + + /*Far Const Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select ".rodata.farConst.cpu0.32bit"; + select ".rodata.farConst.cpu0.16bit"; + select ".rodata.farConst.cpu0.8bit"; + select "(.rodata|.rodata.*)"; + } + } + + /* PSRAM Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Program Scratchpad Sections*/ + group + { + group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0) + { + select "(.text.cpu0_psram|.text.cpu0_psram.*)"; + select "(.text.psram_text_cpu0|.text.psram_text_cpu0.*)"; + } + group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1) + { + select "(.text.cpu1_psram|.text.cpu1_psram.*)"; + select "(.text.psram_text_cpu1|.text.psram_text_cpu1.*)"; + } + group code_psram2 (ordered, attributes=rwx, copy, run_addr=mem:psram2) + { + select "(.text.cpu2_psram|.text.cpu2_psram.*)"; + select "(.text.psram_text_cpu2|.text.psram_text_cpu2.*)"; + } + } + } + } + + /* FLS Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Cpu specific PFLASH Sections*/ + group + { + group (ordered, align = 4, run_addr=mem:pfls0) + { + select ".text.Ifx_Ssw_Tc0.*"; + select ".text.Cpu0_Main.*"; + select ".text.CompilerTasking.Ifx_C_Init"; + select "(.text.text_cpu0|.text.text_cpu0.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".text.Ifx_Ssw_Tc1.*"; + select ".text.Cpu1_Main.*"; + select "(.text.text_cpu1|.text.text_cpu1.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".text.Ifx_Ssw_Tc2.*"; + select ".text.Cpu2_Main.*"; + select "(.text.text_cpu2|.text.text_cpu2.*)"; + } + } + } + + /*Code Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, run_addr=mem:pfls0) +# endif + { + select ".text.fast.pfls.cpu0"; + select ".text.slow.pfls.cpu0"; + select ".text.5ms.pfls.cpu0"; + select ".text.10ms.pfls.cpu0"; + select ".text.callout.pfls.cpu0"; + select "(.text|.text.*)"; + } + } +} diff --git a/IDE/AURIX/wolfBoot-tc3xx/.cproject b/IDE/AURIX/wolfBoot-tc3xx/.cproject new file mode 100644 index 000000000..98356a3ca --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx/.cproject @@ -0,0 +1,778 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/IDE/AURIX/wolfBoot-tc3xx/.project b/IDE/AURIX/wolfBoot-tc3xx/.project new file mode 100644 index 000000000..0086d2417 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx/.project @@ -0,0 +1,90 @@ + + + wolfBoot-tc3xx + + + + + + com.infineon.aurix.buildsystem.builders.booster + full,incremental, + + + + + com.infineon.aurix.buildsystem.builders.autodiscovery + full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.infineon.aurix.buildsystem.aurixnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Configurations + 2 + SDK_CONFIGURATION_DIR + + + Libraries + 2 + SDK_DIR + + + wolfBoot + 2 + virtual:/virtual + + + wolfBoot/hal + 2 + WOLFBOOT_ROOT/hal + + + wolfBoot/include + 2 + WOLFBOOT_ROOT/include + + + wolfBoot/src + 2 + WOLFBOOT_ROOT/src + + + wolfBoot/wolfssl + 2 + WOLFBOOT_ROOT/lib/wolfssl + + + + + SDK_CONFIGURATION_DIR + $%7BPARENT-1-PROJECT_LOC%7D/Configurations + + + SDK_DIR + $%7BPARENT-1-PROJECT_LOC%7D/SDK + + + WOLFBOOT_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/IDE/AURIX/wolfBoot-tc3xx/.settings/language.settings.xml b/IDE/AURIX/wolfBoot-tc3xx/.settings/language.settings.xml new file mode 100644 index 000000000..8f00f9815 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx/.settings/language.settings.xml @@ -0,0 +1,41 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/IDE/AURIX/wolfBoot-tc3xx/Cpu0_Main.c b/IDE/AURIX/wolfBoot-tc3xx/Cpu0_Main.c new file mode 100644 index 000000000..26a94e5b4 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx/Cpu0_Main.c @@ -0,0 +1,47 @@ +/* Cpu0_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "IfxCpu.h" +#include "IfxScuWdt.h" +#include "Ifx_Types.h" + +IFX_ALIGN(4) IfxCpu_syncEvent g_cpuSyncEvent = 0; + +extern void loader_main(void); + +void core0_main(void) +{ + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!! + * Enable the watchdogs and service them periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + /* invoke wolfBoot */ + loader_main(); + + while (1) { + } +} diff --git a/IDE/AURIX/wolfBoot-tc3xx/Cpu1_Main.c b/IDE/AURIX/wolfBoot-tc3xx/Cpu1_Main.c new file mode 100644 index 000000000..4a353f526 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx/Cpu1_Main.c @@ -0,0 +1,42 @@ +/* Cpu1_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "Ifx_Types.h" +#include "IfxCpu.h" +#include "IfxScuWdt.h" + +extern IfxCpu_syncEvent g_cpuSyncEvent; + +void core1_main(void) +{ + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG1 IS DISABLED HERE!! + * Enable the watchdog and service it periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + while(1) + { + } +} diff --git a/IDE/AURIX/wolfBoot-tc3xx/Cpu2_Main.c b/IDE/AURIX/wolfBoot-tc3xx/Cpu2_Main.c new file mode 100644 index 000000000..09d82c438 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx/Cpu2_Main.c @@ -0,0 +1,42 @@ +/* Cpu2_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "Ifx_Types.h" +#include "IfxCpu.h" +#include "IfxScuWdt.h" + +extern IfxCpu_syncEvent g_cpuSyncEvent; + +void core2_main(void) +{ + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG2 IS DISABLED HERE!! + * Enable the watchdog and service it periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + while(1) + { + } +} diff --git a/IDE/AURIX/wolfBoot-tc3xx/Lcf_Gnuc_Tricore_Tc.lsl b/IDE/AURIX/wolfBoot-tc3xx/Lcf_Gnuc_Tricore_Tc.lsl new file mode 100644 index 000000000..7d317d5f9 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx/Lcf_Gnuc_Tricore_Tc.lsl @@ -0,0 +1,1781 @@ +/* Lcf_Gnuc_Tricore_Tc.lsl + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH(tricore) +ENTRY(_START) + +__TRICORE_DERIVATE_MEMORY_MAP__ = 0x380; + +LCF_CSA0_SIZE = 8k; +LCF_USTACK0_SIZE = 2k; +LCF_ISTACK0_SIZE = 1k; + +LCF_CSA1_SIZE = 8k; +LCF_USTACK1_SIZE = 2k; +LCF_ISTACK1_SIZE = 1k; + +LCF_CSA2_SIZE = 8k; +LCF_USTACK2_SIZE = 2k; +LCF_ISTACK2_SIZE = 1k; + +LCF_HEAP_SIZE = 4k; + +LCF_DSPR2_START = 0x50000000; +LCF_DSPR2_SIZE = 96k; + +LCF_DSPR1_START = 0x60000000; +LCF_DSPR1_SIZE = 240k; + +LCF_DSPR0_START = 0x70000000; +LCF_DSPR0_SIZE = 240k; + +LCF_CSA2_OFFSET = (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE); +LCF_ISTACK2_OFFSET = (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE); +LCF_USTACK2_OFFSET = (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE); + +LCF_CSA1_OFFSET = (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE); +LCF_ISTACK1_OFFSET = (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE); +LCF_USTACK1_OFFSET = (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE); + +LCF_CSA0_OFFSET = (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE); +LCF_ISTACK0_OFFSET = (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE); +LCF_USTACK0_OFFSET = (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE); + +LCF_HEAP0_OFFSET = (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE); +LCF_HEAP1_OFFSET = (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE); +LCF_HEAP2_OFFSET = (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE); + +LCF_INTVEC0_START = 0x80000400; +LCF_INTVEC1_START = 0x80002400; +LCF_INTVEC2_START = 0x80004400; + +__INTTAB_CPU0 = LCF_INTVEC0_START; +__INTTAB_CPU1 = LCF_INTVEC1_START; +__INTTAB_CPU2 = LCF_INTVEC2_START; + +LCF_TRAPVEC0_START = 0x80000100; +LCF_TRAPVEC1_START = 0x80000200; +LCF_TRAPVEC2_START = 0x80000300; + +LCF_STARTPTR_CPU0 = 0x80000000; +LCF_STARTPTR_CPU1 = 0x80006400; /* after last intvec */ +LCF_STARTPTR_CPU2 = 0x80006420; + +LCF_STARTPTR_NC_CPU0 = 0xA0000000; +LCF_STARTPTR_NC_CPU1 = 0xA0006400; /* after last intvec */ +LCF_STARTPTR_NC_CPU2 = 0xA0006420; + +RESET = LCF_STARTPTR_NC_CPU0; + +MEMORY +{ + dsram2_local (w!xp): org = 0xd0000000, len = 96K + dsram2 (w!xp): org = 0x50000000, len = 96K + psram2 (w!xp): org = 0x50100000, len = 64K + + dsram1_local (w!xp): org = 0xd0000000, len = 240K + dsram1 (w!xp): org = 0x60000000, len = 240K + psram1 (w!xp): org = 0x60100000, len = 64K + + dsram0_local (w!xp): org = 0xd0000000, len = 240K + dsram0 (w!xp): org = 0x70000000, len = 240K + psram0 (w!xp): org = 0x70100000, len = 64K + + psram_local (w!xp): org = 0xc0000000, len = 64K + + pfls0 (rx!p): org = 0x80000000, len = 128K /* 0x2_0000 : wolfBoot */ + pfls0_nc (rx!p): org = 0xa0000000, len = 128K /* 0x2_0000 : wolfBoot */ + pfls0_swap (rwx!p): org = 0x80020000, len = 16K /* 0x4_000 : Swap sector */ + + /* reserved for wolfBoot BOOT partition */ + pfls1_boot (rwx!p): org = 0x80300000, len = 0x180000 /* 1.5MiB */ + pfls1_boot_nc (rwx!p): org = 0xa0300000, len = 0x180000 /* 1.5MiB */ + + /* reserved for wolfBoot UPDATE partition */ + pfls1_update (rwx!p): org = 0x80480000, len = 0x180000 /* 1.5MiB */ + pfls1_update_nc (rwx!p): org = 0xa0480000, len = 0x180000 /* 1.5MiB */ + + dfls0 (rx!p): org = 0xaf000000, len = 256K + + ucb (rx!p): org = 0xaf400000, len = 24K + + cpu0_dlmu (w!xp): org = 0x90000000, len = 64K + cpu0_dlmu_nc (w!xp): org = 0xb0000000, len = 64K + + cpu1_dlmu (w!xp): org = 0x90010000, len = 64K + cpu1_dlmu_nc (w!xp): org = 0xb0010000, len = 64K + + cpu2_dlmu (w!xp): org = 0x90020000, len = 64K + cpu2_dlmu_nc (w!xp): org = 0xb0020000, len = 64K +} + +/* map local memory address to a global address */ +REGION_MAP( CPU0 , ORIGIN(dsram0_local), LENGTH(dsram0_local), ORIGIN(dsram0)) +REGION_MAP( CPU1 , ORIGIN(dsram1_local), LENGTH(dsram1_local), ORIGIN(dsram1)) +REGION_MAP( CPU2 , ORIGIN(dsram2_local), LENGTH(dsram2_local), ORIGIN(dsram2)) +/* map cached and non cached addresses */ +REGION_MIRROR("pfls0", "pfls0_nc") +REGION_MIRROR("cpu0_dlmu", "cpu0_dlmu_nc") +REGION_MIRROR("cpu1_dlmu", "cpu1_dlmu_nc") +REGION_MIRROR("cpu2_dlmu", "cpu2_dlmu_nc") + +/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ + +REGION_ALIAS( default_ram , dsram0) +REGION_ALIAS( default_rom , pfls0) + +/* +REGION_ALIAS( default_ram , dsram1) +REGION_ALIAS( default_rom , pfls1) +*/ +/* +REGION_ALIAS( default_ram , dsram2) +*/ + +/*Sections located at absolute fixed address*/ + /*Fixed memory Allocations for stack memory and CSA*/ + CORE_ID = CPU2; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR2_START + LCF_USTACK2_OFFSET): + { PROVIDE(__USTACK2_END = .); . = . + LCF_USTACK2_SIZE; PROVIDE(__USTACK2 = .); } + + CORE_SEC(.istack) (LCF_DSPR2_START + LCF_ISTACK2_OFFSET): + { PROVIDE(__ISTACK2_END = .); . = . + LCF_ISTACK2_SIZE; PROVIDE(__ISTACK2 = .); } + + CORE_SEC(.csa) (LCF_DSPR2_START + LCF_CSA2_OFFSET): + { PROVIDE(__CSA2 = .); . = . + LCF_CSA2_SIZE; PROVIDE(__CSA2_END = .); } + } + + CORE_ID = CPU1; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR1_START + LCF_USTACK1_OFFSET): + { PROVIDE(__USTACK1_END = .); . = . + LCF_USTACK1_SIZE; PROVIDE(__USTACK1 = .); } + + CORE_SEC(.istack) (LCF_DSPR1_START + LCF_ISTACK1_OFFSET): + { PROVIDE(__ISTACK1_END = .); . = . + LCF_ISTACK1_SIZE; PROVIDE(__ISTACK1 = .); } + + CORE_SEC(.csa) (LCF_DSPR1_START + LCF_CSA1_OFFSET): + { PROVIDE(__CSA1 = .); . = . + LCF_CSA1_SIZE; PROVIDE(__CSA1_END = .); } + } + + CORE_ID = CPU0; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR0_START + LCF_USTACK0_OFFSET): + { PROVIDE(__USTACK0_END = .); . = . + LCF_USTACK0_SIZE; PROVIDE(__USTACK0 = .); } + + CORE_SEC(.istack) (LCF_DSPR0_START + LCF_ISTACK0_OFFSET): + { PROVIDE(__ISTACK0_END = .); . = . + LCF_ISTACK0_SIZE; PROVIDE(__ISTACK0 = .); } + + CORE_SEC(.csa) (LCF_DSPR0_START + LCF_CSA0_OFFSET): + { PROVIDE(__CSA0 = .); . = . + LCF_CSA0_SIZE; PROVIDE(__CSA0_END = .); } + } + + /*Fixed memory Allocations for _START*/ + CORE_ID = GLOBAL ; + SECTIONS + { + .start_tc0 (LCF_STARTPTR_NC_CPU0) : FLAGS(rxl) + { + PROVIDE(_start_text = .); /* needed by wolfBoot for self update when -DRAM_CODE */ + KEEP (*(.start)); + } > pfls0_nc + .interface_const (0x80000020) : { __IF_CONST = .; KEEP (*(.interface_const)); } > pfls0 + PROVIDE(__START0 = LCF_STARTPTR_NC_CPU0); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); /* Not used */ + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 0); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 0); + } + + /*Fixed memory Allocations for Trap Vector Table*/ + CORE_ID = GLOBAL; + SECTIONS + { + .traptab_tc0 (LCF_TRAPVEC0_START) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU0 = .); + KEEP (*(.traptab_cpu0)); + PROVIDE(__TRAPTAB_CPU0_END = .); + } > pfls0 + + .traptab_tc1 (__TRAPTAB_CPU0_END) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU1 = .); + KEEP (*(.traptab_cpu1)); + PROVIDE(__TRAPTAB_CPU1_END = .); + } > pfls0 + + .traptab_tc2 (__TRAPTAB_CPU1_END) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU2 = .); + KEEP (*(.traptab_cpu2)); + PROVIDE(__TRAPTAB_CPU2_END = .); + } > pfls0 + } + + /*Fixed memory Allocations for _START1 to 2*/ + CORE_ID = GLOBAL ; + SECTIONS + { + .start_tc1 (LCF_STARTPTR_NC_CPU1) : FLAGS(rxl) { KEEP (*(.start_cpu1)); } > pfls0_nc + .start_tc2 (LCF_STARTPTR_NC_CPU2) : FLAGS(rxl) { KEEP (*(.start_cpu2)); } > pfls0_nc + PROVIDE(__START1 = LCF_STARTPTR_NC_CPU1); + PROVIDE(__START2 = LCF_STARTPTR_NC_CPU2); + } + + /*Fixed memory Allocations for Interrupt Vector Table*/ + SECTIONS + { + /*CPU0 Interrupt Vector Table*/ + .inttab_tc0_000 (__INTTAB_CPU0 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_0 )); } + .inttab_tc0_001 (__INTTAB_CPU0 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_1 )); } + .inttab_tc0_002 (__INTTAB_CPU0 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_2 )); } + .inttab_tc0_003 (__INTTAB_CPU0 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_3 )); } + .inttab_tc0_004 (__INTTAB_CPU0 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_4 )); } + .inttab_tc0_005 (__INTTAB_CPU0 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_5 )); } + .inttab_tc0_006 (__INTTAB_CPU0 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_6 )); } + .inttab_tc0_007 (__INTTAB_CPU0 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_7 )); } + .inttab_tc0_008 (__INTTAB_CPU0 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_8 )); } + .inttab_tc0_009 (__INTTAB_CPU0 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_9 )); } + .inttab_tc0_00A (__INTTAB_CPU0 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_10 )); } + .inttab_tc0_00B (__INTTAB_CPU0 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_11 )); } + .inttab_tc0_00C (__INTTAB_CPU0 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_12 )); } + .inttab_tc0_00D (__INTTAB_CPU0 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_13 )); } + .inttab_tc0_00E (__INTTAB_CPU0 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_14 )); } + .inttab_tc0_00F (__INTTAB_CPU0 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_15 )); } + .inttab_tc0_010 (__INTTAB_CPU0 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_16 )); } + .inttab_tc0_011 (__INTTAB_CPU0 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_17 )); } + .inttab_tc0_012 (__INTTAB_CPU0 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_18 )); } + .inttab_tc0_013 (__INTTAB_CPU0 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_19 )); } + .inttab_tc0_014 (__INTTAB_CPU0 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_20 )); } + .inttab_tc0_015 (__INTTAB_CPU0 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_21 )); } + .inttab_tc0_016 (__INTTAB_CPU0 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_22 )); } + .inttab_tc0_017 (__INTTAB_CPU0 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_23 )); } + .inttab_tc0_018 (__INTTAB_CPU0 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_24 )); } + .inttab_tc0_019 (__INTTAB_CPU0 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_25 )); } + .inttab_tc0_01A (__INTTAB_CPU0 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_26 )); } + .inttab_tc0_01B (__INTTAB_CPU0 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_27 )); } + .inttab_tc0_01C (__INTTAB_CPU0 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_28 )); } + .inttab_tc0_01D (__INTTAB_CPU0 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_29 )); } + .inttab_tc0_01E (__INTTAB_CPU0 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_30 )); } + .inttab_tc0_01F (__INTTAB_CPU0 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_31 )); } + .inttab_tc0_020 (__INTTAB_CPU0 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_32 )); } + .inttab_tc0_021 (__INTTAB_CPU0 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_33 )); } + .inttab_tc0_022 (__INTTAB_CPU0 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_34 )); } + .inttab_tc0_023 (__INTTAB_CPU0 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_35 )); } + .inttab_tc0_024 (__INTTAB_CPU0 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_36 )); } + .inttab_tc0_025 (__INTTAB_CPU0 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_37 )); } + .inttab_tc0_026 (__INTTAB_CPU0 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_38 )); } + .inttab_tc0_027 (__INTTAB_CPU0 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_39 )); } + .inttab_tc0_028 (__INTTAB_CPU0 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_40 )); } + .inttab_tc0_029 (__INTTAB_CPU0 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_41 )); } + .inttab_tc0_02A (__INTTAB_CPU0 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_42 )); } + .inttab_tc0_02B (__INTTAB_CPU0 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_43 )); } + .inttab_tc0_02C (__INTTAB_CPU0 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_44 )); } + .inttab_tc0_02D (__INTTAB_CPU0 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_45 )); } + .inttab_tc0_02E (__INTTAB_CPU0 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_46 )); } + .inttab_tc0_02F (__INTTAB_CPU0 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_47 )); } + .inttab_tc0_030 (__INTTAB_CPU0 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_48 )); } + .inttab_tc0_031 (__INTTAB_CPU0 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_49 )); } + .inttab_tc0_032 (__INTTAB_CPU0 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_50 )); } + .inttab_tc0_033 (__INTTAB_CPU0 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_51 )); } + .inttab_tc0_034 (__INTTAB_CPU0 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_52 )); } + .inttab_tc0_035 (__INTTAB_CPU0 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_53 )); } + .inttab_tc0_036 (__INTTAB_CPU0 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_54 )); } + .inttab_tc0_037 (__INTTAB_CPU0 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_55 )); } + .inttab_tc0_038 (__INTTAB_CPU0 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_56 )); } + .inttab_tc0_039 (__INTTAB_CPU0 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_57 )); } + .inttab_tc0_03A (__INTTAB_CPU0 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_58 )); } + .inttab_tc0_03B (__INTTAB_CPU0 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_59 )); } + .inttab_tc0_03C (__INTTAB_CPU0 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_60 )); } + .inttab_tc0_03D (__INTTAB_CPU0 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_61 )); } + .inttab_tc0_03E (__INTTAB_CPU0 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_62 )); } + .inttab_tc0_03F (__INTTAB_CPU0 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_63 )); } + .inttab_tc0_040 (__INTTAB_CPU0 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_64 )); } + .inttab_tc0_041 (__INTTAB_CPU0 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_65 )); } + .inttab_tc0_042 (__INTTAB_CPU0 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_66 )); } + .inttab_tc0_043 (__INTTAB_CPU0 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_67 )); } + .inttab_tc0_044 (__INTTAB_CPU0 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_68 )); } + .inttab_tc0_045 (__INTTAB_CPU0 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_69 )); } + .inttab_tc0_046 (__INTTAB_CPU0 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_70 )); } + .inttab_tc0_047 (__INTTAB_CPU0 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_71 )); } + .inttab_tc0_048 (__INTTAB_CPU0 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_72 )); } + .inttab_tc0_049 (__INTTAB_CPU0 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_73 )); } + .inttab_tc0_04A (__INTTAB_CPU0 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_74 )); } + .inttab_tc0_04B (__INTTAB_CPU0 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_75 )); } + .inttab_tc0_04C (__INTTAB_CPU0 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_76 )); } + .inttab_tc0_04D (__INTTAB_CPU0 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_77 )); } + .inttab_tc0_04E (__INTTAB_CPU0 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_78 )); } + .inttab_tc0_04F (__INTTAB_CPU0 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_79 )); } + .inttab_tc0_050 (__INTTAB_CPU0 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_80 )); } + .inttab_tc0_051 (__INTTAB_CPU0 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_81 )); } + .inttab_tc0_052 (__INTTAB_CPU0 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_82 )); } + .inttab_tc0_053 (__INTTAB_CPU0 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_83 )); } + .inttab_tc0_054 (__INTTAB_CPU0 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_84 )); } + .inttab_tc0_055 (__INTTAB_CPU0 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_85 )); } + .inttab_tc0_056 (__INTTAB_CPU0 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_86 )); } + .inttab_tc0_057 (__INTTAB_CPU0 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_87 )); } + .inttab_tc0_058 (__INTTAB_CPU0 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_88 )); } + .inttab_tc0_059 (__INTTAB_CPU0 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_89 )); } + .inttab_tc0_05A (__INTTAB_CPU0 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_90 )); } + .inttab_tc0_05B (__INTTAB_CPU0 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_91 )); } + .inttab_tc0_05C (__INTTAB_CPU0 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_92 )); } + .inttab_tc0_05D (__INTTAB_CPU0 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_93 )); } + .inttab_tc0_05E (__INTTAB_CPU0 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_94 )); } + .inttab_tc0_05F (__INTTAB_CPU0 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_95 )); } + .inttab_tc0_060 (__INTTAB_CPU0 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_96 )); } + .inttab_tc0_061 (__INTTAB_CPU0 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_97 )); } + .inttab_tc0_062 (__INTTAB_CPU0 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_98 )); } + .inttab_tc0_063 (__INTTAB_CPU0 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_99 )); } + .inttab_tc0_064 (__INTTAB_CPU0 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_100)); } + .inttab_tc0_065 (__INTTAB_CPU0 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_101)); } + .inttab_tc0_066 (__INTTAB_CPU0 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_102)); } + .inttab_tc0_067 (__INTTAB_CPU0 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_103)); } + .inttab_tc0_068 (__INTTAB_CPU0 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_104)); } + .inttab_tc0_069 (__INTTAB_CPU0 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_105)); } + .inttab_tc0_06A (__INTTAB_CPU0 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_106)); } + .inttab_tc0_06B (__INTTAB_CPU0 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_107)); } + .inttab_tc0_06C (__INTTAB_CPU0 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_108)); } + .inttab_tc0_06D (__INTTAB_CPU0 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_109)); } + .inttab_tc0_06E (__INTTAB_CPU0 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_110)); } + .inttab_tc0_06F (__INTTAB_CPU0 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_111)); } + .inttab_tc0_070 (__INTTAB_CPU0 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_112)); } + .inttab_tc0_071 (__INTTAB_CPU0 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_113)); } + .inttab_tc0_072 (__INTTAB_CPU0 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_114)); } + .inttab_tc0_073 (__INTTAB_CPU0 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_115)); } + .inttab_tc0_074 (__INTTAB_CPU0 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_116)); } + .inttab_tc0_075 (__INTTAB_CPU0 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_117)); } + .inttab_tc0_076 (__INTTAB_CPU0 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_118)); } + .inttab_tc0_077 (__INTTAB_CPU0 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_119)); } + .inttab_tc0_078 (__INTTAB_CPU0 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_120)); } + .inttab_tc0_079 (__INTTAB_CPU0 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_121)); } + .inttab_tc0_07A (__INTTAB_CPU0 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_122)); } + .inttab_tc0_07B (__INTTAB_CPU0 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_123)); } + .inttab_tc0_07C (__INTTAB_CPU0 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_124)); } + .inttab_tc0_07D (__INTTAB_CPU0 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_125)); } + .inttab_tc0_07E (__INTTAB_CPU0 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_126)); } + .inttab_tc0_07F (__INTTAB_CPU0 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_127)); } + .inttab_tc0_080 (__INTTAB_CPU0 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_128)); } + .inttab_tc0_081 (__INTTAB_CPU0 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_129)); } + .inttab_tc0_082 (__INTTAB_CPU0 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_130)); } + .inttab_tc0_083 (__INTTAB_CPU0 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_131)); } + .inttab_tc0_084 (__INTTAB_CPU0 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_132)); } + .inttab_tc0_085 (__INTTAB_CPU0 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_133)); } + .inttab_tc0_086 (__INTTAB_CPU0 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_134)); } + .inttab_tc0_087 (__INTTAB_CPU0 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_135)); } + .inttab_tc0_088 (__INTTAB_CPU0 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_136)); } + .inttab_tc0_089 (__INTTAB_CPU0 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_137)); } + .inttab_tc0_08A (__INTTAB_CPU0 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_138)); } + .inttab_tc0_08B (__INTTAB_CPU0 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_139)); } + .inttab_tc0_08C (__INTTAB_CPU0 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_140)); } + .inttab_tc0_08D (__INTTAB_CPU0 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_141)); } + .inttab_tc0_08E (__INTTAB_CPU0 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_142)); } + .inttab_tc0_08F (__INTTAB_CPU0 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_143)); } + .inttab_tc0_090 (__INTTAB_CPU0 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_144)); } + .inttab_tc0_091 (__INTTAB_CPU0 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_145)); } + .inttab_tc0_092 (__INTTAB_CPU0 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_146)); } + .inttab_tc0_093 (__INTTAB_CPU0 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_147)); } + .inttab_tc0_094 (__INTTAB_CPU0 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_148)); } + .inttab_tc0_095 (__INTTAB_CPU0 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_149)); } + .inttab_tc0_096 (__INTTAB_CPU0 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_150)); } + .inttab_tc0_097 (__INTTAB_CPU0 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_151)); } + .inttab_tc0_098 (__INTTAB_CPU0 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_152)); } + .inttab_tc0_099 (__INTTAB_CPU0 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_153)); } + .inttab_tc0_09A (__INTTAB_CPU0 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_154)); } + .inttab_tc0_09B (__INTTAB_CPU0 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_155)); } + .inttab_tc0_09C (__INTTAB_CPU0 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_156)); } + .inttab_tc0_09D (__INTTAB_CPU0 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_157)); } + .inttab_tc0_09E (__INTTAB_CPU0 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_158)); } + .inttab_tc0_09F (__INTTAB_CPU0 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_159)); } + .inttab_tc0_0A0 (__INTTAB_CPU0 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_160)); } + .inttab_tc0_0A1 (__INTTAB_CPU0 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_161)); } + .inttab_tc0_0A2 (__INTTAB_CPU0 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_162)); } + .inttab_tc0_0A3 (__INTTAB_CPU0 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_163)); } + .inttab_tc0_0A4 (__INTTAB_CPU0 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_164)); } + .inttab_tc0_0A5 (__INTTAB_CPU0 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_165)); } + .inttab_tc0_0A6 (__INTTAB_CPU0 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_166)); } + .inttab_tc0_0A7 (__INTTAB_CPU0 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_167)); } + .inttab_tc0_0A8 (__INTTAB_CPU0 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_168)); } + .inttab_tc0_0A9 (__INTTAB_CPU0 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_169)); } + .inttab_tc0_0AA (__INTTAB_CPU0 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_170)); } + .inttab_tc0_0AB (__INTTAB_CPU0 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_171)); } + .inttab_tc0_0AC (__INTTAB_CPU0 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_172)); } + .inttab_tc0_0AD (__INTTAB_CPU0 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_173)); } + .inttab_tc0_0AE (__INTTAB_CPU0 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_174)); } + .inttab_tc0_0AF (__INTTAB_CPU0 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_175)); } + .inttab_tc0_0B0 (__INTTAB_CPU0 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_176)); } + .inttab_tc0_0B1 (__INTTAB_CPU0 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_177)); } + .inttab_tc0_0B2 (__INTTAB_CPU0 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_178)); } + .inttab_tc0_0B3 (__INTTAB_CPU0 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_179)); } + .inttab_tc0_0B4 (__INTTAB_CPU0 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_180)); } + .inttab_tc0_0B5 (__INTTAB_CPU0 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_181)); } + .inttab_tc0_0B6 (__INTTAB_CPU0 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_182)); } + .inttab_tc0_0B7 (__INTTAB_CPU0 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_183)); } + .inttab_tc0_0B8 (__INTTAB_CPU0 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_184)); } + .inttab_tc0_0B9 (__INTTAB_CPU0 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_185)); } + .inttab_tc0_0BA (__INTTAB_CPU0 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_186)); } + .inttab_tc0_0BB (__INTTAB_CPU0 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_187)); } + .inttab_tc0_0BC (__INTTAB_CPU0 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_188)); } + .inttab_tc0_0BD (__INTTAB_CPU0 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_189)); } + .inttab_tc0_0BE (__INTTAB_CPU0 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_190)); } + .inttab_tc0_0BF (__INTTAB_CPU0 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_191)); } + .inttab_tc0_0C0 (__INTTAB_CPU0 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_192)); } + .inttab_tc0_0C1 (__INTTAB_CPU0 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_193)); } + .inttab_tc0_0C2 (__INTTAB_CPU0 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_194)); } + .inttab_tc0_0C3 (__INTTAB_CPU0 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_195)); } + .inttab_tc0_0C4 (__INTTAB_CPU0 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_196)); } + .inttab_tc0_0C5 (__INTTAB_CPU0 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_197)); } + .inttab_tc0_0C6 (__INTTAB_CPU0 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_198)); } + .inttab_tc0_0C7 (__INTTAB_CPU0 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_199)); } + .inttab_tc0_0C8 (__INTTAB_CPU0 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_200)); } + .inttab_tc0_0C9 (__INTTAB_CPU0 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_201)); } + .inttab_tc0_0CA (__INTTAB_CPU0 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_202)); } + .inttab_tc0_0CB (__INTTAB_CPU0 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_203)); } + .inttab_tc0_0CC (__INTTAB_CPU0 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_204)); } + .inttab_tc0_0CD (__INTTAB_CPU0 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_205)); } + .inttab_tc0_0CE (__INTTAB_CPU0 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_206)); } + .inttab_tc0_0CF (__INTTAB_CPU0 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_207)); } + .inttab_tc0_0D0 (__INTTAB_CPU0 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_208)); } + .inttab_tc0_0D1 (__INTTAB_CPU0 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_209)); } + .inttab_tc0_0D2 (__INTTAB_CPU0 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_210)); } + .inttab_tc0_0D3 (__INTTAB_CPU0 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_211)); } + .inttab_tc0_0D4 (__INTTAB_CPU0 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_212)); } + .inttab_tc0_0D5 (__INTTAB_CPU0 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_213)); } + .inttab_tc0_0D6 (__INTTAB_CPU0 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_214)); } + .inttab_tc0_0D7 (__INTTAB_CPU0 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_215)); } + .inttab_tc0_0D8 (__INTTAB_CPU0 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_216)); } + .inttab_tc0_0D9 (__INTTAB_CPU0 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_217)); } + .inttab_tc0_0DA (__INTTAB_CPU0 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_218)); } + .inttab_tc0_0DB (__INTTAB_CPU0 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_219)); } + .inttab_tc0_0DC (__INTTAB_CPU0 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_220)); } + .inttab_tc0_0DD (__INTTAB_CPU0 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_221)); } + .inttab_tc0_0DE (__INTTAB_CPU0 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_222)); } + .inttab_tc0_0DF (__INTTAB_CPU0 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_223)); } + .inttab_tc0_0E0 (__INTTAB_CPU0 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_224)); } + .inttab_tc0_0E1 (__INTTAB_CPU0 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_225)); } + .inttab_tc0_0E2 (__INTTAB_CPU0 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_226)); } + .inttab_tc0_0E3 (__INTTAB_CPU0 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_227)); } + .inttab_tc0_0E4 (__INTTAB_CPU0 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_228)); } + .inttab_tc0_0E5 (__INTTAB_CPU0 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_229)); } + .inttab_tc0_0E6 (__INTTAB_CPU0 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_230)); } + .inttab_tc0_0E7 (__INTTAB_CPU0 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_231)); } + .inttab_tc0_0E8 (__INTTAB_CPU0 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_232)); } + .inttab_tc0_0E9 (__INTTAB_CPU0 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_233)); } + .inttab_tc0_0EA (__INTTAB_CPU0 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_234)); } + .inttab_tc0_0EB (__INTTAB_CPU0 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_235)); } + .inttab_tc0_0EC (__INTTAB_CPU0 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_236)); } + .inttab_tc0_0ED (__INTTAB_CPU0 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_237)); } + .inttab_tc0_0EE (__INTTAB_CPU0 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_238)); } + .inttab_tc0_0EF (__INTTAB_CPU0 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_239)); } + .inttab_tc0_0F0 (__INTTAB_CPU0 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_240)); } + .inttab_tc0_0F1 (__INTTAB_CPU0 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_241)); } + .inttab_tc0_0F2 (__INTTAB_CPU0 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_242)); } + .inttab_tc0_0F3 (__INTTAB_CPU0 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_243)); } + .inttab_tc0_0F4 (__INTTAB_CPU0 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_244)); } + .inttab_tc0_0F5 (__INTTAB_CPU0 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_245)); } + .inttab_tc0_0F6 (__INTTAB_CPU0 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_246)); } + .inttab_tc0_0F7 (__INTTAB_CPU0 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_247)); } + .inttab_tc0_0F8 (__INTTAB_CPU0 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_248)); } + .inttab_tc0_0F9 (__INTTAB_CPU0 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_249)); } + .inttab_tc0_0FA (__INTTAB_CPU0 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_250)); } + .inttab_tc0_0FB (__INTTAB_CPU0 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_251)); } + .inttab_tc0_0FC (__INTTAB_CPU0 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_252)); } + .inttab_tc0_0FD (__INTTAB_CPU0 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_253)); } + .inttab_tc0_0FE (__INTTAB_CPU0 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_254)); } + .inttab_tc0_0FF (__INTTAB_CPU0 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_255)); } + } + SECTIONS + { + /*CPU1 Interrupt Vector Table*/ + .inttab_tc1_000 (__INTTAB_CPU1 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_0 )); } + .inttab_tc1_001 (__INTTAB_CPU1 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_1 )); } + .inttab_tc1_002 (__INTTAB_CPU1 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_2 )); } + .inttab_tc1_003 (__INTTAB_CPU1 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_3 )); } + .inttab_tc1_004 (__INTTAB_CPU1 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_4 )); } + .inttab_tc1_005 (__INTTAB_CPU1 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_5 )); } + .inttab_tc1_006 (__INTTAB_CPU1 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_6 )); } + .inttab_tc1_007 (__INTTAB_CPU1 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_7 )); } + .inttab_tc1_008 (__INTTAB_CPU1 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_8 )); } + .inttab_tc1_009 (__INTTAB_CPU1 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_9 )); } + .inttab_tc1_00A (__INTTAB_CPU1 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_10 )); } + .inttab_tc1_00B (__INTTAB_CPU1 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_11 )); } + .inttab_tc1_00C (__INTTAB_CPU1 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_12 )); } + .inttab_tc1_00D (__INTTAB_CPU1 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_13 )); } + .inttab_tc1_00E (__INTTAB_CPU1 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_14 )); } + .inttab_tc1_00F (__INTTAB_CPU1 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_15 )); } + .inttab_tc1_010 (__INTTAB_CPU1 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_16 )); } + .inttab_tc1_011 (__INTTAB_CPU1 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_17 )); } + .inttab_tc1_012 (__INTTAB_CPU1 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_18 )); } + .inttab_tc1_013 (__INTTAB_CPU1 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_19 )); } + .inttab_tc1_014 (__INTTAB_CPU1 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_20 )); } + .inttab_tc1_015 (__INTTAB_CPU1 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_21 )); } + .inttab_tc1_016 (__INTTAB_CPU1 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_22 )); } + .inttab_tc1_017 (__INTTAB_CPU1 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_23 )); } + .inttab_tc1_018 (__INTTAB_CPU1 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_24 )); } + .inttab_tc1_019 (__INTTAB_CPU1 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_25 )); } + .inttab_tc1_01A (__INTTAB_CPU1 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_26 )); } + .inttab_tc1_01B (__INTTAB_CPU1 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_27 )); } + .inttab_tc1_01C (__INTTAB_CPU1 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_28 )); } + .inttab_tc1_01D (__INTTAB_CPU1 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_29 )); } + .inttab_tc1_01E (__INTTAB_CPU1 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_30 )); } + .inttab_tc1_01F (__INTTAB_CPU1 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_31 )); } + .inttab_tc1_020 (__INTTAB_CPU1 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_32 )); } + .inttab_tc1_021 (__INTTAB_CPU1 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_33 )); } + .inttab_tc1_022 (__INTTAB_CPU1 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_34 )); } + .inttab_tc1_023 (__INTTAB_CPU1 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_35 )); } + .inttab_tc1_024 (__INTTAB_CPU1 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_36 )); } + .inttab_tc1_025 (__INTTAB_CPU1 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_37 )); } + .inttab_tc1_026 (__INTTAB_CPU1 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_38 )); } + .inttab_tc1_027 (__INTTAB_CPU1 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_39 )); } + .inttab_tc1_028 (__INTTAB_CPU1 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_40 )); } + .inttab_tc1_029 (__INTTAB_CPU1 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_41 )); } + .inttab_tc1_02A (__INTTAB_CPU1 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_42 )); } + .inttab_tc1_02B (__INTTAB_CPU1 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_43 )); } + .inttab_tc1_02C (__INTTAB_CPU1 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_44 )); } + .inttab_tc1_02D (__INTTAB_CPU1 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_45 )); } + .inttab_tc1_02E (__INTTAB_CPU1 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_46 )); } + .inttab_tc1_02F (__INTTAB_CPU1 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_47 )); } + .inttab_tc1_030 (__INTTAB_CPU1 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_48 )); } + .inttab_tc1_031 (__INTTAB_CPU1 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_49 )); } + .inttab_tc1_032 (__INTTAB_CPU1 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_50 )); } + .inttab_tc1_033 (__INTTAB_CPU1 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_51 )); } + .inttab_tc1_034 (__INTTAB_CPU1 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_52 )); } + .inttab_tc1_035 (__INTTAB_CPU1 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_53 )); } + .inttab_tc1_036 (__INTTAB_CPU1 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_54 )); } + .inttab_tc1_037 (__INTTAB_CPU1 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_55 )); } + .inttab_tc1_038 (__INTTAB_CPU1 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_56 )); } + .inttab_tc1_039 (__INTTAB_CPU1 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_57 )); } + .inttab_tc1_03A (__INTTAB_CPU1 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_58 )); } + .inttab_tc1_03B (__INTTAB_CPU1 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_59 )); } + .inttab_tc1_03C (__INTTAB_CPU1 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_60 )); } + .inttab_tc1_03D (__INTTAB_CPU1 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_61 )); } + .inttab_tc1_03E (__INTTAB_CPU1 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_62 )); } + .inttab_tc1_03F (__INTTAB_CPU1 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_63 )); } + .inttab_tc1_040 (__INTTAB_CPU1 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_64 )); } + .inttab_tc1_041 (__INTTAB_CPU1 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_65 )); } + .inttab_tc1_042 (__INTTAB_CPU1 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_66 )); } + .inttab_tc1_043 (__INTTAB_CPU1 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_67 )); } + .inttab_tc1_044 (__INTTAB_CPU1 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_68 )); } + .inttab_tc1_045 (__INTTAB_CPU1 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_69 )); } + .inttab_tc1_046 (__INTTAB_CPU1 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_70 )); } + .inttab_tc1_047 (__INTTAB_CPU1 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_71 )); } + .inttab_tc1_048 (__INTTAB_CPU1 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_72 )); } + .inttab_tc1_049 (__INTTAB_CPU1 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_73 )); } + .inttab_tc1_04A (__INTTAB_CPU1 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_74 )); } + .inttab_tc1_04B (__INTTAB_CPU1 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_75 )); } + .inttab_tc1_04C (__INTTAB_CPU1 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_76 )); } + .inttab_tc1_04D (__INTTAB_CPU1 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_77 )); } + .inttab_tc1_04E (__INTTAB_CPU1 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_78 )); } + .inttab_tc1_04F (__INTTAB_CPU1 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_79 )); } + .inttab_tc1_050 (__INTTAB_CPU1 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_80 )); } + .inttab_tc1_051 (__INTTAB_CPU1 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_81 )); } + .inttab_tc1_052 (__INTTAB_CPU1 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_82 )); } + .inttab_tc1_053 (__INTTAB_CPU1 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_83 )); } + .inttab_tc1_054 (__INTTAB_CPU1 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_84 )); } + .inttab_tc1_055 (__INTTAB_CPU1 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_85 )); } + .inttab_tc1_056 (__INTTAB_CPU1 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_86 )); } + .inttab_tc1_057 (__INTTAB_CPU1 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_87 )); } + .inttab_tc1_058 (__INTTAB_CPU1 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_88 )); } + .inttab_tc1_059 (__INTTAB_CPU1 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_89 )); } + .inttab_tc1_05A (__INTTAB_CPU1 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_90 )); } + .inttab_tc1_05B (__INTTAB_CPU1 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_91 )); } + .inttab_tc1_05C (__INTTAB_CPU1 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_92 )); } + .inttab_tc1_05D (__INTTAB_CPU1 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_93 )); } + .inttab_tc1_05E (__INTTAB_CPU1 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_94 )); } + .inttab_tc1_05F (__INTTAB_CPU1 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_95 )); } + .inttab_tc1_060 (__INTTAB_CPU1 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_96 )); } + .inttab_tc1_061 (__INTTAB_CPU1 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_97 )); } + .inttab_tc1_062 (__INTTAB_CPU1 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_98 )); } + .inttab_tc1_063 (__INTTAB_CPU1 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_99 )); } + .inttab_tc1_064 (__INTTAB_CPU1 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_100)); } + .inttab_tc1_065 (__INTTAB_CPU1 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_101)); } + .inttab_tc1_066 (__INTTAB_CPU1 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_102)); } + .inttab_tc1_067 (__INTTAB_CPU1 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_103)); } + .inttab_tc1_068 (__INTTAB_CPU1 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_104)); } + .inttab_tc1_069 (__INTTAB_CPU1 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_105)); } + .inttab_tc1_06A (__INTTAB_CPU1 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_106)); } + .inttab_tc1_06B (__INTTAB_CPU1 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_107)); } + .inttab_tc1_06C (__INTTAB_CPU1 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_108)); } + .inttab_tc1_06D (__INTTAB_CPU1 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_109)); } + .inttab_tc1_06E (__INTTAB_CPU1 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_110)); } + .inttab_tc1_06F (__INTTAB_CPU1 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_111)); } + .inttab_tc1_070 (__INTTAB_CPU1 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_112)); } + .inttab_tc1_071 (__INTTAB_CPU1 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_113)); } + .inttab_tc1_072 (__INTTAB_CPU1 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_114)); } + .inttab_tc1_073 (__INTTAB_CPU1 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_115)); } + .inttab_tc1_074 (__INTTAB_CPU1 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_116)); } + .inttab_tc1_075 (__INTTAB_CPU1 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_117)); } + .inttab_tc1_076 (__INTTAB_CPU1 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_118)); } + .inttab_tc1_077 (__INTTAB_CPU1 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_119)); } + .inttab_tc1_078 (__INTTAB_CPU1 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_120)); } + .inttab_tc1_079 (__INTTAB_CPU1 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_121)); } + .inttab_tc1_07A (__INTTAB_CPU1 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_122)); } + .inttab_tc1_07B (__INTTAB_CPU1 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_123)); } + .inttab_tc1_07C (__INTTAB_CPU1 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_124)); } + .inttab_tc1_07D (__INTTAB_CPU1 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_125)); } + .inttab_tc1_07E (__INTTAB_CPU1 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_126)); } + .inttab_tc1_07F (__INTTAB_CPU1 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_127)); } + .inttab_tc1_080 (__INTTAB_CPU1 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_128)); } + .inttab_tc1_081 (__INTTAB_CPU1 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_129)); } + .inttab_tc1_082 (__INTTAB_CPU1 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_130)); } + .inttab_tc1_083 (__INTTAB_CPU1 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_131)); } + .inttab_tc1_084 (__INTTAB_CPU1 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_132)); } + .inttab_tc1_085 (__INTTAB_CPU1 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_133)); } + .inttab_tc1_086 (__INTTAB_CPU1 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_134)); } + .inttab_tc1_087 (__INTTAB_CPU1 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_135)); } + .inttab_tc1_088 (__INTTAB_CPU1 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_136)); } + .inttab_tc1_089 (__INTTAB_CPU1 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_137)); } + .inttab_tc1_08A (__INTTAB_CPU1 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_138)); } + .inttab_tc1_08B (__INTTAB_CPU1 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_139)); } + .inttab_tc1_08C (__INTTAB_CPU1 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_140)); } + .inttab_tc1_08D (__INTTAB_CPU1 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_141)); } + .inttab_tc1_08E (__INTTAB_CPU1 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_142)); } + .inttab_tc1_08F (__INTTAB_CPU1 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_143)); } + .inttab_tc1_090 (__INTTAB_CPU1 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_144)); } + .inttab_tc1_091 (__INTTAB_CPU1 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_145)); } + .inttab_tc1_092 (__INTTAB_CPU1 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_146)); } + .inttab_tc1_093 (__INTTAB_CPU1 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_147)); } + .inttab_tc1_094 (__INTTAB_CPU1 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_148)); } + .inttab_tc1_095 (__INTTAB_CPU1 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_149)); } + .inttab_tc1_096 (__INTTAB_CPU1 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_150)); } + .inttab_tc1_097 (__INTTAB_CPU1 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_151)); } + .inttab_tc1_098 (__INTTAB_CPU1 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_152)); } + .inttab_tc1_099 (__INTTAB_CPU1 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_153)); } + .inttab_tc1_09A (__INTTAB_CPU1 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_154)); } + .inttab_tc1_09B (__INTTAB_CPU1 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_155)); } + .inttab_tc1_09C (__INTTAB_CPU1 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_156)); } + .inttab_tc1_09D (__INTTAB_CPU1 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_157)); } + .inttab_tc1_09E (__INTTAB_CPU1 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_158)); } + .inttab_tc1_09F (__INTTAB_CPU1 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_159)); } + .inttab_tc1_0A0 (__INTTAB_CPU1 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_160)); } + .inttab_tc1_0A1 (__INTTAB_CPU1 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_161)); } + .inttab_tc1_0A2 (__INTTAB_CPU1 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_162)); } + .inttab_tc1_0A3 (__INTTAB_CPU1 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_163)); } + .inttab_tc1_0A4 (__INTTAB_CPU1 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_164)); } + .inttab_tc1_0A5 (__INTTAB_CPU1 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_165)); } + .inttab_tc1_0A6 (__INTTAB_CPU1 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_166)); } + .inttab_tc1_0A7 (__INTTAB_CPU1 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_167)); } + .inttab_tc1_0A8 (__INTTAB_CPU1 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_168)); } + .inttab_tc1_0A9 (__INTTAB_CPU1 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_169)); } + .inttab_tc1_0AA (__INTTAB_CPU1 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_170)); } + .inttab_tc1_0AB (__INTTAB_CPU1 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_171)); } + .inttab_tc1_0AC (__INTTAB_CPU1 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_172)); } + .inttab_tc1_0AD (__INTTAB_CPU1 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_173)); } + .inttab_tc1_0AE (__INTTAB_CPU1 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_174)); } + .inttab_tc1_0AF (__INTTAB_CPU1 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_175)); } + .inttab_tc1_0B0 (__INTTAB_CPU1 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_176)); } + .inttab_tc1_0B1 (__INTTAB_CPU1 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_177)); } + .inttab_tc1_0B2 (__INTTAB_CPU1 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_178)); } + .inttab_tc1_0B3 (__INTTAB_CPU1 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_179)); } + .inttab_tc1_0B4 (__INTTAB_CPU1 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_180)); } + .inttab_tc1_0B5 (__INTTAB_CPU1 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_181)); } + .inttab_tc1_0B6 (__INTTAB_CPU1 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_182)); } + .inttab_tc1_0B7 (__INTTAB_CPU1 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_183)); } + .inttab_tc1_0B8 (__INTTAB_CPU1 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_184)); } + .inttab_tc1_0B9 (__INTTAB_CPU1 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_185)); } + .inttab_tc1_0BA (__INTTAB_CPU1 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_186)); } + .inttab_tc1_0BB (__INTTAB_CPU1 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_187)); } + .inttab_tc1_0BC (__INTTAB_CPU1 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_188)); } + .inttab_tc1_0BD (__INTTAB_CPU1 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_189)); } + .inttab_tc1_0BE (__INTTAB_CPU1 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_190)); } + .inttab_tc1_0BF (__INTTAB_CPU1 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_191)); } + .inttab_tc1_0C0 (__INTTAB_CPU1 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_192)); } + .inttab_tc1_0C1 (__INTTAB_CPU1 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_193)); } + .inttab_tc1_0C2 (__INTTAB_CPU1 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_194)); } + .inttab_tc1_0C3 (__INTTAB_CPU1 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_195)); } + .inttab_tc1_0C4 (__INTTAB_CPU1 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_196)); } + .inttab_tc1_0C5 (__INTTAB_CPU1 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_197)); } + .inttab_tc1_0C6 (__INTTAB_CPU1 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_198)); } + .inttab_tc1_0C7 (__INTTAB_CPU1 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_199)); } + .inttab_tc1_0C8 (__INTTAB_CPU1 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_200)); } + .inttab_tc1_0C9 (__INTTAB_CPU1 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_201)); } + .inttab_tc1_0CA (__INTTAB_CPU1 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_202)); } + .inttab_tc1_0CB (__INTTAB_CPU1 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_203)); } + .inttab_tc1_0CC (__INTTAB_CPU1 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_204)); } + .inttab_tc1_0CD (__INTTAB_CPU1 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_205)); } + .inttab_tc1_0CE (__INTTAB_CPU1 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_206)); } + .inttab_tc1_0CF (__INTTAB_CPU1 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_207)); } + .inttab_tc1_0D0 (__INTTAB_CPU1 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_208)); } + .inttab_tc1_0D1 (__INTTAB_CPU1 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_209)); } + .inttab_tc1_0D2 (__INTTAB_CPU1 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_210)); } + .inttab_tc1_0D3 (__INTTAB_CPU1 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_211)); } + .inttab_tc1_0D4 (__INTTAB_CPU1 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_212)); } + .inttab_tc1_0D5 (__INTTAB_CPU1 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_213)); } + .inttab_tc1_0D6 (__INTTAB_CPU1 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_214)); } + .inttab_tc1_0D7 (__INTTAB_CPU1 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_215)); } + .inttab_tc1_0D8 (__INTTAB_CPU1 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_216)); } + .inttab_tc1_0D9 (__INTTAB_CPU1 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_217)); } + .inttab_tc1_0DA (__INTTAB_CPU1 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_218)); } + .inttab_tc1_0DB (__INTTAB_CPU1 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_219)); } + .inttab_tc1_0DC (__INTTAB_CPU1 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_220)); } + .inttab_tc1_0DD (__INTTAB_CPU1 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_221)); } + .inttab_tc1_0DE (__INTTAB_CPU1 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_222)); } + .inttab_tc1_0DF (__INTTAB_CPU1 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_223)); } + .inttab_tc1_0E0 (__INTTAB_CPU1 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_224)); } + .inttab_tc1_0E1 (__INTTAB_CPU1 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_225)); } + .inttab_tc1_0E2 (__INTTAB_CPU1 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_226)); } + .inttab_tc1_0E3 (__INTTAB_CPU1 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_227)); } + .inttab_tc1_0E4 (__INTTAB_CPU1 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_228)); } + .inttab_tc1_0E5 (__INTTAB_CPU1 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_229)); } + .inttab_tc1_0E6 (__INTTAB_CPU1 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_230)); } + .inttab_tc1_0E7 (__INTTAB_CPU1 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_231)); } + .inttab_tc1_0E8 (__INTTAB_CPU1 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_232)); } + .inttab_tc1_0E9 (__INTTAB_CPU1 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_233)); } + .inttab_tc1_0EA (__INTTAB_CPU1 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_234)); } + .inttab_tc1_0EB (__INTTAB_CPU1 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_235)); } + .inttab_tc1_0EC (__INTTAB_CPU1 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_236)); } + .inttab_tc1_0ED (__INTTAB_CPU1 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_237)); } + .inttab_tc1_0EE (__INTTAB_CPU1 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_238)); } + .inttab_tc1_0EF (__INTTAB_CPU1 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_239)); } + .inttab_tc1_0F0 (__INTTAB_CPU1 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_240)); } + .inttab_tc1_0F1 (__INTTAB_CPU1 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_241)); } + .inttab_tc1_0F2 (__INTTAB_CPU1 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_242)); } + .inttab_tc1_0F3 (__INTTAB_CPU1 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_243)); } + .inttab_tc1_0F4 (__INTTAB_CPU1 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_244)); } + .inttab_tc1_0F5 (__INTTAB_CPU1 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_245)); } + .inttab_tc1_0F6 (__INTTAB_CPU1 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_246)); } + .inttab_tc1_0F7 (__INTTAB_CPU1 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_247)); } + .inttab_tc1_0F8 (__INTTAB_CPU1 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_248)); } + .inttab_tc1_0F9 (__INTTAB_CPU1 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_249)); } + .inttab_tc1_0FA (__INTTAB_CPU1 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_250)); } + .inttab_tc1_0FB (__INTTAB_CPU1 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_251)); } + .inttab_tc1_0FC (__INTTAB_CPU1 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_252)); } + .inttab_tc1_0FD (__INTTAB_CPU1 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_253)); } + .inttab_tc1_0FE (__INTTAB_CPU1 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_254)); } + .inttab_tc1_0FF (__INTTAB_CPU1 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_255)); } + } + SECTIONS + { + /*CPU2 Interrupt Vector Table*/ + .inttab_tc2_000 (__INTTAB_CPU2 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_0 )); } + .inttab_tc2_001 (__INTTAB_CPU2 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_1 )); } + .inttab_tc2_002 (__INTTAB_CPU2 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_2 )); } + .inttab_tc2_003 (__INTTAB_CPU2 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_3 )); } + .inttab_tc2_004 (__INTTAB_CPU2 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_4 )); } + .inttab_tc2_005 (__INTTAB_CPU2 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_5 )); } + .inttab_tc2_006 (__INTTAB_CPU2 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_6 )); } + .inttab_tc2_007 (__INTTAB_CPU2 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_7 )); } + .inttab_tc2_008 (__INTTAB_CPU2 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_8 )); } + .inttab_tc2_009 (__INTTAB_CPU2 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_9 )); } + .inttab_tc2_00A (__INTTAB_CPU2 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_10 )); } + .inttab_tc2_00B (__INTTAB_CPU2 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_11 )); } + .inttab_tc2_00C (__INTTAB_CPU2 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_12 )); } + .inttab_tc2_00D (__INTTAB_CPU2 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_13 )); } + .inttab_tc2_00E (__INTTAB_CPU2 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_14 )); } + .inttab_tc2_00F (__INTTAB_CPU2 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_15 )); } + .inttab_tc2_010 (__INTTAB_CPU2 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_16 )); } + .inttab_tc2_011 (__INTTAB_CPU2 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_17 )); } + .inttab_tc2_012 (__INTTAB_CPU2 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_18 )); } + .inttab_tc2_013 (__INTTAB_CPU2 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_19 )); } + .inttab_tc2_014 (__INTTAB_CPU2 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_20 )); } + .inttab_tc2_015 (__INTTAB_CPU2 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_21 )); } + .inttab_tc2_016 (__INTTAB_CPU2 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_22 )); } + .inttab_tc2_017 (__INTTAB_CPU2 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_23 )); } + .inttab_tc2_018 (__INTTAB_CPU2 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_24 )); } + .inttab_tc2_019 (__INTTAB_CPU2 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_25 )); } + .inttab_tc2_01A (__INTTAB_CPU2 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_26 )); } + .inttab_tc2_01B (__INTTAB_CPU2 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_27 )); } + .inttab_tc2_01C (__INTTAB_CPU2 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_28 )); } + .inttab_tc2_01D (__INTTAB_CPU2 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_29 )); } + .inttab_tc2_01E (__INTTAB_CPU2 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_30 )); } + .inttab_tc2_01F (__INTTAB_CPU2 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_31 )); } + .inttab_tc2_020 (__INTTAB_CPU2 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_32 )); } + .inttab_tc2_021 (__INTTAB_CPU2 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_33 )); } + .inttab_tc2_022 (__INTTAB_CPU2 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_34 )); } + .inttab_tc2_023 (__INTTAB_CPU2 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_35 )); } + .inttab_tc2_024 (__INTTAB_CPU2 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_36 )); } + .inttab_tc2_025 (__INTTAB_CPU2 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_37 )); } + .inttab_tc2_026 (__INTTAB_CPU2 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_38 )); } + .inttab_tc2_027 (__INTTAB_CPU2 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_39 )); } + .inttab_tc2_028 (__INTTAB_CPU2 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_40 )); } + .inttab_tc2_029 (__INTTAB_CPU2 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_41 )); } + .inttab_tc2_02A (__INTTAB_CPU2 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_42 )); } + .inttab_tc2_02B (__INTTAB_CPU2 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_43 )); } + .inttab_tc2_02C (__INTTAB_CPU2 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_44 )); } + .inttab_tc2_02D (__INTTAB_CPU2 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_45 )); } + .inttab_tc2_02E (__INTTAB_CPU2 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_46 )); } + .inttab_tc2_02F (__INTTAB_CPU2 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_47 )); } + .inttab_tc2_030 (__INTTAB_CPU2 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_48 )); } + .inttab_tc2_031 (__INTTAB_CPU2 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_49 )); } + .inttab_tc2_032 (__INTTAB_CPU2 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_50 )); } + .inttab_tc2_033 (__INTTAB_CPU2 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_51 )); } + .inttab_tc2_034 (__INTTAB_CPU2 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_52 )); } + .inttab_tc2_035 (__INTTAB_CPU2 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_53 )); } + .inttab_tc2_036 (__INTTAB_CPU2 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_54 )); } + .inttab_tc2_037 (__INTTAB_CPU2 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_55 )); } + .inttab_tc2_038 (__INTTAB_CPU2 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_56 )); } + .inttab_tc2_039 (__INTTAB_CPU2 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_57 )); } + .inttab_tc2_03A (__INTTAB_CPU2 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_58 )); } + .inttab_tc2_03B (__INTTAB_CPU2 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_59 )); } + .inttab_tc2_03C (__INTTAB_CPU2 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_60 )); } + .inttab_tc2_03D (__INTTAB_CPU2 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_61 )); } + .inttab_tc2_03E (__INTTAB_CPU2 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_62 )); } + .inttab_tc2_03F (__INTTAB_CPU2 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_63 )); } + .inttab_tc2_040 (__INTTAB_CPU2 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_64 )); } + .inttab_tc2_041 (__INTTAB_CPU2 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_65 )); } + .inttab_tc2_042 (__INTTAB_CPU2 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_66 )); } + .inttab_tc2_043 (__INTTAB_CPU2 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_67 )); } + .inttab_tc2_044 (__INTTAB_CPU2 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_68 )); } + .inttab_tc2_045 (__INTTAB_CPU2 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_69 )); } + .inttab_tc2_046 (__INTTAB_CPU2 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_70 )); } + .inttab_tc2_047 (__INTTAB_CPU2 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_71 )); } + .inttab_tc2_048 (__INTTAB_CPU2 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_72 )); } + .inttab_tc2_049 (__INTTAB_CPU2 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_73 )); } + .inttab_tc2_04A (__INTTAB_CPU2 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_74 )); } + .inttab_tc2_04B (__INTTAB_CPU2 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_75 )); } + .inttab_tc2_04C (__INTTAB_CPU2 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_76 )); } + .inttab_tc2_04D (__INTTAB_CPU2 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_77 )); } + .inttab_tc2_04E (__INTTAB_CPU2 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_78 )); } + .inttab_tc2_04F (__INTTAB_CPU2 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_79 )); } + .inttab_tc2_050 (__INTTAB_CPU2 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_80 )); } + .inttab_tc2_051 (__INTTAB_CPU2 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_81 )); } + .inttab_tc2_052 (__INTTAB_CPU2 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_82 )); } + .inttab_tc2_053 (__INTTAB_CPU2 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_83 )); } + .inttab_tc2_054 (__INTTAB_CPU2 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_84 )); } + .inttab_tc2_055 (__INTTAB_CPU2 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_85 )); } + .inttab_tc2_056 (__INTTAB_CPU2 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_86 )); } + .inttab_tc2_057 (__INTTAB_CPU2 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_87 )); } + .inttab_tc2_058 (__INTTAB_CPU2 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_88 )); } + .inttab_tc2_059 (__INTTAB_CPU2 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_89 )); } + .inttab_tc2_05A (__INTTAB_CPU2 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_90 )); } + .inttab_tc2_05B (__INTTAB_CPU2 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_91 )); } + .inttab_tc2_05C (__INTTAB_CPU2 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_92 )); } + .inttab_tc2_05D (__INTTAB_CPU2 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_93 )); } + .inttab_tc2_05E (__INTTAB_CPU2 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_94 )); } + .inttab_tc2_05F (__INTTAB_CPU2 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_95 )); } + .inttab_tc2_060 (__INTTAB_CPU2 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_96 )); } + .inttab_tc2_061 (__INTTAB_CPU2 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_97 )); } + .inttab_tc2_062 (__INTTAB_CPU2 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_98 )); } + .inttab_tc2_063 (__INTTAB_CPU2 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_99 )); } + .inttab_tc2_064 (__INTTAB_CPU2 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_100)); } + .inttab_tc2_065 (__INTTAB_CPU2 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_101)); } + .inttab_tc2_066 (__INTTAB_CPU2 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_102)); } + .inttab_tc2_067 (__INTTAB_CPU2 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_103)); } + .inttab_tc2_068 (__INTTAB_CPU2 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_104)); } + .inttab_tc2_069 (__INTTAB_CPU2 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_105)); } + .inttab_tc2_06A (__INTTAB_CPU2 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_106)); } + .inttab_tc2_06B (__INTTAB_CPU2 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_107)); } + .inttab_tc2_06C (__INTTAB_CPU2 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_108)); } + .inttab_tc2_06D (__INTTAB_CPU2 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_109)); } + .inttab_tc2_06E (__INTTAB_CPU2 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_110)); } + .inttab_tc2_06F (__INTTAB_CPU2 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_111)); } + .inttab_tc2_070 (__INTTAB_CPU2 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_112)); } + .inttab_tc2_071 (__INTTAB_CPU2 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_113)); } + .inttab_tc2_072 (__INTTAB_CPU2 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_114)); } + .inttab_tc2_073 (__INTTAB_CPU2 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_115)); } + .inttab_tc2_074 (__INTTAB_CPU2 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_116)); } + .inttab_tc2_075 (__INTTAB_CPU2 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_117)); } + .inttab_tc2_076 (__INTTAB_CPU2 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_118)); } + .inttab_tc2_077 (__INTTAB_CPU2 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_119)); } + .inttab_tc2_078 (__INTTAB_CPU2 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_120)); } + .inttab_tc2_079 (__INTTAB_CPU2 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_121)); } + .inttab_tc2_07A (__INTTAB_CPU2 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_122)); } + .inttab_tc2_07B (__INTTAB_CPU2 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_123)); } + .inttab_tc2_07C (__INTTAB_CPU2 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_124)); } + .inttab_tc2_07D (__INTTAB_CPU2 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_125)); } + .inttab_tc2_07E (__INTTAB_CPU2 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_126)); } + .inttab_tc2_07F (__INTTAB_CPU2 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_127)); } + .inttab_tc2_080 (__INTTAB_CPU2 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_128)); } + .inttab_tc2_081 (__INTTAB_CPU2 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_129)); } + .inttab_tc2_082 (__INTTAB_CPU2 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_130)); } + .inttab_tc2_083 (__INTTAB_CPU2 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_131)); } + .inttab_tc2_084 (__INTTAB_CPU2 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_132)); } + .inttab_tc2_085 (__INTTAB_CPU2 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_133)); } + .inttab_tc2_086 (__INTTAB_CPU2 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_134)); } + .inttab_tc2_087 (__INTTAB_CPU2 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_135)); } + .inttab_tc2_088 (__INTTAB_CPU2 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_136)); } + .inttab_tc2_089 (__INTTAB_CPU2 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_137)); } + .inttab_tc2_08A (__INTTAB_CPU2 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_138)); } + .inttab_tc2_08B (__INTTAB_CPU2 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_139)); } + .inttab_tc2_08C (__INTTAB_CPU2 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_140)); } + .inttab_tc2_08D (__INTTAB_CPU2 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_141)); } + .inttab_tc2_08E (__INTTAB_CPU2 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_142)); } + .inttab_tc2_08F (__INTTAB_CPU2 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_143)); } + .inttab_tc2_090 (__INTTAB_CPU2 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_144)); } + .inttab_tc2_091 (__INTTAB_CPU2 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_145)); } + .inttab_tc2_092 (__INTTAB_CPU2 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_146)); } + .inttab_tc2_093 (__INTTAB_CPU2 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_147)); } + .inttab_tc2_094 (__INTTAB_CPU2 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_148)); } + .inttab_tc2_095 (__INTTAB_CPU2 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_149)); } + .inttab_tc2_096 (__INTTAB_CPU2 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_150)); } + .inttab_tc2_097 (__INTTAB_CPU2 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_151)); } + .inttab_tc2_098 (__INTTAB_CPU2 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_152)); } + .inttab_tc2_099 (__INTTAB_CPU2 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_153)); } + .inttab_tc2_09A (__INTTAB_CPU2 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_154)); } + .inttab_tc2_09B (__INTTAB_CPU2 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_155)); } + .inttab_tc2_09C (__INTTAB_CPU2 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_156)); } + .inttab_tc2_09D (__INTTAB_CPU2 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_157)); } + .inttab_tc2_09E (__INTTAB_CPU2 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_158)); } + .inttab_tc2_09F (__INTTAB_CPU2 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_159)); } + .inttab_tc2_0A0 (__INTTAB_CPU2 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_160)); } + .inttab_tc2_0A1 (__INTTAB_CPU2 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_161)); } + .inttab_tc2_0A2 (__INTTAB_CPU2 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_162)); } + .inttab_tc2_0A3 (__INTTAB_CPU2 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_163)); } + .inttab_tc2_0A4 (__INTTAB_CPU2 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_164)); } + .inttab_tc2_0A5 (__INTTAB_CPU2 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_165)); } + .inttab_tc2_0A6 (__INTTAB_CPU2 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_166)); } + .inttab_tc2_0A7 (__INTTAB_CPU2 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_167)); } + .inttab_tc2_0A8 (__INTTAB_CPU2 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_168)); } + .inttab_tc2_0A9 (__INTTAB_CPU2 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_169)); } + .inttab_tc2_0AA (__INTTAB_CPU2 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_170)); } + .inttab_tc2_0AB (__INTTAB_CPU2 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_171)); } + .inttab_tc2_0AC (__INTTAB_CPU2 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_172)); } + .inttab_tc2_0AD (__INTTAB_CPU2 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_173)); } + .inttab_tc2_0AE (__INTTAB_CPU2 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_174)); } + .inttab_tc2_0AF (__INTTAB_CPU2 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_175)); } + .inttab_tc2_0B0 (__INTTAB_CPU2 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_176)); } + .inttab_tc2_0B1 (__INTTAB_CPU2 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_177)); } + .inttab_tc2_0B2 (__INTTAB_CPU2 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_178)); } + .inttab_tc2_0B3 (__INTTAB_CPU2 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_179)); } + .inttab_tc2_0B4 (__INTTAB_CPU2 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_180)); } + .inttab_tc2_0B5 (__INTTAB_CPU2 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_181)); } + .inttab_tc2_0B6 (__INTTAB_CPU2 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_182)); } + .inttab_tc2_0B7 (__INTTAB_CPU2 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_183)); } + .inttab_tc2_0B8 (__INTTAB_CPU2 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_184)); } + .inttab_tc2_0B9 (__INTTAB_CPU2 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_185)); } + .inttab_tc2_0BA (__INTTAB_CPU2 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_186)); } + .inttab_tc2_0BB (__INTTAB_CPU2 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_187)); } + .inttab_tc2_0BC (__INTTAB_CPU2 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_188)); } + .inttab_tc2_0BD (__INTTAB_CPU2 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_189)); } + .inttab_tc2_0BE (__INTTAB_CPU2 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_190)); } + .inttab_tc2_0BF (__INTTAB_CPU2 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_191)); } + .inttab_tc2_0C0 (__INTTAB_CPU2 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_192)); } + .inttab_tc2_0C1 (__INTTAB_CPU2 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_193)); } + .inttab_tc2_0C2 (__INTTAB_CPU2 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_194)); } + .inttab_tc2_0C3 (__INTTAB_CPU2 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_195)); } + .inttab_tc2_0C4 (__INTTAB_CPU2 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_196)); } + .inttab_tc2_0C5 (__INTTAB_CPU2 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_197)); } + .inttab_tc2_0C6 (__INTTAB_CPU2 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_198)); } + .inttab_tc2_0C7 (__INTTAB_CPU2 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_199)); } + .inttab_tc2_0C8 (__INTTAB_CPU2 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_200)); } + .inttab_tc2_0C9 (__INTTAB_CPU2 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_201)); } + .inttab_tc2_0CA (__INTTAB_CPU2 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_202)); } + .inttab_tc2_0CB (__INTTAB_CPU2 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_203)); } + .inttab_tc2_0CC (__INTTAB_CPU2 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_204)); } + .inttab_tc2_0CD (__INTTAB_CPU2 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_205)); } + .inttab_tc2_0CE (__INTTAB_CPU2 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_206)); } + .inttab_tc2_0CF (__INTTAB_CPU2 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_207)); } + .inttab_tc2_0D0 (__INTTAB_CPU2 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_208)); } + .inttab_tc2_0D1 (__INTTAB_CPU2 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_209)); } + .inttab_tc2_0D2 (__INTTAB_CPU2 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_210)); } + .inttab_tc2_0D3 (__INTTAB_CPU2 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_211)); } + .inttab_tc2_0D4 (__INTTAB_CPU2 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_212)); } + .inttab_tc2_0D5 (__INTTAB_CPU2 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_213)); } + .inttab_tc2_0D6 (__INTTAB_CPU2 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_214)); } + .inttab_tc2_0D7 (__INTTAB_CPU2 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_215)); } + .inttab_tc2_0D8 (__INTTAB_CPU2 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_216)); } + .inttab_tc2_0D9 (__INTTAB_CPU2 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_217)); } + .inttab_tc2_0DA (__INTTAB_CPU2 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_218)); } + .inttab_tc2_0DB (__INTTAB_CPU2 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_219)); } + .inttab_tc2_0DC (__INTTAB_CPU2 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_220)); } + .inttab_tc2_0DD (__INTTAB_CPU2 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_221)); } + .inttab_tc2_0DE (__INTTAB_CPU2 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_222)); } + .inttab_tc2_0DF (__INTTAB_CPU2 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_223)); } + .inttab_tc2_0E0 (__INTTAB_CPU2 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_224)); } + .inttab_tc2_0E1 (__INTTAB_CPU2 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_225)); } + .inttab_tc2_0E2 (__INTTAB_CPU2 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_226)); } + .inttab_tc2_0E3 (__INTTAB_CPU2 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_227)); } + .inttab_tc2_0E4 (__INTTAB_CPU2 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_228)); } + .inttab_tc2_0E5 (__INTTAB_CPU2 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_229)); } + .inttab_tc2_0E6 (__INTTAB_CPU2 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_230)); } + .inttab_tc2_0E7 (__INTTAB_CPU2 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_231)); } + .inttab_tc2_0E8 (__INTTAB_CPU2 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_232)); } + .inttab_tc2_0E9 (__INTTAB_CPU2 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_233)); } + .inttab_tc2_0EA (__INTTAB_CPU2 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_234)); } + .inttab_tc2_0EB (__INTTAB_CPU2 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_235)); } + .inttab_tc2_0EC (__INTTAB_CPU2 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_236)); } + .inttab_tc2_0ED (__INTTAB_CPU2 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_237)); } + .inttab_tc2_0EE (__INTTAB_CPU2 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_238)); } + .inttab_tc2_0EF (__INTTAB_CPU2 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_239)); } + .inttab_tc2_0F0 (__INTTAB_CPU2 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_240)); } + .inttab_tc2_0F1 (__INTTAB_CPU2 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_241)); } + .inttab_tc2_0F2 (__INTTAB_CPU2 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_242)); } + .inttab_tc2_0F3 (__INTTAB_CPU2 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_243)); } + .inttab_tc2_0F4 (__INTTAB_CPU2 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_244)); } + .inttab_tc2_0F5 (__INTTAB_CPU2 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_245)); } + .inttab_tc2_0F6 (__INTTAB_CPU2 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_246)); } + .inttab_tc2_0F7 (__INTTAB_CPU2 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_247)); } + .inttab_tc2_0F8 (__INTTAB_CPU2 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_248)); } + .inttab_tc2_0F9 (__INTTAB_CPU2 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_249)); } + .inttab_tc2_0FA (__INTTAB_CPU2 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_250)); } + .inttab_tc2_0FB (__INTTAB_CPU2 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_251)); } + .inttab_tc2_0FC (__INTTAB_CPU2 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_252)); } + .inttab_tc2_0FD (__INTTAB_CPU2 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_253)); } + .inttab_tc2_0FE (__INTTAB_CPU2 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_254)); } + .inttab_tc2_0FF (__INTTAB_CPU2 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_255)); } + } + + /*Fixed memory Allocations for BMHD*/ + CORE_ID = GLOBAL; + SECTIONS + { + .bmhd_0_org (0xaf400000) : FLAGS(arl) { KEEP (*(.bmhd_0_orig)); } > ucb + .bmhd_1_org (0xaf400200) : FLAGS(arl) { KEEP (*(.bmhd_1_orig)); } > ucb + .bmhd_2_org (0xaf400400) : FLAGS(arl) { KEEP (*(.bmhd_2_orig)); } > ucb + .bmhd_3_org (0xaf400600) : FLAGS(arl) { KEEP (*(.bmhd_3_orig)); } > ucb + .ucb_reserved (0xaf400800) : FLAGS(arl) { } > ucb + .bmhd_0_copy (0xaf401000) : FLAGS(arl) { KEEP (*(.bmhd_0_copy)); } > ucb + .bmhd_1_copy (0xaf401200) : FLAGS(arl) { KEEP (*(.bmhd_1_copy)); } > ucb + .bmhd_2_copy (0xaf401400) : FLAGS(arl) { KEEP (*(.bmhd_2_copy)); } > ucb + .bmhd_3_copy (0xaf401600) : FLAGS(arl) { KEEP (*(.bmhd_3_copy)); } > ucb + } + + /*Near Abbsolute Addressable Data Sections*/ + /*Near Absolute Data, selectable with patterns and user defined sections*/ + CORE_ID = CPU2; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR2_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc2.* (.zdata) + *Cpu2_Main.* (.zdata) + *(.zdata_cpu2) + *(.zdata_cpu2.*) + . = ALIGN(2); + } > dsram2 AT> pfls0 + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc2.* (.zbss) + *Cpu2_Main.* (.zbss) + *(.zbss_cpu2) + *(.zbss_cpu2.*) + } > dsram2 + } + CORE_ID = CPU1; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR1_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc1.* (.zdata) + *Cpu1_Main.* (.zdata) + *(.zdata_cpu1) + *(.zdata_cpu1.*) + . = ALIGN(2); + } > dsram1 AT> pfls0 + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc1.* (.zbss) + *Cpu1_Main.* (.zbss) + *(.zbss_cpu1) + *(.zbss_cpu1.*) + } > dsram1 + } + CORE_ID = CPU0; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR0_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc0.* (.zdata) + *Cpu0_Main.* (.zdata) + *(.zdata_cpu0) + *(.zdata_cpu0.*) + . = ALIGN(2); + } > dsram0 AT> pfls0 + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc0.* (.zbss) + *Cpu0_Main.* (.zbss) + *(.zbss_cpu0) + *(.zbss_cpu0.*) + } > dsram0 + } + + /*Near Absolute Data, selectable by toolchain*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zdata_powerOn) : FLAGS(awzl) + { + *(.zdata.dsprPowerOnInit.cpu0.32bit) + *(.zdata.dsprPowerOnInit.cpu0.16bit) + *(.zdata.dsprPowerOnInit.cpu0.8bit) + . = ALIGN(2); + } > default_ram AT> pfls0 + + CORE_SEC(.zdata) : FLAGS(awzl) + { + *(.zdata.dsprInit.cpu0.32bit) + *(.zdata.dsprInit.cpu0.16bit) + *(.zdata.dsprInit.cpu0.8bit) + *(.zdata) + *(.zdata.*) + *(.gnu.linkonce.z.*) + . = ALIGN(2); + } > default_ram AT> pfls0 + + CORE_SEC(.zbss_powerOn) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprPowerOnClear.cpu0.32bit) + *(.zbss.dsprPowerOnClear.cpu0.16bit) + *(.zbss.dsprPowerOnClear.cpu0.8bit) + } > default_ram + + CORE_SEC(.zbss_noClear) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprNoInit.cpu0.32bit) + *(.zbss.dsprNoInit.cpu0.16bit) + *(.zbss.dsprNoInit.cpu0.8bit) + } > default_ram + + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprClearOnInit.cpu0.32bit) + *(.zbss.dsprClearOnInit.cpu0.16bit) + *(.zbss.dsprClearOnInit.cpu0.8bit) + *(.zbss) + *(.zbss.*) + *(.bbss) + *(.bbss.*) + *(.gnu.linkonce.zb.*) + } > default_ram + } + + CORE_ID = GLOBAL; + SECTIONS + { + /*Cpu0_dlmu also is the segment start, all the near lmu data shll be located here*/ + CORE_SEC(.lmuzdata) : FLAGS(awzl) + { + *(.zlmudata) + *(.zlmudata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls0 + + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) + { + *(.zlmubss) + *(.zlmubss.*) + } > cpu0_dlmu + } + + /*Near Absolute Const, selectable with patterns and user defined sections*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zrodata) : FLAGS(arzl) + { + *Ifx_Ssw_Tc?.* (.zrodata) + *Cpu?_Main.* (.zrodata) + *(.zrodata_cpu?) + } > pfls0 + } + + /*Near Absolute Const, selectable by toolchain*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zrodata) : FLAGS(arzl) + { + *(.zrodata.const.cpu0.32bit) + *(.zrodata.const.cpu0.16bit) + *(.zrodata.const.cpu0.8bit) + *(.zrodata.config.cpu0.32bit) + *(.zrodata.config.cpu0.16bit) + *(.zrodata.config.cpu0.8bit) + *(.zrodata) + *(.zrodata.*) + } > pfls0 + } + +/*Relative A0/A1/A8/A9 Addressable Sections*/ +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A0 Addressable Data, selectable with patterns and user defined sections*/ + /*Note: A0 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A0 Addressable Data, selectable by toolchain*/ + CORE_SEC(.sdata) : FLAGS(awsl) + { + *(.sdata) + *(.sdata.*) + . = ALIGN(2); + } > default_ram AT> pfls0 + CORE_SEC(.sbss) (NOLOAD): FLAGS(aws) + { + *(.sbss) + *(.sbss.*) + } > default_ram + _SMALL_DATA_ = SIZEOF(CORE_SEC(.sdata)) ? ADDR(CORE_SEC(.sdata)) : (ADDR(CORE_SEC(.sdata)) & 0xF0000000) + 32k ; + __A0_MEM = _SMALL_DATA_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A1 Addressable Const, selectable with patterns and user defined sections*/ + /*Note: A1 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A1 Addressable Const, selectable by toolchain*/ + CORE_SEC(.sdata2) : FLAGS(arsl) + { + *(.srodata) + *(.srodata.*) + } > default_rom + _SMALL_DATA2_ = SIZEOF(CORE_SEC(.sdata2)) ? ADDR(CORE_SEC(.sdata2)) : (ADDR(CORE_SEC(.sdata2)) & 0xF0000000) + 32k ; + __A1_MEM = _SMALL_DATA2_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata3) : FLAGS(arsl) + { + *(.rodata_a8) + *(.rodata_a8.*) + } > default_rom + + _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; + __A8_MEM = _SMALL_DATA3_; +} + +/*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ +/*Far Data Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU2 ; +SECTIONS +{ + /*DSRAM2 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc2.* (.data) + *Cpu2_Main.* (.data) + *(.data_cpu2) + *(.data_cpu2.*) + . = ALIGN(2); + } > dsram2 AT> pfls0 + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc2.* (.bss) + *Cpu2_Main.* (.bss) + *(.bss_cpu2) + *(.bss_cpu2.*) + } > dsram2 + + /*DLMU2 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu2) + *(.lmudata_cpu2.*) + . = ALIGN(2); + } > cpu2_dlmu AT> pfls0 + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu2) + *(.lmubss_cpu2.*) + } > cpu2_dlmu +} +CORE_ID = CPU1 ; +SECTIONS +{ + /*DSRAM1 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc1.* (.data) + *Cpu1_Main.* (.data) + *(.data_cpu1) + *(.data_cpu1.*) + . = ALIGN(2); + } > dsram1 AT> pfls0 + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc1.* (.bss) + *Cpu1_Main.* (.bss) + *(.bss_cpu1) + *(.bss_cpu1.*) + } > dsram1 + + /*DLMU1 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu1) + *(.lmudata_cpu1.*) + . = ALIGN(2); + } > cpu1_dlmu AT> pfls0 + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu1) + *(.lmubss_cpu1.*) + } > cpu1_dlmu +} +CORE_ID = CPU0 ; +SECTIONS +{ + /*DSRAM0 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc0.* (.data) + *Cpu0_Main.* (.data) + *(.data_cpu0) + *(.data_cpu0.*) + . = ALIGN(2); + } > dsram0 AT> pfls0 + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc0.* (.bss) + *Cpu0_Main.* (.bss) + *(.bss_cpu0) + *(.bss_cpu0.*) + } > dsram0 + + /*DLMU0 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu0) + *(.lmudata_cpu0.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls0 + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu0) + *(.lmubss_cpu0.*) + } > cpu0_dlmu +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata4) : + { + *(.a9sdata) + *(.a9sdata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls0 + + CORE_SEC(.sbss4) : + { + *(.a9sbss) + *(.a9sbss.*) + } > cpu0_dlmu + + _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; + __A9_MEM = _SMALL_DATA4_; +} + +/*Far Data Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.bss_noClear) (NOLOAD) : FLAGS(aw) + { + *(.bss.farDsprNoInit.cpu0.32bit) + *(.bss.farDsprNoInit.cpu0.16bit) + *(.bss.farDsprNoInit.cpu0.8bit) + } > default_ram + + CORE_SEC(.data) : FLAGS(awl) + { + *(.data.farDsprInit.cpu0.32bit) + *(.data.farDsprInit.cpu0.16bit) + *(.data.farDsprInit.cpu0.8bit) + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(2); + } > default_ram AT> pfls0 + + CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) + { + *(.bss.farDsprClearOnInit.cpu0.32bit) + *(.bss.farDsprClearOnInit.cpu0.16bit) + *(.bss.farDsprClearOnInit.cpu0.8bit) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + } > default_ram + + .heap : FLAGS(aw) + { + . = ALIGN(4); + __HEAP = .; + . += LCF_HEAP_SIZE; + __HEAP_END = .; + } > default_ram + + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata) + *(.lmudata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls0 + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss) + *(.lmubss.*) + } > cpu0_dlmu +} +/*Far Const Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU0; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc0.* (.rodata) + *Cpu0_Main.* (.rodata) + *(.rodata_cpu0) + *(.rodata_cpu0.*) + } > pfls0 +} + +CORE_ID = CPU1; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc1.* (.rodata) + *Cpu1_Main.* (.rodata) + *(.rodata_cpu1) + *(.rodata_cpu1.*) + } > pfls0 +} + +CORE_ID = CPU2; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc2.* (.rodata) + *Cpu2_Main.* (.rodata) + *(.rodata_cpu2) + *(.rodata_cpu2.*) + } > pfls0 +} + +/*Far Const Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *(.rodata.farConst.cpu0.32bit) + *(.rodata.farConst.cpu0.16bit) + *(.rodata.farConst.cpu0.8bit) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + /* + * Create the clear and copy tables that tell the startup code + * which memory areas to clear and to copy, respectively. + */ + . = ALIGN(4) ; + PROVIDE(__clear_table = .); + LONG(0 + ADDR(.CPU2.zbss)); LONG(SIZEOF(.CPU2.zbss)); + LONG(0 + ADDR(.CPU2.bss)); LONG(SIZEOF(.CPU2.bss)); + LONG(0 + ADDR(.CPU2.lmubss)); LONG(SIZEOF(.CPU2.lmubss)); + LONG(0 + ADDR(.CPU1.zbss)); LONG(SIZEOF(.CPU1.zbss)); + LONG(0 + ADDR(.CPU1.bss)); LONG(SIZEOF(.CPU1.bss)); + LONG(0 + ADDR(.CPU1.lmubss)); LONG(SIZEOF(.CPU1.lmubss)); + LONG(0 + ADDR(.CPU0.zbss)); LONG(SIZEOF(.CPU0.zbss)); + LONG(0 + ADDR(.CPU0.bss)); LONG(SIZEOF(.CPU0.bss)); + LONG(0 + ADDR(.CPU0.lmubss)); LONG(SIZEOF(.CPU0.lmubss)); + LONG(0 + ADDR(.zbss)); LONG(SIZEOF(.zbss)); + LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss)); + LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); + LONG(0 + ADDR(.lmubss)); LONG(SIZEOF(.lmubss)); + LONG(0 + ADDR(.sbss4)); LONG(SIZEOF(.sbss4)); + LONG(-1); LONG(-1); + PROVIDE(__clear_table_powerOn = .); + LONG(0 + ADDR(.zbss_powerOn)); LONG(SIZEOF(.zbss_powerOn)); + LONG(-1); LONG(-1); + PROVIDE(__copy_table = .); + LONG(LOADADDR(.CPU2.zdata)); LONG(0 + ADDR(.CPU2.zdata)); LONG(SIZEOF(.CPU2.zdata)); + LONG(LOADADDR(.CPU2.data)); LONG(0 + ADDR(.CPU2.data)); LONG(SIZEOF(.CPU2.data)); + LONG(LOADADDR(.CPU2.lmudata)); LONG(0 + ADDR(.CPU2.lmudata)); LONG(SIZEOF(.CPU2.lmudata)); + LONG(LOADADDR(.CPU1.zdata)); LONG(0 + ADDR(.CPU1.zdata)); LONG(SIZEOF(.CPU1.zdata)); + LONG(LOADADDR(.CPU1.data)); LONG(0 + ADDR(.CPU1.data)); LONG(SIZEOF(.CPU1.data)); + LONG(LOADADDR(.CPU1.lmudata)); LONG(0 + ADDR(.CPU1.lmudata)); LONG(SIZEOF(.CPU1.lmudata)); + LONG(LOADADDR(.CPU0.zdata)); LONG(0 + ADDR(.CPU0.zdata)); LONG(SIZEOF(.CPU0.zdata)); + LONG(LOADADDR(.CPU0.data)); LONG(0 + ADDR(.CPU0.data)); LONG(SIZEOF(.CPU0.data)); + LONG(LOADADDR(.CPU0.lmudata)); LONG(0 + ADDR(.CPU0.lmudata)); LONG(SIZEOF(.CPU0.lmudata)); + LONG(LOADADDR(.zdata)); LONG(0 + ADDR(.zdata)); LONG(SIZEOF(.zdata)); + LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata)); + LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); + LONG(LOADADDR(.lmudata)); LONG(0 + ADDR(.lmudata)); LONG(SIZEOF(.lmudata)); + LONG(LOADADDR(.sdata4)); LONG(0 + ADDR(.sdata4)); LONG(SIZEOF(.sdata4)); + LONG(LOADADDR(.CPU0.psram_text)); LONG(0 + ADDR(.CPU0.psram_text)); LONG(SIZEOF(.CPU0.psram_text)); + LONG(LOADADDR(.CPU1.psram_text)); LONG(0 + ADDR(.CPU1.psram_text)); LONG(SIZEOF(.CPU1.psram_text)); + LONG(LOADADDR(.CPU2.psram_text)); LONG(0 + ADDR(.CPU2.psram_text)); LONG(SIZEOF(.CPU2.psram_text)); + LONG(-1); LONG(-1); LONG(-1); + PROVIDE(__copy_table_powerOn = .) ; + LONG(LOADADDR(.zdata_powerOn)); LONG(0 + ADDR(.zdata_powerOn)); LONG(SIZEOF(.zdata_powerOn)); + LONG(-1); LONG(-1); LONG(-1); + . = ALIGN(8); + } > default_rom +} + +/*Code selections*/ +/*Code Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU0; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc0.*(.text) + *Cpu0_Main.*(.text) + *Ifx_Ssw_Tc0.*(.text.*) + *Cpu0_Main.*(.text.*) + *(.text_cpu0) + *(.text_cpu0.*) + } > pfls0 + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + .init : + { + PROVIDE(__init_start = .); + KEEP(*(.init)) + KEEP(*(.init*)) + PROVIDE(__init_end = .); + . = ALIGN(8); + + } > pfls0 + + .fini : + { + PROVIDE(__fini_start = .); + KEEP(*(.fini)) + KEEP(*(.fini*)) + PROVIDE(__fini_end = .); + . = ALIGN(8); + } > pfls0 + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu0) + *(.psram_text_cpu0.*) + *(.cpu0_psram) + *(.cpu0_psram.*) + *(.ramcode) /* wolfBoot RAM function section, for RAM_CODE=1 */ + *(.ramcode.*) /* future proof subsection matching for wolfBoot RAM function section, for RAM_CODE=1 */ + . = ALIGN(2); + } > psram0 AT> pfls0 +} + +CORE_ID = CPU1; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc1.*(.text) + *Cpu1_Main.*(.text) + *Ifx_Ssw_Tc1.*(.text.*) + *Cpu1_Main.*(.text.*) + *(.text_cpu1) + *(.text_cpu1.*) + } > pfls0 + + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu1) + *(.psram_text_cpu1.*) + *(.cpu1_psram) + *(.cpu1_psram.*) + . = ALIGN(2); + } > psram1 AT> pfls0 +} + +CORE_ID = CPU2; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc2.*(.text) + *Cpu2_Main.*(.text) + *Ifx_Ssw_Tc2.*(.text.*) + *Cpu2_Main.*(.text.*) + *(.text_cpu2) + *(.text_cpu2.*) + } > pfls0 + + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu2) + *(.psram_text_cpu2.*) + *(.cpu2_psram) + *(.cpu2_psram.*) + . = ALIGN(2); + } > psram2 AT> pfls0 +} + +/*Code Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + *(.text.fast.pfls.cpu0) + *(.text.slow.pfls.cpu0) + *(.text.5ms.pfls.cpu0) + *(.text.10ms.pfls.cpu0) + *(.text.callout.pfls.cpu0) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ + . = ALIGN(4); + } > default_rom + + /* + * C++ exception handling tables. NOTE: gcc emits .eh_frame + * sections when compiling C sources with debugging enabled (-g). + * If you can be sure that your final application consists + * exclusively of C objects (i.e., no C++ objects), you may use + * the -R option of the "strip" and "objcopy" utilities to remove + * the .eh_frame section from the executable. + */ + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > default_rom + + .eh_frame : + { + __EH_FRAME_BEGIN__ = . ; + KEEP (*(.eh_frame)) + __EH_FRAME_END__ = . ; + . = ALIGN(8); + } > default_rom + + .gcc_except_table : + { + __GCC_EXCEPT_TABLE_BEGIN__ = . ; + KEEP (*(.gcc_except_table)) + __GCC_EXCEPT_TABLE_END__ = . ; + . = ALIGN(8); + } > default_rom + + /* + * Constructors and destructors. + */ + .ctors : FLAGS(ar) + { + __CTOR_LIST__ = . ; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __CTOR_END__ = . ; + . = ALIGN(8); + } > default_rom + .dtors : FLAGS(ar) + { + __DTOR_LIST__ = . ; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ distructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* + * Code executed before calling main extra section for C++ distructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __DTOR_END__ = . ; + . = ALIGN(8); + } > default_rom + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the + * beginning of the section, so we begin them at 0. + */ + /* + * DWARF 1 + */ + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* + * GNU DWARF 1 extensions + */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* + * DWARF 1.1 and DWARF 2 + */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* + * DWARF 2 + */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_ranges 0 : { *(.debug_ranges) } + /* + * SGI/MIPS DWARF 2 extensions + */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* + * Optional sections that may only appear when relocating. + */ + /* + * Optional sections that may appear regardless of relocating. + */ + .version_info 0 : { *(.version_info) } + .boffs 0 : { KEEP (*(.boffs)) } +} + diff --git a/IDE/AURIX/wolfBoot-tc3xx/Lcf_Tasking_Tricore_Tc.lsl b/IDE/AURIX/wolfBoot-tc3xx/Lcf_Tasking_Tricore_Tc.lsl new file mode 100644 index 000000000..da9305ff4 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx/Lcf_Tasking_Tricore_Tc.lsl @@ -0,0 +1,918 @@ +/* Lcf_Tasking_Tricore_Tc.lsl + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#define LCF_CSA0_SIZE 8k +#define LCF_USTACK0_SIZE 2k +#define LCF_ISTACK0_SIZE 1k + +#define LCF_CSA1_SIZE 8k +#define LCF_USTACK1_SIZE 2k +#define LCF_ISTACK1_SIZE 1k + +#define LCF_CSA2_SIZE 8k +#define LCF_USTACK2_SIZE 2k +#define LCF_ISTACK2_SIZE 1k + +#define LCF_HEAP_SIZE 4k + +#define LCF_CPU0 0 +#define LCF_CPU1 1 +#define LCF_CPU2 2 + +/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ +#define LCF_DEFAULT_HOST LCF_CPU0 +/*#define LCF_DEFAULT_HOST LCF_CPU1*/ +/*#define LCF_DEFAULT_HOST LCF_CPU2*/ + +#define LCF_DSPR2_START 0x50000000 +#define LCF_DSPR2_SIZE 96k + +#define LCF_DSPR1_START 0x60000000 +#define LCF_DSPR1_SIZE 240k + +#define LCF_DSPR0_START 0x70000000 +#define LCF_DSPR0_SIZE 240k + +#define LCF_CSA2_OFFSET (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE) +#define LCF_ISTACK2_OFFSET (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE) +#define LCF_USTACK2_OFFSET (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE) + +#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE) +#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE) +#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE) + +#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE) +#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE) +#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE) + +#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP2_OFFSET (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE) + +#define LCF_INTVEC0_START 0x802FE000 +#define LCF_INTVEC1_START 0x805FC000 +#define LCF_INTVEC2_START 0x805FE000 + +#define LCF_TRAPVEC0_START 0x80000100 +#define LCF_TRAPVEC1_START 0x80300000 +#define LCF_TRAPVEC2_START 0x80300100 + +#define LCF_STARTPTR_CPU0 0x80000000 +#define LCF_STARTPTR_CPU1 0x80300200 +#define LCF_STARTPTR_CPU2 0x80300220 + +#define LCF_STARTPTR_NC_CPU0 0xA0000000 +#define LCF_STARTPTR_NC_CPU1 0xA0300200 +#define LCF_STARTPTR_NC_CPU2 0xA0300220 + +#define INTTAB0 (LCF_INTVEC0_START) +#define INTTAB1 (LCF_INTVEC1_START) +#define INTTAB2 (LCF_INTVEC2_START) +#define TRAPTAB0 (LCF_TRAPVEC0_START) +#define TRAPTAB1 (LCF_TRAPVEC1_START) +#define TRAPTAB2 (LCF_TRAPVEC2_START) + +#define RESET LCF_STARTPTR_NC_CPU0 + +#include "tc1v1_6_2.lsl" + +// Specify a multi-core processor environment (mpe) + +processor mpe +{ + derivative = tc37; +} + +derivative tc37 +{ + core tc0 + { + architecture = TC1V1.6.2; + space_id_offset = 100; // add 100 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc1 // core 1 TC16E + { + architecture = TC1V1.6.2; + space_id_offset = 200; // add 200 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc2 // core 2 TC16P + { + architecture = TC1V1.6.2; + space_id_offset = 300; // add 300 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core vtc + { + architecture = TC1V1.6.2; + import tc0; // add all address spaces of core tc0 to core vtc for linking and locating + import tc1; // tc1 + import tc2; // tc2 + } + + bus sri + { + mau = 8; + width = 32; + + // map shared addresses one-to-one to real cores and virtual cores + map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc2:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + } + + memory dsram2 // Data Scratch Pad Ram + { + mau = 8; + size = 96k; + type = ram; + map (dest=bus:tc2:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); + map (dest=bus:sri, dest_offset=0x50000000, size=96k); + } + + memory psram2 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc2:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x50100000, size=64k); + } + + memory dsram1 // Data Scratch Pad Ram + { + mau = 8; + size = 240k; + type = ram; + map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); + map (dest=bus:sri, dest_offset=0x60000000, size=240k); + } + + memory psram1 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x60100000, size=64k); + } + + memory dsram0 // Data Scratch Pad Ram + { + mau = 8; + size = 240k; + type = ram; + map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); + map (dest=bus:sri, dest_offset=0x70000000, size=240k); + } + + memory psram0 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x70100000, size=64k); + } + + memory pfls0 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80000000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=3M); + } + + memory pfls1 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80300000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0300000, reserved, size=3M); + } + + memory dfls0 + { + mau = 8; + size = 256K; + type = reserved nvram; + map (dest=bus:sri, dest_offset=0xaf000000, size=256K); + } + + memory ucb + { + mau = 8; + size = 24k; + type = rom; + map (dest=bus:sri, dest_offset=0xaf400000, reserved, size=24k); + } + + memory cpu0_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90000000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=64k); + } + + memory cpu1_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90010000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0010000, reserved, size=64k); + } + + memory cpu2_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90020000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0020000, reserved, size=64k); + } + +#if (__VERSION__ >= 6003) + section_setup :vtc:linear + { + heap "heap" (min_size = (1k), fixed, align = 8); + } +#endif + + section_setup :vtc:linear + { + start_address + ( + symbol = "_START" + ); + } + + section_setup :vtc:linear + { + stack "ustack_tc0" (min_size = 1k, fixed, align = 8); + stack "istack_tc0" (min_size = 1k, fixed, align = 8); + stack "ustack_tc1" (min_size = 1k, fixed, align = 8); + stack "istack_tc1" (min_size = 1k, fixed, align = 8); + stack "ustack_tc2" (min_size = 1k, fixed, align = 8); + stack "istack_tc2" (min_size = 1k, fixed, align = 8); + } + + /*Section setup for the copy table*/ + section_setup :vtc:linear + { + copytable + ( + align = 4, + dest = linear, + table + { + symbol = "_lc_ub_table_tc0"; + space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa; + }, + table + { + symbol = "_lc_ub_table_tc1"; + space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa; + }, + table + { + symbol = "_lc_ub_table_tc2"; + space = :tc2:linear, :tc2:abs24, :tc2:abs18, :tc2:csa; + } + ); + } + + /*Sections located at absolute fixed address*/ + + section_layout :vtc:linear + { + /*Fixed memory Allocations for stack memory and CSA*/ + group (ordered) + { + group ustack2(align = 8, run_addr = mem:dsram2[LCF_USTACK2_OFFSET]) + { + stack "ustack_tc2" (size = LCF_USTACK2_SIZE); + } + "__USTACK2":= sizeof(group:ustack2) > 0 ? "_lc_ue_ustack_tc2" : 0; + "__USTACK2_END"="_lc_gb_ustack2"; + + group istack2(align = 8, run_addr = mem:dsram2[LCF_ISTACK2_OFFSET]) + { + stack "istack_tc2" (size = LCF_ISTACK2_SIZE); + } + "__ISTACK2":= sizeof(group:istack2) > 0 ? "_lc_ue_istack_tc2" : 0; + "__ISTACK2_END"="_lc_gb_istack2"; + + group (align = 64, attributes=rw, run_addr=mem:dsram2[LCF_CSA2_OFFSET]) + reserved "csa_tc2" (size = LCF_CSA2_SIZE); + "__CSA2":= "_lc_ub_csa_tc2"; + "__CSA2_END":= "_lc_ue_csa_tc2"; + } + group (ordered) + { + group ustack1(align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET]) + { + stack "ustack_tc1" (size = LCF_USTACK1_SIZE); + } + "__USTACK1":= sizeof(group:ustack1) > 0 ? "_lc_ue_ustack_tc1" : 0; + "__USTACK1_END"="_lc_gb_ustack1"; + + group istack1(align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET]) + { + stack "istack_tc1" (size = LCF_ISTACK1_SIZE); + } + "__ISTACK1":= sizeof(group:istack1) > 0 ? "_lc_ue_istack_tc1" : 0; + "__ISTACK1_END"="_lc_gb_istack1"; + + group (align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET]) + reserved "csa_tc1" (size = LCF_CSA1_SIZE); + "__CSA1":= "_lc_ub_csa_tc1"; + "__CSA1_END":= "_lc_ue_csa_tc1"; + } + group (ordered) + { + group ustack0(align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET]) + { + stack "ustack_tc0" (size = LCF_USTACK0_SIZE); + } + "__USTACK0":= sizeof(group:ustack0) > 0 ? "_lc_ue_ustack_tc0" : 0; + "__USTACK0_END"="_lc_gb_ustack0"; + + group istack0(align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET]) + { + stack "istack_tc0" (size = LCF_ISTACK0_SIZE); + } + "__ISTACK0":= sizeof(group:istack0) > 0 ? "_lc_ue_istack_tc0" : 0; + "__ISTACK0_END"="_lc_gb_istack0"; + + group (align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET]) + reserved "csa_tc0" (size = LCF_CSA0_SIZE); + "__CSA0":= "_lc_ub_csa_tc0"; + "__CSA0_END":= "_lc_ue_csa_tc0"; + } + + /*Fixed memory Allocations for _START*/ + group (ordered) + { + group reset (run_addr=RESET) + { + section "reset" ( size = 0x20, fill = 0x0800, attributes = r ) + { + select ".text.start"; + } + } + group interface_const (run_addr=mem:pfls0[0x0020]) + { + select "*.interface_const"; + } + "__IF_CONST" := addressof(group:interface_const); + "__START0" := LCF_STARTPTR_NC_CPU0; + "__START1" := LCF_STARTPTR_NC_CPU1; + "__START2" := LCF_STARTPTR_NC_CPU2; + } + + /*Fixed memory Allocations for Trap Vector Table*/ + group (ordered) + { + group trapvec_tc0 (align = 8, run_addr=LCF_TRAPVEC0_START) + { + section "trapvec_tc0" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu0*)"; + } + } + group trapvec_tc1 (align = 8, run_addr=LCF_TRAPVEC1_START) + { + section "trapvec_tc1" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu1*)"; + } + } + group trapvec_tc2 (align = 8, run_addr=LCF_TRAPVEC2_START) + { + section "trapvec_tc2" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu2*)"; + } + } + "__TRAPTAB_CPU0" := TRAPTAB0; + "__TRAPTAB_CPU1" := TRAPTAB1; + "__TRAPTAB_CPU2" := TRAPTAB2; + } + + /*Fixed memory Allocations for Start up code*/ + group (ordered) + { + group start_tc0 (run_addr=LCF_STARTPTR_NC_CPU0) + { + select "(.text.start_cpu0*)"; + } + group start_tc1 (run_addr=LCF_STARTPTR_NC_CPU1) + { + section "start_tc1" (size=0x20, attributes=rx, fill=0) + { + select "(.text.start_cpu1*)"; + } + } + group start_tc2 (run_addr=LCF_STARTPTR_NC_CPU2) + { + select "(.text.start_cpu2*)"; + } + "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 0; + "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 0; + } + + /*Fixed memory Allocations for Interrupt Vector Table*/ + group (ordered) + { + group int_tab_tc0 (ordered) + { +# include "inttab0.lsl" + } + group int_tab_tc1 (ordered) + { +# include "inttab1.lsl" + } + group int_tab_tc2 (ordered) + { +# include "inttab2.lsl" + } + "_lc_u_int_tab" = (LCF_INTVEC0_START); + "__INTTAB_CPU0" = (LCF_INTVEC0_START); + "__INTTAB_CPU1" = (LCF_INTVEC1_START); + "__INTTAB_CPU2" = (LCF_INTVEC2_START); + } + + /*Fixed memory Allocations for BMHD*/ + group (ordered) + { + group bmh_0_orig (run_addr=mem:ucb[0x0000]) + { + select ".rodata.bmhd_0_orig"; + } + group bmh_1_orig (run_addr=mem:ucb[0x0200]) + { + select ".rodata.bmhd_1_orig"; + } + group bmh_2_orig (run_addr=mem:ucb[0x0400]) + { + select ".rodata.bmhd_2_orig"; + } + group bmh_3_orig (run_addr=mem:ucb[0x0600]) + { + select ".rodata.bmhd_3_orig"; + } + group bmh_blank (run_addr=mem:ucb[0x0800]) + { + } + group bmh_0_copy (run_addr=mem:ucb[0x1000]) + { + select ".rodata.bmhd_0_copy"; + } + group bmh_1_copy (run_addr=mem:ucb[0x1200]) + { + select ".rodata.bmhd_1_copy"; + } + group bmh_2_copy (run_addr=mem:ucb[0x1400]) + { + select ".rodata.bmhd_2_copy"; + } + group bmh_3_copy (run_addr=mem:ucb[0x1600]) + { + select ".rodata.bmhd_3_copy"; + } + } + } + + /*Near Abbsolute Addressable Data Sections*/ + section_layout :vtc:abs18 + { + /*Near Absolute Data, selectable with patterns and user defined sections*/ + group + { + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) + { + select "(.zdata.zdata_cpu2|.zdata.zdata_cpu2.*)"; + select "(.zbss.zbss_cpu2|.zbss.zbss_cpu2.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) + { + select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1.*)"; + select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) + { + select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0.*)"; + select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0.*)"; + } + + group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) + { + select "(.zdata.zlmudata|.zdata.zlmudata.*)"; + select "(.zbss.zlmubss|.zbss.zlmubss.*)"; + } + } + + /*Near Absolute Data, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + group zdata_mcal(attributes=rw) + { + select ".zdata.dsprInit.cpu0.32bit"; + select ".zdata.dsprInit.cpu0.16bit"; + select ".zdata.dsprInit.cpu0.8bit"; + } + + group zdata_powerOn(attributes=rw) + { + select ".zdata.dsprPowerOnInit.cpu0.32bit"; + select ".zdata.dsprPowerOnInit.cpu0.16bit"; + select ".zdata.dsprPowerOnInit.cpu0.8bit"; + } + + group zbss_mcal(attributes=rw) + { + select ".zbss.dsprClearOnInit.cpu0.32bit"; + select ".zbss.dsprClearOnInit.cpu0.16bit"; + select ".zbss.dsprClearOnInit.cpu0.8bit"; + } + + group zbss_noClear(attributes=rw) + { + select ".zbss.dsprNoInit.cpu0.32bit"; + select ".zbss.dsprNoInit.cpu0.16bit"; + select ".zbss.dsprNoInit.cpu0.8bit"; + } + + group zbss_powerOn(attributes=rw) + { + select ".zbss.dsprPowerOnClear.cpu0.32bit"; + select ".zbss.dsprPowerOnClear.cpu0.16bit"; + select ".zbss.dsprPowerOnClear.cpu0.8bit"; + } + + group zdata(attributes=rw) + { + select "(.zdata|.zdata.*)"; + select "(.zbss|.zbss.*)"; + } + } + + /*Near Absolute Const, selectable with patterns and user defined sections*/ + group + { + group (ordered, align = 4, contiguous, run_addr=mem:pfls0) + { + select ".zrodata.Ifx_Ssw_Tc0.*"; + select ".zrodata.Ifx_Ssw_Tc1.*"; + select ".zrodata.Ifx_Ssw_Tc2.*"; + select ".zrodata.Cpu0_Main.*"; + select ".zrodata.Cpu1_Main.*"; + select ".zrodata.Cpu2_Main.*"; + + /*Near Absolute Const, selectable by toolchain*/ + select ".zrodata.const.cpu0.32bit"; + select ".zrodata.const.cpu0.16bit"; + select ".zrodata.const.cpu0.8bit"; + select ".zrodata.config.cpu0.32bit"; + select ".zrodata.config.cpu0.16bit"; + select ".zrodata.config.cpu0.8bit"; + select "(.zrodata|.zrodata.*)"; + } + } + } + + /*Relative A0/A1/A8/A9 Addressable Sections*/ + section_layout :vtc:linear + { + /*Relative A0 Addressable Data, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + select "(.data_a0.sdata|.data_a0.sdata.*)"; + select "(.bss_a0.sbss|.bss_a0.sbss.*)"; + } + "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; + "__A0_MEM" = "_SMALL_DATA_"; + + /*Relative A1 Addressable Const, selectable by toolchain*/ + /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a1 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a1 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a1 (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select "(.rodata_a1.srodata|.rodata_a1.srodata.*)"; + select "(.ldata|.ldata.*)"; + } + "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; + "__A1_MEM" = "_LITERAL_DATA_"; + + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + group a9 (ordered, align = 4, run_addr=mem:cpu0_dlmu) + { + select "(.data_a9.a9sdata|.data_a9.a9sdata.*)"; + select "(.bss_a9.a9sbss|.bss_a9.a9sbss.*)"; + } + "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; + "__A9_MEM" = "_A9_DATA_"; + + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a8 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a8 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a8 (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select "(.rodata_a8.a8srodata|.rodata_a8.a8srodata.*)"; + } + "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; + "__A8_MEM" = "_A8_DATA_"; + } + + /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ + section_layout :vtc:linear + { + /*Far Data Sections, selectable with patterns and user defined sections*/ + group + { + /*DSRAM sections*/ + group + { + group (ordered, attributes=rw, run_addr=mem:dsram2) + { + select ".data.Ifx_Ssw_Tc2.*"; + select ".data.Cpu2_Main.*"; + select "(.data.data_cpu2|.data.data_cpu2.*)"; + select ".bss.Ifx_Ssw_Tc2.*"; + select ".bss.Cpu2_Main.*"; + select "(.bss.bss_cpu2|.bss.bss_cpu2.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram1) + { + select ".data.Ifx_Ssw_Tc1.*"; + select ".data.Cpu1_Main.*"; + select "(.data.data_cpu1|.data.data_cpu1.*)"; + select ".bss.Ifx_Ssw_Tc1.*"; + select ".bss.Cpu1_Main.*"; + select "(.bss.bss_cpu1|.bss.bss_cpu1.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram0) + { + select ".data.Ifx_Ssw_Tc0.*"; + select ".data.Cpu0_Main.*"; + select "(.data.data_cpu0|.data.data_cpu0.*)"; + select ".bss.Ifx_Ssw_Tc0.*"; + select ".bss.Cpu0_Main.*"; + select "(.bss.bss_cpu0|.bss.bss_cpu0.*)"; + } + } + + /*LMU Data sections*/ + group + { + group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) + { + select "(.data.lmudata_cpu0|.data.lmudata_cpu0.*)"; + select "(.bss.lmubss_cpu0|.bss.lmubss_cpu0.*)"; + select "(.data.lmudata|.data.lmudata.*)"; + select "(.bss.lmubss|.bss.lmubss.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu1_dlmu) + { + select "(.data.lmudata_cpu1|.data.lmudata_cpu1.*)"; + select "(.bss.lmubss_cpu1|.bss.lmubss_cpu1.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu2_dlmu) + { + select "(.data.lmudata_cpu2|.data.lmudata_cpu2.*)"; + select "(.bss.lmubss_cpu2|.bss.lmubss_cpu2.*)"; + } + } + } + + /*Far Data Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + group data_mcal(attributes=rw) + { + select ".data.farDsprInit.cpu0.32bit"; + select ".data.farDsprInit.cpu0.16bit"; + select ".data.farDsprInit.cpu0.8bit"; + } + + group bss_mcal(attributes=rw) + { + select ".bss.farDsprClearOnInit.cpu0.32bit"; + select ".bss.farDsprClearOnInit.cpu0.16bit"; + select ".bss.farDsprClearOnInit.cpu0.8bit"; + } + + group bss_noInit(attributes=rw) + { + select ".bss.farDsprNoInit.cpu0.32bit"; + select ".bss.farDsprNoInit.cpu0.16bit"; + select ".bss.farDsprNoInit.cpu0.8bit"; + } + + group data(attributes=rw) + { + select "(.data|.data.*)"; + select "(.bss|.bss.*)"; + } + } + + /*Heap allocation*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, align = 4, run_addr = mem:dsram2[LCF_HEAP2_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET]) +# endif + { + heap "heap" (size = LCF_HEAP_SIZE); + } + + /*Far Const Sections, selectable with patterns and user defined sections*/ + group + { + group (ordered, align = 4, run_addr=mem:pfls0) + { + select ".rodata.Ifx_Ssw_Tc0.*"; + select ".rodata.Cpu0_Main.*"; + select "(.rodata.rodata_cpu0|.rodata.rodata_cpu0.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".rodata.Cpu1_Main.*"; + select ".rodata.Ifx_Ssw_Tc1.*"; + select "(.rodata.rodata_cpu1|.rodata.rodata_cpu1.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".rodata.Ifx_Ssw_Tc2.*"; + select ".rodata.Cpu2_Main.*"; + select "(.rodata.rodata_cpu2|.rodata.rodata_cpu2.*)"; + } + } + + /*Far Const Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select ".rodata.farConst.cpu0.32bit"; + select ".rodata.farConst.cpu0.16bit"; + select ".rodata.farConst.cpu0.8bit"; + select "(.rodata|.rodata.*)"; + } + } + + /* PSRAM Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Program Scratchpad Sections*/ + group + { + group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0) + { + select "(.text.cpu0_psram|.text.cpu0_psram.*)"; + select "(.text.psram_text_cpu0|.text.psram_text_cpu0.*)"; + } + group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1) + { + select "(.text.cpu1_psram|.text.cpu1_psram.*)"; + select "(.text.psram_text_cpu1|.text.psram_text_cpu1.*)"; + } + group code_psram2 (ordered, attributes=rwx, copy, run_addr=mem:psram2) + { + select "(.text.cpu2_psram|.text.cpu2_psram.*)"; + select "(.text.psram_text_cpu2|.text.psram_text_cpu2.*)"; + } + } + } + } + + /* FLS Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Cpu specific PFLASH Sections*/ + group + { + group (ordered, align = 4, run_addr=mem:pfls0) + { + select ".text.Ifx_Ssw_Tc0.*"; + select ".text.Cpu0_Main.*"; + select ".text.CompilerTasking.Ifx_C_Init"; + select "(.text.text_cpu0|.text.text_cpu0.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".text.Ifx_Ssw_Tc1.*"; + select ".text.Cpu1_Main.*"; + select "(.text.text_cpu1|.text.text_cpu1.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".text.Ifx_Ssw_Tc2.*"; + select ".text.Cpu2_Main.*"; + select "(.text.text_cpu2|.text.text_cpu2.*)"; + } + } + } + + /*Code Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, run_addr=mem:pfls0) +# endif + { + select ".text.fast.pfls.cpu0"; + select ".text.slow.pfls.cpu0"; + select ".text.5ms.pfls.cpu0"; + select ".text.10ms.pfls.cpu0"; + select ".text.callout.pfls.cpu0"; + select "(.text|.text.*)"; + } + } +} diff --git a/docs/HAL.md b/docs/HAL.md index 28f48b50d..148deaad7 100644 --- a/docs/HAL.md +++ b/docs/HAL.md @@ -44,8 +44,11 @@ flash. On some targets, this function may be empty. This function provides an implementation of the flash write function, using the target's IAP interface. `address` is the offset from the beginning of the flash area, `data` is the payload to be stored in the flash using the IAP interface, -and `len` is the size of the payload. `hal_flash_write` should return 0 upon success, -or a negative value in case of failure. +and `len` is the size of the payload. Implementations of this function must be able to +handle writes of any size and alignment. Targets with a minimum programmable size +\> 1 byte must implement the appropriate read-modify-write logic in order to enable +wolfBoot to perform unaligned single-byte writes. `hal_flash_write` should return 0 upon +success, or a negative value in case of failure. `void hal_flash_lock(void)` @@ -58,8 +61,9 @@ by the bootloader at the end of every write and erase operations. Called by the bootloader to erase part of the flash memory to allow subsequent boots. Erase operations must be performed via the specific IAP interface of the target microcontroller. `address` marks the start of the area that the bootloader wants to erase, and `len` specifies -the size of the area to be erased. This function must take into account the geometry of the flash -sectors, and erase all the sectors in between. +the size of the area to be erased. `address` is guaranteed to be aligned to `WOLFBOOT_SECTOR_SIZE`, +and `len` is guaranteed to be a multiple of `WOLFBOOT_SECTOR_SIZE`. This function must take into account +the geometry of the flash sectors, and erase all the sectors in between. `void hal_prepare_boot(void)` @@ -71,11 +75,14 @@ that the state of the microcontroller is restored to its original settings. WolfBoot can be compiled with the makefile option `EXT_FLASH=1`. When the external flash support is enabled, update and swap partitions can be associated to an external memory, and will use alternative -HAL function for read/write/erase access. +HAL function for read/write/erase access. It can also be used in any scenario where flash reads require +special handling and must be redirected to a custom implementation. Note that `EXT_FLASH=1` is incompatible +with the `NVM_FLASH_WRITEONCE` option. + To associate the update or the swap partition to an external memory, define `PART_UPDATE_EXT` and/or `PART_SWAP_EXT`, respectively. -The following functions are used to access the external memory, and must be defined when `EXT\_FLASH` +The following functions are used to access the external memory, and must be defined when `EXT_FLASH` is on: `int ext_flash_write(uintptr_t address, const uint8_t *data, int len)` @@ -83,7 +90,8 @@ is on: This function provides an implementation of the flash write function, using the external memory's specific interface. `address` is the offset from the beginning of the addressable space in the device, `data` is the payload to be stored, -and `len` is the size of the payload. `ext_flash_write` should return 0 upon success, +and `len` is the size of the payload. The function is subject to the same restrictions as +`hal_flash_write()`. `ext_flash_write` should return 0 upon success, or a negative value in case of failure. `int ext_flash_read(uintptr_t address, uint8_t *data, int len)` @@ -91,16 +99,18 @@ or a negative value in case of failure. This function provides an indirect read of the external memory, using the driver's specific interface. `address` is the offset from the beginning of the addressable space in the device, `data` is a pointer where payload is stored upon a successful -call, and `len` is the maximum size allowed for the payload. `ext_flash_read` should return 0 -upon success, or a negative value in case of failure. +call, and `len` is the maximum size allowed for the payload. This function must be able to handle +reads of any size and alignment. `ext_flash_read` should return 0 upon success, or a negative value +in case of failure. `int ext_flash_erase(uintptr_t address, int len)` Called by the bootloader to erase part of the external memory. Erase operations must be performed via the specific interface of the target driver (e.g. SPI flash). `address` marks the start of the area relative to the device, that the bootloader wants to erase, -and `len` specifies the size of the area to be erased. This function must take into account the -geometry of the sectors, and erase all the sectors in between. +and `len` specifies the size of the area to be erased. This function is subject to the same restrictions +as `hal_flash_erase()` and must take into account the geometry of the sectors, and erase all the sectors +in between. `void ext_flash_lock(void)` diff --git a/docs/compile.md b/docs/compile.md index 0cf28afe7..76fdca285 100644 --- a/docs/compile.md +++ b/docs/compile.md @@ -202,6 +202,7 @@ forced downgrade attacks. WolfBoot can be compiled with the makefile option `EXT_FLASH=1`. When the external flash support is enabled, update and swap partitions can be associated to an external memory, and will use alternative HAL function for read/write/erase access. + To associate the update or the swap partition to an external memory, define `PART_UPDATE_EXT` and/or `PART_SWAP_EXT`, respectively. By default, the makefile assumes that if an external memory is present, both `PART_UPDATE_EXT` and `PART_SWAP_EXT` are defined. @@ -214,6 +215,15 @@ copied in RAM to boot after verification. When external memory is used, the HAL API must be extended to define methods to access the custom memory. Refer to the [HAL](HAL.md) page for the description of the `ext_flash_*` API. +The `EXT_FLASH` option can also be used if the target device requires special handling for flash reads +(e.g. word size requirements or other restrictions), regardless of whether the flash is internal or external. + +Note that the `EXT_FLASH` option is incompatible with the `NVM_FLASH_WRITEONCE` option. Targets that need +both these options must implement the sector-based read-modify-erase-write sequence at the HAL layer. + +For an example of using `EXT_FLASH` to bypass read restrictions, (in this case, the inability to read from +erased flash due to ECC errors) on a platform with write-once flash, see the [infineon tricore port](../hal/aurix_tc3xx.c). + #### SPI devices In combination with the `EXT_FLASH=1` configuration parameter, it is possible to use a platform-specific SPI drivers, @@ -284,6 +294,13 @@ Note: if you are using an external FLASH (e.g. SPI) in combination with a flash By default, keys are directly incorporated in the firmware image. To store the keys in a separate, one-time programmable (OTP) flash memory, use the `FLASH_OTP_KEYSTORE=1` option. For more information, see [/docs/OTP-keystore.md](/docs/OTP-keystore.md). +### Prefer multi-sector flash erase operations + +wolfBoot HAL flash erase function must be able to handle erase lengths larger than `WOLFBOOT_SECTOR_SIZE`, even if the underlying flash controller does not. However, in some cases, wolfBoot defaults to +iterating over a range of flash sectors and erasing them one at a time. Setting the `FLASH_MULTI_SECTOR_ERASE=1` config option prevents this behavior when possible, configuring wolfBoot to instead prefer a +single HAL flash erase invocation with a larger erase length versus the iterative approach. On targets where multi-sector erases are more performant, this option can be used to dramatically speed up the +image swap procedure. + ### Using Mac OS/X If you see 0xC3 0xBF (C3BF) repeated in your factory.bin then your OS is using Unicode characters. diff --git a/docs/firmware_image.md b/docs/firmware_image.md index f9429c07c..4cceaa9a1 100644 --- a/docs/firmware_image.md +++ b/docs/firmware_image.md @@ -14,15 +14,20 @@ of 256B from the beginning of the flash partition. ## Firmware image header -Each (signed) firmware image is prepended with a fixed-size **image header**, containing -useful information about the firmware. The **image header** is padded to fit in 256B, in order -to guarantee that the entry point of the actual firmware is stored on the flash starting from -a 256-Bytes aligned address. This ensures that the bootloader can relocate the vector table before -chain-loading the firmware the interrupt continue to work properly after the boot is complete. +Each (signed) firmware image is prepended with a fixed-size **image header**, containing useful information about the +firmware. The exact size of the **image header** depends on the size of the image digest and signature, which depend on +the algorithms/key sizes used. Larger key sizes will result in a larger image header. The size of the image header is +determined by the build system and provided to the application code in the `IMAGE_HEADER_SIZE` macro. The size of the generated +image header is also output by the keytools during the signing operation. The **image header** data is padded out to the next +multiple of 256B, in order to guarantee that the entry point of the actual firmware is stored on the flash starting from a +256-Bytes aligned address. This ensures that the bootloader can relocate the vector table before chain-loading the firmware +so interrupts continue to work properly after the boot is complete. When porting wolfBoot to a platform that doesn't use wolfBoot's +Makefile-based build system, extra care should be taken to ensure `IMAGE_HEADER_SIZE` is set to a value that matches the output of +the wolfBoot `sign` key tool. ![Image header](png/image_header.png) -*The image header is stored at the beginning of the slot and the actual firmware image starts 256 Bytes after it* +*The image header is stored at the beginning of the slot and the actual firmware image starts `IMAGE_HEADER_SIZE` Bytes after it* ### Image header: Tags diff --git a/hal/aurix_tc3xx.c b/hal/aurix_tc3xx.c new file mode 100644 index 000000000..6282c25a2 --- /dev/null +++ b/hal/aurix_tc3xx.c @@ -0,0 +1,511 @@ +/* aurix_tc3xx.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include +#include +#include +#include + +/* wolfBoot headers */ +#include "image.h" /* for RAMFUNCTION */ +#include "loader.h" /* for wolfBoot_panic */ + +/* ILLD headers */ +#include "IfxCpu_reg.h" /* for CPU0_FLASHCON1 */ +#include "IfxFlash.h" /* for IfxFlash_eraseMultipleSectors, */ +#include "IfxPort.h" /* for IfxPort_* */ +#include "IfxScuRcu.h" /* for IfxScuRcu_performReset */ +#include "Ifx_Ssw_Infra.h" /* for Ifx_Ssw_jumpToFunction */ + +#define FLASH_MODULE (0) +#define UNUSED_PARAMETER (0) +#define WOLFBOOT_AURIX_RESET_REASON (0x5742) /* "WB" */ + +/* Helper macros to gets the base address of the page, wordline, or sector that + * contains byteAddress */ +#define GET_PAGE_ADDR(addr) \ + ((uintptr_t)(addr) & ~(IFXFLASH_PFLASH_PAGE_LENGTH - 1)) +#define GET_WORDLINE_ADDR(addr) \ + ((uintptr_t)(addr) & ~(IFXFLASH_PFLASH_WORDLINE_LENGTH - 1)) +#define GET_SECTOR_ADDR(addr) ((uintptr_t)(addr) & ~(WOLFBOOT_SECTOR_SIZE - 1)) + +/* RAM buffer to hold the contents of an entire flash sector*/ +static uint32_t sectorBuffer[WOLFBOOT_SECTOR_SIZE / sizeof(uint32_t)]; + +#define LED_PROG (0) +#define LED_ERASE (1) +#define LED_READ (2) +#define LED_WOLFBOOT (5) + +#ifdef WOLFBOOT_AURIX_GPIO_TIMING +#ifndef SWAP_LED_POLARITY +#define LED_ON(led) IfxPort_setPinLow(&MODULE_P00, (led)) +#define LED_OFF(led) IfxPort_setPinHigh(&MODULE_P00, (led)) +#else +#define LED_ON(led) IfxPort_setPinHigh(&MODULE_P00, (led)) +#define LED_OFF(led) IfxPort_setPinLow(&MODULE_P00, (led)) +#endif +#else +#define LED_ON(led) +#define LED_OFF(led) +#endif /* WOLFBOOT_AURIX_GPIO_TIMING */ + +/* Returns the SDK flash type enum based on the address */ +static IfxFlash_FlashType getFlashTypeFromAddr(uint32_t addr) +{ + IfxFlash_FlashType type = 0; + + if (addr >= IFXFLASH_DFLASH_START && addr <= IFXFLASH_DFLASH_END) { + /* Assuming D0 for simplicity */ + type = IfxFlash_FlashType_D0; + } + else if (addr >= IFXFLASH_PFLASH_P0_START && addr <= IFXFLASH_PFLASH_P0_END) + { + type = IfxFlash_FlashType_P0; + } + else if (addr >= IFXFLASH_PFLASH_P1_START && addr <= IFXFLASH_PFLASH_P1_END) + { + type = IfxFlash_FlashType_P1; + } + else { + /* bad address, panic for now */ + wolfBoot_panic(); + } + + return type; +} + +/* Programs a single page in flash */ +static void RAMFUNCTION programPage(uint32_t address, + const uint32_t* data, + IfxFlash_FlashType type) +{ + if (address % IFXFLASH_PFLASH_PAGE_LENGTH != 0) { + wolfBoot_panic(); + } + + const uint16 endInitSafetyPassword = + IfxScuWdt_getSafetyWatchdogPasswordInline(); + + IfxFlash_enterPageMode(address); + IfxFlash_waitUnbusy(FLASH_MODULE, type); + + for (size_t offset = 0; + offset < IFXFLASH_PFLASH_PAGE_LENGTH / sizeof(uint32_t); + offset += 2) + { + IfxFlash_loadPage2X32(address, data[offset], data[offset + 1]); + } + + IfxScuWdt_clearSafetyEndinitInline(endInitSafetyPassword); + IfxFlash_writePage(address); + IfxScuWdt_setSafetyEndinitInline(endInitSafetyPassword); + + IfxFlash_waitUnbusy(FLASH_MODULE, type); +} + +/* Performs a hardware erase verify check on the range specified by address and + * len. Returns true if the region is erased */ +static int RAMFUNCTION flashIsErased(uint32_t address, + int len, + IfxFlash_FlashType type) +{ + uint32_t base = 0; + + IfxFlash_clearStatus(UNUSED_PARAMETER); + + /* sector granularity */ + if (len > IFXFLASH_PFLASH_WORDLINE_LENGTH) { + base = GET_SECTOR_ADDR(address); + IfxFlash_eraseVerifySector(base); + IfxFlash_waitUnbusy(FLASH_MODULE, type); + } + /* wordline granularity */ + else if (len > IFXFLASH_PFLASH_PAGE_LENGTH) { + base = GET_WORDLINE_ADDR(address); + IfxFlash_verifyErasedWordLine(base); + IfxFlash_waitUnbusy(FLASH_MODULE, type); + } + /* page granularity */ + else if (len > 0) { + base = GET_PAGE_ADDR(address); + IfxFlash_verifyErasedPage(base); + IfxFlash_waitUnbusy(FLASH_MODULE, type); + } + /* error on 0 len for now */ + else { + wolfBoot_panic(); + } + + /* No erase verify error means block is erased */ + return (DMU_HF_ERRSR.B.EVER == 0) ? 1 : 0; +} + +/* Returns true if any of the pages spanned by address and len are erased */ +static int RAMFUNCTION containsErasedPage(uint32_t address, + size_t len, + IfxFlash_FlashType type) +{ + const uint32_t startPage = GET_PAGE_ADDR(address); + const uint32_t endPage = GET_PAGE_ADDR(address + len - 1); + + for (uint32_t page = startPage; page <= endPage; + page += IFXFLASH_PFLASH_PAGE_LENGTH) + { + if (flashIsErased(page, IFXFLASH_PFLASH_PAGE_LENGTH, type)) { + return 1; + } + } + + return 0; +} + +/* Programs the contents of the cached sector buffer to flash */ +static void RAMFUNCTION programCachedSector(uint32_t sectorAddress, + IfxFlash_FlashType type) +{ + const uint16 endInitSafetyPassword = + IfxScuWdt_getSafetyWatchdogPasswordInline(); + uint32_t pageAddr = sectorAddress; + + /* Burst program the whole sector with values from sectorBuffer */ + for (int i = 0; i < WOLFBOOT_SECTOR_SIZE / IFXFLASH_PFLASH_BURST_LENGTH; + i++) + { + IfxFlash_enterPageMode(pageAddr); + + /* Wait until page mode is entered */ + IfxFlash_waitUnbusy(FLASH_MODULE, type); + + /* Load a burst worth of data into the page */ + for (size_t offset = 0; + offset < IFXFLASH_PFLASH_BURST_LENGTH / (2 * sizeof(uint32_t)); + offset++) + { + size_t bufferIndex = + i * (IFXFLASH_PFLASH_BURST_LENGTH / sizeof(uint32_t)) + + (offset * 2); + + IfxFlash_loadPage2X32(UNUSED_PARAMETER, + sectorBuffer[bufferIndex], + sectorBuffer[bufferIndex + 1]); + } + + /* Write the page */ + IfxScuWdt_clearSafetyEndinitInline(endInitSafetyPassword); + IfxFlash_writeBurst(pageAddr); + IfxScuWdt_setSafetyEndinitInline(endInitSafetyPassword); + + /* Wait until the page is written in the Program Flash memory */ + IfxFlash_waitUnbusy(FLASH_MODULE, type); + + pageAddr += IFXFLASH_PFLASH_BURST_LENGTH; + } +} + +/* Programs unaligned input data to flash, assuming the underlying memory is + * erased */ +void RAMFUNCTION programBytesToErasedFlash(uint32_t address, + const uint8_t* data, + int size, + IfxFlash_FlashType type) +{ + uint32_t pageBuffer[IFXFLASH_PFLASH_PAGE_LENGTH / sizeof(uint32_t)]; + uint32_t pageAddress = address & ~(IFXFLASH_PFLASH_PAGE_LENGTH - 1); + uint32_t offset = address % IFXFLASH_PFLASH_PAGE_LENGTH; + uint32_t toWrite; + + while (size > 0) { + /* Calculate the number of bytes to write in the current page */ + toWrite = IFXFLASH_PFLASH_PAGE_LENGTH - offset; + if (toWrite > size) { + toWrite = size; + } + + /* Fill the page buffer with the erased byte value */ + memset(pageBuffer, FLASH_BYTE_ERASED, IFXFLASH_PFLASH_PAGE_LENGTH); + + /* Copy the new data into the page buffer at the correct offset */ + memcpy((uint8_t*)pageBuffer + offset, data, toWrite); + + /* Write the modified page buffer back to flash */ + programPage(pageAddress, pageBuffer, type); + + size -= toWrite; + data += toWrite; + address += toWrite; + pageAddress = address & ~(IFXFLASH_PFLASH_PAGE_LENGTH - 1); + offset = address % IFXFLASH_PFLASH_PAGE_LENGTH; + } +} + +/* Directly reads a page from PFLASH using word-aligned reads/writes */ +static void readPage32Aligned(uint32_t pageAddr, uint32_t* data) +{ + uint32_t* ptr = (uint32_t*)pageAddr; + + for (int i = 0; i < IFXFLASH_PFLASH_PAGE_LENGTH / sizeof(uint32_t); i++) { + *data = *ptr; + data++; + ptr++; + } +} + +/* reads an entire flash sector into the RAM cache, making sure to never read + * any pages from flash that are erased */ +static void cacheSector(uint32_t sectorAddress, IfxFlash_FlashType type) +{ + const uint32_t startPage = GET_PAGE_ADDR(sectorAddress); + const uint32_t endPage = + GET_PAGE_ADDR(sectorAddress + WOLFBOOT_SECTOR_SIZE - 1); + uint32_t* pageInSectorBuffer; + + /* Iterate over every page in the sector, caching its contents if not + * erased, and caching 0s if erased */ + for (uint32_t page = startPage; page <= endPage; + page += IFXFLASH_PFLASH_PAGE_LENGTH) + { + pageInSectorBuffer = + sectorBuffer + ((page - sectorAddress) / sizeof(uint32_t)); + + if (flashIsErased(page, IFXFLASH_PFLASH_PAGE_LENGTH, type)) { + memset(pageInSectorBuffer, + FLASH_BYTE_ERASED, + IFXFLASH_PFLASH_PAGE_LENGTH); + } + else { + readPage32Aligned(page, pageInSectorBuffer); + } + } +} + +/* This function is called by the bootloader at the very beginning of the + * execution. Ideally, the implementation provided configures the clock settings + * for the target microcontroller, to ensure that it runs at at the required + * speed to shorten the time required for the cryptography primitives to verify + * the firmware images*/ +void hal_init(void) +{ +#ifdef WOLFBOOT_AURIX_GPIO_TIMING + IfxPort_setPinModeOutput(&MODULE_P00, + LED_WOLFBOOT, + IfxPort_OutputMode_pushPull, + IfxPort_OutputIdx_general); + IfxPort_setPinModeOutput(&MODULE_P00, + LED_PROG, + IfxPort_OutputMode_pushPull, + IfxPort_OutputIdx_general); + IfxPort_setPinModeOutput(&MODULE_P00, + LED_ERASE, + IfxPort_OutputMode_pushPull, + IfxPort_OutputIdx_general); + IfxPort_setPinModeOutput(&MODULE_P00, + LED_READ, + IfxPort_OutputMode_pushPull, + IfxPort_OutputIdx_general); +#endif /* WOLFBOOT_AURIX_GPIO_TIMING */ + + LED_ON(LED_WOLFBOOT); + LED_OFF(LED_PROG); + LED_OFF(LED_ERASE); + LED_OFF(LED_READ); +} + +/* + * This function provides an implementation of the flash write function, using + * the target's IAP interface. address is the offset from the beginning of the + * flash area, data is the payload to be stored in the flash using the IAP + * interface, and len is the size of the payload. hal_flash_write should return + * 0 upon success, or a negative value in case of failure. + */ +int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t* data, int size) +{ + LED_ON(LED_PROG); + + /* base address of containing sector (TODO what if size spans sectors?) + */ + const uint32_t sectorAddress = GET_SECTOR_ADDR(address); + const IfxFlash_FlashType type = getFlashTypeFromAddr(address); + + /* Determine the range of pages affected */ + const uint32_t startPage = GET_PAGE_ADDR(address); + const uint32_t endPage = GET_PAGE_ADDR(address + size - 1); + + /* Flag to check if sector read-modify-write is necessary */ + bool needsSectorRmw = false; + + /* Check if any page within the range is not erased */ + for (uint32_t page = startPage; page <= endPage; + page += IFXFLASH_PFLASH_PAGE_LENGTH) + { + if (!flashIsErased(page, IFXFLASH_PFLASH_PAGE_LENGTH, type)) { + needsSectorRmw = true; + break; + } + } + + /* If a page within the range is erased, we need to read-modify-write the + * whole sector */ + if (needsSectorRmw) { + /* Read entire sector into RAM */ + cacheSector(sectorAddress, type); + + /* Erase the entire sector */ + hal_flash_erase(sectorAddress, WOLFBOOT_SECTOR_SIZE); + + /* Modify the relevant part of the RAM sector buffer */ + size_t offsetInSector = address - sectorAddress; + memcpy((uint8_t*)sectorBuffer + offsetInSector, data, size); + + /* Program the modified sector back into flash */ + programCachedSector(sectorAddress, type); + } + else { + /* All affected pages are erased, program the data directly */ + programBytesToErasedFlash(address, data, size, type); + } + + LED_OFF(LED_PROG); + + return 0; +} + +/* Called by the bootloader to erase part of the flash memory to allow + * subsequent boots. Erase operations must be performed via the specific IAP + * interface of the target microcontroller. address marks the start of the area + * that the bootloader wants to erase, and len specifies the size of the area to + * be erased. This function must take into account the geometry of the flash + * sectors, and erase all the sectors in between. */ +int RAMFUNCTION hal_flash_erase(uint32_t address, int len) +{ + LED_ON(LED_ERASE); + + const uint32_t sectorAddr = GET_SECTOR_ADDR(address); + const size_t numSectors = + (len == 0) ? 0 : ((len - 1) / WOLFBOOT_SECTOR_SIZE) + 1; + const IfxFlash_FlashType type = getFlashTypeFromAddr(address); + + /* Disable ENDINIT protection */ + const uint16 endInitSafetyPassword = + IfxScuWdt_getSafetyWatchdogPasswordInline(); + IfxScuWdt_clearSafetyEndinitInline(endInitSafetyPassword); + + IfxFlash_eraseMultipleSectors(sectorAddr, numSectors); + + /* Reenable ENDINIT protection */ + IfxScuWdt_setSafetyEndinitInline(endInitSafetyPassword); + + IfxFlash_waitUnbusy(FLASH_MODULE, type); + + LED_OFF(LED_ERASE); + + return 0; +} + +/* This function is called by the bootloader at a very late stage, before + * chain-loading the firmware in the next stage. This can be used to revert all + * the changes made to the clock settings, to ensure that the state of the + * microcontroller is restored to its original settings */ +void hal_prepare_boot(void) +{ +} + +/* If the IAP interface of the flash memory of the target requires it, this + * function is called before every write and erase operations to unlock write + * access to the flash. On some targets, this function may be empty. */ +void hal_flash_unlock(void) +{ +} + +/* If the IAP interface of the flash memory requires locking/unlocking, this + * function restores the flash write protection by excluding write accesses. + * This function is called by the bootloader at the end of every write and erase + * operations. */ +void hal_flash_lock(void) +{ +} + +int RAMFUNCTION ext_flash_write(uintptr_t address, const uint8_t* data, int len) +{ + return hal_flash_write(address, data, len); +} + +/* + * Reads data from flash memory, first checking if the data is erased and + * returning dummy erased byte values to prevent ECC errors + */ +int RAMFUNCTION ext_flash_read(uintptr_t address, uint8_t* data, int len) +{ + int bytesRead = 0; + + LED_ON(LED_READ); + + const IfxFlash_FlashType type = getFlashTypeFromAddr(address); + + while (bytesRead < len) { + uint32_t pageAddress = GET_PAGE_ADDR(address); + uint32_t offset = address % IFXFLASH_PFLASH_PAGE_LENGTH; + + int isErased = + flashIsErased(pageAddress, IFXFLASH_PFLASH_PAGE_LENGTH, type); + + while (offset < IFXFLASH_PFLASH_PAGE_LENGTH && bytesRead < len) { + if (isErased) { + data[bytesRead] = FLASH_BYTE_ERASED; + } + else { + data[bytesRead] = *((uint8_t*)address); + } + address++; + bytesRead++; + offset++; + } + } + + LED_OFF(LED_READ); + + return 0; +} + +int RAMFUNCTION ext_flash_erase(uintptr_t address, int len) +{ + return hal_flash_erase(address, len); +} + +void RAMFUNCTION ext_flash_lock(void) +{ + hal_flash_lock(); +} + +void RAMFUNCTION ext_flash_unlock(void) +{ + hal_flash_unlock(); +} + +void do_boot(const uint32_t* app_offset) +{ + LED_OFF(LED_WOLFBOOT); + Ifx_Ssw_jumpToFunction((void (*)(void))app_offset); +} + +void arch_reboot(void) +{ + IfxScuRcu_performReset(IfxScuRcu_ResetType_system, + WOLFBOOT_AURIX_RESET_REASON); +} diff --git a/options.mk b/options.mk index 14ae9cdc0..20174bf0c 100644 --- a/options.mk +++ b/options.mk @@ -819,6 +819,10 @@ ifeq ($(FSP), 1) $(foreach option,$(X86_FSP_OPTIONS),$(if $($(option)), $(eval CFLAGS += -D$(option)=$($(option))))) endif +ifeq ($(FLASH_MULTI_SECTOR_ERASE),1) + CFLAGS+=-DWOLFBOOT_FLASH_MULTI_SECTOR_ERASE +endif + CFLAGS+=$(CFLAGS_EXTRA) OBJS:=$(OBJS_EXTRA) $(OBJS) diff --git a/src/image.c b/src/image.c index f5b755b8b..1c3cf19a4 100644 --- a/src/image.c +++ b/src/image.c @@ -285,7 +285,6 @@ static void wolfBoot_verify_signature(uint8_t key_slot, { int ret; uint8_t output[IMAGE_SIGNATURE_SIZE]; - int output_sz = (int)sizeof(output); uint8_t* digest_out = NULL; uint8_t *pubkey = keystore_get_buffer(key_slot); int pubkey_sz = keystore_get_size(key_slot); diff --git a/src/libwolfboot.c b/src/libwolfboot.c index 541f4cde8..0552adcc9 100644 --- a/src/libwolfboot.c +++ b/src/libwolfboot.c @@ -120,11 +120,13 @@ static uint32_t ext_cache; #if defined(__WOLFBOOT) || defined (UNIT_TEST) #define WOLFSSL_MISC_INCLUDED /* allow misc.c code to be inlined */ #include /* for ByteReverseWord32 */ +#if defined(EXT_ENCRYPTED) || defined(UNIT_TEST) static uint32_t wb_reverse_word32(uint32_t x) { return ByteReverseWord32(x); } #endif +#endif static const uint32_t wolfboot_magic_trail = WOLFBOOT_MAGIC_TRAIL; diff --git a/src/update_flash.c b/src/update_flash.c index cc0d4dc1d..ec43c0ffc 100644 --- a/src/update_flash.c +++ b/src/update_flash.c @@ -229,7 +229,12 @@ static int wolfBoot_swap_and_final_erase(int resume) wolfBoot_get_partition_state(PART_UPDATE, &st); /* read trailer */ +#if defined(EXT_FLASH) && PARTN_IS_EXT(PART_BOOT) + ext_flash_read((uintptr_t)(boot->hdr + tmpBootPos), (void*)tmpBuffer, + sizeof(tmpBuffer)); +#else memcpy(tmpBuffer, boot->hdr + tmpBootPos, sizeof(tmpBuffer)); +#endif /* check for trailing magic (BOOT) */ /* final swap and erase flag is WOLFBOOT_MAGIC_TRAIL */ @@ -475,7 +480,6 @@ static int wolfBoot_get_total_size(struct wolfBoot_image* boot, static int RAMFUNCTION wolfBoot_update(int fallback_allowed) { - int flagRet; uint32_t total_size = 0; const uint32_t sector_size = WOLFBOOT_SECTOR_SIZE; uint32_t sector = 0; @@ -484,7 +488,6 @@ static int RAMFUNCTION wolfBoot_update(int fallback_allowed) * magic has not been set flag will have an un-determined value when we go * to check it */ uint8_t flag = SECT_FLAG_NEW; - uint8_t st; struct wolfBoot_image boot, update, swap; uint16_t update_type; uint32_t fw_size; @@ -494,6 +497,7 @@ static int RAMFUNCTION wolfBoot_update(int fallback_allowed) uint8_t nonce[ENCRYPT_NONCE_SIZE]; #endif #ifdef DELTA_UPDATES + uint8_t st; int inverse = 0; int resume = 0; int stateRet = -1; @@ -501,10 +505,12 @@ static int RAMFUNCTION wolfBoot_update(int fallback_allowed) uint32_t up_v; #endif uint32_t cur_ver, upd_ver; +#ifdef WOLFBOOT_FLASH_MULTI_SECTOR_ERASE + size_t remainderBytes; +#endif wolfBoot_printf("Staring Update (fallback allowed %d)\n", fallback_allowed); - /* No Safety check on open: we might be in the middle of a broken update */ wolfBoot_open_image(&update, PART_UPDATE); wolfBoot_open_image(&boot, PART_BOOT); @@ -657,6 +663,26 @@ static int RAMFUNCTION wolfBoot_update(int fallback_allowed) total_size = wolfBoot_get_total_size(&boot, &update); } } + +#ifdef WOLFBOOT_FLASH_MULTI_SECTOR_ERASE +/* Performant option: Erase remainder of flash sectors in one HAL command */ + +#ifdef NVM_FLASH_WRITEONCE + /* erase up until the start of the second-to-last sector for writeonce */ + remainderBytes = + WOLFBOOT_PARTITION_SIZE - (sector * sector_size) - (2 * sector_size); +#else + /* erase up until the start of the last sector */ + remainderBytes = + WOLFBOOT_PARTITION_SIZE - (sector * sector_size) - sector_size; +#endif + wb_flash_erase(&boot, sector * sector_size, remainderBytes); + wb_flash_erase(&update, sector * sector_size, remainderBytes); + +#else /* WOLFBOOT_FLASH_MULTI_SECTOR_ERASE */ +/* Smaller code size option: Iterate over every remaining sector and erase it + * individually. Required on some targets (stm32f4) to pass code size check */ + /* erase to the last sector, writeonce has 2 sectors */ while((sector * sector_size) < WOLFBOOT_PARTITION_SIZE - sector_size @@ -668,6 +694,9 @@ static int RAMFUNCTION wolfBoot_update(int fallback_allowed) wb_flash_erase(&update, sector * sector_size, sector_size); sector++; } + +#endif /* !WOLFBOOT_FLASH_MULTI_SECTOR_ERASE */ + /* start re-entrant final erase, return code is only for resumption in * wolfBoot_start*/ wolfBoot_swap_and_final_erase(0); @@ -699,8 +728,7 @@ static int RAMFUNCTION wolfBoot_update(int fallback_allowed) wb_flash_erase(&boot, sector * sector_size, sector_size); sector++; } - st = IMG_STATE_SUCCESS; - wolfBoot_set_partition_state(PART_BOOT, st); + wolfBoot_set_partition_state(PART_BOOT, IMG_STATE_SUCCESS); #ifdef EXT_FLASH ext_flash_lock(); diff --git a/tools/config.mk b/tools/config.mk index 32e1abac0..2be184ff4 100644 --- a/tools/config.mk +++ b/tools/config.mk @@ -80,6 +80,7 @@ ifeq ($(ARCH),) DISK_LOCK_PASSWORD?= FLASH_OTP_KEYSTORE?=0 BIG_ENDIAN?=0 + FLASH_MULTI_SECTOR_ERASE=0 endif CONFIG_VARS:= ARCH TARGET SIGN HASH MCUXSDK MCUXPRESSO MCUXPRESSO_CPU MCUXPRESSO_DRIVERS \ diff --git a/tools/scripts/tc3xx/gen-tc3xx-keys.sh b/tools/scripts/tc3xx/gen-tc3xx-keys.sh new file mode 100644 index 000000000..5bfc13da5 --- /dev/null +++ b/tools/scripts/tc3xx/gen-tc3xx-keys.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +set -euxo pipefail + +(cd ../../../ && tools/keytools/keygen --rsa4096 -g priv.der) diff --git a/tools/scripts/tc3xx/gen-tc3xx-signed-test-apps-debug.sh b/tools/scripts/tc3xx/gen-tc3xx-signed-test-apps-debug.sh new file mode 100644 index 000000000..d3d4b6067 --- /dev/null +++ b/tools/scripts/tc3xx/gen-tc3xx-signed-test-apps-debug.sh @@ -0,0 +1,6 @@ +#!/bin/bash + +set -euxo pipefail + +../../keytools/sign --rsa4096 --sha256 "../../../IDE/AURIX/test-app/TriCore Debug (GCC)/test-app.bin" ../../../priv.der 1 +../../keytools/sign --rsa4096 --sha256 "../../../IDE/AURIX/test-app/TriCore Debug (GCC)/test-app.bin" ../../../priv.der 2 diff --git a/tools/scripts/tc3xx/gen-tc3xx-signed-test-apps-release.sh b/tools/scripts/tc3xx/gen-tc3xx-signed-test-apps-release.sh new file mode 100644 index 000000000..389c3ee7d --- /dev/null +++ b/tools/scripts/tc3xx/gen-tc3xx-signed-test-apps-release.sh @@ -0,0 +1,6 @@ +#!/bin/bash + +set -euxo pipefail + +../../keytools/sign --rsa4096 --sha256 "../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin" ../../../priv.der 1 +../../keytools/sign --rsa4096 --sha256 "../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin" ../../../priv.der 2 diff --git a/tools/scripts/tc3xx/gen-tc3xx-target.sh b/tools/scripts/tc3xx/gen-tc3xx-target.sh new file mode 100644 index 000000000..e91a26520 --- /dev/null +++ b/tools/scripts/tc3xx/gen-tc3xx-target.sh @@ -0,0 +1,29 @@ +#!/bin/bash + +set -euxo pipefail + +TARGET_H_TEMPLATE=../../../include/target.h.in +TARGET_H_FILE=../../../include/target.h + +WOLFBOOT_SECTOR_SIZE=0x4000 +WOLFBOOT_PARTITION_SIZE=0x180000 +WOLFBOOT_PARTITION_BOOT_ADDRESS=0xA0300000 +WOLFBOOT_PARTITION_UPDATE_ADDRESS=0xA0480000 +WOLFBOOT_PARTITION_SWAP_ADDRESS=0xA0020000 +WOLFBOOT_DTS_BOOT_ADDRESS= +WOLFBOOT_DTS_UPDATE_ADDRESS= +WOLFBOOT_LOAD_ADDRESS= +WOLFBOOT_LOAD_DTS_ADDRESS= + +cat $TARGET_H_TEMPLATE | \ + sed -e "s/@WOLFBOOT_PARTITION_SIZE@/$WOLFBOOT_PARTITION_SIZE/g" | \ + sed -e "s/@WOLFBOOT_SECTOR_SIZE@/$WOLFBOOT_SECTOR_SIZE/g" | \ + sed -e "s/@WOLFBOOT_PARTITION_BOOT_ADDRESS@/$WOLFBOOT_PARTITION_BOOT_ADDRESS/g" | \ + sed -e "s/@WOLFBOOT_PARTITION_UPDATE_ADDRESS@/$WOLFBOOT_PARTITION_UPDATE_ADDRESS/g" | \ + sed -e "s/@WOLFBOOT_PARTITION_SWAP_ADDRESS@/$WOLFBOOT_PARTITION_SWAP_ADDRESS/g" | \ + sed -e "s/@WOLFBOOT_DTS_BOOT_ADDRESS@/$WOLFBOOT_DTS_BOOT_ADDRESS/g" | \ + sed -e "s/@WOLFBOOT_DTS_UPDATE_ADDRESS@/$WOLFBOOT_DTS_UPDATE_ADDRESS/g" | \ + sed -e "s/@WOLFBOOT_LOAD_ADDRESS@/$WOLFBOOT_LOAD_ADDRESS/g" | \ + sed -e "s/@WOLFBOOT_LOAD_DTS_ADDRESS@/$WOLFBOOT_LOAD_DTS_ADDRESS/g" \ + > $TARGET_H_FILE + diff --git a/tools/scripts/tc3xx/wolfBoot-loadAll-debug.cmm b/tools/scripts/tc3xx/wolfBoot-loadAll-debug.cmm new file mode 100644 index 000000000..60c494144 --- /dev/null +++ b/tools/scripts/tc3xx/wolfBoot-loadAll-debug.cmm @@ -0,0 +1,31 @@ +system.down +system.up + + +LOCAL &wolfBoot &testApp &updateApp +&wolfBoot="..\..\..\IDE\AURIX\wolfBoot-tc3xx\TriCore Debug (GCC)\wolfBoot-tc3xx.elf" +&testApp="..\..\..\IDE\AURIX\test-app\TriCore Debug (GCC)\test-app_v1_signed.bin" +&updateApp="..\..\..\IDE\AURIX\test-app\TriCore Debug (GCC)\test-app_v2_signed.bin" + +DO ~~/demo/tricore/flash/tc37x.cmm PREPAREONLY + +flash.erase all + +flash.reprogram all /erase +data.load.binary "&testApp" 0xA0300000 +data.load.binary "&updateApp" 0xA0480000 +data.load.elf "&wolfBoot" +flash.reprogram off + +break.set core0_main + +system.down +system.up +go + +; Bring up the important views +SYStem +Frame /Locals /Caller +List + + diff --git a/tools/scripts/tc3xx/wolfBoot-loadAll-release.cmm b/tools/scripts/tc3xx/wolfBoot-loadAll-release.cmm new file mode 100644 index 000000000..8ab0f850c --- /dev/null +++ b/tools/scripts/tc3xx/wolfBoot-loadAll-release.cmm @@ -0,0 +1,31 @@ +system.down +system.up + + +LOCAL &wolfBoot &testApp &updateApp +&wolfBoot="..\..\..\IDE\AURIX\wolfBoot-tc3xx\TriCore Release (GCC)\wolfBoot-tc3xx.elf" +&testApp="..\..\..\IDE\AURIX\test-app\TriCore Release (GCC)\test-app_v1_signed.bin" +&updateApp="..\..\..\IDE\AURIX\test-app\TriCore Release (GCC)\test-app_v2_signed.bin" + +DO ~~/demo/tricore/flash/tc37x.cmm PREPAREONLY + +flash.erase all + +flash.reprogram all /erase +data.load.binary "&testApp" 0xA0300000 +data.load.binary "&updateApp" 0xA0480000 +data.load.elf "&wolfBoot" +flash.reprogram off + +break.set core0_main + +system.down +system.up +go + +; Bring up the important views +SYStem +Frame /Locals /Caller +List + +