checkInput.v

`timescale 1ns / 1ps
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// Company: 
// Engineer: 
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// Create Date: 12/01/2019 06:24:08 PM
// Design Name: 
// Module Name: checkInput
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description:
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// Dependencies: 
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module checkInput(reset, rand_in, switch_in, out);

input  reset;
input  [4:0] rand_in, switch_in;
output  out;

wire reset;
wire [4:0] rand_in, switch_in;

assign out = (reset)? 0 : (rand_in == switch_in)? 1 : 0;

endmodule