test axi stream stack overflow

dbhi · Nov 30, 2019 · 1d12db7 · 1d12db7
1 parent 16cb38a
commit 1d12db7
Showing 1 changed file with 29 additions and 16 deletions.
diff --git a/examples/vhdl/array_axis_vcs/src/test/tb_axis_loop.vhd b/examples/vhdl/array_axis_vcs/src/test/tb_axis_loop.vhd
@@ -34,10 +34,15 @@ architecture tb of tb_axis_loop is
   constant clk_period : time    := 20 ns;
   constant data_width : natural := 32;
 
+  constant block_length : natural := 256*128*4;
+
   -- AXI4Stream Verification Components
 
-  constant master_axi_stream : axi_stream_master_t := new_axi_stream_master(data_length => data_width);
-  constant slave_axi_stream  : axi_stream_slave_t  := new_axi_stream_slave(data_length => data_width);
+  constant master_axi_stream : axi_stream_master_t := new_axi_stream_master (data_length => data_width, actor => new_actor(inbox_size => 64, outbox_size => 64));
+  constant slave_axi_stream  : axi_stream_slave_t  := new_axi_stream_slave  (data_length => data_width, actor => new_actor(inbox_size => 64, outbox_size => 64));
+
+  --constant master_axi_stream : axi_stream_master_t := new_axi_stream_master (data_length => data_width);
+  --constant slave_axi_stream  : axi_stream_slave_t  := new_axi_stream_slave  (data_length => data_width);
 
   -- Signals to/from the UUT from/to the verification components
 
@@ -87,12 +92,16 @@ begin
 
     info("Sending m_I of size " & to_string(height(m_I)) & "x" & to_string(width(m_I)) & " to UUT...");
 
-    for y in 0 to height(m_I)-1 loop
-      for x in 0 to width(m_I)-1 loop
-        wait until rising_edge(clk);
-        if x = width(m_I)-1 then last := '1'; else last := '0'; end if;
-        push_axi_stream(net, master_axi_stream, std_logic_vector(to_signed(get(m_I, x, y), data_width)) , tlast => last);
-      end loop;
+    --for y in 0 to height(m_I)-1 loop
+    --  for x in 0 to width(m_I)-1 loop
+    --    wait until rising_edge(clk);
+    --    if x = width(m_I)-1 then last := '1'; else last := '0'; end if;
+    --    push_axi_stream(net, master_axi_stream, std_logic_vector(to_signed(get(m_I, x, y), data_width)) , tlast => last);
+    --  end loop;
+    --end loop;
+
+    for y in 0 to block_length-1 loop
+      push_axi_stream(net, master_axi_stream, std_logic_vector(to_signed(0, data_width)) , tlast => last);
     end loop;
 
     info("m_I sent!");
@@ -111,14 +120,18 @@ begin
 
     info("Receiving m_O of size " & to_string(height(m_O)) & "x" & to_string(width(m_O)) & " from UUT...");
 
-    for y in 0 to height(m_O)-1 loop
-      for x in 0 to width(m_O)-1 loop
-        pop_axi_stream(net, slave_axi_stream, tdata => o, tlast => last);
-        if (x = width(m_O)-1) and (last='0') then
-          error("Something went wrong. Last misaligned!");
-        end if;
-        set(m_O, x, y, to_integer(signed(o)));
-      end loop;
+    --for y in 0 to height(m_O)-1 loop
+    --  for x in 0 to width(m_O)-1 loop
+    --    pop_axi_stream(net, slave_axi_stream, tdata => o, tlast => last);
+    --    if (x = width(m_O)-1) and (last='0') then
+    --      error("Something went wrong. Last misaligned!");
+    --    end if;
+    --    set(m_O, x, y, to_integer(signed(o)));
+    --  end loop;
+    --end loop;
+
+    for y in 0 to block_length-1 loop
+      pop_axi_stream(net, slave_axi_stream, tdata => o, tlast => last);
     end loop;
 
     info("m_O read!");