core-v-mcu.core

CAPI=2:

# Copyright 2021 OpenHW Group
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

name: openhwgroup.org:systems:core-v-mcu
description: CORE-V MCU Top.

filesets:
  files_rtl_generic:
    depend:
    - pulp-platform.org::axi
    - pulp-platform.org::common_cells
    - pulp-platform.org::riscv_dbg
    - pulp-platform.org::tech_cells_generic
    - pulp-platform.org::fpnew
    - pulp-platform.org::fpu_div_sqrt_mvp
    - openhwgroup.org:ip:apb_adv_timer
    - openhwgroup.org:ip:apb_fll_if
    - openhwgroup.org:ip:apb_gpio
    - openhwgroup.org:ip:apb_i2cs
    - openhwgroup.org:ip:apb_node
    - openhwgroup.org:ip:apb2apbcomp
    - openhwgroup.org:ip:apb2per
    - openhwgroup.org:ip:apb_timer_unit
    - openhwgroup.org:ip:udma_uart
    - openhwgroup.org:ip:udma_sdio
    - openhwgroup.org:ip:udma_qspi
    - openhwgroup.org:ip:udma_i2s
    - openhwgroup.org:ip:udma_i2c
    - openhwgroup.org:ip:udma_filter
    - openhwgroup.org:ip:udma_external_per
    - openhwgroup.org:ip:udma_core
    - openhwgroup.org:ip:udma_camera
    - openhwgroup.org:ip:logint_dc_fifo_xbar
    - openhwgroup.org:ip:l2_tcdm_hybrid_interco
    - quicklogic.com:ip:efpga
#    - openhwgroup.org:ip:generic_fll
    - openhwgroup.org:ip:tcdm_interconnect
    - openhwgroup.org:ip:cv32e40p
    files:
    - rtl/includes/periph_bus_defines.svh: {is_include_file: true, include_path: rtl/includes}
    - rtl/includes/pulp_peripheral_defines.svh: {is_include_file: true, include_path: rtl/includes}
    - rtl/includes/pulp_soc_defines.svh: {is_include_file: true, include_path: rtl/includes}
    - rtl/includes/soc_mem_map.svh: {is_include_file: true, include_path: rtl/includes}
    - rtl/core-v-mcu/include/tcdm_macros.svh: {is_include_file: true, include_path: rtl/core-v-mcu/include/}
    - rtl/core-v-mcu/soc/pkg_soc_interconnect.sv
#    - rtl/core-v-mcu/soc/axi64_2_lint32_wrap.sv
    - rtl/core-v-mcu/soc/lint_2_axi_wrap.sv
    - rtl/core-v-mcu/soc/contiguous_crossbar.sv
    - rtl/core-v-mcu/soc/interleaved_crossbar.sv
    - rtl/core-v-mcu/soc/tcdm_demux.sv
    - rtl/core-v-mcu/soc/boot_rom.sv
    - rtl/core-v-mcu/soc/l2_ram_multi_bank.sv
    - rtl/core-v-mcu/soc/lint_jtag_wrap.sv
    - rtl/core-v-mcu/soc/periph_bus_wrap.sv
    - rtl/core-v-mcu/soc/soc_clk_rst_gen.sv
    - rtl/core-v-mcu/soc/clk_and_control.sv
    - rtl/core-v-mcu/soc/soc_event_arbiter.sv
    - rtl/core-v-mcu/soc/soc_event_generator.sv
    - rtl/core-v-mcu/soc/soc_event_queue.sv
    - rtl/core-v-mcu/soc/tcdm_error_slave.sv
    - rtl/core-v-mcu/soc/soc_interconnect.sv
    - rtl/core-v-mcu/soc/soc_interconnect_wrap.sv
    - rtl/core-v-mcu/soc/soc_peripherals.sv
    - rtl/core-v-mcu/udma_subsystem/udma_subsystem.sv
    - rtl/core-v-mcu/fc/fc_demux.sv
    - rtl/core-v-mcu/fc/fc_subsystem.sv
    - rtl/core-v-mcu/fc/fc_hwpe.sv
    - rtl/core-v-mcu/fc/cv32e40p_fp_wrapper.sv
    - rtl/core-v-mcu/components/apb_soc_ctrl.sv
    - rtl/core-v-mcu/components/pulp_interfaces.sv
    - rtl/core-v-mcu/efpga_subsystem/efpga_subsystem.sv
    - rtl/core-v-mcu/efpga_subsystem/A2_fifo.sv
    - rtl/core-v-mcu/efpga_subsystem/A2_fifo_ctl.sv
    - rtl/core-v-mcu/efpga_subsystem/A2_fifo_ram.sv
    - rtl/core-v-mcu/efpga_subsystem/tcdm_interface.sv
    - rtl/core-v-mcu/efpga_subsystem/apbt1_interface.sv
    - rtl/core-v-mcu/top/pad_control.sv
    - rtl/core-v-mcu/top/safe_domain.sv
    - rtl/core-v-mcu/top/soc_domain.sv
    - rtl/core-v-mcu/top/core_v_mcu.sv
    file_type: systemVerilogSource

  rtl-behavioral:
    files:
    - rtl/core-v-mcu/components/freq_meter.sv
    file_type: systemVerilogSource

  rtl-simulation:
    files:
    - rtl/simulation/pPLL02F.sv
    - rtl/simulation/core_v_mcu_sim_ram.sv
    - rtl/simulation/sram512x64.v
    - rtl/simulation/top.sv
    - rtl/simulation/top1_wrapper.sv
    - rtl/simulation/a2_bootrom.sv
    file_type: systemVerilogSource

  not_emulation-rtl:
    files:
    - rtl/core-v-mcu/soc/clk_gen.sv
    file_type: systemVerilogSource

  emulation-rtl:
    depend:
    - pulp-platform.org::tech_cells_xilinx
    files:
    - emulation/xilinx/rtl/cv32e40p_clock_gate.sv

    - emulation/xilinx/rtl/fpga_interleaved_ram.sv
    - emulation/xilinx/rtl/fpga_private_ram.sv
    - emulation/xilinx/rtl/fpga_slow_clk_gen.sv
    - emulation/xilinx/rtl/pad_functional_xilinx.sv
    - emulation/xilinx/rtl/pulp_clock_gating_xilinx.sv
    - emulation/xilinx/rtl/sram512x64.v
    - emulation/xilinx/rtl/DW02_mac.sv
    - rtl/simulation/pPLL02F.sv
    - rtl/simulation/top.sv
    - rtl/simulation/top1_wrapper.sv
    - rtl/simulation/a2_bootrom.sv
    file_type: systemVerilogSource

  nexys-ips:
    files:
    - emulation/xilinx/ips/xilinx_clk_mngr.tcl
    file_type: tclSource

  genesys2-ips:
    files:
    - emulation/core-v-mcu-genesys2/ips/xilinx_clk_mngr.tcl
    file_type: tclSource

  xilinx-ips:
    files:
#    - emulation/xilinx/ips/xilinx_slow_clk_mngr.tcl
    - emulation/xilinx/ips/xilinx_interleaved_ram.tcl
    - emulation/xilinx/ips/xilinx_private_ram.tcl
    file_type: tclSource

  rom_init:
    files:
    - tb/mem_init_files/boot.mem: {copyto: mem_init/boot.mem}
    file_type: mem


  mem_init_modelsim:
    files:
    - tb/mem_init_files/boot.mem: {copyto: mem_init/boot.mem}
    - tb/mem_init_files/cli_sim.txt: {copyto: mem_init/cli.txt}
    - tb/mem_init_files/col0.mem: {copyto: 'mem_init/core_v_mcu_tb.core_v_mcu_i.i_soc_domain.l2_ram_i.CUTS[0].bank_i.u0.mem'}
    - tb/mem_init_files/col1.mem: {copyto: 'mem_init/core_v_mcu_tb.core_v_mcu_i.i_soc_domain.l2_ram_i.CUTS[1].bank_i.u0.mem'}
    - tb/mem_init_files/col2.mem: {copyto: 'mem_init/core_v_mcu_tb.core_v_mcu_i.i_soc_domain.l2_ram_i.CUTS[2].bank_i.u0.mem'}
    - tb/mem_init_files/col3.mem: {copyto: 'mem_init/core_v_mcu_tb.core_v_mcu_i.i_soc_domain.l2_ram_i.CUTS[3].bank_i.u0.mem'}
    - tb/mem_init_files/privateBank0.mem: {copyto: mem_init/core_v_mcu_tb.core_v_mcu_i.i_soc_domain.l2_ram_i.bank_sram_pri0_i.u0.mem}
    - tb/mem_init_files/privateBank1.mem: {copyto: mem_init/core_v_mcu_tb.core_v_mcu_i.i_soc_domain.l2_ram_i.bank_sram_pri1_i.u0.mem}
    file_type: user

  mem_init_verilator:
    files:
    - tb/mem_init_files/verilatorBoot.mem: {copyto: mem_init/boot.mem}
    - tb/mem_init_files/cli_sim.txt: {copyto: mem_init/cli.txt}
    - tb/mem_init_files/col0.mem: {copyto: 'mem_init/TOP.core_v_mcu.i_soc_domain.l2_ram_i.CUTS[0].bank_i.u0.mem'}
    - tb/mem_init_files/col1.mem: {copyto: 'mem_init/TOP.core_v_mcu.i_soc_domain.l2_ram_i.CUTS[1].bank_i.u0.mem'}
    - tb/mem_init_files/col2.mem: {copyto: 'mem_init/TOP.core_v_mcu.i_soc_domain.l2_ram_i.CUTS[2].bank_i.u0.mem'}
    - tb/mem_init_files/col3.mem: {copyto: 'mem_init/TOP.core_v_mcu.i_soc_domain.l2_ram_i.CUTS[3].bank_i.u0.mem'}
    - tb/mem_init_files/privateBank0.mem: {copyto: mem_init/TOP.core_v_mcu.i_soc_domain.l2_ram_i.bank_sram_pri0_i.u0.mem}
    - tb/mem_init_files/privateBank1.mem: {copyto: mem_init/TOP.core_v_mcu.i_soc_domain.l2_ram_i.bank_sram_pri1_i.u0.mem}
    file_type: user


  tb-rtl:
    files:
    - tb/core_v_mcu_tb.sv
    - tb/uartdpi/uartdpi.sv
    - tb/qspi_model/GD25Q128B.v
    file_type: systemVerilogSource


  nexys-rtl:
    files:
    - emulation/core-v-mcu-nexys/rtl/core_v_mcu_nexys.v
    - emulation/xilinx/rtl/fpga_clk_gen.sv
    file_type: systemVerilogSource

  nexys-xdc:
    files:
    - emulation/core-v-mcu-nexys/constraints/core-v-mcu-pin-assignment.xdc
    file_type: xdc

  xilinx-tcl:
    files:
    - emulation/xilinx/tcl/common.tcl
    - emulation/xilinx/tcl/flatten.tcl
    file_type: tclSource

  genesys2-rtl:
    files:
    - emulation/core-v-mcu-genesys2/rtl/core_v_mcu_genesys2.v
    - emulation/core-v-mcu-genesys2/rtl/fpga_clk_gen.sv
    file_type: systemVerilogSource

  genesys2-xdc:
    files:
    - emulation/core-v-mcu-genesys2/constraints/core-v-mcu-pin-assignment.xdc
    file_type: xdc

  # Scripts for hooks
  pre_build_scripts:
    files:
    - rtl/core-v-mcu/scripts/vedit.sh
    file_type: user
  # Waiver file, without which the model lib will not build.
  verilator-waiver:
    files:
    - rtl/core-v-mcu/verilator.waiver
    file_type: vlt

parameters:
  PULP_FPGA_EMUL:
    datatype: bool
    paramtype: vlogdefine
    default: true
  VERILATOR:
    datatype: bool
    paramtype: vlogdefine
    default: true
  USE_BW:
    datatype: bool
    paramtype: vlogdefine
    default: true

# A script to modify Verilator pre-build to generate a library, not an
# executable.
scripts:
  pre_build_scripts:
    cmd:
    - sh
    - ../src/openhwgroup.org_systems_core-v-mcu_0/rtl/core-v-mcu/scripts/vedit.sh
    - openhwgroup.org_systems_core-v-mcu_0.vc

targets:
  default: &default_target
    filesets:
    - files_rtl_generic
    - not_emulation-rtl
    - target_lint? (rtl-behavioral)
    - target_model-lib? (rtl-behavioral)
    toplevel: [core_v_mcu]

  sim:
    <<: *default_target
    default_tool: modelsim
    filesets_append:
    - not_emulation-rtl
    - rtl-simulation
    - mem_init_modelsim
    - rtl-behavioral
    - tb-rtl
    toplevel:
    - core_v_mcu_tb
    parameters:
    - USE_BW=true
    tools:
      modelsim:
        vlog_options:
        - -override_timescale 1ns/1ps
        - -suppress vlog-2583
        vsim_options:
        - -sv_lib ../../../tb/uartdpi/uartdpi -voptargs="-O1 +acc"
      xcelium:
        xrun_options:
        - -64bit
        - -timescale 1ns/1ps
        - -disable_sem2009
        xmsim_options:
        - -sv_lib ../../../tb/uartdpi/uartdpi.so
      xsim:
        xelab_options:
        - --define XSIM
        - --incr
        - -dup_entity_as_module
        - -relax
        - --O0
        - -v 0
        - -timescale 1ns/1ps
        xsim_options:

  # A target for a Verilator model as a library.  Note that we do not disable
  # UNOPTFLAT warnings, since these will affect performance, so we want to see
  # them.
  model-lib:
    <<: *default_target
    default_tool: verilator
    parameters:
    - VERILATOR=true
    - USE_BW=true
    filesets_append:
    - pre_build_scripts
    - verilator-waiver
    - mem_init_verilator
    - rtl-simulation
    - not_emulation-rtl
    toplevel: [core_v_mcu]
    hooks:
      pre_build: [pre_build_scripts]
    tools:
      verilator:
        mode: cc
        verilator_options:
        - -Wno-fatal
        - --trace
        - --CFLAGS -DVL_TIME_CONTEXT

  lint:
    <<: *default_target
    default_tool: verilator
    toplevel: [core_v_mcu]
    filesets_append:
    - rtl-simulation
    - not_emulation-rtl
    tools:
      verilator:
        mode: lint-only
        verilator_options:
        - -Wno-fatal

  nexys-a7-100t:
    <<: *default_target
    default_tool: vivado
    description: Digilent Nexys-A7-100T Board
    parameters:
    - PULP_FPGA_EMUL=true
    filesets_append:
    - nexys-ips
    - xilinx-ips
    - xilinx-tcl
    - emulation-rtl
    - nexys-rtl
    - nexys-xdc
    - rom_init
    tools:
      vivado:
        part: xc7a100tcsg324-1
    toplevel: core_v_mcu_nexys

  genesys2:
    <<: *default_target
    default_tool: vivado
    description: Digilent Nexys-A7-100T Board
    parameters:
    - PULP_FPGA_EMUL=true
    filesets_append:
    - genesys2-ips
    - xilinx-ips
    - xilinx-tcl
    - emulation-rtl
    - genesys2-rtl
    - genesys2-xdc
    - rom_init
    tools:
      vivado:
        part: xc7k325tffg900-2
    toplevel: core_v_mcu_genesys2