From 641e687ab5c6da41e4fbbebe62ca26670d707279 Mon Sep 17 00:00:00 2001 From: Daniel Lehmann <59584561+danlehmann@users.noreply.github.com> Date: Tue, 6 Aug 2024 11:28:01 -0700 Subject: [PATCH] RISC-V: List all integer registers for lldb compatibility (#149) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * lldb/risc-v: Add all integer registers lldb requires a full list of registers in the target_description_xml (gdb on the other hand seems to ignore the list completely). The gdb manual sounds like these registers should exist anyway: > The ‘org.gnu.gdb.riscv.cpu’ feature is required for RISC-V targets. It should contain the registers ‘x0’ through ‘x31’, and ‘pc’. Therefore it seems reasonable that the RISC-V arch returns the full list. * Include original files via include_str! instead --- gdbstub_arch/src/riscv/mod.rs | 8 +++--- gdbstub_arch/src/riscv/rv32i.xml | 47 ++++++++++++++++++++++++++++++++ gdbstub_arch/src/riscv/rv64i.xml | 47 ++++++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+), 4 deletions(-) create mode 100644 gdbstub_arch/src/riscv/rv32i.xml create mode 100644 gdbstub_arch/src/riscv/rv64i.xml diff --git a/gdbstub_arch/src/riscv/mod.rs b/gdbstub_arch/src/riscv/mod.rs index b086396..8faed74 100644 --- a/gdbstub_arch/src/riscv/mod.rs +++ b/gdbstub_arch/src/riscv/mod.rs @@ -15,21 +15,21 @@ pub enum Riscv64 {} impl Arch for Riscv32 { type Usize = u32; type Registers = reg::RiscvCoreRegs; - type RegId = reg::id::RiscvRegId; type BreakpointKind = usize; + type RegId = reg::id::RiscvRegId; fn target_description_xml() -> Option<&'static str> { - Some(r#"riscv:rv32"#) + Some(include_str!("rv32i.xml")) } } impl Arch for Riscv64 { type Usize = u64; type Registers = reg::RiscvCoreRegs; - type RegId = reg::id::RiscvRegId; type BreakpointKind = usize; + type RegId = reg::id::RiscvRegId; fn target_description_xml() -> Option<&'static str> { - Some(r#"riscv:rv64"#) + Some(include_str!("rv64i.xml")) } } diff --git a/gdbstub_arch/src/riscv/rv32i.xml b/gdbstub_arch/src/riscv/rv32i.xml new file mode 100644 index 0000000..dc948c7 --- /dev/null +++ b/gdbstub_arch/src/riscv/rv32i.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub_arch/src/riscv/rv64i.xml b/gdbstub_arch/src/riscv/rv64i.xml new file mode 100644 index 0000000..60f42f2 --- /dev/null +++ b/gdbstub_arch/src/riscv/rv64i.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +