Add options for preprocessor macros, module parameters and custom compile-time flags

[ganoam]

It would be useful to be able to set certain compile time flags in the dbt module decalarations. For example, setting a preprocessor variable (e.g. for conditional compilation of simulation-only code), for setting module parameters (e.g. simulate an arbitrator module with a configurable number o fmasters/slaves). The semantics for those functionalities depend on the simulator/synthesis tool:

Preprocessor macros:

• Questa: vlog +define+<macrro_name>[=<macro_val>]
• Xsim: xvlog --define <macro_name>[=<macro_val>]
• Xilnix synthesis: synth_design -verilog_define <name>=<value>

Module parameters

• Questa: vsim -G<param_name>=<param_value> (Note: runtime argument, not compile-time).
• Xsim: There seems to be no good way. I'll investigate when I have time.
• Xilnix synthesis: synth_design -generic <param_name>=<param_value>

In addition it would be nice to set custom simulator/synthesis tool specific flags.

I propose to add the following fields to hdl.Simulation:

• Define: []string
• Generic: []string
• vlog_args: []string (ignored if using xsim)
• xvlog_args: []string (ignored if using questa)

And the following to hdl.Bitstream:

• Define: []string
• Generic: []string
• xsynth_args: []string

What's your opinions?

[paulhankin]

Maybe related: daedaleanai/dbt#96

(It's related in as much that in that issue I request a way to feed down configuration from the top-level to sub-rules. There are many differences).

[ganoam]

All my dreams are comming true in #47. Thanks, Niels.