From 9da3a6097f2c89a854f4728e53f08cf563db4d74 Mon Sep 17 00:00:00 2001
From: CyrIng <labs@cyring.fr>
Date: Sat, 27 Jan 2024 22:01:41 +0100
Subject: [PATCH] [AArch64] Query and export TME, FHM, TS and TLB features

---
 aarch64/corefreq-cli-json.c |  8 ++++++++
 aarch64/corefreqk.c         | 38 +++++++++++++++++++++++++++++++++++++
 aarch64/coretypes.h         | 14 +++++++++-----
 3 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/aarch64/corefreq-cli-json.c b/aarch64/corefreq-cli-json.c
index 86193ce1..717c1968 100644
--- a/aarch64/corefreq-cli-json.c
+++ b/aarch64/corefreq-cli-json.c
@@ -459,6 +459,14 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SM4);
 					json_key(&s, "RAND");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RAND);
+					json_key(&s, "TME");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TME);
+					json_key(&s, "FHM");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FHM);
+					json_key(&s, "TS");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TS);
+					json_key(&s, "TLB");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TLB);
 					json_key(&s, "RDMA");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RDMA);
 					json_end_object(&s);
diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c
index 6a357bb1..ea50adeb 100644
--- a/aarch64/corefreqk.c
+++ b/aarch64/corefreqk.c
@@ -680,6 +680,15 @@ static void Query_Features(void *pArg)
 		iArg->Features->CAS = 0;
 		break;
 	}
+	switch (isar0.TME) {
+	case 0b0001:
+		iArg->Features->TME = 1;
+		break;
+	case 0b0000:
+	default:
+		iArg->Features->TME = 0;
+		break;
+	}
 	switch (isar0.RDM) {
 	case 0b0001:
 		iArg->Features->RDMA = 1;
@@ -716,6 +725,35 @@ static void Query_Features(void *pArg)
 		iArg->Features->SM4 = 0;
 		break;
 	}
+	switch (isar0.FHM) {
+	case 0b0001:
+		iArg->Features->FHM = 1;
+		break;
+	case 0b0000:
+	default:
+		iArg->Features->FHM = 0;
+		break;
+	}
+	switch (isar0.TS) {
+	case 0b0001:
+	case 0b0010:
+		iArg->Features->TS = 1;
+		break;
+	case 0b0000:
+	default:
+		iArg->Features->TS = 0;
+		break;
+	}
+	switch (isar0.TLB) {
+	case 0b0001:
+	case 0b0010:
+		iArg->Features->TLB = 1;
+		break;
+	case 0b0000:
+	default:
+		iArg->Features->TLB = 0;
+		break;
+	}
 	switch (isar0.RNDR) {
 	case 0b0001:
 		iArg->Features->RAND = 1;
diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h
index 401d72b7..c4726a97 100644
--- a/aarch64/coretypes.h
+++ b/aarch64/coretypes.h
@@ -788,11 +788,15 @@ typedef struct	/* BSP features.					*/
 		SVE		: 12-11,
 		VHE		: 13-12,
 		SME		: 14-13,
-		RDMA		: 15-14,
-		DP		: 16-15,
-		SM3		: 17-16,
-		SM4		: 18-17,
-		_Unused1_	: 24-18,
+		TME		: 15-14,
+		RDMA		: 16-15,
+		DP		: 17-16,
+		SM3		: 18-17,
+		SM4		: 19-18,
+		FHM		: 20-19,
+		TS		: 21-20,
+		TLB		: 22-21,
+		_Unused1_	: 24-22,
 		HTT		: 25-24,
 		TSC		: 26-25,
 		MONITOR 	: 27-26,