From 8d534d064ac726a5b728384992f264f151af0f7b Mon Sep 17 00:00:00 2001 From: CyrIng Date: Sun, 28 Jan 2024 07:55:21 +0100 Subject: [PATCH] [AArch64] Presents TLB, TME, FCMA, FHM, LRCPC, TS --- aarch64/corefreq-cli-json.c | 9 ++++++ aarch64/corefreq-cli-rsc-en.h | 18 ++++++++++-- aarch64/corefreq-cli-rsc-fr.h | 20 ++++++------- aarch64/corefreq-cli-rsc.c | 14 +++++++-- aarch64/corefreq-cli-rsc.h | 14 +++++++-- aarch64/corefreq-cli.c | 53 ++++++++++++++++++++++++++++++++--- aarch64/corefreqk.c | 22 +++++++++++++++ aarch64/coretypes.h | 9 +++--- 8 files changed, 135 insertions(+), 24 deletions(-) diff --git a/aarch64/corefreq-cli-json.c b/aarch64/corefreq-cli-json.c index 717c1968..e0d90d22 100644 --- a/aarch64/corefreq-cli-json.c +++ b/aarch64/corefreq-cli-json.c @@ -471,6 +471,15 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RDMA); json_end_object(&s); } + json_key(&s, "ISAR1"); + { + json_start_object(&s); + json_key(&s, "FCMA"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FCMA); + json_key(&s, "LRCPC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC); + json_end_object(&s); + } json_key(&s, "MMFR1"); { json_start_object(&s); diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h index 5c1b4999..767e6311 100644 --- a/aarch64/corefreq-cli-rsc-en.h +++ b/aarch64/corefreq-cli-rsc-en.h @@ -774,8 +774,15 @@ #define RSC_ISA_AES_COMM_CODE_EN " Advanced Encryption Standard " #define RSC_ISA_CAS_COMM_CODE_EN " Atomic instructions " #define RSC_ISA_CRC32_COMM_CODE_EN " Cyclic Redundancy Check " -#define RSC_ISA_FP_COMM_CODE_EN " Floating Point " #define RSC_ISA_DP_COMM_CODE_EN " Dot Product instructions " +#define RSC_ISA_FCMA_COMM_CODE_EN \ + " Floating-point Complex Multiplication & Addition " + +#define RSC_ISA_FHM_COMM_CODE_EN \ + " Floating-point Half-precision Multiplication " + +#define RSC_ISA_FP_COMM_CODE_EN " Floating Point " +#define RSC_ISA_LRCPC_COMM_CODE_EN " Load-Acquire RCpc instructions " #define RSC_ISA_RAND_COMM_CODE_EN " Read Random Number " #define RSC_ISA_RDMA_COMM_CODE_EN " Rounding Double Multiply Accumulate " #define RSC_ISA_SHA_COMM_CODE_EN " Secure Hash Algorithms extensions " @@ -783,6 +790,7 @@ #define RSC_ISA_SIMD_COMM_CODE_EN " Advanced SIMD Extensions " #define RSC_ISA_SME_COMM_CODE_EN " Scalable Matrix Extension " #define RSC_ISA_SVE_COMM_CODE_EN " Scalable Vector Extension " +#define RSC_ISA_TS_COMM_CODE_EN " Flag manipulation instructions " #define RSC_FEATURES_TITLE_CODE_EN " Features " #define RSC_ON_CODE_EN " ON" @@ -803,6 +811,8 @@ #define RSC_FEATURES_MTE_CODE_EN "Memory Tagging Extension" #define RSC_FEATURES_NMI_CODE_EN "Non Maskable Interrupt" #define RSC_FEATURES_PAN_CODE_EN "Privileged Access Never" +#define RSC_FEATURES_TLB_CODE_EN "TLB maintenance instructions" +#define RSC_FEATURES_TME_CODE_EN "Transactional Memory Extension" #define RSC_FEATURES_TSC_CODE_EN "Time Stamp Counter" #define RSC_FEATURES_UAO_CODE_EN "User Access Override" #define RSC_FEATURES_VHE_CODE_EN "Virtualization Host Extensions" @@ -1930,8 +1940,11 @@ #define RSC_ISA_AES_CODE " AES [%c]" #define RSC_ISA_CAS_CODE " CAS [%c]" #define RSC_ISA_CRC32_CODE " CRC32 [%c]" -#define RSC_ISA_DP_CODE " DP [%c]" +#define RSC_ISA_DP_CODE " DP [%c]" +#define RSC_ISA_FCMA_CODE " FCMA [%c]" +#define RSC_ISA_FHM_CODE " FHM [%c]" #define RSC_ISA_FP_CODE " FP [%c]" +#define RSC_ISA_LRCPC_CODE " LRCPC [%c]" #define RSC_ISA_RAND_CODE " RAND [%c]" #define RSC_ISA_RDMA_CODE " RDMA [%c]" #define RSC_ISA_SHA1_CODE " SHA1 [%c]" @@ -1943,3 +1956,4 @@ #define RSC_ISA_SM4_CODE " SM4 [%c]" #define RSC_ISA_SME_CODE " SME [%c]" #define RSC_ISA_SVE_CODE " SVE [%c]" +#define RSC_ISA_TS_CODE " TS [%c]" diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h index 7007397c..7fe8a429 100644 --- a/aarch64/corefreq-cli-rsc-fr.h +++ b/aarch64/corefreq-cli-rsc-fr.h @@ -466,8 +466,11 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_ISA_AES_COMM_CODE_FR RSC_ISA_AES_COMM_CODE_EN #define RSC_ISA_CAS_COMM_CODE_FR RSC_ISA_CAS_COMM_CODE_EN #define RSC_ISA_CRC32_COMM_CODE_FR RSC_ISA_CRC32_COMM_CODE_EN -#define RSC_ISA_FP_COMM_CODE_FR RSC_ISA_FP_COMM_CODE_EN #define RSC_ISA_DP_COMM_CODE_FR RSC_ISA_DP_COMM_CODE_EN +#define RSC_ISA_FCMA_COMM_CODE_FR RSC_ISA_FCMA_COMM_CODE_EN +#define RSC_ISA_FHM_COMM_CODE_FR RSC_ISA_FHM_COMM_CODE_EN +#define RSC_ISA_FP_COMM_CODE_FR RSC_ISA_FP_COMM_CODE_EN +#define RSC_ISA_LRCPC_COMM_CODE_FR RSC_ISA_LRCPC_COMM_CODE_EN #define RSC_ISA_RAND_COMM_CODE_FR RSC_ISA_RAND_COMM_CODE_EN #define RSC_ISA_RDMA_COMM_CODE_FR RSC_ISA_RDMA_COMM_CODE_EN #define RSC_ISA_SHA_COMM_CODE_FR RSC_ISA_SHA_COMM_CODE_EN @@ -475,6 +478,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_ISA_SIMD_COMM_CODE_FR RSC_ISA_SIMD_COMM_CODE_EN #define RSC_ISA_SME_COMM_CODE_FR RSC_ISA_SME_COMM_CODE_EN #define RSC_ISA_SVE_COMM_CODE_FR RSC_ISA_SVE_COMM_CODE_EN +#define RSC_ISA_TS_COMM_CODE_FR RSC_ISA_TS_COMM_CODE_EN #define RSC_FEATURES_TITLE_CODE_FR " Caract""\xa9""ristiques " #define RSC_ON_CODE_FR " ON" @@ -498,18 +502,14 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_FEATURES_GIC_CODE_FR \ "Contr""\xb4""leur d'interruption g""\xa9""n""\xa9""rique" -#define RSC_FEATURES_MTE_CODE_FR \ - "Extension de marquage de m""\xa9""moire" - +#define RSC_FEATURES_MTE_CODE_FR "Extension de marquage de m""\xa9""moire" #define RSC_FEATURES_NMI_CODE_FR "Interruption non masquable" #define RSC_FEATURES_PAN_CODE_FR "Aucun privil""\xa8""ge d'acc""\xa8""s" +#define RSC_FEATURES_TLB_CODE_FR "Instructions de gestion TLB" +#define RSC_FEATURES_TME_CODE_FR "Extension de m""\xa9""moire transactionnelle" #define RSC_FEATURES_TSC_CODE_FR "Compteur d'horodatage" -#define RSC_FEATURES_UAO_CODE_FR \ - "Surcharge de l'acc""\xa8""s utilisateur" - -#define RSC_FEATURES_VHE_CODE_FR \ - "Extensions d'H""\xb4""te de Virtualisation" - +#define RSC_FEATURES_UAO_CODE_FR "Surcharge de l'acc""\xa8""s utilisateur" +#define RSC_FEATURES_VHE_CODE_FR "Extensions d'H""\xb4""te de Virtualisation" #define RSC_FEAT_SECTION_MECH_CODE_FR "M""\xa9""canismes d'att""\xa9""nuation" #define RSC_FEAT_SECTION_SEC_CODE_FR "Fonctions de s""\xa9""curit""\xa9" diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c index dd35a758..20b49bec 100644 --- a/aarch64/corefreq-cli-rsc.c +++ b/aarch64/corefreq-cli-rsc.c @@ -670,10 +670,16 @@ RESOURCE_ST Resource[] = { LDT(RSC_ISA_CAS_COMM), LDQ(RSC_ISA_CRC32), LDT(RSC_ISA_CRC32_COMM), - LDQ(RSC_ISA_FP), - LDT(RSC_ISA_FP_COMM), LDQ(RSC_ISA_DP), LDT(RSC_ISA_DP_COMM), + LDQ(RSC_ISA_FCMA), + LDT(RSC_ISA_FCMA_COMM), + LDQ(RSC_ISA_FHM), + LDT(RSC_ISA_FHM_COMM), + LDQ(RSC_ISA_FP), + LDT(RSC_ISA_FP_COMM), + LDQ(RSC_ISA_LRCPC), + LDT(RSC_ISA_LRCPC_COMM), LDQ(RSC_ISA_RAND), LDT(RSC_ISA_RAND_COMM), LDQ(RSC_ISA_RDMA), @@ -692,6 +698,8 @@ RESOURCE_ST Resource[] = { LDT(RSC_ISA_SME_COMM), LDQ(RSC_ISA_SVE), LDT(RSC_ISA_SVE_COMM), + LDQ(RSC_ISA_TS), + LDT(RSC_ISA_TS_COMM), LDT(RSC_FEATURES_TITLE), LDT(RSC_ON), LDT(RSC_OFF), @@ -710,6 +718,8 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_MTE), LDT(RSC_FEATURES_NMI), LDT(RSC_FEATURES_PAN), + LDT(RSC_FEATURES_TLB), + LDT(RSC_FEATURES_TME), LDT(RSC_FEATURES_TSC), LDT(RSC_FEATURES_UAO), LDT(RSC_FEATURES_VHE), diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h index f94436de..541e6916 100644 --- a/aarch64/corefreq-cli-rsc.h +++ b/aarch64/corefreq-cli-rsc.h @@ -493,10 +493,16 @@ enum { RSC_ISA_CAS_COMM, RSC_ISA_CRC32, RSC_ISA_CRC32_COMM, - RSC_ISA_FP, - RSC_ISA_FP_COMM, RSC_ISA_DP, RSC_ISA_DP_COMM, + RSC_ISA_FCMA, + RSC_ISA_FCMA_COMM, + RSC_ISA_FHM, + RSC_ISA_FHM_COMM, + RSC_ISA_FP, + RSC_ISA_FP_COMM, + RSC_ISA_LRCPC, + RSC_ISA_LRCPC_COMM, RSC_ISA_RAND, RSC_ISA_RAND_COMM, RSC_ISA_RDMA, @@ -515,6 +521,8 @@ enum { RSC_ISA_SME_COMM, RSC_ISA_SVE, RSC_ISA_SVE_COMM, + RSC_ISA_TS, + RSC_ISA_TS_COMM, RSC_FEATURES_TITLE, RSC_ON, RSC_OFF, @@ -533,6 +541,8 @@ enum { RSC_FEATURES_MTE, RSC_FEATURES_NMI, RSC_FEATURES_PAN, + RSC_FEATURES_TLB, + RSC_FEATURES_TME, RSC_FEATURES_TSC, RSC_FEATURES_UAO, RSC_FEATURES_VHE, diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c index 20cba2be..a2cfb880 100644 --- a/aarch64/corefreq-cli.c +++ b/aarch64/corefreq-cli.c @@ -1389,6 +1389,20 @@ REASON_CODE SysInfoISA( Window *win, { RO(Shm)->Proc.Features.DP }, }, /* Row Mark */ + { + NULL, + RSC(ISA_FCMA).CODE(), RSC(ISA_FCMA_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FCMA }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FCMA }, + }, + { + NULL, + RSC(ISA_FHM).CODE(), RSC(ISA_FHM_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FHM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FHM }, + }, { NULL, RSC(ISA_FP).CODE(), RSC(ISA_FP_COMM).CODE(), @@ -1396,6 +1410,14 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.FP }, }, + { + NULL, + RSC(ISA_LRCPC).CODE(), RSC(ISA_LRCPC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LRCPC }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LRCPC }, + }, +/* Row Mark */ { NULL, RSC(ISA_RAND).CODE(), RSC(ISA_RAND_COMM).CODE(), @@ -1417,7 +1439,6 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SHA1 }, }, -/* Row Mark */ { NULL, RSC(ISA_SHA256).CODE(), RSC(ISA_SHA_COMM).CODE(), @@ -1425,6 +1446,7 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SHA256 }, }, +/* Row Mark */ { NULL, RSC(ISA_SHA512).CODE(), RSC(ISA_SHA_COMM).CODE(), @@ -1446,7 +1468,6 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SIMD }, }, -/* Row Mark */ { NULL, RSC(ISA_SM3).CODE(), RSC(ISA_SM_COMM).CODE(), @@ -1454,6 +1475,7 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SM3 }, }, +/* Row Mark */ { NULL, RSC(ISA_SM4).CODE(), RSC(ISA_SM_COMM).CODE(), @@ -1475,6 +1497,13 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SVE }, }, + { + NULL, + RSC(ISA_TS).CODE(), RSC(ISA_TS_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.TS }, + (unsigned short[]) + { RO(Shm)->Proc.Features.TS }, + }, }; CUINT cells_per_line = win->matrix.size.wth, *nl = &cells_per_line; @@ -1604,6 +1633,22 @@ REASON_CODE SysInfoFeatures( Window *win, width - 18 - RSZ(FEATURES_PAN), NULL }, + { + NULL, + RO(Shm)->Proc.Features.TLB == 1, + attr_Feat, + 2, "%s%.*sTLB [%7s]", RSC(FEATURES_TLB).CODE(), + width - 18 - RSZ(FEATURES_TLB), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.TME == 1, + attr_Feat, + 2, "%s%.*sTME [%7s]", RSC(FEATURES_TME).CODE(), + width - 18 - RSZ(FEATURES_TME), + NULL + }, { NULL, RO(Shm)->Proc.Features.InvariantTSC, @@ -6261,7 +6306,7 @@ Window *CreateSysInfo(unsigned long long id) { winOrigin.row = TOP_HEADER_ROW + 1; winOrigin.col = 4; - matrixSize.hth = 10; + matrixSize.hth = 16; winWidth = 72; SysInfoFunc = SysInfoFeatures; title = RSC(FEATURES_TITLE).CODE(); @@ -6443,7 +6488,7 @@ Window *CreateTopology(unsigned long long id) Window *CreateISA(unsigned long long id) { - Window *wISA = CreateWindow(wLayer, id, 4, 4, 6, TOP_HEADER_ROW + 2); + Window *wISA = CreateWindow(wLayer, id, 4, 5, 6, TOP_HEADER_ROW + 2); if (wISA != NULL) { diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c index a8924475..d7d4b14e 100644 --- a/aarch64/corefreqk.c +++ b/aarch64/corefreqk.c @@ -535,6 +535,7 @@ static void Query_Features(void *pArg) volatile AA64DFR0 dfr0; volatile AA64DFR1 dfr1; volatile AA64ISAR0 isar0; + volatile AA64ISAR1 isar1; volatile AA64MMFR1 mmfr1; volatile AA64MMFR2 mmfr2; volatile AA64PFR0 pfr0; @@ -553,6 +554,7 @@ static void Query_Features(void *pArg) "mrs %[dfr0], id_aa64dfr0_el1""\n\t" "mrs %[dfr1], id_aa64dfr1_el1""\n\t" "mrs %[isar0], id_aa64isar0_el1""\n\t" + "mrs %[isar1], id_aa64isar1_el1""\n\t" "mrs %[mmfr1], id_aa64mmfr1_el1""\n\t" "mrs %[pfr0] , id_aa64pfr0_el1""\n\t" "mrs %[pfr1] , id_aa64pfr1_el1""\n\t" @@ -564,6 +566,7 @@ static void Query_Features(void *pArg) [dfr0] "=r" (dfr0), [dfr1] "=r" (dfr1), [isar0] "=r" (isar0), + [isar1] "=r" (isar1), [mmfr1] "=r" (mmfr1), [pfr0] "=r" (pfr0), [pfr1] "=r" (pfr1) @@ -763,6 +766,25 @@ static void Query_Features(void *pArg) iArg->Features->RAND = 0; break; } + switch (isar1.FCMA) { + case 0b0001: + iArg->Features->FCMA = 1; + break; + case 0b0000: + default: + iArg->Features->FCMA = 0; + break; + } + switch (isar1.LRCPC) { + case 0b0001: + case 0b0010: + iArg->Features->LRCPC = 1; + break; + case 0b0000: + default: + iArg->Features->LRCPC = 0; + break; + } switch (mmfr1.VH) { case 0b0001: iArg->Features->VHE = 1; diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h index c4726a97..a369e419 100644 --- a/aarch64/coretypes.h +++ b/aarch64/coretypes.h @@ -796,7 +796,8 @@ typedef struct /* BSP features. */ FHM : 20-19, TS : 21-20, TLB : 22-21, - _Unused1_ : 24-22, + FCMA : 23-22, + LRCPC : 24-23, HTT : 25-24, TSC : 26-25, MONITOR : 27-26, @@ -898,7 +899,7 @@ typedef struct /* BSP features. */ MTE : 12-11, NMI : 13-12, EBEP : 14-13, - _Unused2_ : 64-14; + _Unused1_ : 64-14; Bit64 InvariantTSC : 8-0, HyperThreading : 9-8, @@ -915,7 +916,7 @@ typedef struct /* BSP features. */ HWP_Enable : 23-22, Other_Capable : 24-23, SpecTurboRatio : 32-24, - _Unused3_ : 40-32, + _Unused2_ : 40-32, ACPI_PCT_CAP : 41-40, ACPI_PCT : 42-41, ACPI_PSS_CAP : 43-42, @@ -927,7 +928,7 @@ typedef struct /* BSP features. */ OSPM_EPP : 55-54, ACPI_CST_CAP : 56-55, ACPI_CST : 60-56, /* 15 CState sub-packages */ - _Unused4_ : 64-60; + _Unused3_ : 64-60; }; } FEATURES;