diff --git a/aarch64/corefreq-cli-json.c b/aarch64/corefreq-cli-json.c
index 361abf87..fd3b7361 100644
--- a/aarch64/corefreq-cli-json.c
+++ b/aarch64/corefreq-cli-json.c
@@ -471,8 +471,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FlagM);
 					json_key(&s, "FlagM2");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FlagM2);
-					json_key(&s, "TLB");
-					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TLB);
+					json_key(&s, "TLBIOS");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TLBIOS);
+					json_key(&s, "TLBIRANGE");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TLBIRANGE);
 					json_key(&s, "RDMA");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RDMA);
 					json_end_object(&s);
@@ -482,8 +484,16 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 					json_start_object(&s);
 					json_key(&s, "FCMA");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FCMA);
+					json_key(&s, "PACIMP");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PACIMP);
+					json_key(&s, "PACQARMA5");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PACQARMA5);
 					json_key(&s, "LRCPC");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC);
+					json_key(&s, "LRCPC2");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC2);
+					json_key(&s, "LRCPC3");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC3);
 					json_key(&s, "JSCVT");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.JSCVT);
 					json_key(&s, "FRINTTS");
diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h
index adaac9e3..3ce24453 100644
--- a/aarch64/corefreq-cli-rsc-en.h
+++ b/aarch64/corefreq-cli-rsc-en.h
@@ -788,6 +788,12 @@
 #define RSC_ISA_FP_COMM_CODE_EN 	" Floating Point "
 #define RSC_ISA_JSCVT_COMM_CODE_EN	" JavaScript Conversion "
 #define RSC_ISA_LRCPC_COMM_CODE_EN	" Load-Acquire RCpc instructions "
+#define RSC_ISA_PACIMP_COMM_CODE_EN	\
+			" Pointer Authentication Code, using Generic key "
+
+#define RSC_ISA_PACQARMA5_COMM_CODE_EN	\
+		" Pointer Authentication Code, using the QARMA5 algorithm "
+
 #define RSC_ISA_FRINTTS_COMM_CODE_EN	" Floating-point to Integer "
 #define RSC_ISA_SPECRES_COMM_CODE_EN	" Prediction Invalidation "
 #define RSC_ISA_BF16_COMM_CODE_EN	" BFloat16 instructions "
@@ -1954,15 +1960,19 @@
 #define RSC_ISA_FHM_CODE		"          FHM [%c]"
 #define RSC_ISA_FP_CODE 		"           FP [%c]"
 #define RSC_ISA_JSCVT_CODE		"        JSCVT [%c]"
-#define RSC_ISA_LRCPC_CODE 		"        LRCPC [%c]"
+#define RSC_ISA_LRCPC_CODE		"        LRCPC [%c]"
+#define RSC_ISA_LRCPC2_CODE		"       LRCPC2 [%c]"
+#define RSC_ISA_LRCPC3_CODE		"       LRCPC3 [%c]"
+#define RSC_ISA_PACGA_CODE		"        PACGA [%c]"
+#define RSC_ISA_PACQARMA5_CODE		"    PACQARMA5 [%c]"
 #define RSC_ISA_FRINTTS_CODE		"      FRINTTS [%c]"
 #define RSC_ISA_SPECRES_CODE		"      SPECRES [%c]"
 #define RSC_ISA_SPECRES2_CODE		"     SPECRES2 [%c]"
 #define RSC_ISA_BF16_CODE		"         BF16 [%c]"
 #define RSC_ISA_EBF16_CODE		"        EBF16 [%c]"
 #define RSC_ISA_I8MM_CODE		"         I8MM [%c]"
-#define RSC_ISA_SB_CODE			"           SB [%c]"
-#define RSC_ISA_XS_CODE			"           XS [%c]"
+#define RSC_ISA_SB_CODE 		"           SB [%c]"
+#define RSC_ISA_XS_CODE 		"           XS [%c]"
 #define RSC_ISA_LS64_CODE		"         LS64 [%c]"
 #define RSC_ISA_LS64_V_CODE		"       LS64_V [%c]"
 #define RSC_ISA_LS64_ACCDATA_CODE	" LS64_ACCDATA [%c]"
@@ -2010,5 +2020,5 @@
 #define RSC_ISA_SME_SF8FMA_CODE 	"   SME_SF8FMA [%c]"
 #define RSC_ISA_SME_SF8DP4_CODE 	"   SME_SF8DP4 [%c]"
 #define RSC_ISA_SME_SF8DP2_CODE 	"   SME_SF8DP2 [%c]"
-#define RSC_ISA_FlagM_CODE 		"        FlagM [%c]"
-#define RSC_ISA_FlagM2_CODE 		"       FlagM2 [%c]"
+#define RSC_ISA_FlagM_CODE		"        FlagM [%c]"
+#define RSC_ISA_FlagM2_CODE		"       FlagM2 [%c]"
diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h
index 3a2dd679..22f4d01d 100644
--- a/aarch64/corefreq-cli-rsc-fr.h
+++ b/aarch64/corefreq-cli-rsc-fr.h
@@ -476,6 +476,8 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_ISA_FP_COMM_CODE_FR 	RSC_ISA_FP_COMM_CODE_EN
 #define RSC_ISA_JSCVT_COMM_CODE_FR	RSC_ISA_JSCVT_COMM_CODE_EN
 #define RSC_ISA_LRCPC_COMM_CODE_FR	RSC_ISA_LRCPC_COMM_CODE_EN
+#define RSC_ISA_PACIMP_COMM_CODE_FR	RSC_ISA_PACIMP_COMM_CODE_EN
+#define RSC_ISA_PACQARMA5_COMM_CODE_FR	RSC_ISA_PACQARMA5_COMM_CODE_EN
 #define RSC_ISA_FRINTTS_COMM_CODE_FR	RSC_ISA_FRINTTS_COMM_CODE_EN
 #define RSC_ISA_SPECRES_COMM_CODE_FR	RSC_ISA_SPECRES_COMM_CODE_EN
 #define RSC_ISA_BF16_COMM_CODE_FR	RSC_ISA_BF16_COMM_CODE_EN
diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c
index bb7b0e87..140fc8db 100644
--- a/aarch64/corefreq-cli-rsc.c
+++ b/aarch64/corefreq-cli-rsc.c
@@ -690,7 +690,13 @@ RESOURCE_ST Resource[] = {
 	LDQ(RSC_ISA_JSCVT),
 	LDT(RSC_ISA_JSCVT_COMM),
 	LDQ(RSC_ISA_LRCPC),
+	LDQ(RSC_ISA_LRCPC2),
+	LDQ(RSC_ISA_LRCPC3),
 	LDT(RSC_ISA_LRCPC_COMM),
+	LDQ(RSC_ISA_PACGA),
+	LDT(RSC_ISA_PACIMP_COMM),
+	LDQ(RSC_ISA_PACQARMA5),
+	LDT(RSC_ISA_PACQARMA5_COMM),
 	LDQ(RSC_ISA_FRINTTS),
 	LDT(RSC_ISA_FRINTTS_COMM),
 	LDQ(RSC_ISA_SPECRES),
diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h
index e35608ab..2abe796a 100644
--- a/aarch64/corefreq-cli-rsc.h
+++ b/aarch64/corefreq-cli-rsc.h
@@ -513,7 +513,13 @@ enum {
 	RSC_ISA_JSCVT,
 	RSC_ISA_JSCVT_COMM,
 	RSC_ISA_LRCPC,
+	RSC_ISA_LRCPC2,
+	RSC_ISA_LRCPC3,
 	RSC_ISA_LRCPC_COMM,
+	RSC_ISA_PACGA,
+	RSC_ISA_PACIMP_COMM,
+	RSC_ISA_PACQARMA5,
+	RSC_ISA_PACQARMA5_COMM,
 	RSC_ISA_FRINTTS,
 	RSC_ISA_FRINTTS_COMM,
 	RSC_ISA_SPECRES,
diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c
index f9fba7c3..bb69fef9 100644
--- a/aarch64/corefreq-cli.c
+++ b/aarch64/corefreq-cli.c
@@ -1606,6 +1606,21 @@ REASON_CODE SysInfoISA( Window *win,
 		(unsigned short[])
 		{ RO(Shm)->Proc.Features.LRCPC },
 	},
+	{
+		NULL,
+		RSC(ISA_LRCPC2).CODE(), RSC(ISA_LRCPC_COMM).CODE(),
+		{ 0, RO(Shm)->Proc.Features.LRCPC2 },
+		(unsigned short[])
+		{ RO(Shm)->Proc.Features.LRCPC2 },
+	},
+	{
+		NULL,
+		RSC(ISA_LRCPC3).CODE(), RSC(ISA_LRCPC_COMM).CODE(),
+		{ 0, RO(Shm)->Proc.Features.LRCPC3 },
+		(unsigned short[])
+		{ RO(Shm)->Proc.Features.LRCPC3 },
+	},
+/* Row Mark */
 	{
 		NULL,
 		RSC(ISA_LS64).CODE(), RSC(ISA_LS64_COMM).CODE(),
@@ -1620,7 +1635,6 @@ REASON_CODE SysInfoISA( Window *win,
 		(unsigned short[])
 		{ RO(Shm)->Proc.Features.LS64_V },
 	},
-/* Row Mark */
 	{
 		NULL,
 		RSC(ISA_LS64_ACCDATA).CODE(), RSC(ISA_LS64_COMM).CODE(),
@@ -1635,6 +1649,7 @@ REASON_CODE SysInfoISA( Window *win,
 		(unsigned short[])
 		{ RO(Shm)->Proc.Features.LSE },
 	},
+/* Row Mark */
 	{
 		NULL,
 		RSC(ISA_LSE128).CODE(), RSC(ISA_LSE_COMM).CODE(),
@@ -1642,6 +1657,20 @@ REASON_CODE SysInfoISA( Window *win,
 		(unsigned short[])
 		{ RO(Shm)->Proc.Features.LSE128 },
 	},
+	{
+		NULL,
+		RSC(ISA_PACGA).CODE(), RSC(ISA_PACIMP_COMM).CODE(),
+		{ 0, RO(Shm)->Proc.Features.PACIMP },
+		(unsigned short[])
+		{ RO(Shm)->Proc.Features.PACIMP },
+	},
+	{
+		NULL,
+		RSC(ISA_PACQARMA5).CODE(), RSC(ISA_PACQARMA5_COMM).CODE(),
+		{ 0, RO(Shm)->Proc.Features.PACQARMA5 },
+		(unsigned short[])
+		{ RO(Shm)->Proc.Features.PACQARMA5 },
+	},
 	{
 		NULL,
 		RSC(ISA_PMULL).CODE(), RSC(ISA_AES_COMM).CODE(),
@@ -2218,10 +2247,18 @@ REASON_CODE SysInfoFeatures(	Window *win,
 	},
 	{
 		NULL,
-		RO(Shm)->Proc.Features.TLB == 1,
+		RO(Shm)->Proc.Features.TLBIOS == 1,
+		attr_Feat,
+		2, "%s%.*sTLBIOS   [%7s]", RSC(FEATURES_TLB).CODE(),
+		width - 21 - RSZ(FEATURES_TLB),
+		NULL
+	},
+	{
+		NULL,
+		RO(Shm)->Proc.Features.TLBIRANGE == 1,
 		attr_Feat,
-		2, "%s%.*sTLB   [%7s]", RSC(FEATURES_TLB).CODE(),
-		width - 18 - RSZ(FEATURES_TLB),
+		2, "%s%.*sTLBIRANGE   [%7s]", RSC(FEATURES_TLB).CODE(),
+		width - 24 - RSZ(FEATURES_TLB),
 		NULL
 	},
 	{
diff --git a/aarch64/corefreqd.c b/aarch64/corefreqd.c
index 36f8ae65..89d0d3ab 100644
--- a/aarch64/corefreqd.c
+++ b/aarch64/corefreqd.c
@@ -36,7 +36,7 @@
 	sysconf(_SC_PAGESIZE) > 0 ? sysconf(_SC_PAGESIZE) : 4096	\
 )
 
-/* §8.10.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory */
+/* AArch64 LDAXP/STLXP alignment, 128-Byte Blocks of Memory */
 static BitCC roomSeed	__attribute__ ((aligned (16))) = InitCC(0x0);
 static BitCC roomCore	__attribute__ ((aligned (16))) = InitCC(0x0);
 static BitCC roomClear	__attribute__ ((aligned (16))) = InitCC(0x0);
diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c
index ff339798..5f20e71b 100644
--- a/aarch64/corefreqk.c
+++ b/aarch64/corefreqk.c
@@ -745,13 +745,16 @@ static void Query_Features(void *pArg)
 		break;
 	}
 	switch (isar0.TLB) {
-	case 0b0001:
 	case 0b0010:
-		iArg->Features->TLB = 1;
+		iArg->Features->TLBIRANGE = 1;
+		fallthrough;
+	case 0b0001:
+		iArg->Features->TLBIOS = 1;
 		break;
 	case 0b0000:
 	default:
-		iArg->Features->TLB = 0;
+		iArg->Features->TLBIRANGE = \
+		iArg->Features->TLBIOS = 0;
 		break;
 	}
 	switch (isar0.RNDR) {
@@ -772,13 +775,36 @@ static void Query_Features(void *pArg)
 		iArg->Features->FCMA = 0;
 		break;
 	}
-	switch (isar1.LRCPC) {
+	switch (isar1.GPI) {
+	case 0b0001:
+		iArg->Features->PACIMP = 1;
+		break;
+	case 0b0000:
+		iArg->Features->PACIMP = 0;
+		break;
+	}
+	switch (isar1.GPA) {
 	case 0b0001:
+		iArg->Features->PACQARMA5 = 1;
+		break;
+	case 0b0000:
+		iArg->Features->PACQARMA5 = 0;
+		break;
+	}
+	switch (isar1.LRCPC) {
+	case 0b0011:
+		iArg->Features->LRCPC3 = 1;
+		fallthrough;
 	case 0b0010:
+		iArg->Features->LRCPC2 = 1;
+		fallthrough;
+	case 0b0001:
 		iArg->Features->LRCPC = 1;
 		break;
 	case 0b0000:
 	default:
+		iArg->Features->LRCPC3 = \
+		iArg->Features->LRCPC2 = \
 		iArg->Features->LRCPC = 0;
 		break;
 	}
diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h
index 012a296b..9db8790f 100644
--- a/aarch64/coretypes.h
+++ b/aarch64/coretypes.h
@@ -806,7 +806,7 @@ typedef struct	/* BSP features.					*/
 			SM4		: 19-18,
 			FHM		: 20-19,
 			LSE128		: 21-20,
-			TLB		: 22-21,
+			TLBIOS		: 22-21,
 			FCMA		: 23-22,
 			LRCPC		: 24-23,
 			JSCVT		: 25-24,
@@ -836,7 +836,8 @@ typedef struct	/* BSP features.					*/
 			BigEnd_EE	: 49-48,
 			PARange 	: 53-49,
 			VARange 	: 62-59,
-			_Unused1_	: 64-62;
+			TLBIRANGE	: 63-62,
+			PACIMP		: 64-63;
 
 		Bit64	CSV2		:  4-0,
 			SSBS		:  8-4,
@@ -886,7 +887,10 @@ typedef struct	/* BSP features.					*/
 			SME_SF8FMA	: 53-52,
 			SME_SF8DP4	: 54-53,
 			SME_SF8DP2	: 55-54,
-			_Unused2_	: 64-55;
+			PACQARMA5	: 56-55,
+			LRCPC2		: 57-56,
+			LRCPC3		: 58-57,
+			_Unused1_	: 64-58;
 
 		Bit64	InvariantTSC	:  8-0,
 			HyperThreading	:  9-8,
@@ -922,7 +926,7 @@ typedef struct	/* BSP features.					*/
 			OSPM_EPP	: 55-54,
 			ACPI_CST_CAP	: 56-55,
 			ACPI_CST	: 60-56, /* 15 CState sub-packages */
-			_Unused3_	: 64-60;
+			_Unused2_	: 64-60;
 	};
 	struct
 	{