From 3271cc9c227201514fc89f721a326f890840bcd8 Mon Sep 17 00:00:00 2001 From: CyrIng Date: Tue, 30 Jan 2024 22:39:14 +0100 Subject: [PATCH] [AArch64] Adding ISA Extensions --- aarch64/arm_reg.h | 35 ++++- aarch64/corefreq-cli-json.c | 74 +++++++++++ aarch64/corefreq-cli-rsc-en.h | 34 +++++ aarch64/corefreq-cli-rsc-fr.h | 2 + aarch64/corefreq-cli-rsc.c | 34 +++++ aarch64/corefreq-cli-rsc.h | 34 +++++ aarch64/corefreq-cli.c | 240 +++++++++++++++++++++++++++++++++- aarch64/corefreqk.c | 178 ++++++++++++++++++++++++- aarch64/coretypes.h | 36 ++++- 9 files changed, 658 insertions(+), 9 deletions(-) diff --git a/aarch64/arm_reg.h b/aarch64/arm_reg.h index 6da019e1..dc348d67 100644 --- a/aarch64/arm_reg.h +++ b/aarch64/arm_reg.h @@ -8,6 +8,8 @@ #define ID_AA64ISAR2_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b010) #define ID_AA64MMFR2_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b010) #define ID_AA64MMFR3_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b011) +#define ID_AA64SMFR0_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b101) +#define ID_AA64ZFR0_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b100) #define SCTLR2_EL1 sys_reg(0b11, 0b000, 0b0001, 0b0000, 0b011) #define MRS_SSBS2 sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b110) #define MRS_PAN sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b011) @@ -611,6 +613,37 @@ typedef union }; } AA64PFR2; +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + RES0 : 28-0, + SF8DP2 : 29-28, + SF8DP4 : 30-29, + SF8FMA : 31-30, + RES1 : 32-31, + F32F32 : 33-32, + BI32I32 : 34-33, + B16F32 : 35-34, + F16F32 : 36-35, + I8I32 : 40-36, + F8F32 : 41-40, + F8F16 : 42-41, + F16F16 : 43-42, + B16B16 : 44-43, + I16I32 : 48-44, + F64F64 : 49-48, + RES2 : 52-49, + I16I64 : 56-52, + SMEver : 60-56, + LUTv2 : 61-60, + RES3 : 63-61, + FA64 : 64-63; + }; +} AA64SMFR0; + typedef union { unsigned long long value; @@ -620,7 +653,7 @@ typedef union SVE_Ver : 4-0, SVE_AES : 8-4, RES0 : 16-8, - BitPermute : 20-16, + BitPerm : 20-16, SVE_BF16 : 24-20, B16B16 : 28-24, RES1 : 32-28, diff --git a/aarch64/corefreq-cli-json.c b/aarch64/corefreq-cli-json.c index fd467d82..469d29bb 100644 --- a/aarch64/corefreq-cli-json.c +++ b/aarch64/corefreq-cli-json.c @@ -478,6 +478,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FCMA); json_key(&s, "LRCPC"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC); + json_key(&s, "JSCVT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.JSCVT); + json_key(&s, "LS64"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LS64); json_end_object(&s); } json_key(&s, "MMFR1"); @@ -542,6 +546,76 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.THE); json_end_object(&s); } + json_key(&s, "ZFR0"); + { + json_start_object(&s); + json_key(&s, "SVE_F64MM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_F64MM); + json_key(&s, "SVE_F32MM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_F32MM); + json_key(&s, "SVE_I8MM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_I8MM); + json_key(&s, "SVE_SM4"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_SM4); + json_key(&s, "SVE_SHA3"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_SHA3); + json_key(&s, "SVE_BF16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_BF16); + json_key(&s, "SVE_EBF16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_EBF16); + json_key(&s, "SVE_BitPerm"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_BitPerm); + json_key(&s, "SVE_AES"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_AES); + json_key(&s, "SVE_PMULL128"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_PMULL128); + json_key(&s, "SVE2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE2); + json_end_object(&s); + } + json_key(&s, "SMFR0"); + { + json_start_object(&s); + json_key(&s, "SME_FA64"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_FA64); + json_key(&s, "SME_LUTv2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_LUTv2); + json_key(&s, "SME2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME2); + json_key(&s, "SME2p1"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME2p1); + json_key(&s, "SME_I16I64"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I16I64); + json_key(&s, "SME_F64F64"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F64F64); + json_key(&s, "SME_I16I32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I16I32); + json_key(&s, "SME_B16B16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_B16B16); + json_key(&s, "SME_F16F16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F16F16); + json_key(&s, "SME_F8F16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F8F16); + json_key(&s, "SME_F8F32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F8F32); + json_key(&s, "SME_I8I32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I8I32); + json_key(&s, "SME_F16F32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F16F32); + json_key(&s, "SME_B16F32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_B16F32); + json_key(&s, "SME_BI32I32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_BI32I32); + json_key(&s, "SME_F32F32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F32F32); + json_key(&s, "SME_SF8FMA"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8FMA); + json_key(&s, "SME_SF8DP4"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8DP4); + json_key(&s, "SME_SF8DP2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8DP2); + json_end_object(&s); + } json_key(&s, "MISC"); { json_start_object(&s); diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h index 97779d4a..8c76a94c 100644 --- a/aarch64/corefreq-cli-rsc-en.h +++ b/aarch64/corefreq-cli-rsc-en.h @@ -782,7 +782,9 @@ " Floating-point Half-precision Multiplication " #define RSC_ISA_FP_COMM_CODE_EN " Floating Point " +#define RSC_ISA_JSCVT_COMM_CODE_EN " JavaScript Conversion " #define RSC_ISA_LRCPC_COMM_CODE_EN " Load-Acquire RCpc instructions " +#define RSC_ISA_LS64_COMM_CODE_EN " Atomic 64-byte loads and stores " #define RSC_ISA_RAND_COMM_CODE_EN " Read Random Number " #define RSC_ISA_RDMA_COMM_CODE_EN " Rounding Double Multiply Accumulate " #define RSC_ISA_SHA_COMM_CODE_EN " Secure Hash Algorithms extensions " @@ -1951,7 +1953,9 @@ #define RSC_ISA_FCMA_CODE " FCMA [%c]" #define RSC_ISA_FHM_CODE " FHM [%c]" #define RSC_ISA_FP_CODE " FP [%c]" +#define RSC_ISA_JSCVT_CODE " JSCVT [%c]" #define RSC_ISA_LRCPC_CODE " LRCPC [%c]" +#define RSC_ISA_LS64_CODE " LS64 [%c]" #define RSC_ISA_RAND_CODE " RAND [%c]" #define RSC_ISA_RDMA_CODE " RDMA [%c]" #define RSC_ISA_SHA1_CODE " SHA1 [%c]" @@ -1963,4 +1967,34 @@ #define RSC_ISA_SM4_CODE " SM4 [%c]" #define RSC_ISA_SME_CODE " SME [%c]" #define RSC_ISA_SVE_CODE " SVE [%c]" +#define RSC_ISA_SVE_F64MM_CODE " SVE_F64MM [%c]" +#define RSC_ISA_SVE_F32MM_CODE " SVE_F32MM [%c]" +#define RSC_ISA_SVE_I8MM_CODE " SVE_I8MM [%c]" +#define RSC_ISA_SVE_SM4_CODE " SVE_SM4 [%c]" +#define RSC_ISA_SVE_SHA3_CODE " SVE_SHA3 [%c]" +#define RSC_ISA_SVE_BF16_CODE " SVE_BF16 [%c]" +#define RSC_ISA_SVE_EBF16_CODE " SVE_EBF16 [%c]" +#define RSC_ISA_SVE_BitPerm_CODE " SVE_BitPerm [%c]" +#define RSC_ISA_SVE_AES_CODE " SVE_AES [%c]" +#define RSC_ISA_SVE_PMULL128_CODE " SVE_PMULL128 [%c]" +#define RSC_ISA_SVE2_CODE " SVE2 [%c]" +#define RSC_ISA_SME2_CODE " SME2 [%c]" +#define RSC_ISA_SME2p1_CODE " SME2p1 [%c]" +#define RSC_ISA_SME_FA64_CODE " SME_FA64 [%c]" +#define RSC_ISA_SME_LUTv2_CODE " SME_LUTv2 [%c]" +#define RSC_ISA_SME_I16I64_CODE " SME_I16I64 [%c]" +#define RSC_ISA_SME_F64F64_CODE " SME_F64F64 [%c]" +#define RSC_ISA_SME_I16I32_CODE " SME_I16I32 [%c]" +#define RSC_ISA_SME_B16B16_CODE " SME_B16B16 [%c]" +#define RSC_ISA_SME_F16F16_CODE " SME_F16F16 [%c]" +#define RSC_ISA_SME_F8F16_CODE " SME_F8F16 [%c]" +#define RSC_ISA_SME_F8F32_CODE " SME_F8F32 [%c]" +#define RSC_ISA_SME_I8I32_CODE " SME_I8I32 [%c]" +#define RSC_ISA_SME_F16F32_CODE " SME_F16F32 [%c]" +#define RSC_ISA_SME_B16F32_CODE " SME_B16F32 [%c]" +#define RSC_ISA_SME_BI32I32_CODE " SME_BI32I32 [%c]" +#define RSC_ISA_SME_F32F32_CODE " SME_F32F32 [%c]" +#define RSC_ISA_SME_SF8FMA_CODE " SME_SF8FMA [%c]" +#define RSC_ISA_SME_SF8DP4_CODE " SME_SF8DP4 [%c]" +#define RSC_ISA_SME_SF8DP2_CODE " SME_SF8DP2 [%c]" #define RSC_ISA_TS_CODE " TS [%c]" diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h index 77475f56..1b3f6149 100644 --- a/aarch64/corefreq-cli-rsc-fr.h +++ b/aarch64/corefreq-cli-rsc-fr.h @@ -470,7 +470,9 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_ISA_FCMA_COMM_CODE_FR RSC_ISA_FCMA_COMM_CODE_EN #define RSC_ISA_FHM_COMM_CODE_FR RSC_ISA_FHM_COMM_CODE_EN #define RSC_ISA_FP_COMM_CODE_FR RSC_ISA_FP_COMM_CODE_EN +#define RSC_ISA_JSCVT_COMM_CODE_FR RSC_ISA_JSCVT_COMM_CODE_EN #define RSC_ISA_LRCPC_COMM_CODE_FR RSC_ISA_LRCPC_COMM_CODE_EN +#define RSC_ISA_LS64_COMM_CODE_FR RSC_ISA_LS64_COMM_CODE_EN #define RSC_ISA_RAND_COMM_CODE_FR RSC_ISA_RAND_COMM_CODE_EN #define RSC_ISA_RDMA_COMM_CODE_FR RSC_ISA_RDMA_COMM_CODE_EN #define RSC_ISA_SHA_COMM_CODE_FR RSC_ISA_SHA_COMM_CODE_EN diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c index 8ddd7b1b..7ebac222 100644 --- a/aarch64/corefreq-cli-rsc.c +++ b/aarch64/corefreq-cli-rsc.c @@ -678,8 +678,12 @@ RESOURCE_ST Resource[] = { LDT(RSC_ISA_FHM_COMM), LDQ(RSC_ISA_FP), LDT(RSC_ISA_FP_COMM), + LDQ(RSC_ISA_JSCVT), + LDT(RSC_ISA_JSCVT_COMM), LDQ(RSC_ISA_LRCPC), LDT(RSC_ISA_LRCPC_COMM), + LDQ(RSC_ISA_LS64), + LDT(RSC_ISA_LS64_COMM), LDQ(RSC_ISA_RAND), LDT(RSC_ISA_RAND_COMM), LDQ(RSC_ISA_RDMA), @@ -698,6 +702,36 @@ RESOURCE_ST Resource[] = { LDT(RSC_ISA_SME_COMM), LDQ(RSC_ISA_SVE), LDT(RSC_ISA_SVE_COMM), + LDQ(RSC_ISA_SVE_F64MM), + LDQ(RSC_ISA_SVE_F32MM), + LDQ(RSC_ISA_SVE_I8MM), + LDQ(RSC_ISA_SVE_SM4), + LDQ(RSC_ISA_SVE_SHA3), + LDQ(RSC_ISA_SVE_BF16), + LDQ(RSC_ISA_SVE_EBF16), + LDQ(RSC_ISA_SVE_BitPerm), + LDQ(RSC_ISA_SVE_AES), + LDQ(RSC_ISA_SVE_PMULL128), + LDQ(RSC_ISA_SVE2), + LDQ(RSC_ISA_SME2), + LDQ(RSC_ISA_SME2p1), + LDQ(RSC_ISA_SME_FA64), + LDQ(RSC_ISA_SME_LUTv2), + LDQ(RSC_ISA_SME_I16I64), + LDQ(RSC_ISA_SME_F64F64), + LDQ(RSC_ISA_SME_I16I32), + LDQ(RSC_ISA_SME_B16B16), + LDQ(RSC_ISA_SME_F16F16), + LDQ(RSC_ISA_SME_F8F16), + LDQ(RSC_ISA_SME_F8F32), + LDQ(RSC_ISA_SME_I8I32), + LDQ(RSC_ISA_SME_F16F32), + LDQ(RSC_ISA_SME_B16F32), + LDQ(RSC_ISA_SME_BI32I32), + LDQ(RSC_ISA_SME_F32F32), + LDQ(RSC_ISA_SME_SF8FMA), + LDQ(RSC_ISA_SME_SF8DP4), + LDQ(RSC_ISA_SME_SF8DP2), LDQ(RSC_ISA_TS), LDT(RSC_ISA_TS_COMM), LDT(RSC_FEATURES_TITLE), diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h index 8f23afd6..35ccb738 100644 --- a/aarch64/corefreq-cli-rsc.h +++ b/aarch64/corefreq-cli-rsc.h @@ -501,8 +501,12 @@ enum { RSC_ISA_FHM_COMM, RSC_ISA_FP, RSC_ISA_FP_COMM, + RSC_ISA_JSCVT, + RSC_ISA_JSCVT_COMM, RSC_ISA_LRCPC, RSC_ISA_LRCPC_COMM, + RSC_ISA_LS64, + RSC_ISA_LS64_COMM, RSC_ISA_RAND, RSC_ISA_RAND_COMM, RSC_ISA_RDMA, @@ -521,6 +525,36 @@ enum { RSC_ISA_SME_COMM, RSC_ISA_SVE, RSC_ISA_SVE_COMM, + RSC_ISA_SVE_F64MM, + RSC_ISA_SVE_F32MM, + RSC_ISA_SVE_I8MM, + RSC_ISA_SVE_SM4, + RSC_ISA_SVE_SHA3, + RSC_ISA_SVE_BF16, + RSC_ISA_SVE_EBF16, + RSC_ISA_SVE_BitPerm, + RSC_ISA_SVE_AES, + RSC_ISA_SVE_PMULL128, + RSC_ISA_SVE2, + RSC_ISA_SME2, + RSC_ISA_SME2p1, + RSC_ISA_SME_FA64, + RSC_ISA_SME_LUTv2, + RSC_ISA_SME_I16I64, + RSC_ISA_SME_F64F64, + RSC_ISA_SME_I16I32, + RSC_ISA_SME_B16B16, + RSC_ISA_SME_F16F16, + RSC_ISA_SME_F8F16, + RSC_ISA_SME_F8F32, + RSC_ISA_SME_I8I32, + RSC_ISA_SME_F16F32, + RSC_ISA_SME_B16F32, + RSC_ISA_SME_BI32I32, + RSC_ISA_SME_F32F32, + RSC_ISA_SME_SF8FMA, + RSC_ISA_SME_SF8DP4, + RSC_ISA_SME_SF8DP2, RSC_ISA_TS, RSC_ISA_TS_COMM, RSC_FEATURES_TITLE, diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c index e0fc9186..07b7bab0 100644 --- a/aarch64/corefreq-cli.c +++ b/aarch64/corefreq-cli.c @@ -1410,6 +1410,14 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.FP }, }, + { + NULL, + RSC(ISA_JSCVT).CODE(), RSC(ISA_JSCVT_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.JSCVT }, + (unsigned short[]) + { RO(Shm)->Proc.Features.JSCVT }, + }, +/* Row Mark */ { NULL, RSC(ISA_LRCPC).CODE(), RSC(ISA_LRCPC_COMM).CODE(), @@ -1417,7 +1425,13 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.LRCPC }, }, -/* Row Mark */ + { + NULL, + RSC(ISA_LS64).CODE(), RSC(ISA_LS64_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LS64 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LS64 }, + }, { NULL, RSC(ISA_RAND).CODE(), RSC(ISA_RAND_COMM).CODE(), @@ -1432,6 +1446,7 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.RDMA }, }, +/* Row Mark */ { NULL, RSC(ISA_SHA1).CODE(), RSC(ISA_SHA_COMM).CODE(), @@ -1446,7 +1461,6 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SHA256 }, }, -/* Row Mark */ { NULL, RSC(ISA_SHA512).CODE(), RSC(ISA_SHA_COMM).CODE(), @@ -1461,6 +1475,7 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SHA3 }, }, +/* Row Mark */ { NULL, RSC(ISA_SIMD).CODE(), RSC(ISA_SIMD_COMM).CODE(), @@ -1475,7 +1490,6 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SM3 }, }, -/* Row Mark */ { NULL, RSC(ISA_SM4).CODE(), RSC(ISA_SM_COMM).CODE(), @@ -1490,6 +1504,144 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SME }, }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME2).CODE(), RSC(ISA_SME_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SME2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME2 }, + }, + { + NULL, + RSC(ISA_SME2p1).CODE(), RSC(ISA_SME_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SME2p1 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME2p1 }, + }, + { + NULL, + RSC(ISA_SME_FA64).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_FA64 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_FA64 }, + }, + { + NULL, + RSC(ISA_SME_LUTv2).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_LUTv2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_LUTv2 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME_I16I64).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_I16I64 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_I16I64 }, + }, + { + NULL, + RSC(ISA_SME_F64F64).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F64F64 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F64F64 }, + }, + { + NULL, + RSC(ISA_SME_I16I32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_I16I32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_I16I32 }, + }, + { + NULL, + RSC(ISA_SME_B16B16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_B16B16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_B16B16 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME_F16F16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F16F16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F16F16 }, + }, + { + NULL, + RSC(ISA_SME_F8F16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F8F16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F8F16 }, + }, + { + NULL, + RSC(ISA_SME_F8F32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F8F32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F8F32 }, + }, + { + NULL, + RSC(ISA_SME_I8I32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_I8I32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_I8I32 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME_F16F32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F16F32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F16F32 }, + }, + { + NULL, + RSC(ISA_SME_B16F32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_B16F32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_B16F32 }, + }, + { + NULL, + RSC(ISA_SME_BI32I32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_BI32I32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_BI32I32 }, + }, + { + NULL, + RSC(ISA_SME_F32F32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F32F32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F32F32 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME_SF8FMA).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_SF8FMA }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_SF8FMA }, + }, + { + NULL, + RSC(ISA_SME_SF8DP4).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_SF8DP4 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_SF8DP4 }, + }, + { + NULL, + RSC(ISA_SME_SF8DP2).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_SF8DP2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_SF8DP2 }, + }, { NULL, RSC(ISA_SVE).CODE(), RSC(ISA_SVE_COMM).CODE(), @@ -1497,6 +1649,86 @@ REASON_CODE SysInfoISA( Window *win, (unsigned short[]) { RO(Shm)->Proc.Features.SVE }, }, +/* Row Mark */ + { + NULL, + RSC(ISA_SVE2).CODE(), RSC(ISA_SVE_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SVE2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE2 }, + }, + { + NULL, + RSC(ISA_SVE_F64MM).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_F64MM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_F64MM }, + }, + { + NULL, + RSC(ISA_SVE_F32MM).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_F32MM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_F32MM }, + }, + { + NULL, + RSC(ISA_SVE_I8MM).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_I8MM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_I8MM }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SVE_SM4).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_SM4 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_SM4 }, + }, + { + NULL, + RSC(ISA_SVE_SHA3).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_SHA3 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_SHA3 }, + }, + { + NULL, + RSC(ISA_SVE_BF16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_BF16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_BF16 }, + }, + { + NULL, + RSC(ISA_SVE_EBF16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_EBF16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_EBF16 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SVE_BitPerm).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_BitPerm }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_BitPerm }, + }, + { + NULL, + RSC(ISA_SVE_AES).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_AES }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_AES }, + }, + { + NULL, + RSC(ISA_SVE_PMULL128).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_PMULL128 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_PMULL128 }, + }, { NULL, RSC(ISA_TS).CODE(), RSC(ISA_TS_COMM).CODE(), @@ -6562,7 +6794,7 @@ Window *CreateTopology(unsigned long long id) Window *CreateISA(unsigned long long id) { - Window *wISA = CreateWindow(wLayer, id, 4, 5, 6, TOP_HEADER_ROW + 2); + Window *wISA = CreateWindow(wLayer, id, 4, 13, 6, TOP_HEADER_ROW + 2); if (wISA != NULL) { diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c index bfa05ba2..071e33c8 100644 --- a/aarch64/corefreqk.c +++ b/aarch64/corefreqk.c @@ -540,7 +540,6 @@ static void Query_Features(void *pArg) volatile AA64MMFR2 mmfr2; volatile AA64PFR0 pfr0; volatile AA64PFR1 pfr1; - volatile CLUSTERCFR clustercfg; iArg->Features->Info.Vendor.CRC = CRC_RESERVED; iArg->SMT_Count = 1; @@ -785,6 +784,26 @@ static void Query_Features(void *pArg) iArg->Features->LRCPC = 0; break; } + switch (isar1.JSCVT) { + case 0b0001: + iArg->Features->JSCVT = 1; + break; + case 0b0000: + default: + iArg->Features->JSCVT = 0; + break; + } + switch (isar1.LS64) { + case 0b0001: + case 0b0010: + case 0b0011: + iArg->Features->LS64 = 1; + break; + case 0b0000: + default: + iArg->Features->LS64 = 0; + break; + } switch (mmfr1.VH) { case 0b0001: iArg->Features->VHE = 1; @@ -1007,10 +1026,165 @@ static void Query_Features(void *pArg) iArg->Features->THE = 0; break; } + if (iArg->Features->SVE | iArg->Features->SME) + { + volatile AA64ZFR0 zfr0 = {.value = read_sysreg_s(ID_AA64ZFR0_EL1)}; + switch (zfr0.SVE_F64MM) { + case 0b0001: + iArg->Features->SVE_F64MM = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_F64MM = 0; + break; + } + switch (zfr0.SVE_F32MM) { + case 0b0001: + iArg->Features->SVE_F32MM = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_F32MM = 0; + break; + } + switch (zfr0.SVE_I8MM) { + case 0b0001: + iArg->Features->SVE_I8MM = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_I8MM = 0; + break; + } + switch (zfr0.SVE_SM4) { + case 0b0001: + iArg->Features->SVE_SM4 = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_SM4 = 0; + break; + } + switch (zfr0.SVE_SHA3) { + case 0b0001: + iArg->Features->SVE_SHA3 = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_SHA3 = 0; + break; + } + switch (zfr0.SVE_BF16) { + case 0b0010: + iArg->Features->SVE_EBF16 = 1; + fallthrough; + case 0b0001: + iArg->Features->SVE_BF16 = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_EBF16 = \ + iArg->Features->SVE_BF16 = 0; + break; + } + switch (zfr0.BitPerm) { + case 0b0001: + iArg->Features->SVE_BitPerm = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_BitPerm = 0; + break; + } + switch (zfr0.SVE_AES) { + case 0b0010: + iArg->Features->SVE_PMULL128 = 1; + fallthrough; + case 0b0001: + iArg->Features->SVE_AES = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_PMULL128 = \ + iArg->Features->SVE_AES = 0; + } + switch (zfr0.SVE_Ver) { + case 0b0001: + iArg->Features->SVE2 = 1; + break; + default: + iArg->Features->SVE2 = 0; + break; + } + } + if (iArg->Features->SME) { + volatile AA64SMFR0 smfr0 = {.value = read_sysreg_s(ID_AA64SMFR0_EL1)}; + + switch (smfr0.SMEver) { + case 0b0010: + iArg->Features->SME2p1 = 1; + fallthrough; + case 0b0001: + iArg->Features->SME2 = 1; + break; + default: + iArg->Features->SME2p1 = \ + iArg->Features->SME2 = 0; + break; + } + + iArg->Features->SME_FA64 = smfr0.FA64; + iArg->Features->SME_LUTv2 = smfr0.LUTv2; + + switch (smfr0.I16I64) { + case 0b1111: + iArg->Features->SME_I16I64 = 1; + break; + case 0b0000: + default: + iArg->Features->SME_I16I64 = 0; + break; + } + + iArg->Features->SME_F64F64 = smfr0.F64F64; + + switch (smfr0.I16I32) { + case 0b0101: + iArg->Features->SME_I16I32 = 1; + break; + case 0b0000: + default: + iArg->Features->SME_I16I32 = 0; + break; + } + + iArg->Features->SME_B16B16 = smfr0.B16B16; + iArg->Features->SME_F16F16 = smfr0.F16F16; + iArg->Features->SME_F8F16 = smfr0.F8F16; + iArg->Features->SME_F8F32 = smfr0.F8F32; + + switch (smfr0.I8I32) { + case 0b1111: + iArg->Features->SME_I8I32 = 1; + break; + case 0b0000: + default: + iArg->Features->SME_I8I32 = 0; + break; + } + + iArg->Features->SME_F16F32 = smfr0.F16F32; + iArg->Features->SME_B16F32 = smfr0.B16F32; + iArg->Features->SME_BI32I32 = smfr0.BI32I32; + iArg->Features->SME_F32F32 = smfr0.F32F32; + iArg->Features->SME_SF8FMA = smfr0.SF8FMA; + iArg->Features->SME_SF8DP4 = smfr0.SF8DP4; + iArg->Features->SME_SF8DP2 = smfr0.SF8DP2; + } if (Experimental && (iArg->HypervisorID == HYPERV_NONE)) { /* Query the Cluster Configuration */ - clustercfg.value = read_sysreg_s(CLUSTERCFR_EL1); + volatile CLUSTERCFR clustercfg = {.value=read_sysreg_s(CLUSTERCFR_EL1)}; if (clustercfg.NUMCORE) { iArg->SMT_Count = iArg->SMT_Count + clustercfg.NUMCORE; } diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h index 29153eeb..801e9d47 100644 --- a/aarch64/coretypes.h +++ b/aarch64/coretypes.h @@ -799,7 +799,9 @@ typedef struct /* BSP features. */ TLB : 22-21, FCMA : 23-22, LRCPC : 24-23, - _Unused1_ : 64-24; + JSCVT : 25-24, + LS64 : 26-25, + _Unused1_ : 64-26; Bit64 CSV2 : 4-0, SSBS : 8-4, @@ -819,7 +821,37 @@ typedef struct /* BSP features. */ MTE : 23-21, GCS : 24-23, THE : 25-24, - _Unused2_ : 64-25; + SVE_F64MM : 26-25, + SVE_F32MM : 27-26, + SVE_I8MM : 28-27, + SVE_SM4 : 29-28, + SVE_SHA3 : 30-29, + SVE_BF16 : 31-30, + SVE_EBF16 : 32-31, + SVE_BitPerm : 33-32, + SVE_AES : 34-33, + SVE_PMULL128 : 35-34, + SVE2 : 36-35, + SME_FA64 : 37-36, + SME_LUTv2 : 38-37, + SME2 : 39-38, + SME2p1 : 40-39, + SME_I16I64 : 41-40, + SME_F64F64 : 42-41, + SME_I16I32 : 43-42, + SME_B16B16 : 44-43, + SME_F16F16 : 45-44, + SME_F8F16 : 46-45, + SME_F8F32 : 47-46, + SME_I8I32 : 48-47, + SME_F16F32 : 49-48, + SME_B16F32 : 50-49, + SME_BI32I32 : 51-50, + SME_F32F32 : 52-51, + SME_SF8FMA : 53-52, + SME_SF8DP4 : 54-53, + SME_SF8DP2 : 55-54, + _Unused2_ : 64-55; Bit64 InvariantTSC : 8-0, HyperThreading : 9-8,