From 2499c3c389fb16e3792dce4a7400fd347c050745 Mon Sep 17 00:00:00 2001
From: CyrIng <labs@cyring.fr>
Date: Tue, 15 Oct 2024 18:38:57 +0200
Subject: [PATCH] [Intel][ARL][IMC] DDR5: `tWR = tWRPRE - tCWL - 10`

---
 x86_64/corefreqd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/x86_64/corefreqd.c b/x86_64/corefreqd.c
index 4ace2790..45e6ca05 100644
--- a/x86_64/corefreqd.c
+++ b/x86_64/corefreqd.c
@@ -6183,7 +6183,7 @@ void MTL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
 		tWR_quantity = 4U;
 		break;
 	case 5:
-		tWR_quantity = 8U;
+		tWR_quantity = 10U;
 		break;
 	}
       if (RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.Timing.tWRPRE >=