From 117b8c04ef0ef18f877472c268aadc74dd3cffb4 Mon Sep 17 00:00:00 2001 From: CyrIng Date: Wed, 28 Feb 2024 02:40:18 +0100 Subject: [PATCH] [AArch64] Features PFAR, DF2, SEL2, ECBHB added * Define MTE up to version 4 * French translation revised --- aarch64/corefreq-cli-json.c | 8 +++++ aarch64/corefreq-cli-rsc-en.h | 6 ++++ aarch64/corefreq-cli-rsc-fr.h | 58 +++++++++++++++++++++++++---------- aarch64/corefreq-cli-rsc.c | 4 +++ aarch64/corefreq-cli-rsc.h | 4 +++ aarch64/corefreq-cli.c | 40 ++++++++++++++++++++++-- aarch64/corefreqk.c | 55 ++++++++++++++++++++++++++++++--- aarch64/coretypes.h | 8 +++-- 8 files changed, 159 insertions(+), 24 deletions(-) diff --git a/aarch64/corefreq-cli-json.c b/aarch64/corefreq-cli-json.c index 9c759ed9..0b3e3272 100644 --- a/aarch64/corefreq-cli-json.c +++ b/aarch64/corefreq-cli-json.c @@ -589,6 +589,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_key(&s, "MMFR1"); { json_start_object(&s); + json_key(&s, "ECBHB"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ECBHB); json_key(&s, "PAN"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PAN); json_key(&s, "VHE"); @@ -629,6 +631,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AMU_frac); json_key(&s, "RME"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RME); + json_key(&s, "SEL2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SEL2); json_end_object(&s); } json_key(&s, "PFR1"); @@ -652,6 +656,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MPAM_frac); json_key(&s, "THE"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.THE); + json_key(&s, "DF2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DF2); + json_key(&s, "PFAR"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PFAR); json_end_object(&s); } json_key(&s, "ZFR0"); diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h index 69bd0306..ed1629e3 100644 --- a/aarch64/corefreq-cli-rsc-en.h +++ b/aarch64/corefreq-cli-rsc-en.h @@ -867,10 +867,15 @@ #define RSC_FEATURES_BIG_END_CODE_EN "Mixed-Endianness" #define RSC_FEATURES_BTI_CODE_EN "Branch Target Identification" #define RSC_FEATURES_EBEP_CODE_EN "Exception-based event profiling" +#define RSC_FEATURES_ECBHB_CODE_EN \ + "Exploitative Control w/ Branch History Buffer" + #define RSC_FEATURES_ECV_CODE_EN "Enhanced Counter Virtualization" +#define RSC_FEATURES_DF2_CODE_EN "Double Fault Extension" #define RSC_FEATURES_DIT_CODE_EN "Data Independent Timing" #define RSC_FEATURES_EXS_CODE_EN "Context Synchronization & Exception Handling" #define RSC_FEATURES_FGT_CODE_EN "Fine-Grained Trap controls" +#define RSC_FEATURES_PFAR_CODE_EN "Physical Fault Address Registers" #define RSC_FEATURES_GCS_CODE_EN "Guarded Control Stack" #define RSC_FEATURES_GIC_CODE_EN "Generic Interrupt Controller" #define RSC_FEATURES_MPAM_CODE_EN "Memory Partitioning and Monitoring" @@ -880,6 +885,7 @@ #define RSC_FEATURES_PAN_CODE_EN "Privileged Access Never" #define RSC_FEATURES_RAS_CODE_EN "Reliability Availability & Serviceability" #define RSC_FEATURES_RME_CODE_EN "Realm Management Extension" +#define RSC_FEATURES_SEL2_CODE_EN "Secure EL2 Implementation" #define RSC_FEATURES_THE_CODE_EN "Translation Hardening Extension" #define RSC_FEATURES_TLB_CODE_EN "TLB maintenance instructions" #define RSC_FEATURES_TME_CODE_EN "Transactional Memory Extension" diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h index 7ac97bfe..9fce744f 100644 --- a/aarch64/corefreq-cli-rsc-fr.h +++ b/aarch64/corefreq-cli-rsc-fr.h @@ -530,30 +530,45 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_INVARIANT_CODE_FR "Invariant" #define RSC_FEATURES_ACPI_CODE_FR \ - "Configuration avanc""\xa9""e et interface d'alimentation" + "Configuration Avanc""\xa9""e & Interface d'Alimentation" #define RSC_FEATURES_AMU_CODE_FR \ "Unit""\xa9"" de surveillance de l'activit""\xa9" -#define RSC_FEATURES_BIG_END_CODE_FR RSC_FEATURES_BIG_END_CODE_EN +#define RSC_FEATURES_BIG_END_CODE_FR "Endianisme Mixte" #define RSC_FEATURES_BTI_CODE_FR "Validation des cibles de branche" #define RSC_FEATURES_EBEP_CODE_FR \ - "Profilage d'""\xa9""v""\xa9""nements en fonction des exceptions" + "Profilage d'""\xa9""v""\xa9""nements bas""\xa9"" sur les exceptions" + +#define RSC_FEATURES_ECBHB_CODE_FR \ + "Contr. Exploit. avec Tampon Hist. Branchement" #define RSC_FEATURES_ECV_CODE_FR \ - "Virtualisation am""\xa9""lior""\xa9""e des compteurs" + "Virtualisation am""\xa9""lior""\xa9""e des compteurs" + +#define RSC_FEATURES_DF2_CODE_FR "Extension de Double D""\xa9""faut" +#define RSC_FEATURES_DIT_CODE_FR \ + "Chronom""\xa9""trage Ind""\xa9""pendant des Donn""\xa9""es" -#define RSC_FEATURES_DIT_CODE_FR RSC_FEATURES_DIT_CODE_EN #define RSC_FEATURES_EXS_CODE_FR \ - "Synchronisation du contexte & gestion d'exceptions" + "Sync. de Contexte & Gestion d'Exceptions" + +#define RSC_FEATURES_FGT_CODE_FR \ + "Contr""\xb4""les de Pi""\xa8""ges ""\xa0"" Granularit""\xa9"" Fine" + +#define RSC_FEATURES_PFAR_CODE_FR \ + "Registres de D""\xa9""faut d'Adresse Physique" + +#define RSC_FEATURES_GCS_CODE_FR \ + "Pile de Contr""\xb4""le Prot""\xa9""g""\xa9""e" -#define RSC_FEATURES_FGT_CODE_FR RSC_FEATURES_FGT_CODE_EN -#define RSC_FEATURES_GCS_CODE_FR RSC_FEATURES_GCS_CODE_EN #define RSC_FEATURES_GIC_CODE_FR \ "Contr""\xb4""leur d'interruption g""\xa9""n""\xa9""rique" -#define RSC_FEATURES_MTE_CODE_FR "Extension de marquage de m""\xa9""moire" +#define RSC_FEATURES_MTE_CODE_FR \ + "Extension de marquage de m""\xa9""moire" + #define RSC_FEATURES_MPAM_CODE_FR \ "Partitionnement et supervision de la m""\xa9""moire" @@ -563,14 +578,25 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_FEATURES_RAS_CODE_FR \ "Fiabilit""\xa9"" Disponibilit""\xa9"" et Durabilit""\xa9" -#define RSC_FEATURES_RME_CODE_FR RSC_FEATURES_RME_CODE_EN -#define RSC_FEATURES_THE_CODE_FR RSC_FEATURES_THE_CODE_EN +#define RSC_FEATURES_RME_CODE_FR "Extension de Gestion de Domaine" +#define RSC_FEATURES_SEL2_CODE_FR \ + "Impl""\xa9""mentation S""\xa9""curis""\xa9""e de l'EL2" + +#define RSC_FEATURES_THE_CODE_FR \ + "Endurcissement ""\x89""tendu de la Translation" + #define RSC_FEATURES_TLB_CODE_FR "Instructions de gestion TLB" -#define RSC_FEATURES_TME_CODE_FR "Extension de m""\xa9""moire transactionnelle" +#define RSC_FEATURES_TME_CODE_FR \ + "Extension de m""\xa9""moire transactionnelle" + #define RSC_FEATURES_TSC_CODE_FR "Compteur d'horodatage" -#define RSC_FEATURES_UAO_CODE_FR "Surcharge de l'acc""\xa8""s utilisateur" +#define RSC_FEATURES_UAO_CODE_FR \ + "Surcharge de l'acc""\xa8""s utilisateur" + #define RSC_FEATURES_VA_CODE_FR "Plage d'adressage virtuel" -#define RSC_FEATURES_VHE_CODE_FR "Extensions d'H""\xb4""te de Virtualisation" +#define RSC_FEATURES_VHE_CODE_FR \ + "Extensions d'H""\xb4""te de Virtualisation" + #define RSC_FEAT_SECTION_MECH_CODE_FR "M""\xa9""canismes d'att""\xa9""nuation" #define RSC_FEAT_SECTION_SEC_CODE_FR "Fonctions de s""\xa9""curit""\xa9" @@ -1264,10 +1290,10 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_MECH_CLRBHB_CODE_FR "Effacement de l'historique de branche" #define RSC_MECH_SSBD_CODE_FR \ - "Contournement du rangement sp""\xa9""culatif d""\xa9""sactiv""\xa9" + "Contournement Sp""\xa9""culatif de Magasin d""\xa9""sactiv""\xa9" #define RSC_MECH_SSBS_CODE_FR \ - "Contournement s""\xbb""r du rangement sp""\xa9""culatif" + "Contournement Sp""\xa9""culatif de Magasin Prot""\xa9""g""\xa9" #define RSC_CREATE_SELECT_AUTO_TURBO_CODE_FR " %3s Processeur " \ " %s %c%4u %c " diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c index 1dec78ed..4ed423ad 100644 --- a/aarch64/corefreq-cli-rsc.c +++ b/aarch64/corefreq-cli-rsc.c @@ -828,10 +828,13 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_BIG_END), LDT(RSC_FEATURES_BTI), LDT(RSC_FEATURES_EBEP), + LDT(RSC_FEATURES_ECBHB), LDT(RSC_FEATURES_ECV), + LDT(RSC_FEATURES_DF2), LDT(RSC_FEATURES_DIT), LDT(RSC_FEATURES_EXS), LDT(RSC_FEATURES_FGT), + LDT(RSC_FEATURES_PFAR), LDT(RSC_FEATURES_GCS), LDT(RSC_FEATURES_GIC), LDT(RSC_FEATURES_MPAM), @@ -841,6 +844,7 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_PAN), LDT(RSC_FEATURES_RAS), LDT(RSC_FEATURES_RME), + LDT(RSC_FEATURES_SEL2), LDT(RSC_FEATURES_THE), LDT(RSC_FEATURES_TLB), LDT(RSC_FEATURES_TME), diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h index eea24440..718398d9 100644 --- a/aarch64/corefreq-cli-rsc.h +++ b/aarch64/corefreq-cli-rsc.h @@ -651,10 +651,13 @@ enum { RSC_FEATURES_BIG_END, RSC_FEATURES_BTI, RSC_FEATURES_EBEP, + RSC_FEATURES_ECBHB, RSC_FEATURES_ECV, + RSC_FEATURES_DF2, RSC_FEATURES_DIT, RSC_FEATURES_EXS, RSC_FEATURES_FGT, + RSC_FEATURES_PFAR, RSC_FEATURES_GCS, RSC_FEATURES_GIC, RSC_FEATURES_MPAM, @@ -664,6 +667,7 @@ enum { RSC_FEATURES_PAN, RSC_FEATURES_RAS, RSC_FEATURES_RME, + RSC_FEATURES_SEL2, RSC_FEATURES_THE, RSC_FEATURES_TLB, RSC_FEATURES_TME, diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c index e702418f..42fb3eb9 100644 --- a/aarch64/corefreq-cli.c +++ b/aarch64/corefreq-cli.c @@ -2268,6 +2268,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 18 - RSZ(FEATURES_ECV), NULL }, + { + NULL, + RO(Shm)->Proc.Features.DF2 == 1, + attr_Feat, + 2, "%s%.*sDF2 [%7s]", RSC(FEATURES_DF2).CODE(), + width - 18 - RSZ(FEATURES_DF2), + NULL + }, { NULL, RO(Shm)->Proc.Features.DIT == 1, @@ -2300,6 +2308,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 19 - RSZ(FEATURES_FGT), NULL }, + { + NULL, + RO(Shm)->Proc.Features.PFAR == 1, + attr_Feat, + 2, "%s%.*sPFAR [%7s]", RSC(FEATURES_PFAR).CODE(), + width - 19 - RSZ(FEATURES_PFAR), + NULL + }, { NULL, ( RO(Shm)->Proc.Features.GIC_vers @@ -2330,10 +2346,14 @@ REASON_CODE SysInfoFeatures( Window *win, NULL, RO(Shm)->Proc.Features.MTE > 0, attr_Feat, - 2, RO(Shm)->Proc.Features.MTE == 3 ? + 2, RO(Shm)->Proc.Features.MTE == 4 ? + "%s v4%.*sMTE [%7s]" + : RO(Shm)->Proc.Features.MTE == 3 ? "%s v3%.*sMTE [%7s]" : RO(Shm)->Proc.Features.MTE == 2 ? - "%s v2%.*sMTE [%7s]" : "%s %.*sMTE [%7s]", + "%s v2%.*sMTE [%7s]" + : RO(Shm)->Proc.Features.MTE == 1 ? + "%s v1%.*sMTE [%7s]" : "%s %.*sMTE [%7s]", RSC(FEATURES_MTE).CODE(), width - 21 - RSZ(FEATURES_MTE), NULL }, @@ -2503,6 +2523,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 19 - RSZ(MECH_SSBD), MECH }, + { + NULL, + RO(Shm)->Proc.Features.ECBHB == 1, + attr_Feat, + 2, "%s%.*sECBHB [%7s]", RSC(FEATURES_ECBHB).CODE(), + width - 20 - RSZ(FEATURES_ECBHB), + MECH + }, { NULL, RO(Shm)->Proc.Mechanisms.SSBS, @@ -2544,6 +2572,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 18 - RSZ(FEATURES_RME), NULL }, + { + NULL, + RO(Shm)->Proc.Features.SEL2 == 1, + attr_Feat, + 2, "%s%.*sSEL2 [%7s]", RSC(FEATURES_SEL2).CODE(), + width - 19 - RSZ(FEATURES_SEL2), + NULL + }, { NULL, RO(Shm)->Proc.Features.THE == 1, diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c index 556d3467..0cb0cdcd 100644 --- a/aarch64/corefreqk.c +++ b/aarch64/corefreqk.c @@ -1057,6 +1057,7 @@ static void Query_Features(void *pArg) iArg->Features->CONSTPACFIELD = 0; break; } + switch (mmfr0.ECV) { case 0b0010: case 0b0001: @@ -1129,6 +1130,16 @@ static void Query_Features(void *pArg) iArg->Features->PAN = 0; break; } + switch (mmfr1.ECBHB) { + case 0b0001: + iArg->Features->ECBHB = 1; + break; + case 0b0000: + default: + iArg->Features->ECBHB = 0; + break; + } + switch (mmfr2.UAO) { case 0b0001: iArg->Features->UAO = 1; @@ -1143,6 +1154,7 @@ static void Query_Features(void *pArg) } else { iArg->Features->VARange = 0b11; } + switch (pfr0.FP) { case 0b0000: case 0b0001: @@ -1266,6 +1278,15 @@ static void Query_Features(void *pArg) iArg->Features->RME = 0; break; } + switch (pfr0.SEL2) { + case 0b0001: + iArg->Features->SEL2 = 1; + break; + case 0b0000: + default: + iArg->Features->SEL2 = 0; + break; + } switch (pfr1.BT) { case 0b0001: @@ -1293,14 +1314,22 @@ static void Query_Features(void *pArg) break; } break; + case 0b0011: + default: + switch (pfr1.MTEX) { + case 0b0001: + iArg->Features->MTE = 4; + break; + case 0b0000: + default: + iArg->Features->MTE = 3; + break; + } + break; case 0b0001: iArg->Features->MTE = 1; break; - case 0b0011: - iArg->Features->MTE = 3; - break; case 0b0000: - default: iArg->Features->MTE = 0; break; } @@ -1353,6 +1382,24 @@ static void Query_Features(void *pArg) iArg->Features->THE = 0; break; } + switch (pfr1.DF2) { + case 0b0001: + iArg->Features->DF2 = 1; + break; + case 0b0000: + default: + iArg->Features->DF2 = 0; + break; + } + switch (pfr1.PFAR) { + case 0b0001: + iArg->Features->PFAR = 1; + break; + case 0b0000: + default: + iArg->Features->PFAR = 0; + break; + } if (iArg->Features->SVE | iArg->Features->SME) { volatile AA64ZFR0 zfr0 = {.value = SysRegRead(ID_AA64ZFR0_EL1)}; diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h index df04c0c2..ff31e863 100644 --- a/aarch64/coretypes.h +++ b/aarch64/coretypes.h @@ -854,7 +854,8 @@ typedef struct /* BSP features. */ AMU_vers : 19-18, AMU_frac : 20-19, RME : 21-20, - MTE : 23-21, + SEL2 : 22-21, + ECBHB : 23-22, GCS : 24-23, THE : 25-24, SVE_F64MM : 26-25, @@ -911,7 +912,10 @@ typedef struct /* BSP features. */ ATS1A : 12-11, CONSTPACFIELD : 13-12, RNG_TRAP : 14-13, - _Unused1_ : 64-14; + MTE : 17-14, + DF2 : 18-17, + PFAR : 19-18, + _Unused1_ : 64-19; Bit64 InvariantTSC : 8-0, HyperThreading : 9-8,