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CPU 実験 (IS 2019 A Semester)

東京大学理学部情報科学科 CPU 実験 第7班

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  1. core core Public

    RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019@UTokyo

    SystemVerilog 5 2

  2. compiler compiler Public

    compile compile compile ....

    OCaml 1

  3. simulator simulator Public

    Unprivileged rv32imf simulator written in C.

    C

  4. fpu fpu Public

    SystemVerilog

  5. assembler assembler Public

    simple assembler (having a little functions)

    Assembly

Repositories

Showing 5 of 5 repositories
  • core Public

    RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019@UTokyo

    cpuex2019-7th/core’s past year of commit activity
    SystemVerilog 5 2 2 0 Updated Feb 27, 2020
  • compiler Public

    compile compile compile ....

    cpuex2019-7th/compiler’s past year of commit activity
    OCaml 1 0 0 0 Updated Feb 27, 2020
  • assembler Public

    simple assembler (having a little functions)

    cpuex2019-7th/assembler’s past year of commit activity
    Assembly 0 0 6 0 Updated Dec 5, 2019
  • simulator Public

    Unprivileged rv32imf simulator written in C.

    cpuex2019-7th/simulator’s past year of commit activity
    C 0 0 1 0 Updated Dec 5, 2019
  • fpu Public
    cpuex2019-7th/fpu’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Dec 4, 2019

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