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mediatek: filogic: sync upstream dts changes
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| // SPDX-License-Identifier: GPL-2.0-or-later OR MIT | ||
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| /dts-v1/; | ||
| #include "mt7981b-cetron-ct3003.dts" | ||
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| / { | ||
| model = "Cetron CT3003 (U-Boot mod)"; | ||
| compatible = "cetron,ct3003-mod", "mediatek,mt7981"; | ||
| }; | ||
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||
| &spi0 { | ||
| spi_nand@0 { | ||
| partitions { | ||
| partition@580000 { | ||
| label = "ubi"; | ||
| reg = <0x0580000 0x7000000>; | ||
| }; | ||
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| /delete-node/ partition@2580000; | ||
| /delete-node/ partition@4580000; | ||
| }; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,7 +1,4 @@ | ||
| // SPDX-License-Identifier: GPL-2.0-or-later OR MIT | ||
| /* | ||
| * Copyright (C) Tianling Shen <[email protected]> | ||
| */ | ||
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| /dts-v1/; | ||
| #include <dt-bindings/gpio/gpio.h> | ||
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|
@@ -10,64 +7,60 @@ | |
| #include "mt7981.dtsi" | ||
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| / { | ||
| model = "JCG Q30 Pro"; | ||
| compatible = "jcg,q30_pro", "mediatek,mt7981"; | ||
| model = "JCG Q30 PRO"; | ||
| compatible = "jcg,q30-pro", "mediatek,mt7981"; | ||
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| aliases { | ||
| led-boot = &status_red_led; | ||
| led-failsafe = &status_red_led; | ||
| led-running = &status_blue_led; | ||
| led-upgrade = &status_blue_led; | ||
| serial0 = &uart0; | ||
| label-mac-device = &gmac0; | ||
| led-boot = &led_status_red; | ||
| led-failsafe = &led_status_red; | ||
| led-running = &led_status_blue; | ||
| led-upgrade = &led_status_blue; | ||
| }; | ||
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| chosen { | ||
| stdout-path = "serial0:115200n8"; | ||
| }; | ||
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| memory { | ||
| reg = <0 0x40000000 0 0x10000000>; | ||
| }; | ||
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| gpio-keys { | ||
| compatible = "gpio-keys"; | ||
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| button-reset { | ||
| reset { | ||
| label = "reset"; | ||
| linux,code = <KEY_RESTART>; | ||
| gpios = <&pio 1 GPIO_ACTIVE_LOW>; | ||
| }; | ||
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| button-wps { | ||
| label = "wps"; | ||
| linux,code = <KEY_WPS_BUTTON>; | ||
| gpios = <&pio 0 GPIO_ACTIVE_HIGH>; | ||
| }; | ||
| }; | ||
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| gpio-leds { | ||
| leds { | ||
| compatible = "gpio-leds"; | ||
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| status_red_led: led-0 { | ||
| led_status_red: red { | ||
| label = "red:status"; | ||
| gpios = <&pio 8 GPIO_ACTIVE_HIGH>; | ||
| }; | ||
|
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||
| status_blue_led: led-1 { | ||
| led_status_blue: blue { | ||
| label = "blue:status"; | ||
| gpios = <&pio 13 GPIO_ACTIVE_LOW>; | ||
| }; | ||
| }; | ||
| }; | ||
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| ð { | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&mdio_pins>; | ||
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| status = "okay"; | ||
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| gmac0: mac@0 { | ||
| compatible = "mediatek,eth-mac"; | ||
| reg = <0>; | ||
| phy-mode = "2500base-x"; | ||
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| nvmem-cells = <&macaddr_factory_a002a>; | ||
| nvmem-cells = <&macaddr_lan>; | ||
| nvmem-cell-names = "mac-address"; | ||
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| fixed-link { | ||
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@@ -95,22 +88,16 @@ | |
| pinctrl-0 = <&spi0_flash_pins>; | ||
| status = "okay"; | ||
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| spi_nand: flash@0 { | ||
| spi_nand@0 { | ||
| compatible = "spi-nand"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "spi-nand"; | ||
| reg = <0>; | ||
| spi-max-frequency = <52000000>; | ||
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| spi-cal-enable; | ||
| spi-cal-mode = "read-data"; | ||
| spi-cal-datalen = <7>; | ||
| spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; | ||
| spi-cal-addrlen = <5>; | ||
| spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; | ||
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| spi-max-frequency = <52000000>; | ||
| spi-tx-buswidth = <4>; | ||
| spi-rx-buswidth = <4>; | ||
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| mediatek,nmbm; | ||
| mediatek,bmt-max-ratio = <1>; | ||
| mediatek,bmt-max-reserved-blocks = <64>; | ||
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@@ -121,40 +108,31 @@ | |
| #size-cells = <1>; | ||
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| partition@0 { | ||
| label = "BL2"; | ||
| reg = <0x00000 0x100000>; | ||
| label = "bl2"; | ||
| reg = <0x0000000 0x0100000>; | ||
| read-only; | ||
| }; | ||
|
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||
| partition@100000 { | ||
| label = "u-boot-env"; | ||
| reg = <0x100000 0x80000>; | ||
| reg = <0x0100000 0x0080000>; | ||
| }; | ||
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| factory: partition@180000 { | ||
| label = "Factory"; | ||
| reg = <0x180000 0x200000>; | ||
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| compatible = "nvmem-cells"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
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| macaddr_factory_a002a: macaddr@a002a { | ||
| reg = <0xa002a 0x6>; | ||
| }; | ||
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| macaddr_factory_a0024: macaddr@a0024 { | ||
| reg = <0xa0024 0x6>; | ||
| }; | ||
| reg = <0x0180000 0x0200000>; | ||
| read-only; | ||
| }; | ||
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| partition@380000 { | ||
| label = "FIP"; | ||
| reg = <0x380000 0x200000>; | ||
| label = "fip"; | ||
| reg = <0x0380000 0x0200000>; | ||
| read-only; | ||
| }; | ||
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| partition@580000 { | ||
| label = "ubi"; | ||
| reg = <0x580000 0x6e80000>; | ||
| reg = <0x0580000 0x7000000>; | ||
| }; | ||
| }; | ||
| }; | ||
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@@ -168,8 +146,7 @@ | |
| port@0 { | ||
| reg = <0>; | ||
| label = "wan"; | ||
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| nvmem-cells = <&macaddr_factory_a0024>; | ||
| nvmem-cells = <&macaddr_wan>; | ||
| nvmem-cell-names = "mac-address"; | ||
| }; | ||
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@@ -190,6 +167,7 @@ | |
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| port@6 { | ||
| reg = <6>; | ||
| label = "cpu"; | ||
| ethernet = <&gmac0>; | ||
| phy-mode = "2500base-x"; | ||
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@@ -212,13 +190,13 @@ | |
| conf-pu { | ||
| pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; | ||
| drive-strength = <8>; | ||
| bias-pull-up = <103>; | ||
| mediatek,pull-up-adv = <0>; /* bias-disable */ | ||
| }; | ||
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| conf-pd { | ||
| pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; | ||
| drive-strength = <8>; | ||
| bias-pull-down = <103>; | ||
| mediatek,pull-up-adv = <0>; /* bias-disable */ | ||
| }; | ||
| }; | ||
| }; | ||
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@@ -236,3 +214,17 @@ | |
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| mediatek,mtd-eeprom = <&factory 0x0>; | ||
| }; | ||
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| &factory { | ||
| compatible = "nvmem-cells"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
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| macaddr_wan: macaddr@a0024 { | ||
| reg = <0xa0024 0x6>; | ||
| }; | ||
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| macaddr_lan: macaddr@a002a { | ||
| reg = <0xa002a 0x6>; | ||
| }; | ||
| }; | ||
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