AvalonMM: Initial Support for Burst read/write transactions

[mawillia]

First pass; fixes #43

Review / comments appreciated.

[cmarqu]

Thanks for the contribution, just some small stylistic things.

[cmarqu]

Would it be possible to implement a test for this in https://github.com/cocotb/cocotb-bus/blob/master/tests/test_cases/test_avalon/test_avalon.py?

[mawillia]

I understand what you are asking for. At the moment the test_avalon.py really only tests the AvalonMemory slave python class. There isn't anything that tests any of the AvalonMM driver class. To test that out, would need a different HDL design block that implemented the slave side of the Avalon MM bus (I've done that for IP my company is developing, but can't share it yet). I might be able to get something like that together, but it will take a little weekend time. Is VHDL acceptable or only Verilog for the designs section of the repository? What simulators do you normally test with (I am using Intel's version of Questa)? I'm not a strong verilog guy, but if you back me into a corner I could probably pull something together.

I am planning to add additional capability to the AvalonMM to support additional testing (e.g., handling parameterized read latency, byte enables for writes, etc.).

[themperek]

@mawillia We can add GHDL for testing here. Possibly even Questa but this is a bit more involved.