This document describes the design of the Memory Mapped IO (MMIO) sub-system used by the cloudFPGA platform.
A block diagram of MMIO is depicted in Figure [TODO-Under construction]. It features a ...
The design of MEM uses some specific HDL and HLS naming rules to ease the description and the understanding of
its architecture. Please consider reading the two documents HDL coding style and naming conventions
and HLS coding style and naming conventions before diving into the code or starting
to contribute to this part of the cloudFPGA project.
The following table lists the sub-components of MMIO and provides a link to their documentation as well as their
architecture body.
| Entity | Description | Architecture |
|---|---|---|
| TODO | Under construction | Todo |
| TODO | Under construction | Todo |
| TODO | Under construction | Todo |