This document describes the design of the 10 Gigabit Ethernet (ETH) sub-system used by the cloudFPGA platform.
A block diagram of ETH is depicted in Figure [TODO-Under construction]. It features a ...
From an Open Systems Interconnection (OSI) model point of view, the ETH module implements the Physical layer
(L1) and the Data Link layer (L2) of the OSI model. These two layers are also referred to as the Network
Access layer in the TCP/IP model.
The design of ETH uses some specific HDL and HLS naming rules to ease the description and the understanding of
its architecture. Please consider reading the two documents HDL coding style and naming conventions
and HLS coding style and naming conventions before diving into the code or starting
to contribute to this part of the cloudFPGA project.
The following table lists the sub-components of ETH and provides a link to their documentation as well as their
architecture body.
| Entity | Description | Architecture |
|---|---|---|
| META | Synchronization block | TenGigEth_SyncBlock |
| CORE | 10GbE core | TenGigEth_Core |
| ALGC | Clock source | TenGigEth_AxiLiteClk |