From 7ff9dea1064d09b52cebc2ab0d3f7acb1a454e22 Mon Sep 17 00:00:00 2001 From: Akira Moroo Date: Tue, 21 Mar 2023 17:52:53 +0900 Subject: [PATCH 1/2] pci: Fix typo Signed-off-by: Akira Moroo --- src/pci.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/pci.rs b/src/pci.rs index 8e02bde4..5919e54b 100644 --- a/src/pci.rs +++ b/src/pci.rs @@ -295,7 +295,7 @@ impl PciDevice { panic!("I/O BARs are not supported on this platform"); } } else { - // bits 2-1 are the type 0 is 32-but, 2 is 64 bit + // bits 2-1 are the type 0 is 32-bit, 2 is 64 bit match bar >> 1 & 3 { 0 => { self.bars[current_bar].bar_type = PciBarType::MemorySpace32; From 62558d16ee4f35a06dd7bdf947655761590aad0d Mon Sep 17 00:00:00 2001 From: Akira Moroo Date: Tue, 21 Mar 2023 17:48:34 +0900 Subject: [PATCH 2/2] pci: Handle overflow on 32-bit PCI BAR size calculation The firmware panics if the calculated 32-bit BAR size overflows on debug build. Signed-off-by: Akira Moroo --- src/pci.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/pci.rs b/src/pci.rs index 5919e54b..4495bf99 100644 --- a/src/pci.rs +++ b/src/pci.rs @@ -302,7 +302,9 @@ impl PciDevice { self.bars[current_bar].address = u64::from(bar & 0xffff_fff0); self.write_u32(current_bar_offset, 0xffff_ffff); - let size = !(self.read_u32(current_bar_offset) & 0xffff_fff0) + 1; + let size = (!(self.read_u32(current_bar_offset) & 0xffff_fff0)) + .checked_add(1) + .unwrap_or(0); self.bars[current_bar].size = u64::from(size); self.write_u32(current_bar_offset, bar); }