From 3b4c7f930b850461cc0fe389478d74727270e158 Mon Sep 17 00:00:00 2001 From: Christiaan Baaij Date: Fri, 27 Oct 2023 16:54:13 +0200 Subject: [PATCH] Add index to assingnment pattern in SV Without them, the following SV tests fail on QuestaSim Intel Starter Edition 2023.1: * T1524 * Transpose * VMerge --- changelog/2023-10-31T11_39_43+01_00_sv_compat | 1 + clash-lib/src/Clash/Backend/SystemVerilog.hs | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) create mode 100644 changelog/2023-10-31T11_39_43+01_00_sv_compat diff --git a/changelog/2023-10-31T11_39_43+01_00_sv_compat b/changelog/2023-10-31T11_39_43+01_00_sv_compat new file mode 100644 index 0000000000..986a26e74d --- /dev/null +++ b/changelog/2023-10-31T11_39_43+01_00_sv_compat @@ -0,0 +1 @@ +FIXED: SystemVerilog backend: Assignment patterns for unpacked arrays now have an index for every element; improves QuestaSim compatibility. diff --git a/clash-lib/src/Clash/Backend/SystemVerilog.hs b/clash-lib/src/Clash/Backend/SystemVerilog.hs index 9a46329ff3..88928dc138 100644 --- a/clash-lib/src/Clash/Backend/SystemVerilog.hs +++ b/clash-lib/src/Clash/Backend/SystemVerilog.hs @@ -1147,10 +1147,10 @@ expr_ b (DataCon _ (DC (Void {}, -1)) [e]) = expr_ b e expr_ _ (DataCon ty@(Vector 0 _) _ _) = verilogTypeErrValue ty -expr_ _ (DataCon (Vector 1 elTy) _ [e]) = "'" <> braces (toSLV elTy e) +expr_ _ (DataCon (Vector 1 elTy) _ [e]) = "'" <> braces (int 0 <> colon <+> toSLV elTy e) expr_ _ e@(DataCon ty@(Vector _ elTy) _ [e1,e2]) = case vectorChain e of - Just es -> "'" <> listBraces (mapM (toSLV elTy) es) + Just es -> "'" <> listBraces (zipWithM (\i e3 -> int i <> colon <+> toSLV elTy e3) [0..] es) Nothing -> verilogTypeMark ty <> "_cons" <> parens (expr_ False e1 <> comma <+> expr_ False e2) expr_ _ (DataCon (MemBlob n m) _ [n0, m0, _, runs, _, ends])