workshop: too many steps exposed

[proppy]

from @mdagois

Everything after the IR is basically the steps most people will not understand. These would need way more explanation. In a future where one creates all their hardware using DSLX, they would never care about placement and routing.
I see those steps as the equivalent of assembly for C++. You expect the C++ compiler to do its job of spitting an executable, and only advanced users would peek into the generated assembly.
By the way, the chairman (forgot his name) was confused about the whole thing as well. He wanted to know how to deep dive into the steps that are actually automatic in the flow.

The most important steps to show are: the DSLX, the generated Verilog, the gate graph and the final result.