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Improve boundaryBuffers API | move boundaryBuffers to within-Tile (backport #3342) #3344

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May 5, 2023
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Improve boundaryBuffers API | move boundaryBuffers to within-Tile (backport #3342) #3344

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17 changes: 8 additions & 9 deletions src/main/scala/tile/RocketTile.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ import freechips.rocketchip.subsystem.TileCrossingParamsLike
import freechips.rocketchip.util._
import freechips.rocketchip.prci.{ClockSinkParameters}

case class RocketTileBoundaryBufferParams(force: Boolean = false)

case class RocketTileParams(
core: RocketCoreParams = RocketCoreParams(),
Expand All @@ -26,7 +27,7 @@ case class RocketTileParams(
beuAddr: Option[BigInt] = None,
blockerCtrlAddr: Option[BigInt] = None,
clockSinkParams: ClockSinkParameters = ClockSinkParameters(),
boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None
) extends InstantiableTileParams[RocketTile] {
require(icache.isDefined)
require(dcache.isDefined)
Expand Down Expand Up @@ -104,17 +105,15 @@ class RocketTile private(

override lazy val module = new RocketTileModuleImp(this)

override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = crossing match {
case _: RationalCrossing =>
if (!rocketParams.boundaryBuffers) TLBuffer(BufferParams.none)
else TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1))
override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match {
case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer()
case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1))
case _ => TLBuffer(BufferParams.none)
}

override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = crossing match {
case _: RationalCrossing =>
if (!rocketParams.boundaryBuffers) TLBuffer(BufferParams.none)
else TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none)
override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match {
case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer()
case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none)
case _ => TLBuffer(BufferParams.none)
}
}
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/tile/TilePRCIDomain.scala
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Expand Up @@ -93,7 +93,7 @@ abstract class TilePRCIDomain[T <: BaseTile](
def crossSlavePort(crossingType: ClockCrossingType): TLInwardNode = { DisableMonitors { implicit p => FlipRendering { implicit p =>
val tlSlaveResetXing = this {
tile_reset_domain.crossTLIn(tile.slaveNode) :*=
tile.makeSlaveBoundaryBuffers(crossingType)
tile { tile.makeSlaveBoundaryBuffers(crossingType) }
}
val tlSlaveClockXing = this.crossIn(tlSlaveResetXing)
tlSlaveClockXing(crossingType)
Expand All @@ -104,7 +104,7 @@ abstract class TilePRCIDomain[T <: BaseTile](
*/
def crossMasterPort(crossingType: ClockCrossingType): TLOutwardNode = {
val tlMasterResetXing = this { DisableMonitors { implicit p =>
tile.makeMasterBoundaryBuffers(crossingType) :=*
tile { tile.makeMasterBoundaryBuffers(crossingType) } :=*
tile_reset_domain.crossTLOut(tile.masterNode)
} }
val tlMasterClockXing = this.crossOut(tlMasterResetXing)
Expand Down