diff --git a/src/main/scala/interrupts/Nodes.scala b/src/main/scala/interrupts/Nodes.scala index 568395520cc..43d9c49f117 100644 --- a/src/main/scala/interrupts/Nodes.scala +++ b/src/main/scala/interrupts/Nodes.scala @@ -21,7 +21,7 @@ object IntImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParamete trait IntFormatNode extends BaseNode { - override def formatNode() = "Interrupt Node\n" + override def formatNode = "Interrupt Node\n" } case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams) with IntFormatNode diff --git a/src/main/scala/jtag/JtagStateMachine.scala b/src/main/scala/jtag/JtagStateMachine.scala index 443019ff802..ffeae2a6590 100644 --- a/src/main/scala/jtag/JtagStateMachine.scala +++ b/src/main/scala/jtag/JtagStateMachine.scala @@ -70,7 +70,7 @@ object JtagState { class JtagStateMachine(implicit val p: Parameters) extends Module() { class StateMachineIO extends Bundle { val tms = Input(Bool()) - val currState = Output(JtagState.State.chiselType) + val currState = Output(JtagState.State.chiselType()) } val io = IO(new StateMachineIO) diff --git a/src/main/scala/jtag/JtagTap.scala b/src/main/scala/jtag/JtagTap.scala index 519c91a887d..7f647846c3c 100644 --- a/src/main/scala/jtag/JtagTap.scala +++ b/src/main/scala/jtag/JtagTap.scala @@ -72,7 +72,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val // JTAG state machine // - val currState = Wire(JtagState.State.chiselType) + val currState = Wire(JtagState.State.chiselType()) // At this point, the TRSTn should already have been // combined with any POR, and it should also be diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala index f59eabda848..5e7713a3267 100644 --- a/src/main/scala/subsystem/BaseSubsystem.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -31,7 +31,7 @@ abstract class BareSubsystemModuleImp[+L <: BareSubsystem](_outer: L) extends La ElaborationArtefacts.add("graphml", outer.graphML) ElaborationArtefacts.add("dts", outer.dts) ElaborationArtefacts.add("json", outer.json) - ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader) + ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader()) println(outer.dts) } diff --git a/src/main/scala/tilelink/Arbiter.scala b/src/main/scala/tilelink/Arbiter.scala index cda2a5b58af..b6a761f6151 100644 --- a/src/main/scala/tilelink/Arbiter.scala +++ b/src/main/scala/tilelink/Arbiter.scala @@ -91,7 +91,7 @@ object TLArbiter // Who wants access to the sink? val earlyValids = sourcesIn.map(_.earlyValid) - val validQuals = sourcesIn.map(_.validQual) + val validQuals = sourcesIn.map(_.validQual()) // Arbitrate amongst the requests val readys = VecInit(policy(earlyValids.size, Cat(earlyValids.reverse), latch).asBools) // Which request wins arbitration? diff --git a/src/main/scala/tilelink/AtomicAutomata.scala b/src/main/scala/tilelink/AtomicAutomata.scala index 816f59ad033..05aa72e4074 100644 --- a/src/main/scala/tilelink/AtomicAutomata.scala +++ b/src/main/scala/tilelink/AtomicAutomata.scala @@ -46,7 +46,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) - val violations = managersNeedingHelp.flatMap(_.findTreeViolation).map { node => (node.name, node.inputs.map(_._1.name)) } + val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + diff --git a/src/main/scala/tilelink/Buffer.scala b/src/main/scala/tilelink/Buffer.scala index d7f6c9fd04f..c5cc2fa39cf 100644 --- a/src/main/scala/tilelink/Buffer.scala +++ b/src/main/scala/tilelink/Buffer.scala @@ -112,7 +112,7 @@ class TLBufferAndNotCancel( lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - out.a <> a(in.a.asDecoupled) + out.a <> a(in.a.asDecoupled()) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { diff --git a/src/main/scala/unittest/UnitTest.scala b/src/main/scala/unittest/UnitTest.scala index 0e0866bf505..5c722064389 100644 --- a/src/main/scala/unittest/UnitTest.scala +++ b/src/main/scala/unittest/UnitTest.scala @@ -23,7 +23,7 @@ trait UnitTestLegacyModule extends HasUnitTestIO { trait UnitTestModule extends Module with HasUnitTestIO { val io = IO(new Bundle with UnitTestIO) - ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader) + ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader()) } abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule { diff --git a/src/main/scala/util/ReadyValidCancel.scala b/src/main/scala/util/ReadyValidCancel.scala index 231cae0f0a6..bc10c2af344 100644 --- a/src/main/scala/util/ReadyValidCancel.scala +++ b/src/main/scala/util/ReadyValidCancel.scala @@ -157,7 +157,7 @@ class ReadyValidCancelRRArbiter[T <: Data](gen: T, n: Int, rr: Boolean) extends when (io.out.earlyValid) { assert(selectEnc_q < n.U, "arbiter round-robin select out of range") } - when (io.in(selectEnc_q).mightFire && io.in.map(i => i.earlyValid && !i.ready).orR) { + when (io.in(selectEnc_q).mightFire() && io.in.map(i => i.earlyValid && !i.ready).orR) { assert(selectEnc_in =/= selectEnc_q, "arbiter round-robin select did not advance") } } diff --git a/src/main/scala/util/package.scala b/src/main/scala/util/package.scala index 3f36b138715..d1babb70029 100644 --- a/src/main/scala/util/package.scala +++ b/src/main/scala/util/package.scala @@ -68,7 +68,7 @@ package object util { def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n - def unary_~(): Seq[Bool] = x.map(!_) + def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)