From 17098580c07db8af0dbc3036f26b3769d7251c6e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 30 May 2024 12:05:32 -0700 Subject: [PATCH 1/3] Set ClockDomain desiredName by ClockParameters name --- src/main/scala/prci/ClockDomain.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/prci/ClockDomain.scala b/src/main/scala/prci/ClockDomain.scala index 8304d6178af..2eb98c3d8c4 100644 --- a/src/main/scala/prci/ClockDomain.scala +++ b/src/main/scala/prci/ClockDomain.scala @@ -34,6 +34,7 @@ class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Para def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 + override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain @@ -41,6 +42,7 @@ class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 + override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing From c82a93dea2c0ac57b4e225f0fe59410f404b9a85 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 30 May 2024 12:06:00 -0700 Subject: [PATCH 2/3] Add generateSynchronousDomain API to set domain desiredName --- src/main/scala/tilelink/BusWrapper.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/BusWrapper.scala b/src/main/scala/tilelink/BusWrapper.scala index c5793feea57..a6bdb52802a 100644 --- a/src/main/scala/tilelink/BusWrapper.scala +++ b/src/main/scala/tilelink/BusWrapper.scala @@ -85,11 +85,12 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici def unifyManagers: List[TLManagerParameters] = ManagerUnification(busView.manager.managers) def crossOutHelper = this.crossOut(outwardNode)(ValName("bus_xing")) def crossInHelper = this.crossIn(inwardNode)(ValName("bus_xing")) - def generateSynchronousDomain: ClockSinkDomain = { - val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt)) + def generateSynchronousDomain(domainName: String): ClockSinkDomain = { + val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt, name = Some(domainName))) domain.clockNode := fixedClockNode domain } + def generateSynchronousDomain: ClockSinkDomain = generateSynchronousDomain("") protected val addressPrefixNexusNode = BundleBroadcast[UInt](registered = false, default = Some(() => 0.U(1.W))) From 3cec0f0dee432d6bb2da5ce6aa1142474807ff86 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 30 May 2024 12:06:52 -0700 Subject: [PATCH 3/3] Set desiredName for ClockDomains of rom/plic/clint --- src/main/scala/devices/tilelink/BootROM.scala | 2 +- src/main/scala/devices/tilelink/CLINT.scala | 2 +- src/main/scala/devices/tilelink/Plic.scala | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/devices/tilelink/BootROM.scala b/src/main/scala/devices/tilelink/BootROM.scala index a7af5079ffb..4e28e7d6028 100644 --- a/src/main/scala/devices/tilelink/BootROM.scala +++ b/src/main/scala/devices/tilelink/BootROM.scala @@ -72,7 +72,7 @@ object BootROM { def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation) (implicit p: Parameters): TLROM = { val tlbus = subsystem.locateTLBusWrapper(where) - val bootROMDomainWrapper = tlbus.generateSynchronousDomain.suggestName("bootrom_domain") + val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain") val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]() lazy val contents = { diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala index 25263adc0c9..6fc438c4c54 100644 --- a/src/main/scala/devices/tilelink/CLINT.scala +++ b/src/main/scala/devices/tilelink/CLINT.scala @@ -107,7 +107,7 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) - val clintDomainWrapper = tlbus.generateSynchronousDomain.suggestName("clint_domain") + val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ } } val clintTick = clintDomainWrapper { InModuleBody { diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index 3b175df22d6..126cfe9e89c 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -361,7 +361,7 @@ class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) - val plicDomainWrapper = tlbus.generateSynchronousDomain.suggestName("plic_domain") + val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus) := _ } }