diff --git a/build.sbt b/build.sbt
index 4d04cbc6cf8..c95dcd10a0f 100644
--- a/build.sbt
+++ b/build.sbt
@@ -5,7 +5,7 @@ import scala.sys.process._
 
 enablePlugins(PackPlugin)
 
-val chiselVersion = "3.5.6"
+val chiselVersion = "3.6.0"
 
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
@@ -15,7 +15,7 @@ lazy val commonSettings = Seq(
   traceLevel   := 15,
   scalacOptions ++= Seq("-deprecation","-unchecked"),
   libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value),
-  libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.6.6"),
+  libraryDependencies ++= Seq("org.json4s" %% "json4s-native" % "4.0.6"),
   libraryDependencies ++= Seq("org.scalatest" %% "scalatest" % "3.2.0" % "test"),
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
diff --git a/build.sc b/build.sc
index 32429ba8240..790f028377e 100644
--- a/build.sc
+++ b/build.sc
@@ -33,6 +33,15 @@ object hardfloatRocket extends hardfloat.build.hardfloat {
   def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
     common.getVersion("chisel3")
   ) else Agg.empty[Dep]
+
+  def chisel3PluginIvyDeps = if(chisel3Module.isEmpty) Agg(
+    common.getVersion("chisel3-plugin", cross = true)
+  ) else Agg.empty[Dep]
+
+  override def repositories = super.repositories ++ Seq(
+    MavenRepository("https://oss.sonatype.org/content/repositories/snapshots"),
+    MavenRepository("https://oss.sonatype.org/content/repositories/releases")
+  )
 }
 
 object rocketchip extends common.CommonRocketChip {
@@ -78,47 +87,65 @@ object emulator extends mill.Cross[Emulator](
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.MemPortOnlyConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.MMIOPortOnlyConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.CloneTileConfig"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.HypervisorConfig"),
 )
-class Emulator(top: String, config: String) extends ScalaModule {
-  override def moduleDeps = Seq(rocketchip)
-
-  override def scalaVersion: T[String] = T {
-    "2.13.10"
-  }
-
-  def spikeRoot = T { envByNameOrRiscv("SPIKE_ROOT") }
-
-  def generator = T {
-    // class path for `moduleDeps` is only a directory, not a jar, which breaks the cache.
-    // so we need to manually add the class files of `moduleDeps` here.
-    upstreamCompileOutput()
-    mill.modules.Jvm.runLocal(
-      "freechips.rocketchip.system.Generator",
-      runClasspath().map(_.path),
-      Seq(
+class Emulator(top: String, config: String) extends Module {
+
+  object generator extends Module {
+    def elaborate = T {
+      os.proc(
+        mill.modules.Jvm.javaExe,
+        "-jar",
+        rocketchip.assembly().path,
+        "freechips.rocketchip.system.Generator",
         "-td", T.dest.toString,
         "-T", top,
         "-C", config,
-      ),
-    )
-    PathRef(T.dest)
+      ).call()
+      PathRef(T.dest)
+    }
+
+    def chiselAnno = T {
+      os.walk(elaborate().path).collectFirst { case p if p.last.endsWith("anno.json") => p }.map(PathRef(_)).get
+    }
+
+    def chirrtl = T {
+      os.walk(elaborate().path).collectFirst { case p if p.last.endsWith("fir") => p }.map(PathRef(_)).get
+    }
   }
 
-  def firrtl = T {
-    val input = generator().path / (config + ".fir")
-    val output = T.dest / (top + "-" + config + ".v")
-    mill.modules.Jvm.runLocal(
-      "firrtl.stage.FirrtlMain",
-      runClasspath().map(_.path),
-      Seq(
-        "-i", input.toString,
-        "-o", output.toString,
-      ),
-    )
-    PathRef(output)
+  object mfccompiler extends Module {
+    def compile = T {
+      os.proc("firtool",
+        generator.chirrtl().path,
+        s"--annotation-file=${generator.chiselAnno().path}",
+        "-disable-infer-rw",
+        "--disable-annotation-unknown",
+        "-dedup",
+        "-O=debug",
+        "--split-verilog",
+        "--preserve-values=named",
+        "--output-annotation-file=mfc.anno.json",
+        s"-o=${T.dest}"
+      ).call(T.dest)
+      PathRef(T.dest)
+    }
+
+    def rtls = T {
+      os.read(compile().path / "filelist.f").split("\n").map(str =>
+        try {
+          os.Path(str)
+        } catch {
+          case e: IllegalArgumentException if e.getMessage.contains("is not an absolute path") =>
+            compile().path / str.stripPrefix("./")
+        }
+      ).filter(p => p.ext == "v" || p.ext == "sv").map(PathRef(_)).toSeq
+    }
   }
 
   object verilator extends Module {
+    def spikeRoot = T { envByNameOrRiscv("SPIKE_ROOT") }
+
     def csrcDir = T {
       PathRef(os.pwd / "src" / "main" / "resources" / "csrc")
     }
@@ -142,7 +169,7 @@ class Emulator(top: String, config: String) extends ScalaModule {
          |project(emulator)
          |include_directories(${csrcDir().path})
          |# plusarg is here
-         |include_directories(${generator().path})
+         |include_directories(${generator.elaborate().path})
          |link_directories(${spikeRoot() + "/lib"})
          |include_directories(${spikeRoot() + "/include"})
          |
@@ -151,7 +178,7 @@ class Emulator(top: String, config: String) extends ScalaModule {
          |set(CMAKE_C_COMPILER "clang")
          |set(CMAKE_CXX_COMPILER "clang++")
          |set(CMAKE_CXX_FLAGS
-         |"$${CMAKE_CXX_FLAGS} -DVERILATOR -DTEST_HARNESS=VTestHarness -include VTestHarness.h -include verilator.h -include ${generator().path / config + ".plusArgs"}")
+         |"$${CMAKE_CXX_FLAGS} -DVERILATOR -DTEST_HARNESS=VTestHarness -include VTestHarness.h -include verilator.h -include ${generator.elaborate().path / config + ".plusArgs"}")
          |set(THREADS_PREFER_PTHREAD_FLAG ON)
          |
          |find_package(verilator)
@@ -165,7 +192,7 @@ class Emulator(top: String, config: String) extends ScalaModule {
          |target_link_libraries(emulator PRIVATE fesvr)
          |verilate(emulator
          |  SOURCES
-         |${firrtl().path}
+         |  ${mfccompiler.rtls().map(_.path.toString).mkString("\n")}
          |  TOP_MODULE TestHarness
          |  PREFIX VTestHarness
          |  VERILATOR_ARGS ${verilatorArgs().mkString(" ")}
diff --git a/common.sc b/common.sc
index 82572914f28..e5ed6eaed9d 100644
--- a/common.sc
+++ b/common.sc
@@ -4,8 +4,8 @@ import mill.scalalib.publish._
 import coursier.maven.MavenRepository
 
 val defaultVersions = Map(
-  "chisel3" -> "3.5.6",
-  "chisel3-plugin" -> "3.5.6"
+  "chisel3" -> "3.6.0",
+  "chisel3-plugin" -> "3.6.0"
 )
 
 def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = false) = {
@@ -45,6 +45,11 @@ trait CommonRocketChip extends SbtModule with PublishModule {
     override def publishVersion = T {
       m.publishVersion()
     }
+
+    override def repositories = super.repositories ++ Seq(
+      MavenRepository("https://oss.sonatype.org/content/repositories/snapshots"),
+      MavenRepository("https://oss.sonatype.org/content/repositories/releases")
+    )
   }
 
   object test extends Tests {
@@ -84,7 +89,7 @@ trait CommonRocketChip extends SbtModule with PublishModule {
   override def ivyDeps = T {
     Agg(
       ivy"${scalaOrganization()}:scala-reflect:${scalaVersion()}",
-      ivy"org.json4s::json4s-jackson:3.6.6",
+      ivy"org.json4s::json4s-jackson:4.0.5",
       ivy"org.scalatest::scalatest:3.2.0"
     ) ++ chisel3IvyDeps
   }
diff --git a/flake.lock b/flake.lock
index 248cf0b6525..b0128cb6f91 100644
--- a/flake.lock
+++ b/flake.lock
@@ -2,11 +2,11 @@
   "nodes": {
     "flake-utils": {
       "locked": {
-        "lastModified": 1667395993,
-        "narHash": "sha256-nuEHfE/LcWyuSWnS8t12N1wc105Qtau+/OdUAjtQ0rA=",
+        "lastModified": 1676283394,
+        "narHash": "sha256-XX2f9c3iySLCw54rJ/CZs+ZK6IQy7GXNY4nSOyu2QG4=",
         "owner": "numtide",
         "repo": "flake-utils",
-        "rev": "5aed5285a952e0b949eb3ba02c12fa4fcfef535f",
+        "rev": "3db36a8b464d0c4532ba1c7dda728f4576d6d073",
         "type": "github"
       },
       "original": {
@@ -17,11 +17,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1671359686,
-        "narHash": "sha256-3MpC6yZo+Xn9cPordGz2/ii6IJpP2n8LE8e/ebUXLrs=",
+        "lastModified": 1676300157,
+        "narHash": "sha256-1HjRzfp6LOLfcj/HJHdVKWAkX9QRAouoh6AjzJiIerU=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "04f574a1c0fde90b51bf68198e2297ca4e7cccf4",
+        "rev": "545c7a31e5dedea4a6d372712a18e00ce097d462",
         "type": "github"
       },
       "original": {
diff --git a/flake.nix b/flake.nix
index a5ccb06a2b4..4d1bd74f526 100644
--- a/flake.nix
+++ b/flake.nix
@@ -22,6 +22,7 @@
           verilator cmake ninja
           python3 python3Packages.bootstrapped-pip
           pkgsCross.riscv64-embedded.buildPackages.gcc
+          circt
 
           spike riscvTests
         ];
diff --git a/hardfloat b/hardfloat
index 72709416c4c..9deaf1d49f4 160000
--- a/hardfloat
+++ b/hardfloat
@@ -1 +1 @@
-Subproject commit 72709416c4cf8847aa8feeb58aec5ea875267e67
+Subproject commit 9deaf1d49f487347be371641ba6ea637b669ad21
diff --git a/src/main/scala/amba/axis/Bundles.scala b/src/main/scala/amba/axis/Bundles.scala
index 80d6e1776f8..be107726cab 100644
--- a/src/main/scala/amba/axis/Bundles.scala
+++ b/src/main/scala/amba/axis/Bundles.scala
@@ -24,7 +24,6 @@ case class AXISDataField(width: Int) extends BundleField(AXISData) {
 }
 
 class AXISBundleBits(val params: AXISBundleParameters) extends BundleMap(AXISBundle.keys(params)) {
-  override def cloneType: this.type = (new AXISBundleBits(params)).asInstanceOf[this.type]
   def last = if (params.hasLast) apply(AXISLast) else true.B
   def id   = if (params.hasId)   apply(AXISId)   else 0.U
   def dest = if (params.hasDest) apply(AXISDest) else 0.U
diff --git a/src/main/scala/diplomacy/CloneModule.scala b/src/main/scala/diplomacy/CloneModule.scala
index 5750eb83ecf..07f7269b522 100644
--- a/src/main/scala/diplomacy/CloneModule.scala
+++ b/src/main/scala/diplomacy/CloneModule.scala
@@ -17,5 +17,4 @@ class ClonePorts protected[shim](elts: Data*) extends Record
 {
   val elements = ListMap(elts.map(d => d.instanceName -> d.chiselCloneType): _*)
   def apply(field: String) = elements(field)
-  override def cloneType = (new ClonePorts(elts: _*)).asInstanceOf[this.type]
 }
diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala
index 69ad5cbfdc1..5849657f5d7 100644
--- a/src/main/scala/diplomacy/LazyModule.scala
+++ b/src/main/scala/diplomacy/LazyModule.scala
@@ -562,8 +562,6 @@ final class AutoBundle(elts: (String, Data, Boolean)*) extends Record {
     val element = if (flip) data.cloneType.flip() else data.cloneType
     (regex.replaceAllIn(key, ""), element, i)
   }
-
-  override def cloneType: this.type = new AutoBundle(elts: _*).asInstanceOf[this.type]
 }
 
 trait ModuleValue[T] {
diff --git a/src/main/scala/diplomacy/package.scala b/src/main/scala/diplomacy/package.scala
index b3ff60d6953..7afe1eb54a8 100644
--- a/src/main/scala/diplomacy/package.scala
+++ b/src/main/scala/diplomacy/package.scala
@@ -2,7 +2,7 @@
 
 package freechips.rocketchip
 
-import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
+import chisel3.experimental.{SourceInfo, SourceLine}
 import chisel3.Data
 import org.chipsalliance.cde.config.Parameters
 import scala.language.implicitConversions
diff --git a/src/main/scala/formal/FormalUtils.scala b/src/main/scala/formal/FormalUtils.scala
index 2f8f797fe1d..e4d8ee8eb2c 100644
--- a/src/main/scala/formal/FormalUtils.scala
+++ b/src/main/scala/formal/FormalUtils.scala
@@ -3,8 +3,8 @@ package freechips.rocketchip.formal
 
 import chisel3._
 import chisel3.util._
-import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
 import org.chipsalliance.cde.config.Field
+import chisel3.experimental.{SourceInfo, SourceLine}
 
 sealed abstract class MonitorDirection(name: String) {
   override def toString: String = name
diff --git a/src/main/scala/tilelink/Bundle_ACancel.scala b/src/main/scala/tilelink/Bundle_ACancel.scala
index 10576f1589a..342b7ac0eab 100644
--- a/src/main/scala/tilelink/Bundle_ACancel.scala
+++ b/src/main/scala/tilelink/Bundle_ACancel.scala
@@ -16,7 +16,6 @@ class TLBundle_ACancel(val params: TLBundleParameters) extends Record
   val d = Flipped(Decoupled(new TLBundleD(params)))
   val e =         Decoupled(new TLBundleE(params))
 
-  override def cloneType: this.type = (new TLBundle_ACancel(params)).asInstanceOf[this.type]
   val elements = ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
 
   /** Down-converts a TLBundle_ACancel to a plain TLBundle, dropping early/late timing split. */
diff --git a/src/main/scala/tilelink/Bundles.scala b/src/main/scala/tilelink/Bundles.scala
index cba6218df83..d5fbaabf400 100644
--- a/src/main/scala/tilelink/Bundles.scala
+++ b/src/main/scala/tilelink/Bundles.scala
@@ -261,7 +261,6 @@ class TLBundle(val params: TLBundleParameters) extends Record
   def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
   def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
 
-  override def cloneType: this.type = (new TLBundle(params)).asInstanceOf[this.type]
   val elements =
     if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
     else ListMap("d" -> d, "a" -> a)
diff --git a/src/main/scala/tilelink/Monitor.scala b/src/main/scala/tilelink/Monitor.scala
index 0845260d633..a941d00b7a4 100644
--- a/src/main/scala/tilelink/Monitor.scala
+++ b/src/main/scala/tilelink/Monitor.scala
@@ -4,8 +4,8 @@ package freechips.rocketchip.tilelink
 
 import chisel3._
 import chisel3.util._
-import chisel3.internal.sourceinfo.SourceLine
 import org.chipsalliance.cde.config.Parameters
+import chisel3.experimental.SourceLine
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.PlusArg
 import freechips.rocketchip.formal._
diff --git a/src/main/scala/util/Annotations.scala b/src/main/scala/util/Annotations.scala
index c64d3f8891f..e85bdf59a37 100644
--- a/src/main/scala/util/Annotations.scala
+++ b/src/main/scala/util/Annotations.scala
@@ -12,7 +12,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 
 import org.json4s.JsonDSL._
-import org.json4s.jackson.JsonMethods.{pretty, render}
+import org.json4s.native.JsonMethods.{pretty, render}
 
 /** Record a sram. */
 case class SRAMAnnotation(target: Named,
diff --git a/src/main/scala/util/BundleMap.scala b/src/main/scala/util/BundleMap.scala
index 1439abfcad3..5cae5fbf027 100644
--- a/src/main/scala/util/BundleMap.scala
+++ b/src/main/scala/util/BundleMap.scala
@@ -100,23 +100,11 @@ abstract class DataKey   [T <: Data](name: String) extends BundleKey[T](name) wi
  * Generally, this categorization belongs in different BundleMaps
  */
 
-// If you extend this class, you must either redefine cloneType or have a fields constructor
 class BundleMap(val fields: Seq[BundleFieldBase]) extends Record with CustomBulkAssignable {
   // All fields must have distinct key.names
   require(fields.map(_.key.name).distinct.size == fields.size)
 
   val elements: ListMap[String, Data] = ListMap(fields.map { bf => bf.key.name -> chisel3.experimental.DataMirror.internal.chiselTypeClone(bf.data) } :_*)
-  override def cloneType: this.type = {
-    try {
-      this.getClass.getConstructors.head.newInstance(fields).asInstanceOf[this.type]
-    } catch {
-      case e: java.lang.IllegalArgumentException =>
-        throw new Exception("Unable to use BundleMap.cloneType on " +
-                       this.getClass + ", probably because " + this.getClass +
-                       " does not have a constructor accepting BundleFields.  Consider overriding " +
-                       "cloneType() on " + this.getClass, e)
-    }
-  }
 
   // A BundleMap is best viewed as a map from BundleKey to Data
   def keydata: Seq[(BundleKeyBase, Data)] = (fields zip elements) map { case (field, (_, data)) => (field.key, data) }
diff --git a/src/main/scala/util/HeterogeneousBag.scala b/src/main/scala/util/HeterogeneousBag.scala
index 8970dc9ebbc..d56b644f99f 100644
--- a/src/main/scala/util/HeterogeneousBag.scala
+++ b/src/main/scala/util/HeterogeneousBag.scala
@@ -2,17 +2,20 @@
 
 package freechips.rocketchip.util
 
-import Chisel._
-import chisel3.Record
-import scala.collection.immutable.ListMap
+import chisel3._
+import chisel3.experimental.DataMirror
+import scala.collection.immutable.VectorMap
 
 final case class HeterogeneousBag[T <: Data](elts: Seq[T]) extends Record with collection.IndexedSeq[T] {
-  def apply(x: Int) = elts(x)
+  val elements = VectorMap(elts.zipWithIndex.map { case (n,i) => (i.toString, DataMirror.internal.chiselTypeClone(n)) }:_*)
+
+  def apply(x: Int): T = {
+    val key = elements.keys(x) // VectorMap.keys returns a Vector
+    elements(key)
+  }
   def length = elts.length
 
   override def className: String = super.className
-  val elements = ListMap(elts.zipWithIndex.map { case (n,i) => (i.toString, n) }:_*)
-  override def cloneType: this.type = (new HeterogeneousBag(elts.map(_.chiselCloneType))).asInstanceOf[this.type]
   // IndexedSeq has its own hashCode/equals that we must not use
   override def hashCode: Int = super[Record].hashCode
   override def equals(that: Any): Boolean = super[Record].equals(that)
diff --git a/src/main/scala/util/RecordMap.scala b/src/main/scala/util/RecordMap.scala
index 648713c6cbf..4dd6bc11ae9 100644
--- a/src/main/scala/util/RecordMap.scala
+++ b/src/main/scala/util/RecordMap.scala
@@ -20,8 +20,6 @@ final class RecordMap[T <: Data] (eltMap: ListMap[String, T])
   def size = elements.size
   def data = elements.values
 
-  override def cloneType: this.type = (new RecordMap(eltMap)).asInstanceOf[this.type]
-
 }
 
 object RecordMap {