diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index 4a4b37d2bcd..cf7a283e732 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -36,19 +36,18 @@ class GroundTestBaseConfig extends Config( class WithTraceGen( n: Int = 2, - overrideIdOffset: Option[Int] = None, overrideMemOffset: Option[BigInt] = None)( params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, nReqs: Int = 8192 ) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) params.zipWithIndex.map { case (dcp, i) => TraceGenTileAttachParams( tileParams = TraceGenParams( - hartId = i + idOffset, + tileId = i + idOffset, dcache = Some(dcp), wordBits = site(XLen), addrBits = 32, @@ -68,4 +67,5 @@ class WithTraceGen( ) } ++ prev } + case NumTiles => up(NumTiles) + n }) diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index 1b4457f50b7..4abed974664 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -68,14 +68,14 @@ case class TraceGenParams( memStart: BigInt, //p(ExtMem).base numGens: Int, dcache: Option[DCacheParams] = Some(DCacheParams()), - hartId: Int = 0 + tileId: Int = 0 ) extends InstantiableTileParams[TraceGenTile] with GroundTestTileParams { def instantiate(crossing: ElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): TraceGenTile = { new TraceGenTile(this, crossing, lookup) } val blockerCtrlAddr = None - val name = s"tracegen_$hartId" + val name = s"tracegen_$tileId" val clockSinkParams = ClockSinkParameters() } @@ -643,5 +643,5 @@ class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp status.timeout.bits := 0.U status.error.valid := false.B - assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.hartId}: request timed out") + assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.tileId}: request timed out") } diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index f6c0ad52b68..30297c5033c 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -61,9 +61,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val progress = Output(Bool()) } -class Frontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule { +class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) - val icache = LazyModule(new ICache(icacheParams, staticIdForMetadataUseOnly)) + val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) @@ -383,7 +383,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule - val frontend = LazyModule(new Frontend(tileParams.icache.get, staticIdForMetadataUseOnly)) + val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 7360ab89fc0..41c8bdfdfe8 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -188,17 +188,17 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { /** Base classes for Diplomatic TL2 HellaCaches */ -abstract class HellaCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule +abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( - name = s"Core ${staticIdForMetadataUseOnly} DCache", + name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( - name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO", + name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) @@ -254,9 +254,9 @@ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache]( object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) - new DCache(tile.staticIdForMetadataUseOnly, tile.crossing)(p) + new DCache(tile.tileId, tile.crossing)(p) else - new NonBlockingDCache(tile.staticIdForMetadataUseOnly)(p) + new NonBlockingDCache(tile.tileId)(p) } } diff --git a/src/main/scala/subsystem/Cluster.scala b/src/main/scala/subsystem/Cluster.scala index a5c8163dc63..fda1ef3843c 100644 --- a/src/main/scala/subsystem/Cluster.scala +++ b/src/main/scala/subsystem/Cluster.scala @@ -39,12 +39,6 @@ class Cluster( lazy val location = InCluster(clusterId) val clockGroupNode = ClockGroupAggregator() - println(p(TLNetworkTopologyLocated(InCluster(0)))) - println(p(TLNetworkTopologyLocated(InCluster(1)))) - println(thisClusterParams) - println(clusterId) - println(location) - println(tlBusWrapperLocationMap) val csbus = tlBusWrapperLocationMap(CSBUS(clusterId)) // like the sbus in the base subsystem val ccbus = tlBusWrapperLocationMap(CCBUS(clusterId)) // like the cbus in the base subsystem @@ -60,16 +54,16 @@ class Cluster( ibus.clockNode := csbus.fixedClockNode implicit val asyncClockGroupsNode = p(AsyncClockGroupsKey)() - lazy val msipNodes = totalHartIdList.map { i => (i, IntIdentityNode()) }.toMap - lazy val meipNodes = totalHartIdList.map { i => (i, IntIdentityNode()) }.toMap - lazy val seipNodes = totalHartIdList.map { i => (i, IntIdentityNode()) }.toMap - lazy val tileToPlicNodes = totalHartIdList.map { i => (i, IntIdentityNode()) }.toMap - lazy val debugNodes = totalHartIdList.map { i => (i, IntSyncIdentityNode()) }.toMap - lazy val nmiNodes = totalTiles.filter(_.tileParams.core.useNMI).map { t => (t.hartId, BundleBridgeIdentityNode[NMI]()) }.toMap - lazy val tileHartIdNodes = totalHartIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.toMap - lazy val tileResetVectorNodes = totalHartIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.toMap - lazy val traceCoreNodes = totalHartIdList.map { i => (i, BundleBridgeIdentityNode[TraceCoreInterface]()) }.toMap - lazy val traceNodes = totalHartIdList.map { i => (i, BundleBridgeIdentityNode[TraceBundle]()) }.toMap + lazy val msipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.toMap + lazy val meipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.toMap + lazy val seipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.toMap + lazy val tileToPlicNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.toMap + lazy val debugNodes = totalTileIdList.map { i => (i, IntSyncIdentityNode()) }.toMap + lazy val nmiNodes = totalTiles.filter(_.tileParams.core.useNMI).map { t => (t.tileId, BundleBridgeIdentityNode[NMI]()) }.toMap + lazy val tileHartIdNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.toMap + lazy val tileResetVectorNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.toMap + lazy val traceCoreNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[TraceCoreInterface]()) }.toMap + lazy val traceNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[TraceBundle]()) }.toMap // TODO fix: shouldn't need to connect dummy notifications tileHaltXbarNode := NullIntSource() diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala index b70fc4cb64b..7804551f192 100644 --- a/src/main/scala/subsystem/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -17,7 +17,7 @@ class BaseSubsystemConfig extends Config ((site, here, up) => { case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */ case XLen => 64 // Applies to all cores case MaxHartIdBits => log2Up((site(PossibleTileLocations).flatMap(loc => site(TilesLocated(loc))) - .map(_.tileParams.hartId) :+ 0).max+1) + .map(_.tileParams.tileId) :+ 0).max+1) // Interconnect parameters case SystemBusKey => SystemBusParams( beatBytes = site(XLen)/8, @@ -91,13 +91,12 @@ class WithCoherentBusTopology extends Config((site, here, up) => { class WithNBigCores( n: Int, - overrideIdOffset: Option[Int] = None, crossing: RocketCrossingParams = RocketCrossingParams(), location: HierarchicalLocation = InSubsystem ) extends Config((site, here, up) => { case TilesLocated(`location`) => { val prev = up(TilesLocated(location), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val big = RocketTileParams( core = RocketCoreParams(mulDiv = Some(MulDivParams( mulUnroll = 8, @@ -111,20 +110,21 @@ class WithNBigCores( rowBits = site(SystemBusKey).beatBits, blockBytes = site(CacheBlockBytes)))) List.tabulate(n)(i => RocketTileAttachParams( - big.copy(hartId = i + idOffset), + big.copy(tileId = i + idOffset), crossing )) ++ prev } + case NumTiles => up(NumTiles) + n }) class WithNMedCores( n: Int, - overrideIdOffset: Option[Int] = None, - crossing: RocketCrossingParams = RocketCrossingParams() + crossing: RocketCrossingParams = RocketCrossingParams(), + location: HierarchicalLocation = InSubsystem ) extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => { - val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + case TilesLocated(`location`) => { + val prev = up(TilesLocated(location), site) + val idOffset = up(NumTiles) val med = RocketTileParams( core = RocketCoreParams(fpu = None), btb = None, @@ -144,20 +144,21 @@ class WithNMedCores( nTLBWays = 4, blockBytes = site(CacheBlockBytes)))) List.tabulate(n)(i => RocketTileAttachParams( - med.copy(hartId = i + idOffset), + med.copy(tileId = i + idOffset), crossing )) ++ prev } + case NumTiles => up(NumTiles) + n }) class WithNSmallCores( n: Int, - overrideIdOffset: Option[Int] = None, - crossing: RocketCrossingParams = RocketCrossingParams() + crossing: RocketCrossingParams = RocketCrossingParams(), + location: HierarchicalLocation = InSubsystem ) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val small = RocketTileParams( core = RocketCoreParams(useVM = false, fpu = None), btb = None, @@ -177,10 +178,11 @@ class WithNSmallCores( nTLBWays = 4, blockBytes = site(CacheBlockBytes)))) List.tabulate(n)(i => RocketTileAttachParams( - small.copy(hartId = i + idOffset), + small.copy(tileId = i + idOffset), crossing )) ++ prev } + case NumTiles => up(NumTiles) + n }) class With1TinyCore extends Config((site, here, up) => { @@ -216,6 +218,8 @@ class With1TinyCore extends Config((site, here, up) => { master = ElementMasterPortParams()) )) } + case NumTiles => 1 + case ClustersLocated(_) => Nil }) class WithCluster( @@ -679,7 +683,7 @@ class WithCloneRocketTiles(n: Int = 1, cloneHart: Int = 0, overrideIdOffset: Opt val tileAttachParams = prev(cloneHart).asInstanceOf[RocketTileAttachParams] (0 until n).map { i => CloneTileAttachParams(cloneHart, tileAttachParams.copy( - tileParams = tileAttachParams.tileParams.copy(hartId = i + idOffset) + tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset) )) } ++ prev } diff --git a/src/main/scala/subsystem/HasElements.scala b/src/main/scala/subsystem/HasElements.scala index fb25ba5733c..24525555014 100644 --- a/src/main/scala/subsystem/HasElements.scala +++ b/src/main/scala/subsystem/HasElements.scala @@ -61,7 +61,7 @@ trait InstantiatesElements { this: LazyModule with Attachable => * Note that these ids, which are often used as the tiles' default hartid input, * may or may not be those actually reflected at runtime in e.g. the $mhartid CSR */ - val tileAttachParams: Seq[CanAttachTile] = p(TilesLocated(location)).sortBy(_.tileParams.hartId) + val tileAttachParams: Seq[CanAttachTile] = p(TilesLocated(location)).sortBy(_.tileParams.tileId) val tileParams: Seq[TileParams] = tileAttachParams.map(_.tileParams) val tileCrossingTypes: Seq[ClockCrossingType] = tileAttachParams.map(_.crossingParams.crossingType) @@ -79,17 +79,17 @@ trait InstantiatesElements { this: LazyModule with Attachable => val element_prci_domains: Seq[ElementPRCIDomain[_]] = tile_prci_domains ++ cluster_prci_domains - val leafTiles: Seq[BaseTile] = tile_prci_domains.map(_.element.asInstanceOf[BaseTile]).sortBy(_.hartId) - val totalTiles: Seq[BaseTile] = (leafTiles ++ cluster_prci_domains.map(_.element.asInstanceOf[Cluster].totalTiles).flatten).sortBy(_.hartId) + val leafTiles: Seq[BaseTile] = tile_prci_domains.map(_.element.asInstanceOf[BaseTile]).sortBy(_.tileId) + val totalTiles: Seq[BaseTile] = (leafTiles ++ cluster_prci_domains.map(_.element.asInstanceOf[Cluster].totalTiles).flatten).sortBy(_.tileId) // Helper functions for accessing certain parameters that are popular to refer to in subsystem code def nLeafTiles: Int = leafTiles.size def nTotalTiles: Int = totalTiles.size - def leafHartIdList: Seq[Int] = leafTiles.map(_.hartId) - def totalHartIdList: Seq[Int] = totalTiles.map(_.hartId) + def leafTileIdList: Seq[Int] = leafTiles.map(_.tileId) + def totalTileIdList: Seq[Int] = totalTiles.map(_.tileId) def localIntCounts: Seq[Int] = totalTiles.map(_.tileParams.core.nLocalInterrupts) - require(totalHartIdList.distinct.size == totalTiles.size, s"Every tile must be statically assigned a unique id, but got:\n${totalHartIdList}") + require(totalTileIdList.distinct.size == totalTiles.size, s"Every tile must be statically assigned a unique id, but got:\n${totalTileIdList}") } /** HasTiles instantiates and also connects a Config-urable sequence of tiles of any type to subsystem interconnect resources. */ @@ -201,7 +201,7 @@ trait HasElementsRootContext node := debugOpt.map(_.intnode).getOrElse(IntSyncCrossingSource() := NullIntSource()) } - val nmiHarts = totalTiles.filter(_.tileParams.core.useNMI).map(_.hartId) + val nmiHarts = totalTiles.filter(_.tileParams.core.useNMI).map(_.tileId) val nmiIONodes = nmiHarts.map { i => (i, BundleBridgeSource[NMI]()) }.toMap val nmiNodes: Map[Int, BundleBridgeNode[NMI]] = nmiIONodes.map { case (i, n) => (i, BundleBridgeEphemeralNode[NMI]() := n) diff --git a/src/main/scala/subsystem/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala index f9fe6f98605..39392b303ab 100644 --- a/src/main/scala/subsystem/HasTiles.scala +++ b/src/main/scala/subsystem/HasTiles.scala @@ -21,6 +21,9 @@ case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTi /** List of HierarchicalLocations which might contain a Tile */ case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) +/** For determining static tile id */ +case object NumTiles extends Field[Int](0) + /** Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * @@ -68,7 +71,7 @@ trait HasTileInputConstants { this: LazyModule with Attachable with Instantiates val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => - val y = dontTouch(prefix | totalHartIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup + val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), @@ -199,23 +202,23 @@ trait CanAttachTile { // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := - context.debugNodes(domain.element.hartId) + context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the TileLink bus clock, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := - context.msipNodes(domain.element.hartId) + context.msipNodes(domain.element.tileId) // From PLIC: "meip" domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := - context.meipNodes(domain.element.hartId) + context.meipNodes(domain.element.tileId) // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := - context.seipNodes(domain.element.hartId) + context.seipNodes(domain.element.tileId) } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. @@ -223,14 +226,14 @@ trait CanAttachTile { // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. - context.tileToPlicNodes.get(domain.element.hartId).foreach { node => + context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => node :*= domain.crossIntOut(crossingParams.crossingType, out) }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. - domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.hartId)) + domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */ @@ -247,8 +250,8 @@ trait CanAttachTile { def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) - domain.element.hartIdNode := context.tileHartIdNodes(domain.element.hartId) - domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.hartId) + domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) + domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } @@ -281,10 +284,10 @@ trait CanAttachTile { implicit val p = context.p val traceNexusNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) - context.traceNodes(domain.element.hartId) := traceNexusNode := domain.element.traceNode + context.traceNodes(domain.element.tileId) := traceNexusNode := domain.element.traceNode val traceCoreNexusNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) - context.traceCoreNodes(domain.element.hartId) :*= traceCoreNexusNode := domain.element.traceCoreNode + context.traceCoreNodes(domain.element.tileId) :*= traceCoreNexusNode := domain.element.traceCoreNode } } diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala index 36aea77bea6..4202fe62c06 100644 --- a/src/main/scala/system/Configs.scala +++ b/src/main/scala/system/Configs.scala @@ -38,7 +38,7 @@ class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new Default class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new DefaultConfig) class ClusterConfig extends Config( - new WithNBigCores(2, location=InCluster(0), overrideIdOffset=Some(1), crossing=RocketCrossingParams( + new WithNBigCores(2, location=InCluster(0), crossing=RocketCrossingParams( master=ElementMasterPortParams(where=CSBUS(0)), slave=ElementSlavePortParams(blockerCtrlWhere=CCBUS(0), where=CCBUS(0)), mmioBaseAddressPrefixWhere=CCBUS(0), diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 8a2795b7e63..3801d3a410f 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -23,7 +23,7 @@ trait TileParams extends ElementParams { val icache: Option[ICacheParams] val dcache: Option[DCacheParams] val btb: Option[BTBParams] - val hartId: Int + val tileId: Int // may not be hartid val blockerCtrlAddr: Option[BigInt] } @@ -76,15 +76,7 @@ trait HasNonDiplomaticTileParameters { xLen match { case 32 => 34; case 64 => 56 } } - /** Use staticIdForMetadataUseOnly to emit information during the build or identify a component to diplomacy. - * - * Including it in a constructed Chisel circuit by converting it to a UInt will prevent - * Chisel/FIRRTL from being able to deduplicate tiles that are otherwise homogeneous, - * a property which is important for hierarchical place & route flows. - */ - def staticIdForMetadataUseOnly: Int = tileParams.hartId - @deprecated("use hartIdSinkNodeOpt.map(_.bundle) or staticIdForMetadataUseOnly", "rocket-chip 1.3") - def hartId: Int = staticIdForMetadataUseOnly + def tileId: Int = tileParams.tileId def cacheBlockBytes = p(CacheBlockBytes) def lgCacheBlockBytes = log2Up(cacheBlockBytes) diff --git a/src/main/scala/tile/LookupByHartId.scala b/src/main/scala/tile/LookupByHartId.scala index 263dd43c66f..631bb8f651e 100644 --- a/src/main/scala/tile/LookupByHartId.scala +++ b/src/main/scala/tile/LookupByHartId.scala @@ -10,10 +10,10 @@ abstract class LookupByHartIdImpl { } case class HartsWontDeduplicate(t: TileParams) extends LookupByHartIdImpl { - def apply[T <: Data](f: TileParams => Option[T], hartId: UInt): T = f(t).get + def apply[T <: Data](f: TileParams => Option[T], tileId: UInt): T = f(t).get } case class PriorityMuxHartIdFromSeq(seq: Seq[TileParams]) extends LookupByHartIdImpl { - def apply[T <: Data](f: TileParams => Option[T], hartId: UInt): T = - PriorityMux(seq.collect { case t if f(t).isDefined => (t.hartId.U === hartId) -> f(t).get }) + def apply[T <: Data](f: TileParams => Option[T], tileId: UInt): T = + PriorityMux(seq.collect { case t if f(t).isDefined => (t.tileId.U === tileId) -> f(t).get }) } diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index bcfef753f15..d0bcd0234f7 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -22,7 +22,7 @@ case class RocketTileParams( dcache: Option[DCacheParams] = Some(DCacheParams()), btb: Option[BTBParams] = Some(BTBParams()), dataScratchpadBytes: Int = 0, - hartId: Int = 0, + tileId: Int = 0, beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, clockSinkParams: ClockSinkParameters = ClockSinkParameters(), @@ -30,7 +30,7 @@ case class RocketTileParams( ) extends InstantiableTileParams[RocketTile] { require(icache.isDefined) require(dcache.isDefined) - val name = s"rockettile_$hartId" + val name = s"rockettile_$tileId" def instantiate(crossing: ElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = { new RocketTile(this, crossing, lookup) } @@ -100,7 +100,7 @@ class RocketTile private( } ResourceBinding { - Resource(cpuDevice, "reg").bind(ResourceAddress(staticIdForMetadataUseOnly)) + Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } override lazy val module = new RocketTileModuleImp(this)