diff --git a/src/main/scala/amba/axi4/Xbar.scala b/src/main/scala/amba/axi4/Xbar.scala
index be65db13834..0aa2a57bcc7 100644
--- a/src/main/scala/amba/axi4/Xbar.scala
+++ b/src/main/scala/amba/axi4/Xbar.scala
@@ -85,7 +85,12 @@ class AXI4Xbar(
     // Transform input bundles
     val in = Wire(Vec(io_in.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until in.size) {
-      in(i).squeezeAll :<>= io_in(i).squeezeAll
+      in(i).aw.bits.user := DontCare
+      in(i).aw.bits.echo := DontCare
+      in(i).ar.bits.user := DontCare
+      in(i).ar.bits.echo := DontCare
+      in(i).w.bits.user := DontCare
+      in(i).squeezeAll.waiveAll :<>= io_in(i).squeezeAll.waiveAll
 
       // Handle size = 1 gracefully (Chisel3 empty range is broken)
       def trim(id: UInt, size: Int) = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
@@ -168,7 +173,9 @@ class AXI4Xbar(
     // Transform output bundles
     val out = Wire(Vec(io_out.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until out.size) {
-      io_out(i).squeezeAll :<>= out(i).squeezeAll
+      out(i).b.bits.user := DontCare
+      out(i).r.bits.user := DontCare
+      io_out(i).squeezeAll.waiveAll :<>= out(i).squeezeAll.waiveAll
 
       if (io_in.size > 1) {
         // Block AW if we cannot record the W source