From 14ba271dee8dc754162852ec37ffd8aa7aa0bdfb Mon Sep 17 00:00:00 2001
From: Sungkeun Kim <sk84.kim@samsung.com>
Date: Thu, 30 May 2024 08:53:32 +0900
Subject: [PATCH] Add IO Connections for Custom User Field in TL Channels
 within Xbar module Please refer to the issue page below.
 https://github.com/ucb-bar/chipyard/issues/1888

---
 src/main/scala/tilelink/Xbar.scala | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/src/main/scala/tilelink/Xbar.scala b/src/main/scala/tilelink/Xbar.scala
index 3ef0047bb12..d625b0ffb35 100644
--- a/src/main/scala/tilelink/Xbar.scala
+++ b/src/main/scala/tilelink/Xbar.scala
@@ -163,6 +163,12 @@ object TLXbar
       if (connectAIO(i).exists(x=>x)) {
         in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
         in(i).a.bits.user := DontCare
+        // If there are user defined bundles in both sides, connect them.
+        io_in(i).a.bits.user.keydata.foreach { case (io_in_key, io_in_bundle) =>
+          in(i).a.bits.user.lift(io_in_key).foreach { in_bundle =>
+            in_bundle <> io_in_bundle
+          }
+        }
         in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
       } else {
         in(i).a := DontCare
@@ -184,6 +190,12 @@ object TLXbar
       if (connectCIO(i).exists(x=>x)) {
         in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
         in(i).c.bits.user := DontCare
+        // If there are user defined bundles in both sides, connect them.
+        io_in(i).c.bits.user.keydata.foreach { case (io_in_key, io_in_bundle) =>
+          in(i).c.bits.user.lift(io_in_key).foreach { in_bundle =>
+            in_bundle <> io_in_bundle
+          }
+        }
         in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
       } else {
         in(i).c := DontCare
@@ -220,6 +232,12 @@ object TLXbar
       if (connectAOI(o).exists(x=>x)) {
         io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
         out(o).a.bits.user := DontCare
+        // If there are user defined bundles in both sides, connect them.
+        out(o).a.bits.user.keydata.foreach { case (out_key, out_bundle) =>
+          io_out(o).a.bits.user.lift(out_key).foreach { io_out_bundle =>
+            io_out_bundle <> out_bundle
+          }
+        }
       } else {
         out(o).a := DontCare
         io_out(o).a := DontCare
@@ -239,6 +257,12 @@ object TLXbar
       if (connectCOI(o).exists(x=>x)) {
         io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
         out(o).c.bits.user := DontCare
+        // If there are user defined bundles in both sides, connect them.
+        out(o).c.bits.user.keydata.foreach { case (out_key, out_bundle) =>
+          io_out(o).c.bits.user.lift(out_key).foreach { io_out_bundle =>
+            io_out_bundle <> out_bundle
+          }
+        }
       } else {
         out(o).c  := DontCare
         io_out(o).c  := DontCare