From 072bc412dcb7684f46874f3392c81ecdc3ea20b6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 28 Feb 2024 16:21:26 -0800 Subject: [PATCH] Fix vsetvl with rs1=x0 --- src/main/scala/rocket/RocketCore.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index 71b7e995fc1..b4c6610496b 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -467,7 +467,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, - Mux(ex_reg_inst(11,6) === 0.U, csr.io.vector.get.vconfig.vl, ~(0.U(log2Ceil(maxVLMax).W))), + Mux(ex_reg_inst(11,6) === 0.U, csr.io.vector.get.vconfig.vl, ~(0.U((1+log2Ceil(maxVLMax)).W))), ex_rs(0) ), ex_reg_inst(19,15))