diff --git a/euvm/riscv/gen/isa/riscv_vector_instr.d b/euvm/riscv/gen/isa/riscv_vector_instr.d index 9b5cecd8..f069b281 100644 --- a/euvm/riscv/gen/isa/riscv_vector_instr.d +++ b/euvm/riscv/gen/isa/riscv_vector_instr.d @@ -21,7 +21,7 @@ module riscv.gen.isa.riscv_vector_instr; import riscv.gen.riscv_instr_pkg: riscv_vreg_t, va_variant_t, - riscv_instr_name_t, riscv_instr_format_t, + riscv_instr_name_t, riscv_instr_format_t, va_base_instr, MAX_INSTR_STR_LEN, riscv_instr_category_t; import riscv.gen.isa.riscv_instr: riscv_instr; import riscv.gen.isa.riscv_floating_point_instr: riscv_floating_point_instr; @@ -63,6 +63,8 @@ class riscv_vector_instr: riscv_floating_point_instr bool rand_nfields; @rand ubvec!4 emul; + enum va_base_instr VA_BASE = va_base_instr.VA_NO_BASE; + constraint!q{ if (m_cfg.vector_cfg.reserved_vregs.length > 0) { !(vd inside [m_cfg.vector_cfg.reserved_vregs]); @@ -126,14 +128,14 @@ class riscv_vector_instr: riscv_floating_point_instr if (m_cfg.vector_cfg.vtype.vlmul > 1) { // For vadc and vsbc, an illegal instruction exception is raised if the // destination vector register is v0 and LMUL> 1 - if (instr_name inside [riscv_instr_name_t.VADC, - riscv_instr_name_t.VSBC]) { + if (VA_BASE inside [va_base_instr.VADC, + va_base_instr.VSBC]) { vd != 0; } // For vmadc and vmsbc, an illegal instruction exception is raised if the // destination vector register overlaps asource vector register group and LMUL > 1 - if (instr_name inside [riscv_instr_name_t.VMADC, - riscv_instr_name_t.VMSBC]) { + if (VA_BASE inside [va_base_instr.VMADC, + va_base_instr.VMSBC]) { vd != vs2; vd != vs1; } @@ -175,10 +177,10 @@ class riscv_vector_instr: riscv_floating_point_instr // The destination vector register group for vslideup cannot overlap the vector register // group of the source vector register group or the mask register constraint!q{ - if (instr_name inside [riscv_instr_name_t.VSLIDEUP, - riscv_instr_name_t.VSLIDE1UP, - riscv_instr_name_t.VSLIDEDOWN, - riscv_instr_name_t.VSLIDE1DOWN]) { + if (VA_BASE inside [va_base_instr.VSLIDEUP, + va_base_instr.VSLIDE1UP, + va_base_instr.VSLIDEDOWN, + va_base_instr.VSLIDE1DOWN]) { vd != vs2; vd != vs1; (vm == false) -> (vd != 0); @@ -189,7 +191,7 @@ class riscv_vector_instr: riscv_floating_point_instr // For any vrgather instruction, the destination vector register group cannot overlap // with the source vector register group constraint!q{ - if (instr_name == riscv_instr_name_t.VRGATHER) { + if (VA_BASE == va_base_instr.VRGATHER) { vd != vs2; vd != vs1; (vm == false) -> (vd != 0); @@ -200,7 +202,7 @@ class riscv_vector_instr: riscv_floating_point_instr // The destination vector register group cannot overlap the source vector register // group or the source vector mask register constraint!q{ - if (instr_name == riscv_instr_name_t.VCOMPRESS) { + if (VA_BASE == va_base_instr.VCOMPRESS) { vd != vs2; vd != vs1; (vm == false) -> (vd != 0); @@ -257,18 +259,18 @@ class riscv_vector_instr: riscv_floating_point_instr constraint!q{ // Below instruction is always masked - if (instr_name inside [riscv_instr_name_t.VMERGE, - riscv_instr_name_t.VFMERGE, - riscv_instr_name_t.VADC, - riscv_instr_name_t.VSBC]) { + if (VA_BASE inside [va_base_instr.VMERGE, + va_base_instr.VFMERGE, + va_base_instr.VADC, + va_base_instr.VSBC]) { vm == false; } } vector_mask_enable_c; constraint!q{ // (vm=0) is reserved for below ops - if (instr_name inside [riscv_instr_name_t.VMV, riscv_instr_name_t.VFMV, - riscv_instr_name_t.VCOMPRESS, riscv_instr_name_t.VFMV_F_S, + if (instr_name inside [riscv_instr_name_t.VMV_VV, riscv_instr_name_t.VMV_VX, riscv_instr_name_t.VMV_VI, + riscv_instr_name_t.VFMV_VF, riscv_instr_name_t.VCOMPRESS_VM, riscv_instr_name_t.VFMV_F_S, riscv_instr_name_t.VFMV_S_F, riscv_instr_name_t.VMV_X_S, riscv_instr_name_t.VMV_S_X, riscv_instr_name_t.VMV1R_V, riscv_instr_name_t.VMV2R_V, riscv_instr_name_t.VMV4R_V, @@ -285,11 +287,12 @@ class riscv_vector_instr: riscv_floating_point_instr } } vector_mask_instr_c; - constraint!q{ - if (! m_cfg.vector_cfg.vec_fp) { - va_variant != va_variant_t.VF; - } - } disable_floating_point_varaint_c; + // This is now dealt with in config object + // constraint!q{ + // if (! m_cfg.vector_cfg.vec_fp) { + // va_variant != va_variant_t.VF; + // } + // } disable_floating_point_varaint_c; constraint!q{ // TODO: Check why this is needed? @@ -351,8 +354,8 @@ class riscv_vector_instr: riscv_floating_point_instr string name = instr_name.to!string(); // 19.2.2. Vector Add with Carry/Subtract with Borrow Reserved under EDIV>1 if ((cfg.vector_cfg.vtype.vediv > 1) && - (instr_name.inside(riscv_instr_name_t.VADC, riscv_instr_name_t.VSBC, - riscv_instr_name_t.VMADC, riscv_instr_name_t.VMSBC))) { + (VA_BASE.inside(va_base_instr.VADC, va_base_instr.VSBC, + va_base_instr.VMADC, va_base_instr.VMSBC))) { return false; } // Disable widening/narrowing instruction when LMUL == 8 @@ -364,11 +367,11 @@ class riscv_vector_instr: riscv_floating_point_instr return false; } // TODO: Clean up this list, it's causing gcc compile error now - if (instr_name.inside(riscv_instr_name_t.VWMACCSU, - riscv_instr_name_t.VMERGE, - riscv_instr_name_t.VFMERGE, - riscv_instr_name_t.VMADC, - riscv_instr_name_t.VMSBC)) { + if (VA_BASE.inside(va_base_instr.VWMACCSU, + va_base_instr.VMERGE, + va_base_instr.VFMERGE, + va_base_instr.VMADC, + va_base_instr.VMSBC)) { return false; } // The standard vector floating-point instructions treat 16-bit, 32-bit, 64-bit, @@ -437,7 +440,7 @@ class riscv_vector_instr: riscv_floating_point_instr } break; case riscv_instr_format_t.VA_FORMAT: - if (instr_name == riscv_instr_name_t.VMV) { + if (VA_BASE == va_base_instr.VMV) { switch (va_variant) { case va_variant_t.VV: asm_str = format("vmv.v.v %s,%s", vd, vs1); @@ -451,7 +454,7 @@ class riscv_vector_instr: riscv_floating_point_instr default: uvm_info(get_full_name(), format("Unsupported va_variant %0s", va_variant), UVM_LOW); } } - else if (instr_name == riscv_instr_name_t.VFMV) { + else if (VA_BASE == va_base_instr.VFMV) { asm_str = format("vfmv.v.f %s,%s", vd, fs1); } else if (instr_name == riscv_instr_name_t.VMV_X_S) { @@ -489,18 +492,18 @@ class riscv_vector_instr: riscv_floating_point_instr break; case va_variant_t.VF, va_variant_t.VFM: - if (instr_name.inside(riscv_instr_name_t.VFMADD, - riscv_instr_name_t.VFNMADD, - riscv_instr_name_t.VFMACC, - riscv_instr_name_t.VFNMACC, - riscv_instr_name_t.VFNMSUB, - riscv_instr_name_t.VFWNMSAC, - riscv_instr_name_t.VFWMACC, - riscv_instr_name_t.VFMSUB, - riscv_instr_name_t.VFMSAC, - riscv_instr_name_t.VFNMSAC, - riscv_instr_name_t.VFWNMACC, - riscv_instr_name_t.VFWMSAC)) { + if (VA_BASE.inside(va_base_instr.VFMADD, + va_base_instr.VFNMADD, + va_base_instr.VFMACC, + va_base_instr.VFNMACC, + va_base_instr.VFNMSUB, + va_base_instr.VFWNMSAC, + va_base_instr.VFWMACC, + va_base_instr.VFMSUB, + va_base_instr.VFMSAC, + va_base_instr.VFNMSAC, + va_base_instr.VFWNMACC, + va_base_instr.VFWMSAC)) { asm_str = asm_str ~ format("%0s,%0s,%0s", vd, fs1, vs2); } else { @@ -510,14 +513,14 @@ class riscv_vector_instr: riscv_floating_point_instr case va_variant_t.WX, va_variant_t.VX, va_variant_t.VXM: - if (instr_name.inside(riscv_instr_name_t.VMADD, - riscv_instr_name_t.VNMSUB, - riscv_instr_name_t.VMACC, - riscv_instr_name_t.VNMSAC, - riscv_instr_name_t.VWMACCSU, - riscv_instr_name_t.VWMACCU, - riscv_instr_name_t.VWMACCUS, - riscv_instr_name_t.VWMACC)) { + if (VA_BASE.inside(va_base_instr.VMADD, + va_base_instr.VNMSUB, + va_base_instr.VMACC, + va_base_instr.VNMSAC, + va_base_instr.VWMACCSU, + va_base_instr.VWMACCU, + va_base_instr.VWMACCUS, + va_base_instr.VWMACC)) { asm_str ~= format("%0s,%0s,%0s", vd, rs1, vs2); } else { @@ -636,7 +639,7 @@ class riscv_vector_instr: riscv_floating_point_instr } break; case riscv_instr_format_t.VA_FORMAT: - if (instr_name == riscv_instr_name_t.VMV) { + if (VA_BASE == va_base_instr.VMV) { switch (va_variant) { case va_variant_t.VV: asm_buf = sformat!("vmv.v.v %s,%s")(buf, vd, vs1); @@ -650,7 +653,7 @@ class riscv_vector_instr: riscv_floating_point_instr default: uvm_info(get_full_name(), format("Unsupported va_variant %0s", va_variant), UVM_LOW); } } - else if (instr_name == riscv_instr_name_t.VFMV) { + else if (VA_BASE == va_base_instr.VFMV) { asm_buf = sformat!("vfmv.v.f %s,%s")(buf, vd, fs1); } else if (instr_name == riscv_instr_name_t.VMV_X_S) { @@ -688,18 +691,18 @@ class riscv_vector_instr: riscv_floating_point_instr break; case va_variant_t.VF, va_variant_t.VFM: - if (instr_name.inside(riscv_instr_name_t.VFMADD, - riscv_instr_name_t.VFNMADD, - riscv_instr_name_t.VFMACC, - riscv_instr_name_t.VFNMACC, - riscv_instr_name_t.VFNMSUB, - riscv_instr_name_t.VFWNMSAC, - riscv_instr_name_t.VFWMACC, - riscv_instr_name_t.VFMSUB, - riscv_instr_name_t.VFMSAC, - riscv_instr_name_t.VFNMSAC, - riscv_instr_name_t.VFWNMACC, - riscv_instr_name_t.VFWMSAC)) { + if (VA_BASE.inside(va_base_instr.VFMADD, + va_base_instr.VFNMADD, + va_base_instr.VFMACC, + va_base_instr.VFNMACC, + va_base_instr.VFNMSUB, + va_base_instr.VFWNMSAC, + va_base_instr.VFWMACC, + va_base_instr.VFMSUB, + va_base_instr.VFMSAC, + va_base_instr.VFNMSAC, + va_base_instr.VFWNMACC, + va_base_instr.VFWMSAC)) { asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, fs1, vs2); } else { @@ -709,14 +712,14 @@ class riscv_vector_instr: riscv_floating_point_instr case va_variant_t.WX, va_variant_t.VX, va_variant_t.VXM: - if (instr_name.inside(riscv_instr_name_t.VMADD, - riscv_instr_name_t.VNMSUB, - riscv_instr_name_t.VMACC, - riscv_instr_name_t.VNMSAC, - riscv_instr_name_t.VWMACCSU, - riscv_instr_name_t.VWMACCU, - riscv_instr_name_t.VWMACCUS, - riscv_instr_name_t.VWMACC)) { + if (VA_BASE.inside(va_base_instr.VMADD, + va_base_instr.VNMSUB, + va_base_instr.VMACC, + va_base_instr.VNMSAC, + va_base_instr.VWMACCSU, + va_base_instr.VWMACCU, + va_base_instr.VWMACCUS, + va_base_instr.VWMACC)) { asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, rs1, vs2); } else { @@ -874,12 +877,12 @@ class riscv_vector_instr: riscv_floating_point_instr return ""; } else { - if (instr_name.inside(riscv_instr_name_t.VMERGE, - riscv_instr_name_t.VFMERGE, - riscv_instr_name_t.VADC, - riscv_instr_name_t.VSBC, - riscv_instr_name_t.VMADC, - riscv_instr_name_t.VMSBC)) { + if (VA_BASE.inside(va_base_instr.VMERGE, + va_base_instr.VFMERGE, + va_base_instr.VADC, + va_base_instr.VSBC, + va_base_instr.VMADC, + va_base_instr.VMSBC)) { return ",v0"; } else { diff --git a/euvm/riscv/gen/isa/rv32i_instr.d b/euvm/riscv/gen/isa/rv32i_instr.d index 7e952ad3..3ec8afdb 100644 --- a/euvm/riscv/gen/isa/rv32i_instr.d +++ b/euvm/riscv/gen/isa/rv32i_instr.d @@ -17,6 +17,7 @@ module riscv.gen.isa.rv32i_instr; import riscv.gen.riscv_defines; +import riscv.gen.isa.riscv_instr: riscv_instr; import uvm; diff --git a/euvm/riscv/gen/isa/rv32m_instr.d b/euvm/riscv/gen/isa/rv32m_instr.d index 87f07fc1..91937145 100644 --- a/euvm/riscv/gen/isa/rv32m_instr.d +++ b/euvm/riscv/gen/isa/rv32m_instr.d @@ -17,6 +17,7 @@ module riscv.gen.isa.rv32m_instr; import riscv.gen.riscv_defines; +import riscv.gen.isa.riscv_instr: riscv_instr; import uvm; diff --git a/euvm/riscv/gen/isa/rv32v_instr.d b/euvm/riscv/gen/isa/rv32v_instr.d index 8352bfbd..1e96ae37 100644 --- a/euvm/riscv/gen/isa/rv32v_instr.d +++ b/euvm/riscv/gen/isa/rv32v_instr.d @@ -19,6 +19,7 @@ module riscv.gen.isa.rv32v_instr; import riscv.gen.riscv_defines; +import riscv.gen.isa.riscv_instr: riscv_instr; import uvm; @@ -257,410 +258,460 @@ version (RISCV_INSTR_STRING_MIXIN) { { mixin RISCV_INSTR_MIXIN!(VSETVL, VSET_FORMAT, CSR, RVV); } // Vector integer arithmetic instruction - class riscv_VADD_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } - class riscv_VSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VRSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VRSUB, VA_FORMAT, ARITHMETIC, RVV, VX, VI); } - class riscv_VWADDU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWADDU, VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); } - class riscv_VWSUBU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU, VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); } - class riscv_VWADD_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); } - class riscv_VWSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); } - class riscv_VADC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VADC, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM); } - class riscv_VMADC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMADC, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM, VV, VX, VI); } - class riscv_VSBC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSBC, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM); } - class riscv_VMSBC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSBC, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VV, VX); } - class riscv_VAND_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VAND, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } - class riscv_VOR_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VOR, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } - class riscv_VXOR_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VXOR, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } - class riscv_VSLL_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSLL, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } - class riscv_VSRL_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSRL, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } - class riscv_VSRA_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSRA, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } - class riscv_VNSRL_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VNSRL, VA_FORMAT, SHIFT, RVV, WV, WX, WI); } - class riscv_VNSRA_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VNSRA, VA_FORMAT, SHIFT, RVV, WV, WX, WI); } - class riscv_VMSEQ_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ, VA_FORMAT, COMPARE, RVV, VV, VX, VI); } - class riscv_VMSNE_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSNE, VA_FORMAT, COMPARE, RVV, VV, VX, VI); } - class riscv_VMSLTU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSLTU, VA_FORMAT, COMPARE, RVV, VV, VX); } - class riscv_VMSLT_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSLT, VA_FORMAT, COMPARE, RVV, VV, VX); } - class riscv_VMSLEU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU, VA_FORMAT, COMPARE, RVV, VV, VX, VI); } - class riscv_VMSLE_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSLE, VA_FORMAT, COMPARE, RVV, VV, VX, VI); } - class riscv_VMSGTU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSGTU, VA_FORMAT, COMPARE, RVV, VX, VI); } - class riscv_VMSGT_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSGT, VA_FORMAT, COMPARE, RVV, VX, VI); } - class riscv_VMINU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMINU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMIN_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMIN, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMAXU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMAXU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMAX_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMAX, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMUL_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMUL, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMULH_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMULH, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMULHU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMULHU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMULHSU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMULHSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VDIVU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VDIVU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VDIV_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VDIV, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VREMU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREMU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VREM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREM, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VWMUL_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWMUL, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VWMULU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWMULU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VWMULSU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWMULSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMACC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VNMSAC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VNMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VMADD_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VNMSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VNMSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VWMACCU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWMACCU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VWMACC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VWMACCSU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWMACCSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VWMACCUS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWMACCUS, VA_FORMAT, ARITHMETIC, RVV, VX); } - /* Quad widening is not yet supported - class riscv_VQMACCU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VQMACCU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VQMACC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VQMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VQMACCSU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VQMACCSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VQMACCUS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VQMACCUS, VA_FORMAT, ARITHMETIC, RVV, VX); } - */ - class riscv_VMERGE_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMERGE, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM); } - class riscv_VMV_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMV, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + // class riscv_VADD_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + class riscv_VADD_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VADD + class riscv_VADD_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VADD + class riscv_VADD_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VADD_VI, VA_FORMAT, ARITHMETIC, RVV); } // VADD + // class riscv_VSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VSUB_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSUB + class riscv_VSUB_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSUB + // class riscv_VRSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VRSUB, VA_FORMAT, ARITHMETIC, RVV, VX, VI); } + class riscv_VRSUB_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VRSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VRSUB + class riscv_VRSUB_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VRSUB_VI, VA_FORMAT, ARITHMETIC, RVV); } // VRSUB + // class riscv_VWADDU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWADDU, VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); } + class riscv_VWADDU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWADDU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWADDU + class riscv_VWADDU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWADDU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWADDU + class riscv_VWADDU_WV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWADDU_WV, VA_FORMAT, ARITHMETIC, RVV); } // VWADDU + class riscv_VWADDU_WX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWADDU_WX, VA_FORMAT, ARITHMETIC, RVV); } // VWADDU + // class riscv_VWSUBU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU, VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); } + class riscv_VWSUBU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWSUBU + class riscv_VWSUBU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWSUBU + class riscv_VWSUBU_WV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU_WV, VA_FORMAT, ARITHMETIC, RVV); } // VWSUBU + class riscv_VWSUBU_WX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU_WX, VA_FORMAT, ARITHMETIC, RVV); } // VWSUBU + // class riscv_VWADD_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); } + class riscv_VWADD_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWADD + class riscv_VWADD_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWADD + class riscv_VWADD_WV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWADD_WV, VA_FORMAT, ARITHMETIC, RVV); } // VWADD + class riscv_VWADD_WX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWADD_WX, VA_FORMAT, ARITHMETIC, RVV); } // VWADD + // class riscv_VWSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); } + class riscv_VWSUB_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWSUB + class riscv_VWSUB_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWSUB + class riscv_VWSUB_WV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWSUB_WV, VA_FORMAT, ARITHMETIC, RVV); } // VWSUB + class riscv_VWSUB_WX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWSUB_WX, VA_FORMAT, ARITHMETIC, RVV); } // VWSUB + // class riscv_VADC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VADC, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM); } + class riscv_VADC_VVM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VADC_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VADC + class riscv_VADC_VXM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VADC_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VADC + class riscv_VADC_VIM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VADC_VIM, VA_FORMAT, ARITHMETIC, RVV); } // VADC + // class riscv_VMADC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMADC, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM, VV, VX, VI); } + class riscv_VMADC_VVM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VMADC + class riscv_VMADC_VXM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VMADC + class riscv_VMADC_VIM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VIM, VA_FORMAT, ARITHMETIC, RVV); } // VMADC + class riscv_VMADC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMADC + class riscv_VMADC_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMADC + class riscv_VMADC_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VI, VA_FORMAT, ARITHMETIC, RVV); } // VMADC + // class riscv_VSBC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSBC, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM); } + class riscv_VSBC_VVM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSBC_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VSBC + class riscv_VSBC_VXM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSBC_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VSBC + // class riscv_VMSBC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSBC, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VV, VX); } + class riscv_VMSBC_VVM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSBC_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VMSBC + class riscv_VMSBC_VXM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSBC_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VMSBC + class riscv_VMSBC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSBC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMSBC + class riscv_VMSBC_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSBC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMSBC + // class riscv_VAND_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VAND, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + class riscv_VAND_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VAND_VV, VA_FORMAT, ARITHMETIC, RVV); } // VAND + class riscv_VAND_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VAND_VX, VA_FORMAT, ARITHMETIC, RVV); } // VAND + class riscv_VAND_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VAND_VI, VA_FORMAT, ARITHMETIC, RVV); } // VAND + // class riscv_VOR_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VOR, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + class riscv_VOR_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VOR_VV, VA_FORMAT, ARITHMETIC, RVV); } // VOR + class riscv_VOR_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VOR_VX, VA_FORMAT, ARITHMETIC, RVV); } // VOR + class riscv_VOR_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VOR_VI, VA_FORMAT, ARITHMETIC, RVV); } // VOR + // class riscv_VXOR_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VXOR, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + class riscv_VXOR_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VXOR_VV, VA_FORMAT, ARITHMETIC, RVV); } // VXOR + class riscv_VXOR_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VXOR_VX, VA_FORMAT, ARITHMETIC, RVV); } // VXOR + class riscv_VXOR_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VXOR_VI, VA_FORMAT, ARITHMETIC, RVV); } // VXOR + // class riscv_VSLL_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSLL, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } + class riscv_VSLL_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLL_VV, VA_FORMAT, SHIFT, RVV); } // VSLL + class riscv_VSLL_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLL_VX, VA_FORMAT, SHIFT, RVV); } // VSLL + class riscv_VSLL_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLL_VI, VA_FORMAT, SHIFT, RVV); } // VSLL + // class riscv_VSRL_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSRL, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } + class riscv_VSRL_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSRL_VV, VA_FORMAT, SHIFT, RVV); } // VSRL + class riscv_VSRL_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSRL_VX, VA_FORMAT, SHIFT, RVV); } // VSRL + class riscv_VSRL_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSRL_VI, VA_FORMAT, SHIFT, RVV); } // VSRL + // class riscv_VSRA_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSRA, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } + class riscv_VSRA_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSRA_VV, VA_FORMAT, SHIFT, RVV); } // VSRA + class riscv_VSRA_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSRA_VX, VA_FORMAT, SHIFT, RVV); } // VSRA + class riscv_VSRA_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSRA_VI, VA_FORMAT, SHIFT, RVV); } // VSRA + // class riscv_VNSRL_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VNSRL, VA_FORMAT, SHIFT, RVV, WV, WX, WI); } + class riscv_VNSRL_WV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNSRL_WV, VA_FORMAT, SHIFT, RVV); } // VNSRL + class riscv_VNSRL_WX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNSRL_WX, VA_FORMAT, SHIFT, RVV); } // VNSRL + class riscv_VNSRL_WI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNSRL_WI, VA_FORMAT, SHIFT, RVV); } // VNSRL + // class riscv_VNSRA_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VNSRA, VA_FORMAT, SHIFT, RVV, WV, WX, WI); } + class riscv_VNSRA_WV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNSRA_WV, VA_FORMAT, SHIFT, RVV); } // VNSRA + class riscv_VNSRA_WX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNSRA_WX, VA_FORMAT, SHIFT, RVV); } // VNSRA + class riscv_VNSRA_WI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNSRA_WI, VA_FORMAT, SHIFT, RVV); } // VNSRA + // class riscv_VMSEQ_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ, VA_FORMAT, COMPARE, RVV, VV, VX, VI); } + class riscv_VMSEQ_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ_VV, VA_FORMAT, COMPARE, RVV); } // VMSEQ + class riscv_VMSEQ_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ_VX, VA_FORMAT, COMPARE, RVV); } // VMSEQ + class riscv_VMSEQ_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ_VI, VA_FORMAT, COMPARE, RVV); } // VMSEQ + // class riscv_VMSNE_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSNE, VA_FORMAT, COMPARE, RVV, VV, VX, VI); } + class riscv_VMSNE_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSNE_VV, VA_FORMAT, COMPARE, RVV); } // VMSNE + class riscv_VMSNE_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSNE_VX, VA_FORMAT, COMPARE, RVV); } // VMSNE + class riscv_VMSNE_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSNE_VI, VA_FORMAT, COMPARE, RVV); } // VMSNE + // class riscv_VMSLTU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSLTU, VA_FORMAT, COMPARE, RVV, VV, VX); } + class riscv_VMSLTU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLTU_VV, VA_FORMAT, COMPARE, RVV); } // VMSLTU + class riscv_VMSLTU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLTU_VX, VA_FORMAT, COMPARE, RVV); } // VMSLTU + // class riscv_VMSLT_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSLT, VA_FORMAT, COMPARE, RVV, VV, VX); } + class riscv_VMSLT_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLT_VV, VA_FORMAT, COMPARE, RVV); } // VMSLT + class riscv_VMSLT_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLT_VX, VA_FORMAT, COMPARE, RVV); } // VMSLT + // class riscv_VMSLEU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU, VA_FORMAT, COMPARE, RVV, VV, VX, VI); } + class riscv_VMSLEU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU_VV, VA_FORMAT, COMPARE, RVV); } // VMSLEU + class riscv_VMSLEU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU_VX, VA_FORMAT, COMPARE, RVV); } // VMSLEU + class riscv_VMSLEU_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU_VI, VA_FORMAT, COMPARE, RVV); } // VMSLEU + // class riscv_VMSLE_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSLE, VA_FORMAT, COMPARE, RVV, VV, VX, VI); } + class riscv_VMSLE_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLE_VV, VA_FORMAT, COMPARE, RVV); } // VMSLE + class riscv_VMSLE_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLE_VX, VA_FORMAT, COMPARE, RVV); } // VMSLE + class riscv_VMSLE_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSLE_VI, VA_FORMAT, COMPARE, RVV); } // VMSLE + // class riscv_VMSGTU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSGTU, VA_FORMAT, COMPARE, RVV, VX, VI); } + class riscv_VMSGTU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSGTU_VX, VA_FORMAT, COMPARE, RVV); } // VMSGTU + class riscv_VMSGTU_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSGTU_VI, VA_FORMAT, COMPARE, RVV); } // VMSGTU + // class riscv_VMSGT_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMSGT, VA_FORMAT, COMPARE, RVV, VX, VI); } + class riscv_VMSGT_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSGT_VX, VA_FORMAT, COMPARE, RVV); } // VMSGT + class riscv_VMSGT_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSGT_VI, VA_FORMAT, COMPARE, RVV); } // VMSGT + // class riscv_VMINU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMINU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMINU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMINU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMINU + class riscv_VMINU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMINU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMINU + // class riscv_VMIN_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMIN, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMIN_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMIN_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMIN + class riscv_VMIN_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMIN_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMIN + // class riscv_VMAXU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMAXU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMAXU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMAXU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMAXU + class riscv_VMAXU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMAXU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMAXU + // class riscv_VMAX_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMAX, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMAX_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMAX_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMAX + class riscv_VMAX_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMAX_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMAX + // class riscv_VMUL_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMUL, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMUL_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMUL + class riscv_VMUL_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMUL_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMUL + // class riscv_VMULH_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMULH, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMULH_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMULH_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMULH + class riscv_VMULH_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMULH_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMULH + // class riscv_VMULHU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMULHU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMULHU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMULHU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMULHU + class riscv_VMULHU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMULHU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMULHU + // class riscv_VMULHSU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMULHSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMULHSU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMULHSU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMULHSU + class riscv_VMULHSU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMULHSU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMULHSU + // class riscv_VDIVU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VDIVU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VDIVU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VDIVU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VDIVU + class riscv_VDIVU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VDIVU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VDIVU + // class riscv_VDIV_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VDIV, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VDIV_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VDIV_VV, VA_FORMAT, ARITHMETIC, RVV); } // VDIV + class riscv_VDIV_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VDIV_VX, VA_FORMAT, ARITHMETIC, RVV); } // VDIV + // class riscv_VREMU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VREMU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VREMU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREMU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VREMU + class riscv_VREMU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREMU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VREMU + // class riscv_VREM_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VREM, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VREM_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREM_VV, VA_FORMAT, ARITHMETIC, RVV); } // VREM + class riscv_VREM_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREM_VX, VA_FORMAT, ARITHMETIC, RVV); } // VREM + // class riscv_VWMUL_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWMUL, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VWMUL_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMUL + class riscv_VWMUL_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMUL_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMUL + // class riscv_VWMULU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWMULU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VWMULU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMULU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMULU + class riscv_VWMULU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMULU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMULU + // class riscv_VWMULSU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWMULSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VWMULSU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMULSU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMULSU + class riscv_VWMULSU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMULSU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMULSU + // class riscv_VMACC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMACC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMACC + class riscv_VMACC_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMACC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMACC + // class riscv_VNMSAC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VNMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VNMSAC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VNMSAC + class riscv_VNMSAC_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNMSAC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VNMSAC + // class riscv_VMADD_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VMADD_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMADD + class riscv_VMADD_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMADD + // class riscv_VNMSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VNMSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VNMSUB_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNMSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VNMSUB + class riscv_VNMSUB_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNMSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VNMSUB + // class riscv_VWMACCU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWMACCU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VWMACCU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMACCU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCU + class riscv_VWMACCU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMACCU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCU + // class riscv_VWMACC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VWMACC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMACC + class riscv_VWMACC_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMACC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMACC + // class riscv_VWMACCSU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWMACCSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VWMACCSU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMACCSU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCSU + class riscv_VWMACCSU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMACCSU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCSU + // class riscv_VWMACCUS_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VWMACCUS, VA_FORMAT, ARITHMETIC, RVV, VX); } + class riscv_VWMACCUS_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWMACCUS_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCUS + // /* Quad widening is not yet supported + // class riscv_VQMACCU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VQMACCU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + // class riscv_VQMACC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VQMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + // class riscv_VQMACCSU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VQMACCSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + // class riscv_VQMACCUS_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VQMACCUS, VA_FORMAT, ARITHMETIC, RVV, VX); } + // */ + // class riscv_VMERGE_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMERGE, VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM); } + // class riscv_VMV_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMV, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + class riscv_VMERGE_VVM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMERGE_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VMERGE + class riscv_VMERGE_VXM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMERGE_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VMERGE + class riscv_VMERGE_VIM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMERGE_VIM, VA_FORMAT, ARITHMETIC, RVV); } // VMERGE + class riscv_VMV_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMV + class riscv_VMV_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMV + class riscv_VMV_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV_VI, VA_FORMAT, ARITHMETIC, RVV); } // VMV // Vector Fixed-Point Arithmetic Instructions - class riscv_VSADDU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSADDU, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } - class riscv_VSADD_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } - class riscv_VSSUBU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSSUBU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VSSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VAADDU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VAADDU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VAADD_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VAADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VASUBU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VASUBU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VASUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VASUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } - class riscv_VSSRL_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSSRL, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } - class riscv_VSSRA_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSSRA, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } - class riscv_VNCLIPU_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU, VA_FORMAT, ARITHMETIC, RVV, WV, WX, WI); } - class riscv_VNCLIP_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP, VA_FORMAT, ARITHMETIC, RVV, WV, WX, WI); } + // class riscv_VSADDU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSADDU, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + class riscv_VSADDU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSADDU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSADDU + class riscv_VSADDU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSADDU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSADDU + class riscv_VSADDU_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSADDU_VI, VA_FORMAT, ARITHMETIC, RVV); } // VSADDU + // class riscv_VSADD_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + class riscv_VSADD_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSADD + class riscv_VSADD_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSADD + class riscv_VSADD_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSADD_VI, VA_FORMAT, ARITHMETIC, RVV); } // VSADD + // class riscv_VSSUBU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSSUBU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VSSUBU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSUBU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSSUBU + class riscv_VSSUBU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSUBU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSSUBU + // class riscv_VSSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VSSUB_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSSUB + class riscv_VSSUB_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSSUB + // class riscv_VAADDU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VAADDU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VAADDU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VAADDU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VAADDU + class riscv_VAADDU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VAADDU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VAADDU + // class riscv_VAADD_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VAADD, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VAADD_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VAADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VAADD + class riscv_VAADD_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VAADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VAADD + // class riscv_VASUBU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VASUBU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VASUBU_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VASUBU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VASUBU + class riscv_VASUBU_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VASUBU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VASUBU + // class riscv_VASUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VASUB, VA_FORMAT, ARITHMETIC, RVV, VV, VX); } + class riscv_VASUB_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VASUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VASUB + class riscv_VASUB_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VASUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VASUB + // class riscv_VSSRL_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSSRL, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } + class riscv_VSSRL_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSRL_VV, VA_FORMAT, SHIFT, RVV); } // VSSRL + class riscv_VSSRL_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSRL_VX, VA_FORMAT, SHIFT, RVV); } // VSSRL + class riscv_VSSRL_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSRL_VI, VA_FORMAT, SHIFT, RVV); } // VSSRL + // class riscv_VSSRA_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSSRA, VA_FORMAT, SHIFT, RVV, VV, VX, VI); } + class riscv_VSSRA_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSRA_VV, VA_FORMAT, SHIFT, RVV); } // VSSRA + class riscv_VSSRA_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSRA_VX, VA_FORMAT, SHIFT, RVV); } // VSSRA + class riscv_VSSRA_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSRA_VI, VA_FORMAT, SHIFT, RVV); } // VSSRA + // class riscv_VNCLIPU_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU, VA_FORMAT, ARITHMETIC, RVV, WV, WX, WI); } + class riscv_VNCLIPU_WV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU_WV, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIPU + class riscv_VNCLIPU_WX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU_WX, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIPU + class riscv_VNCLIPU_WI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU_WI, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIPU + // class riscv_VNCLIP_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP, VA_FORMAT, ARITHMETIC, RVV, WV, WX, WI); } + class riscv_VNCLIP_WV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP_WV, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIP + class riscv_VNCLIP_WX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP_WX, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIP + class riscv_VNCLIP_WI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP_WI, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIP // Vector Floating-Point Instructions - class riscv_VFADD_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFADD, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFRSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFRSUB, VA_FORMAT, ARITHMETIC, RVV, VF); } - class riscv_VFMUL_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMUL, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFDIV_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFDIV, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFRDIV_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFRDIV, VA_FORMAT, ARITHMETIC, RVV, VF); } - class riscv_VFWMUL_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWMUL, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFMACC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFNMACC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFMSAC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFNMSAC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFMADD_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMADD, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFNMADD_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNMADD, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFMSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFNMSUB_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNMSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFWMACC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFWNMACC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWNMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFWMSAC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFWNMSAC_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWNMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFSQRT_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFSQRT_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFMIN_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMIN, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFMAX_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMAX, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFSGNJ_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJ, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFSGNJN_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJN, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VFSGNJX_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJX, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } - class riscv_VMFEQ_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMFEQ, VA_FORMAT, COMPARE, RVV, VV, VF); } - class riscv_VMFNE_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMFNE, VA_FORMAT, COMPARE, RVV, VV, VF); } - class riscv_VMFLT_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMFLT, VA_FORMAT, COMPARE, RVV, VV, VF); } - class riscv_VMFLE_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMFLE, VA_FORMAT, COMPARE, RVV, VV, VF); } - class riscv_VMFGT_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMFGT, VA_FORMAT, COMPARE, RVV, VF); } - class riscv_VMFGE_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMFGE, VA_FORMAT, COMPARE, RVV, VF); } - class riscv_VFCLASS_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFCLASS_V,VS2_FORMAT, COMPARE, RVV); } - class riscv_VFMERGE_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMERGE, VA_FORMAT, ARITHMETIC, RVV, VFM); } - class riscv_VFMV_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMV, VA_FORMAT, ARITHMETIC, RVV, VF); } + // class riscv_VFADD_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFADD, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFADD_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFADD + class riscv_VFADD_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFADD_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFADD + // class riscv_VFSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFSUB_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFSUB + class riscv_VFSUB_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSUB + // class riscv_VFRSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFRSUB, VA_FORMAT, ARITHMETIC, RVV, VF); } + class riscv_VFRSUB_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFRSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFRSUB + // class riscv_VFMUL_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMUL, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFMUL_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMUL + class riscv_VFMUL_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMUL_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMUL + // class riscv_VFDIV_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFDIV, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFDIV_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFDIV_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFDIV + class riscv_VFDIV_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFDIV_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFDIV + // class riscv_VFRDIV_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFRDIV, VA_FORMAT, ARITHMETIC, RVV, VF); } + class riscv_VFRDIV_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFRDIV_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFRDIV + // class riscv_VFWMUL_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFWMUL, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFWMUL_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWMUL + class riscv_VFWMUL_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWMUL_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWMUL + // class riscv_VFMACC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFMACC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMACC + class riscv_VFMACC_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMACC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMACC + // class riscv_VFNMACC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFNMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFNMACC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFNMACC + class riscv_VFNMACC_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNMACC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFNMACC + // class riscv_VFMSAC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFMSAC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMSAC + class riscv_VFMSAC_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMSAC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMSAC + // class riscv_VFNMSAC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFNMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFNMSAC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFNMSAC + class riscv_VFNMSAC_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNMSAC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFNMSAC + // class riscv_VFMADD_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMADD, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFMADD_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMADD + class riscv_VFMADD_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMADD_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMADD + // class riscv_VFNMADD_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFNMADD, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFNMADD_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNMADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFNMADD + class riscv_VFNMADD_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNMADD_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFNMADD + // class riscv_VFMSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFMSUB_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMSUB + class riscv_VFMSUB_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMSUB + // class riscv_VFNMSUB_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFNMSUB, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFNMSUB_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNMSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFNMSUB + class riscv_VFNMSUB_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNMSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFNMSUB + // class riscv_VFWMACC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFWMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFWMACC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWMACC + class riscv_VFWMACC_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWMACC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWMACC + // class riscv_VFWNMACC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFWNMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFWNMACC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWNMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWNMACC + class riscv_VFWNMACC_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWNMACC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWNMACC + // class riscv_VFWMSAC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFWMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFWMSAC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWMSAC + class riscv_VFWMSAC_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWMSAC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWMSAC + // class riscv_VFWNMSAC_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFWNMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFWNMSAC_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWNMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWNMSAC + class riscv_VFWNMSAC_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWNMSAC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWNMSAC + + class riscv_VFSQRT_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSQRT_V, VS2_FORMAT, ARITHMETIC, RVV); } + + // class riscv_VFMIN_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMIN, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFMIN_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMIN_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMIN + class riscv_VFMIN_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMIN_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMIN + // class riscv_VFMAX_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMAX, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFMAX_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMAX_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMAX + class riscv_VFMAX_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMAX_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMAX + // class riscv_VFSGNJ_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJ, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFSGNJ_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJ_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJ + class riscv_VFSGNJ_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJ_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJ + // class riscv_VFSGNJN_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJN, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFSGNJN_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJN_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJN + class riscv_VFSGNJN_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJN_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJN + // class riscv_VFSGNJX_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJX, VA_FORMAT, ARITHMETIC, RVV, VV, VF); } + class riscv_VFSGNJX_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJX_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJX + class riscv_VFSGNJX_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJX_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJX + // class riscv_VMFEQ_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMFEQ, VA_FORMAT, COMPARE, RVV, VV, VF); } + class riscv_VMFEQ_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFEQ_VV, VA_FORMAT, COMPARE, RVV); } // VMFEQ + class riscv_VMFEQ_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFEQ_VF, VA_FORMAT, COMPARE, RVV); } // VMFEQ + // class riscv_VMFNE_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMFNE, VA_FORMAT, COMPARE, RVV, VV, VF); } + class riscv_VMFNE_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFNE_VV, VA_FORMAT, COMPARE, RVV); } // VMFNE + class riscv_VMFNE_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFNE_VF, VA_FORMAT, COMPARE, RVV); } // VMFNE + // class riscv_VMFLT_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMFLT, VA_FORMAT, COMPARE, RVV, VV, VF); } + class riscv_VMFLT_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFLT_VV, VA_FORMAT, COMPARE, RVV); } // VMFLT + class riscv_VMFLT_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFLT_VF, VA_FORMAT, COMPARE, RVV); } // VMFLT + // class riscv_VMFLE_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMFLE, VA_FORMAT, COMPARE, RVV, VV, VF); } + class riscv_VMFLE_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFLE_VV, VA_FORMAT, COMPARE, RVV); } // VMFLE + class riscv_VMFLE_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFLE_VF, VA_FORMAT, COMPARE, RVV); } // VMFLE + // class riscv_VMFGT_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMFGT, VA_FORMAT, COMPARE, RVV, VF); } + class riscv_VMFGT_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFGT_VF, VA_FORMAT, COMPARE, RVV); } // VMFGT + // class riscv_VMFGE_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VMFGE, VA_FORMAT, COMPARE, RVV, VF); } + class riscv_VMFGE_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMFGE_VF, VA_FORMAT, COMPARE, RVV); } // VMFGE + + class riscv_VFCLASS_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFCLASS_V,VS2_FORMAT, COMPARE, RVV); } + + // class riscv_VFMERGE_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMERGE, VA_FORMAT, ARITHMETIC, RVV, VFM); } + class riscv_VFMERGE_VFM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMERGE_VFM, VA_FORMAT, ARITHMETIC, RVV); } // VFMERGE + // class riscv_VFMV_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VFMV, VA_FORMAT, ARITHMETIC, RVV, VF); } + class riscv_VFMV_VF_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMV_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMV // Vector conversion instructions - class riscv_VFCVT_XU_F_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_XU_F_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFCVT_X_F_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_X_F_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFCVT_F_XU_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_F_XU_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFCVT_F_X_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_F_X_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFWCVT_XU_F_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_XU_F_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFWCVT_X_F_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_X_F_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFWCVT_F_XU_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_XU_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFWCVT_F_X_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_X_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFWCVT_F_F_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_F_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFNCVT_XU_F_W_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_XU_F_W, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFNCVT_X_F_W_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_X_F_W, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFNCVT_F_XU_W_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_XU_W, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFNCVT_F_X_W_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_X_W, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFNCVT_F_F_W_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_F_W, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFNCVT_ROD_F_F_W_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_ROD_F_F_W, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFCVT_XU_F_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_XU_F_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFCVT_X_F_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_X_F_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFCVT_F_XU_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_F_XU_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFCVT_F_X_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_F_X_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFWCVT_XU_F_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_XU_F_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFWCVT_X_F_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_X_F_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFWCVT_F_XU_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_XU_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFWCVT_F_X_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_X_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFWCVT_F_F_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_F_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFNCVT_XU_F_W_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_XU_F_W, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFNCVT_X_F_W_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_X_F_W, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFNCVT_F_XU_W_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_XU_W, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFNCVT_F_X_W_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_X_W, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFNCVT_F_F_W_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_F_W, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFNCVT_ROD_F_F_W_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_ROD_F_F_W, VS2_FORMAT, ARITHMETIC, RVV); } // Vector reduction instruction - class riscv_VREDSUM_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREDSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VREDMAXU_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREDMAXU_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VREDMAX_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREDMAX_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VREDMINU_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREDMINU_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VREDMIN_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREDMIN_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VREDAND_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREDAND_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VREDOR_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREDOR_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VREDXOR_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VREDXOR_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VWREDSUMU_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWREDSUMU_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VWREDSUM_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VWREDSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VFREDOSUM_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFREDOSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VFREDSUM_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFREDSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VFREDMAX_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFREDMAX_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VFWREDOSUM_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWREDOSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VFWREDSUM_VS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFWREDSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VREDSUM_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREDSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VREDMAXU_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREDMAXU_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VREDMAX_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREDMAX_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VREDMINU_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREDMINU_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VREDMIN_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREDMIN_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VREDAND_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREDAND_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VREDOR_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREDOR_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VREDXOR_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VREDXOR_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VWREDSUMU_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWREDSUMU_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VWREDSUM_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VWREDSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VFREDOSUM_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFREDOSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VFREDSUM_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFREDSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VFREDMAX_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFREDMAX_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VFWREDOSUM_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWREDOSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VFWREDSUM_VS_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFWREDSUM_VS, VA_FORMAT, ARITHMETIC, RVV); } // Vector mask instruction - class riscv_VMAND_MM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMAND_MM, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VMNAND_MM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMNAND_MM, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VMANDNOT_MM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMANDNOT_MM, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VMXOR_MM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMXOR_MM, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VMOR_MM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMOR_MM, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VMNOR_MM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMNOR_MM, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VMORNOT_MM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMORNOT_MM, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VMXNOR_MM_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMXNOR_MM, VA_FORMAT, ARITHMETIC, RVV); } - - class riscv_VPOPC_M_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VPOPC_M, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VFIRST_M_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFIRST_M, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VMSBF_M_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSBF_M, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VMSIF_M_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSIF_M, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VMSOF_M_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMSOF_M, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VIOTA_M_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VIOTA_M, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VID_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VID_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VMAND_MM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMAND_MM, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VMNAND_MM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMNAND_MM, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VMANDNOT_MM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMANDNOT_MM, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VMXOR_MM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMXOR_MM, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VMOR_MM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMOR_MM, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VMNOR_MM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMNOR_MM, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VMORNOT_MM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMORNOT_MM, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VMXNOR_MM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMXNOR_MM, VA_FORMAT, ARITHMETIC, RVV); } + + class riscv_VPOPC_M_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VPOPC_M, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VFIRST_M_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFIRST_M, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VMSBF_M_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSBF_M, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VMSIF_M_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSIF_M, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VMSOF_M_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMSOF_M, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VIOTA_M_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VIOTA_M, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VID_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VID_V, VS2_FORMAT, ARITHMETIC, RVV); } // Vector permutation instruction - class riscv_VMV_X_S_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMV_X_S, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VMV_S_X_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMV_S_X, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VFMV_F_S_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMV_F_S, VA_FORMAT, ARITHMETIC, RVV); } - class riscv_VFMV_S_F_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VFMV_S_F, VA_FORMAT, ARITHMETIC, RVV); } - - class riscv_VSLIDEUP_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEUP, VA_FORMAT, ARITHMETIC, RVV, VI, VX); } - class riscv_VSLIDEDOWN_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEDOWN, VA_FORMAT, ARITHMETIC, RVV, VI, VX); } - class riscv_VSLIDE1UP_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1UP, VA_FORMAT, ARITHMETIC, RVV, VX); } - class riscv_VSLIDE1DOWN_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1DOWN, VA_FORMAT, ARITHMETIC, RVV, VX); } - class riscv_VRGATHER_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } - class riscv_VCOMPRESS_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VCOMPRESS, VA_FORMAT, ARITHMETIC, RVV, VM); } - - class riscv_VMV1R_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMV1R_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VMV2R_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMV2R_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VMV4R_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMV4R_V, VS2_FORMAT, ARITHMETIC, RVV); } - class riscv_VMV8R_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VMV8R_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VMV_X_S_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV_X_S, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VMV_S_X_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV_S_X, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VFMV_F_S_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMV_F_S, VA_FORMAT, ARITHMETIC, RVV); } + class riscv_VFMV_S_F_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VFMV_S_F, VA_FORMAT, ARITHMETIC, RVV); } + + + // class riscv_VSLIDEUP_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEUP, VA_FORMAT, ARITHMETIC, RVV, VI, VX); } + class riscv_VSLIDEUP_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEUP_VI, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDEUP + class riscv_VSLIDEUP_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEUP_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDEUP + // class riscv_VSLIDEDOWN_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEDOWN, VA_FORMAT, ARITHMETIC, RVV, VI, VX); } + class riscv_VSLIDEDOWN_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEDOWN_VI, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDEDOWN + class riscv_VSLIDEDOWN_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEDOWN_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDEDOWN + // class riscv_VSLIDE1UP_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1UP, VA_FORMAT, ARITHMETIC, RVV, VX); } + class riscv_VSLIDE1UP_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1UP_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDE1UP + // class riscv_VSLIDE1DOWN_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1DOWN, VA_FORMAT, ARITHMETIC, RVV, VX); } + class riscv_VSLIDE1DOWN_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1DOWN_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDE1DOWN + // class riscv_VRGATHER_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER, VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); } + class riscv_VRGATHER_VV_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER_VV, VA_FORMAT, ARITHMETIC, RVV); } // VRGATHER + class riscv_VRGATHER_VX_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER_VX, VA_FORMAT, ARITHMETIC, RVV); } // VRGATHER + class riscv_VRGATHER_VI_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER_VI, VA_FORMAT, ARITHMETIC, RVV); } // VRGATHER + // class riscv_VCOMPRESS_instr: riscv_vector_instr // { mixin RISCV_VA_INSTR_MIXIN!(VCOMPRESS, VA_FORMAT, ARITHMETIC, RVV, VM); } + class riscv_VCOMPRESS_VM_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VCOMPRESS_VM, VA_FORMAT, ARITHMETIC, RVV); } // VCOMPRESS + + class riscv_VMV1R_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV1R_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VMV2R_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV2R_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VMV4R_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV4R_V, VS2_FORMAT, ARITHMETIC, RVV); } + class riscv_VMV8R_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VMV8R_V, VS2_FORMAT, ARITHMETIC, RVV); } // ------------------------------------------------------------------------- // Section 7. Vector Loads and Stores // ------------------------------------------------------------------------- // Section 7.4 - Vector Unit-Stride Instructions - class riscv_VLE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VLE_V, VL_FORMAT, LOAD, RVV); } - class riscv_VSE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSE_V, VS_FORMAT, STORE, RVV); } + class riscv_VLE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VLE_V, VL_FORMAT, LOAD, RVV); } + class riscv_VSE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSE_V, VS_FORMAT, STORE, RVV); } // Section 7.5 - Vector Strided Instructions - class riscv_VLSE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VLSE_V, VLS_FORMAT, LOAD, RVV); } - class riscv_VSSE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSSE_V, VSS_FORMAT, STORE, RVV); } + class riscv_VLSE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VLSE_V, VLS_FORMAT, LOAD, RVV); } + class riscv_VSSE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSSE_V, VSS_FORMAT, STORE, RVV); } // Section 7.6 - Vector Indexed Instructions - class riscv_VLXEI_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VLXEI_V, VLX_FORMAT, LOAD, RVV); } - class riscv_VSXEI_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSXEI_V, VSX_FORMAT, STORE, RVV); } - class riscv_VSUXEI_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI_V, VSX_FORMAT, STORE, RVV); } + class riscv_VLXEI_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VLXEI_V, VLX_FORMAT, LOAD, RVV); } + class riscv_VSXEI_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSXEI_V, VSX_FORMAT, STORE, RVV); } + class riscv_VSUXEI_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI_V, VSX_FORMAT, STORE, RVV); } // Section 7.7 - Vector Unit-Stride Fault-Only-First Loads - class riscv_VLEFF_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!(VLEFF_V, VL_FORMAT, LOAD, RVV); } + class riscv_VLEFF_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!(VLEFF_V, VL_FORMAT, LOAD, RVV); } // Section 7.8 - Vector Load/Store Segment Instructions (Zvlsseg) // 7.8.1. Vector Unit Strided Segment Loads and Stores - class riscv_VLSEGE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSEGE_V, VL_FORMAT, LOAD, RVV); } - class riscv_VSSEGE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSSEGE_V, VS_FORMAT, STORE, RVV); } - class riscv_VLSEGEFF_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSEGEFF_V, VL_FORMAT, LOAD, RVV); } + class riscv_VLSEGE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSEGE_V, VL_FORMAT, LOAD, RVV); } + class riscv_VSSEGE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSSEGE_V, VS_FORMAT, STORE, RVV); } + class riscv_VLSEGEFF_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSEGEFF_V, VL_FORMAT, LOAD, RVV); } // 7.8.2. Vector Strided Segment Loads and Stores - class riscv_VLSSEGE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSSEGE_V, VLS_FORMAT, LOAD, RVV); } - class riscv_VSSSEGE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSSSEGE_V, VSS_FORMAT, STORE, RVV); } + class riscv_VLSSEGE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSSEGE_V, VLS_FORMAT, LOAD, RVV); } + class riscv_VSSSEGE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSSSEGE_V, VSS_FORMAT, STORE, RVV); } // 7.8.3. Vector Indexed Segment Loads and Stores - class riscv_VLXSEGEI_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLXSEGEI_V, VLX_FORMAT, LOAD, RVV); } - class riscv_VSXSEGEI_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSXSEGEI_V, VSX_FORMAT, STORE, RVV); } - class riscv_VSUXSEGEI_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSUXSEGEI_V, VSX_FORMAT, STORE, RVV); } + class riscv_VLXSEGEI_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLXSEGEI_V, VLX_FORMAT, LOAD, RVV); } + class riscv_VSXSEGEI_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSXSEGEI_V, VSX_FORMAT, STORE, RVV); } + class riscv_VSUXSEGEI_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSUXSEGEI_V, VSX_FORMAT, STORE, RVV); } // ------------------------------------------------------------------------- // Section 8. Vector AMO Operations (Zvamo) // ------------------------------------------------------------------------- // EEW vector AMOs - class riscv_VAMOSWAPE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOSWAPE_V, VAMO_FORMAT, AMO, RVV); } - class riscv_VAMOADDE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOADDE_V, VAMO_FORMAT, AMO, RVV); } - class riscv_VAMOXORE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOXORE_V, VAMO_FORMAT, AMO, RVV); } - class riscv_VAMOANDE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOANDE_V, VAMO_FORMAT, AMO, RVV); } - class riscv_VAMOORE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOORE_V, VAMO_FORMAT, AMO, RVV); } - class riscv_VAMOMINE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINE_V, VAMO_FORMAT, AMO, RVV); } - class riscv_VAMOMAXE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXE_V, VAMO_FORMAT, AMO, RVV); } - class riscv_VAMOMINUE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINUE_V, VAMO_FORMAT, AMO, RVV); } - class riscv_VAMOMAXUE_V_instr: riscv_vector_instr - { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXUE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOSWAPE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOSWAPE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOADDE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOADDE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOXORE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOXORE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOANDE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOANDE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOORE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOORE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOMINE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOMAXE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOMINUE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINUE_V, VAMO_FORMAT, AMO, RVV); } + class riscv_VAMOMAXUE_V_instr: riscv_vector_instr { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXUE_V, VAMO_FORMAT, AMO, RVV); } } diff --git a/euvm/riscv/gen/isa/rv64i_instr.d b/euvm/riscv/gen/isa/rv64i_instr.d index 525756d7..9ef0a06c 100644 --- a/euvm/riscv/gen/isa/rv64i_instr.d +++ b/euvm/riscv/gen/isa/rv64i_instr.d @@ -18,6 +18,7 @@ module riscv.gen.isa.rv64i_instr; import riscv.gen.riscv_defines; +import riscv.gen.isa.riscv_instr: riscv_instr; import uvm; diff --git a/euvm/riscv/gen/isa/rv64m_instr.d b/euvm/riscv/gen/isa/rv64m_instr.d index 7fd35a42..ffde1d54 100644 --- a/euvm/riscv/gen/isa/rv64m_instr.d +++ b/euvm/riscv/gen/isa/rv64m_instr.d @@ -18,6 +18,7 @@ module riscv.gen.isa.rv64m_instr; import riscv.gen.riscv_defines; +import riscv.gen.isa.riscv_instr: riscv_instr; import uvm; diff --git a/euvm/riscv/gen/riscv_defines.d b/euvm/riscv/gen/riscv_defines.d index ff78fffd..548e5981 100644 --- a/euvm/riscv/gen/riscv_defines.d +++ b/euvm/riscv/gen/riscv_defines.d @@ -183,8 +183,7 @@ class RISCV_VA_INSTR_TMPL(string ext, riscv_instr_name_t instr_n, mixin template RISCV_VA_INSTR_MIXIN(string ext, riscv_instr_name_t instr_n, riscv_instr_format_t instr_format, riscv_instr_category_t instr_category, - riscv_instr_group_t instr_group, - vav...) + riscv_instr_group_t instr_group) { enum riscv_instr_name_t RISCV_INSTR_NAME_T = instr_n; mixin uvm_object_utils; @@ -195,7 +194,7 @@ mixin template RISCV_VA_INSTR_MIXIN(string ext, riscv_instr_name_t instr_n, this.group = instr_group; this.category = instr_category; this.imm_type = imm_t.IMM; - this.allowed_va_variants = [vav]; + this.allowed_va_variants = []; this.sub_extension = ext; set_imm_len(); set_rand_mode(); @@ -205,8 +204,7 @@ mixin template RISCV_VA_INSTR_MIXIN(string ext, riscv_instr_name_t instr_n, mixin template RISCV_VA_INSTR_MIXIN(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format, riscv_instr_category_t instr_category, - riscv_instr_group_t instr_group, - vav...) + riscv_instr_group_t instr_group) { enum riscv_instr_name_t RISCV_INSTR_NAME_T = instr_n; mixin uvm_object_utils; @@ -217,7 +215,7 @@ mixin template RISCV_VA_INSTR_MIXIN(riscv_instr_name_t instr_n, this.group = instr_group; this.category = instr_category; this.imm_type = imm_t.IMM; - this.allowed_va_variants = [vav]; + this.allowed_va_variants = []; this.sub_extension = ""; set_imm_len(); set_rand_mode(); diff --git a/euvm/riscv/gen/riscv_instr_pkg.d b/euvm/riscv/gen/riscv_instr_pkg.d index a70f8f38..d428d56b 100644 --- a/euvm/riscv/gen/riscv_instr_pkg.d +++ b/euvm/riscv/gen/riscv_instr_pkg.d @@ -449,109 +449,330 @@ enum riscv_instr_name_t: ushort { // Vector instructions VSETVL, VSETVLI, - VADD, - VSUB, - VRSUB, - VWADDU, - VWSUBU, - VWADD, - VWSUB, - VADC, - VMADC, - VSBC, - VMSBC, - VAND, - VOR, - VXOR, - VSLL, - VSRL, - VSRA, - VNSRL, - VNSRA, - VMSEQ, - VMSNE, - VMSLTU, - VMSLT, - VMSLEU, - VMSLE, - VMSGTU, - VMSGT, - VMINU, - VMIN, - VMAXU, - VMAX, - VMUL, - VMULH, - VMULHU, - VMULHSU, - VDIVU, - VDIV, - VREMU, - VREM, - VWMUL, - VWMULU, - VWMULSU, - VMACC, - VNMSAC, - VMADD, - VNMSUB, - VWMACCU, - VWMACC, - VWMACCSU, - VWMACCUS, + VADD_VV, + VADD_VX, + VADD_VI, + // // // VADD, # # # + VSUB_VV, + VSUB_VX, + // // VSUB, # # + VRSUB_VX, + VRSUB_VI, + // // VRSUB, # # + VWADDU_VV, + VWADDU_VX, + VWADDU_WV, + VWADDU_WX, + // // // // VWADDU, # # # # + VWSUBU_VV, + VWSUBU_VX, + VWSUBU_WV, + VWSUBU_WX, + // // // // VWSUBU, # # # # + VWADD_VV, + VWADD_VX, + VWADD_WV, + VWADD_WX, + // // // // VWADD, # # # # + VWSUB_VV, + VWSUB_VX, + VWSUB_WV, + VWSUB_WX, + // // // // VWSUB, # # # # + VADC_VVM, + VADC_VXM, + VADC_VIM, + // // // VADC, # # # + VMADC_VVM, + VMADC_VXM, + VMADC_VIM, + VMADC_VV, + VMADC_VX, + VMADC_VI, + // // // // // // VMADC, # # # # # # + VSBC_VVM, + VSBC_VXM, + // // VSBC, # # + VMSBC_VVM, + VMSBC_VXM, + VMSBC_VV, + VMSBC_VX, + // // // // VMSBC, # # # # + VAND_VV, + VAND_VX, + VAND_VI, + // // // VAND, # # # + VOR_VV, + VOR_VX, + VOR_VI, + // // // VOR, # # # + VXOR_VV, + VXOR_VX, + VXOR_VI, + // // // VXOR, # # # + VSLL_VV, + VSLL_VX, + VSLL_VI, + // // // VSLL, # # # + VSRL_VV, + VSRL_VX, + VSRL_VI, + // // // VSRL, # # # + VSRA_VV, + VSRA_VX, + VSRA_VI, + // // // VSRA, # # # + VNSRL_WV, + VNSRL_WX, + VNSRL_WI, + // // // VNSRL, # # # + VNSRA_WV, + VNSRA_WX, + VNSRA_WI, + // // // VNSRA, # # # + VMSEQ_VV, + VMSEQ_VX, + VMSEQ_VI, + // // // VMSEQ, # # # + VMSNE_VV, + VMSNE_VX, + VMSNE_VI, + // // // VMSNE, # # # + VMSLTU_VV, + VMSLTU_VX, + // // VMSLTU, # # + VMSLT_VV, + VMSLT_VX, + // // VMSLT, # # + VMSLEU_VV, + VMSLEU_VX, + VMSLEU_VI, + // // // VMSLEU, # # # + VMSLE_VV, + VMSLE_VX, + VMSLE_VI, + // // // VMSLE, # # # + VMSGTU_VX, + VMSGTU_VI, + // // VMSGTU, # # + VMSGT_VX, + VMSGT_VI, + // // VMSGT, # # + VMINU_VV, + VMINU_VX, + // // VMINU, # # + VMIN_VV, + VMIN_VX, + // // VMIN, # # + VMAXU_VV, + VMAXU_VX, + // // VMAXU, # # + VMAX_VV, + VMAX_VX, + // // VMAX, # # + VMUL_VV, + VMUL_VX, + // // VMUL, # # + VMULH_VV, + VMULH_VX, + // // VMULH, # # + VMULHU_VV, + VMULHU_VX, + // // VMULHU, # # + VMULHSU_VV, + VMULHSU_VX, + // // VMULHSU, # # + VDIVU_VV, + VDIVU_VX, + // // VDIVU, # # + VDIV_VV, + VDIV_VX, + // // VDIV, # # + VREMU_VV, + VREMU_VX, + // // VREMU, # # + VREM_VV, + VREM_VX, + // // VREM, # # + VWMUL_VV, + VWMUL_VX, + // // VWMUL, # # + VWMULU_VV, + VWMULU_VX, + // // VWMULU, # # + VWMULSU_VV, + VWMULSU_VX, + // // VWMULSU, # # + VMACC_VV, + VMACC_VX, + // // VMACC, # # + VNMSAC_VV, + VNMSAC_VX, + // // VNMSAC, # # + VMADD_VV, + VMADD_VX, + // // VMADD, # # + VNMSUB_VV, + VNMSUB_VX, + // // VNMSUB, # # + VWMACCU_VV, + VWMACCU_VX, + // // VWMACCU, # # + VWMACC_VV, + VWMACC_VX, + // // VWMACC, # # + VWMACCSU_VV, + VWMACCSU_VX, + // // VWMACCSU, # # + VWMACCUS_VX, + // VWMACCUS, # //VQMACCU, //VQMACC, //VQMACCSU, //VQMACCUS, - VMERGE, - VMV, - VSADDU, - VSADD, - VSSUBU, - VSSUB, - VAADDU, - VAADD, - VASUBU, - VASUB, - VSSRL, - VSSRA, - VNCLIPU, - VNCLIP, + VMERGE_VVM, + VMERGE_VXM, + VMERGE_VIM, + // // // VMERGE, # # # + VMV_VV, + VMV_VX, + VMV_VI, + // // // VMV, # # # + VSADDU_VV, + VSADDU_VX, + VSADDU_VI, + // // // VSADDU, # # # + VSADD_VV, + VSADD_VX, + VSADD_VI, + // // // VSADD, # # # + VSSUBU_VV, + VSSUBU_VX, + // // VSSUBU, # # + VSSUB_VV, + VSSUB_VX, + // // VSSUB, # # + VAADDU_VV, + VAADDU_VX, + // // VAADDU, # # + VAADD_VV, + VAADD_VX, + // // VAADD, # # + VASUBU_VV, + VASUBU_VX, + // // VASUBU, # # + VASUB_VV, + VASUB_VX, + // // VASUB, # # + VSSRL_VV, + VSSRL_VX, + VSSRL_VI, + // // // VSSRL, # # # + VSSRA_VV, + VSSRA_VX, + VSSRA_VI, + // // // VSSRA, # # # + VNCLIPU_WV, + VNCLIPU_WX, + VNCLIPU_WI, + // // // VNCLIPU, # # # + VNCLIP_WV, + VNCLIP_WX, + VNCLIP_WI, + // // // VNCLIP, # # # // 14. Vector Floating-Point Instructions - VFADD, - VFSUB, - VFRSUB, - VFMUL, - VFDIV, - VFRDIV, - VFWMUL, - VFMACC, - VFNMACC, - VFMSAC, - VFNMSAC, - VFMADD, - VFNMADD, - VFMSUB, - VFNMSUB, - VFWMACC, - VFWNMACC, - VFWMSAC, - VFWNMSAC, + VFADD_VV, + VFADD_VF, + // // VFADD, # # + VFSUB_VV, + VFSUB_VF, + // // VFSUB, # # + VFRSUB_VF, + // VFRSUB, # + VFMUL_VV, + VFMUL_VF, + // // VFMUL, # # + VFDIV_VV, + VFDIV_VF, + // // VFDIV, # # + VFRDIV_VF, + // VFRDIV, # + VFWMUL_VV, + VFWMUL_VF, + // // VFWMUL, # # + VFMACC_VV, + VFMACC_VF, + // // VFMACC, # # + VFNMACC_VV, + VFNMACC_VF, + // // VFNMACC, # # + VFMSAC_VV, + VFMSAC_VF, + // // VFMSAC, # # + VFNMSAC_VV, + VFNMSAC_VF, + // // VFNMSAC, # # + VFMADD_VV, + VFMADD_VF, + // // VFMADD, # # + VFNMADD_VV, + VFNMADD_VF, + // // VFNMADD, # # + VFMSUB_VV, + VFMSUB_VF, + // // VFMSUB, # # + VFNMSUB_VV, + VFNMSUB_VF, + // // VFNMSUB, # # + VFWMACC_VV, + VFWMACC_VF, + // // VFWMACC, # # + VFWNMACC_VV, + VFWNMACC_VF, + // // VFWNMACC, # # + VFWMSAC_VV, + VFWMSAC_VF, + // // VFWMSAC, # # + VFWNMSAC_VV, + VFWNMSAC_VF, + // // VFWNMSAC, # # VFSQRT_V, - VFMIN, - VFMAX, - VFSGNJ, - VFSGNJN, - VFSGNJX, - VMFEQ, - VMFNE, - VMFLT, - VMFLE, - VMFGT, - VMFGE, + VFMIN_VV, + VFMIN_VF, + // // VFMIN, # # + VFMAX_VV, + VFMAX_VF, + // // VFMAX, # # + VFSGNJ_VV, + VFSGNJ_VF, + // // VFSGNJ, # # + VFSGNJN_VV, + VFSGNJN_VF, + // // VFSGNJN, # # + VFSGNJX_VV, + VFSGNJX_VF, + // // VFSGNJX, # # + VMFEQ_VV, + VMFEQ_VF, + // // VMFEQ, # # + VMFNE_VV, + VMFNE_VF, + // // VMFNE, # # + VMFLT_VV, + VMFLT_VF, + // // VMFLT, # # + VMFLE_VV, + VMFLE_VF, + // // VMFLE, # # + VMFGT_VF, + // VMFGT, # + VMFGE_VF, + // VMFGE, # VFCLASS_V, - VFMERGE, - VFMV, + VFMERGE_VFM, + // VFMERGE, # + VFMV_VF, + // VFMV, # VFCVT_XU_F_V, VFCVT_X_F_V, VFCVT_F_XU_V, @@ -604,12 +825,22 @@ enum riscv_instr_name_t: ushort { VMV_S_X, VFMV_F_S, VFMV_S_F, - VSLIDEUP, - VSLIDEDOWN, - VSLIDE1UP, - VSLIDE1DOWN, - VRGATHER, - VCOMPRESS, + VSLIDEUP_VI, + VSLIDEUP_VX, + // // VSLIDEUP, # # + VSLIDEDOWN_VI, + VSLIDEDOWN_VX, + // // VSLIDEDOWN, # # + VSLIDE1UP_VX, + // VSLIDE1UP, # + VSLIDE1DOWN_VX, + // VSLIDE1DOWN, # + VRGATHER_VV, + VRGATHER_VX, + VRGATHER_VI, + // // // VRGATHER, # # # + VCOMPRESS_VM, + // VCOMPRESS, # VMV1R_V, VMV2R_V, VMV4R_V, @@ -656,6 +887,352 @@ enum riscv_instr_name_t: ushort { INVALID_INSTR } + +enum va_base_instr: byte { + VADD, + VSUB, + VRSUB, + VWADDU, + VWSUBU, + VWADD, + VWSUB, + VADC, + VMADC, + VSBC, + VMSBC, + VAND, + VOR, + VXOR, + VSLL, + VSRL, + VSRA, + VNSRL, + VNSRA, + VMSEQ, + VMSNE, + VMSLTU, + VMSLT, + VMSLEU, + VMSLE, + VMSGTU, + VMSGT, + VMINU, + VMIN, + VMAXU, + VMAX, + VMUL, + VMULH, + VMULHU, + VMULHSU, + VDIVU, + VDIV, + VREMU, + VREM, + VWMUL, + VWMULU, + VWMULSU, + VMACC, + VNMSAC, + VMADD, + VNMSUB, + VWMACCU, + VWMACC, + VWMACCSU, + VWMACCUS, + VMERGE, + VMV, + VSADDU, + VSADD, + VSSUBU, + VSSUB, + VAADDU, + VAADD, + VASUBU, + VASUB, + VSSRL, + VSSRA, + VNCLIPU, + VNCLIP, + VFADD, + VFSUB, + VFRSUB, + VFMUL, + VFDIV, + VFRDIV, + VFWMUL, + VFMACC, + VFNMACC, + VFMSAC, + VFNMSAC, + VFMADD, + VFNMADD, + VFMSUB, + VFNMSUB, + VFWMACC, + VFWNMACC, + VFWMSAC, + VFWNMSAC, + VFMIN, + VFMAX, + VFSGNJ, + VFSGNJN, + VFSGNJX, + VMFEQ, + VMFNE, + VMFLT, + VMFLE, + VMFGT, + VMFGE, + VFMERGE, + VFMV, + VSLIDEUP, + VSLIDEDOWN, + VSLIDE1UP, + VSLIDE1DOWN, + VRGATHER, + VCOMPRESS, + // Not every Vector Instruction has a base + VA_NO_BASE +} + +va_base_instr va_get_base(riscv_instr_name_t INSTR) { + switch (INSTR) { + case riscv_instr_name_t.VADD_VV: return va_base_instr.VADD; + case riscv_instr_name_t.VADD_VX: return va_base_instr.VADD; + case riscv_instr_name_t.VADD_VI: return va_base_instr.VADD; + case riscv_instr_name_t.VSUB_VV: return va_base_instr.VSUB; + case riscv_instr_name_t.VSUB_VX: return va_base_instr.VSUB; + case riscv_instr_name_t.VRSUB_VX: return va_base_instr.VRSUB; + case riscv_instr_name_t.VRSUB_VI: return va_base_instr.VRSUB; + case riscv_instr_name_t.VWADDU_VV: return va_base_instr.VWADDU; + case riscv_instr_name_t.VWADDU_VX: return va_base_instr.VWADDU; + case riscv_instr_name_t.VWADDU_WV: return va_base_instr.VWADDU; + case riscv_instr_name_t.VWADDU_WX: return va_base_instr.VWADDU; + case riscv_instr_name_t.VWSUBU_VV: return va_base_instr.VWSUBU; + case riscv_instr_name_t.VWSUBU_VX: return va_base_instr.VWSUBU; + case riscv_instr_name_t.VWSUBU_WV: return va_base_instr.VWSUBU; + case riscv_instr_name_t.VWSUBU_WX: return va_base_instr.VWSUBU; + case riscv_instr_name_t.VWADD_VV: return va_base_instr.VWADD; + case riscv_instr_name_t.VWADD_VX: return va_base_instr.VWADD; + case riscv_instr_name_t.VWADD_WV: return va_base_instr.VWADD; + case riscv_instr_name_t.VWADD_WX: return va_base_instr.VWADD; + case riscv_instr_name_t.VWSUB_VV: return va_base_instr.VWSUB; + case riscv_instr_name_t.VWSUB_VX: return va_base_instr.VWSUB; + case riscv_instr_name_t.VWSUB_WV: return va_base_instr.VWSUB; + case riscv_instr_name_t.VWSUB_WX: return va_base_instr.VWSUB; + case riscv_instr_name_t.VADC_VVM: return va_base_instr.VADC; + case riscv_instr_name_t.VADC_VXM: return va_base_instr.VADC; + case riscv_instr_name_t.VADC_VIM: return va_base_instr.VADC; + case riscv_instr_name_t.VMADC_VVM: return va_base_instr.VMADC; + case riscv_instr_name_t.VMADC_VXM: return va_base_instr.VMADC; + case riscv_instr_name_t.VMADC_VIM: return va_base_instr.VMADC; + case riscv_instr_name_t.VMADC_VV: return va_base_instr.VMADC; + case riscv_instr_name_t.VMADC_VX: return va_base_instr.VMADC; + case riscv_instr_name_t.VMADC_VI: return va_base_instr.VMADC; + case riscv_instr_name_t.VSBC_VVM: return va_base_instr.VSBC; + case riscv_instr_name_t.VSBC_VXM: return va_base_instr.VSBC; + case riscv_instr_name_t.VMSBC_VVM: return va_base_instr.VMSBC; + case riscv_instr_name_t.VMSBC_VXM: return va_base_instr.VMSBC; + case riscv_instr_name_t.VMSBC_VV: return va_base_instr.VMSBC; + case riscv_instr_name_t.VMSBC_VX: return va_base_instr.VMSBC; + case riscv_instr_name_t.VAND_VV: return va_base_instr.VAND; + case riscv_instr_name_t.VAND_VX: return va_base_instr.VAND; + case riscv_instr_name_t.VAND_VI: return va_base_instr.VAND; + case riscv_instr_name_t.VOR_VV: return va_base_instr.VOR; + case riscv_instr_name_t.VOR_VX: return va_base_instr.VOR; + case riscv_instr_name_t.VOR_VI: return va_base_instr.VOR; + case riscv_instr_name_t.VXOR_VV: return va_base_instr.VXOR; + case riscv_instr_name_t.VXOR_VX: return va_base_instr.VXOR; + case riscv_instr_name_t.VXOR_VI: return va_base_instr.VXOR; + case riscv_instr_name_t.VSLL_VV: return va_base_instr.VSLL; + case riscv_instr_name_t.VSLL_VX: return va_base_instr.VSLL; + case riscv_instr_name_t.VSLL_VI: return va_base_instr.VSLL; + case riscv_instr_name_t.VSRL_VV: return va_base_instr.VSRL; + case riscv_instr_name_t.VSRL_VX: return va_base_instr.VSRL; + case riscv_instr_name_t.VSRL_VI: return va_base_instr.VSRL; + case riscv_instr_name_t.VSRA_VV: return va_base_instr.VSRA; + case riscv_instr_name_t.VSRA_VX: return va_base_instr.VSRA; + case riscv_instr_name_t.VSRA_VI: return va_base_instr.VSRA; + case riscv_instr_name_t.VNSRL_WV: return va_base_instr.VNSRL; + case riscv_instr_name_t.VNSRL_WX: return va_base_instr.VNSRL; + case riscv_instr_name_t.VNSRL_WI: return va_base_instr.VNSRL; + case riscv_instr_name_t.VNSRA_WV: return va_base_instr.VNSRA; + case riscv_instr_name_t.VNSRA_WX: return va_base_instr.VNSRA; + case riscv_instr_name_t.VNSRA_WI: return va_base_instr.VNSRA; + case riscv_instr_name_t.VMSEQ_VV: return va_base_instr.VMSEQ; + case riscv_instr_name_t.VMSEQ_VX: return va_base_instr.VMSEQ; + case riscv_instr_name_t.VMSEQ_VI: return va_base_instr.VMSEQ; + case riscv_instr_name_t.VMSNE_VV: return va_base_instr.VMSNE; + case riscv_instr_name_t.VMSNE_VX: return va_base_instr.VMSNE; + case riscv_instr_name_t.VMSNE_VI: return va_base_instr.VMSNE; + case riscv_instr_name_t.VMSLTU_VV: return va_base_instr.VMSLTU; + case riscv_instr_name_t.VMSLTU_VX: return va_base_instr.VMSLTU; + case riscv_instr_name_t.VMSLT_VV: return va_base_instr.VMSLT; + case riscv_instr_name_t.VMSLT_VX: return va_base_instr.VMSLT; + case riscv_instr_name_t.VMSLEU_VV: return va_base_instr.VMSLEU; + case riscv_instr_name_t.VMSLEU_VX: return va_base_instr.VMSLEU; + case riscv_instr_name_t.VMSLEU_VI: return va_base_instr.VMSLEU; + case riscv_instr_name_t.VMSLE_VV: return va_base_instr.VMSLE; + case riscv_instr_name_t.VMSLE_VX: return va_base_instr.VMSLE; + case riscv_instr_name_t.VMSLE_VI: return va_base_instr.VMSLE; + case riscv_instr_name_t.VMSGTU_VX: return va_base_instr.VMSGTU; + case riscv_instr_name_t.VMSGTU_VI: return va_base_instr.VMSGTU; + case riscv_instr_name_t.VMSGT_VX: return va_base_instr.VMSGT; + case riscv_instr_name_t.VMSGT_VI: return va_base_instr.VMSGT; + case riscv_instr_name_t.VMINU_VV: return va_base_instr.VMINU; + case riscv_instr_name_t.VMINU_VX: return va_base_instr.VMINU; + case riscv_instr_name_t.VMIN_VV: return va_base_instr.VMIN; + case riscv_instr_name_t.VMIN_VX: return va_base_instr.VMIN; + case riscv_instr_name_t.VMAXU_VV: return va_base_instr.VMAXU; + case riscv_instr_name_t.VMAXU_VX: return va_base_instr.VMAXU; + case riscv_instr_name_t.VMAX_VV: return va_base_instr.VMAX; + case riscv_instr_name_t.VMAX_VX: return va_base_instr.VMAX; + case riscv_instr_name_t.VMUL_VV: return va_base_instr.VMUL; + case riscv_instr_name_t.VMUL_VX: return va_base_instr.VMUL; + case riscv_instr_name_t.VMULH_VV: return va_base_instr.VMULH; + case riscv_instr_name_t.VMULH_VX: return va_base_instr.VMULH; + case riscv_instr_name_t.VMULHU_VV: return va_base_instr.VMULHU; + case riscv_instr_name_t.VMULHU_VX: return va_base_instr.VMULHU; + case riscv_instr_name_t.VMULHSU_VV: return va_base_instr.VMULHSU; + case riscv_instr_name_t.VMULHSU_VX: return va_base_instr.VMULHSU; + case riscv_instr_name_t.VDIVU_VV: return va_base_instr.VDIVU; + case riscv_instr_name_t.VDIVU_VX: return va_base_instr.VDIVU; + case riscv_instr_name_t.VDIV_VV: return va_base_instr.VDIV; + case riscv_instr_name_t.VDIV_VX: return va_base_instr.VDIV; + case riscv_instr_name_t.VREMU_VV: return va_base_instr.VREMU; + case riscv_instr_name_t.VREMU_VX: return va_base_instr.VREMU; + case riscv_instr_name_t.VREM_VV: return va_base_instr.VREM; + case riscv_instr_name_t.VREM_VX: return va_base_instr.VREM; + case riscv_instr_name_t.VWMUL_VV: return va_base_instr.VWMUL; + case riscv_instr_name_t.VWMUL_VX: return va_base_instr.VWMUL; + case riscv_instr_name_t.VWMULU_VV: return va_base_instr.VWMULU; + case riscv_instr_name_t.VWMULU_VX: return va_base_instr.VWMULU; + case riscv_instr_name_t.VWMULSU_VV: return va_base_instr.VWMULSU; + case riscv_instr_name_t.VWMULSU_VX: return va_base_instr.VWMULSU; + case riscv_instr_name_t.VMACC_VV: return va_base_instr.VMACC; + case riscv_instr_name_t.VMACC_VX: return va_base_instr.VMACC; + case riscv_instr_name_t.VNMSAC_VV: return va_base_instr.VNMSAC; + case riscv_instr_name_t.VNMSAC_VX: return va_base_instr.VNMSAC; + case riscv_instr_name_t.VMADD_VV: return va_base_instr.VMADD; + case riscv_instr_name_t.VMADD_VX: return va_base_instr.VMADD; + case riscv_instr_name_t.VNMSUB_VV: return va_base_instr.VNMSUB; + case riscv_instr_name_t.VNMSUB_VX: return va_base_instr.VNMSUB; + case riscv_instr_name_t.VWMACCU_VV: return va_base_instr.VWMACCU; + case riscv_instr_name_t.VWMACCU_VX: return va_base_instr.VWMACCU; + case riscv_instr_name_t.VWMACC_VV: return va_base_instr.VWMACC; + case riscv_instr_name_t.VWMACC_VX: return va_base_instr.VWMACC; + case riscv_instr_name_t.VWMACCSU_VV: return va_base_instr.VWMACCSU; + case riscv_instr_name_t.VWMACCSU_VX: return va_base_instr.VWMACCSU; + case riscv_instr_name_t.VWMACCUS_VX: return va_base_instr.VWMACCUS; + case riscv_instr_name_t.VMERGE_VVM: return va_base_instr.VMERGE; + case riscv_instr_name_t.VMERGE_VXM: return va_base_instr.VMERGE; + case riscv_instr_name_t.VMERGE_VIM: return va_base_instr.VMERGE; + case riscv_instr_name_t.VMV_VV: return va_base_instr.VMV; + case riscv_instr_name_t.VMV_VX: return va_base_instr.VMV; + case riscv_instr_name_t.VMV_VI: return va_base_instr.VMV; + case riscv_instr_name_t.VSADDU_VV: return va_base_instr.VSADDU; + case riscv_instr_name_t.VSADDU_VX: return va_base_instr.VSADDU; + case riscv_instr_name_t.VSADDU_VI: return va_base_instr.VSADDU; + case riscv_instr_name_t.VSADD_VV: return va_base_instr.VSADD; + case riscv_instr_name_t.VSADD_VX: return va_base_instr.VSADD; + case riscv_instr_name_t.VSADD_VI: return va_base_instr.VSADD; + case riscv_instr_name_t.VSSUBU_VV: return va_base_instr.VSSUBU; + case riscv_instr_name_t.VSSUBU_VX: return va_base_instr.VSSUBU; + case riscv_instr_name_t.VSSUB_VV: return va_base_instr.VSSUB; + case riscv_instr_name_t.VSSUB_VX: return va_base_instr.VSSUB; + case riscv_instr_name_t.VAADDU_VV: return va_base_instr.VAADDU; + case riscv_instr_name_t.VAADDU_VX: return va_base_instr.VAADDU; + case riscv_instr_name_t.VAADD_VV: return va_base_instr.VAADD; + case riscv_instr_name_t.VAADD_VX: return va_base_instr.VAADD; + case riscv_instr_name_t.VASUBU_VV: return va_base_instr.VASUBU; + case riscv_instr_name_t.VASUBU_VX: return va_base_instr.VASUBU; + case riscv_instr_name_t.VASUB_VV: return va_base_instr.VASUB; + case riscv_instr_name_t.VASUB_VX: return va_base_instr.VASUB; + case riscv_instr_name_t.VSSRL_VV: return va_base_instr.VSSRL; + case riscv_instr_name_t.VSSRL_VX: return va_base_instr.VSSRL; + case riscv_instr_name_t.VSSRL_VI: return va_base_instr.VSSRL; + case riscv_instr_name_t.VSSRA_VV: return va_base_instr.VSSRA; + case riscv_instr_name_t.VSSRA_VX: return va_base_instr.VSSRA; + case riscv_instr_name_t.VSSRA_VI: return va_base_instr.VSSRA; + case riscv_instr_name_t.VNCLIPU_WV: return va_base_instr.VNCLIPU; + case riscv_instr_name_t.VNCLIPU_WX: return va_base_instr.VNCLIPU; + case riscv_instr_name_t.VNCLIPU_WI: return va_base_instr.VNCLIPU; + case riscv_instr_name_t.VNCLIP_WV: return va_base_instr.VNCLIP; + case riscv_instr_name_t.VNCLIP_WX: return va_base_instr.VNCLIP; + case riscv_instr_name_t.VNCLIP_WI: return va_base_instr.VNCLIP; + case riscv_instr_name_t.VFADD_VV: return va_base_instr.VFADD; + case riscv_instr_name_t.VFADD_VF: return va_base_instr.VFADD; + case riscv_instr_name_t.VFSUB_VV: return va_base_instr.VFSUB; + case riscv_instr_name_t.VFSUB_VF: return va_base_instr.VFSUB; + case riscv_instr_name_t.VFRSUB_VF: return va_base_instr.VFRSUB; + case riscv_instr_name_t.VFMUL_VV: return va_base_instr.VFMUL; + case riscv_instr_name_t.VFMUL_VF: return va_base_instr.VFMUL; + case riscv_instr_name_t.VFDIV_VV: return va_base_instr.VFDIV; + case riscv_instr_name_t.VFDIV_VF: return va_base_instr.VFDIV; + case riscv_instr_name_t.VFRDIV_VF: return va_base_instr.VFRDIV; + case riscv_instr_name_t.VFWMUL_VV: return va_base_instr.VFWMUL; + case riscv_instr_name_t.VFWMUL_VF: return va_base_instr.VFWMUL; + case riscv_instr_name_t.VFMACC_VV: return va_base_instr.VFMACC; + case riscv_instr_name_t.VFMACC_VF: return va_base_instr.VFMACC; + case riscv_instr_name_t.VFNMACC_VV: return va_base_instr.VFNMACC; + case riscv_instr_name_t.VFNMACC_VF: return va_base_instr.VFNMACC; + case riscv_instr_name_t.VFMSAC_VV: return va_base_instr.VFMSAC; + case riscv_instr_name_t.VFMSAC_VF: return va_base_instr.VFMSAC; + case riscv_instr_name_t.VFNMSAC_VV: return va_base_instr.VFNMSAC; + case riscv_instr_name_t.VFNMSAC_VF: return va_base_instr.VFNMSAC; + case riscv_instr_name_t.VFMADD_VV: return va_base_instr.VFMADD; + case riscv_instr_name_t.VFMADD_VF: return va_base_instr.VFMADD; + case riscv_instr_name_t.VFNMADD_VV: return va_base_instr.VFNMADD; + case riscv_instr_name_t.VFNMADD_VF: return va_base_instr.VFNMADD; + case riscv_instr_name_t.VFMSUB_VV: return va_base_instr.VFMSUB; + case riscv_instr_name_t.VFMSUB_VF: return va_base_instr.VFMSUB; + case riscv_instr_name_t.VFNMSUB_VV: return va_base_instr.VFNMSUB; + case riscv_instr_name_t.VFNMSUB_VF: return va_base_instr.VFNMSUB; + case riscv_instr_name_t.VFWMACC_VV: return va_base_instr.VFWMACC; + case riscv_instr_name_t.VFWMACC_VF: return va_base_instr.VFWMACC; + case riscv_instr_name_t.VFWNMACC_VV: return va_base_instr.VFWNMACC; + case riscv_instr_name_t.VFWNMACC_VF: return va_base_instr.VFWNMACC; + case riscv_instr_name_t.VFWMSAC_VV: return va_base_instr.VFWMSAC; + case riscv_instr_name_t.VFWMSAC_VF: return va_base_instr.VFWMSAC; + case riscv_instr_name_t.VFWNMSAC_VV: return va_base_instr.VFWNMSAC; + case riscv_instr_name_t.VFWNMSAC_VF: return va_base_instr.VFWNMSAC; + case riscv_instr_name_t.VFMIN_VV: return va_base_instr.VFMIN; + case riscv_instr_name_t.VFMIN_VF: return va_base_instr.VFMIN; + case riscv_instr_name_t.VFMAX_VV: return va_base_instr.VFMAX; + case riscv_instr_name_t.VFMAX_VF: return va_base_instr.VFMAX; + case riscv_instr_name_t.VFSGNJ_VV: return va_base_instr.VFSGNJ; + case riscv_instr_name_t.VFSGNJ_VF: return va_base_instr.VFSGNJ; + case riscv_instr_name_t.VFSGNJN_VV: return va_base_instr.VFSGNJN; + case riscv_instr_name_t.VFSGNJN_VF: return va_base_instr.VFSGNJN; + case riscv_instr_name_t.VFSGNJX_VV: return va_base_instr.VFSGNJX; + case riscv_instr_name_t.VFSGNJX_VF: return va_base_instr.VFSGNJX; + case riscv_instr_name_t.VMFEQ_VV: return va_base_instr.VMFEQ; + case riscv_instr_name_t.VMFEQ_VF: return va_base_instr.VMFEQ; + case riscv_instr_name_t.VMFNE_VV: return va_base_instr.VMFNE; + case riscv_instr_name_t.VMFNE_VF: return va_base_instr.VMFNE; + case riscv_instr_name_t.VMFLT_VV: return va_base_instr.VMFLT; + case riscv_instr_name_t.VMFLT_VF: return va_base_instr.VMFLT; + case riscv_instr_name_t.VMFLE_VV: return va_base_instr.VMFLE; + case riscv_instr_name_t.VMFLE_VF: return va_base_instr.VMFLE; + case riscv_instr_name_t.VMFGT_VF: return va_base_instr.VMFGT; + case riscv_instr_name_t.VMFGE_VF: return va_base_instr.VMFGE; + case riscv_instr_name_t.VFMERGE_VFM: return va_base_instr.VFMERGE; + case riscv_instr_name_t.VFMV_VF: return va_base_instr.VFMV; + case riscv_instr_name_t.VSLIDEUP_VI: return va_base_instr.VSLIDEUP; + case riscv_instr_name_t.VSLIDEUP_VX: return va_base_instr.VSLIDEUP; + case riscv_instr_name_t.VSLIDEDOWN_VI: return va_base_instr.VSLIDEDOWN; + case riscv_instr_name_t.VSLIDEDOWN_VX: return va_base_instr.VSLIDEDOWN; + case riscv_instr_name_t.VSLIDE1UP_VX: return va_base_instr.VSLIDE1UP; + case riscv_instr_name_t.VSLIDE1DOWN_VX: return va_base_instr.VSLIDE1DOWN; + case riscv_instr_name_t.VRGATHER_VV: return va_base_instr.VRGATHER; + case riscv_instr_name_t.VRGATHER_VX: return va_base_instr.VRGATHER; + case riscv_instr_name_t.VRGATHER_VI: return va_base_instr.VRGATHER; + case riscv_instr_name_t.VCOMPRESS_VM: return va_base_instr.VCOMPRESS; + default: return va_base_instr.VA_NO_BASE; + } +} + + // Maximum virtual address bits used by the program enum uint MAX_USED_VADDR_BITS = 30; @@ -802,19 +1379,20 @@ enum riscv_instr_format_t: ubyte { // 6'b // Vector arithmetic instruction variant enum va_variant_t: ubvec!4 { - VV = UBVEC!(4, 0), - VI = UBVEC!(4, 1), - VX = UBVEC!(4, 2), - VF = UBVEC!(4, 3), - WV = UBVEC!(4, 4), - WI = UBVEC!(4, 5), - WX = UBVEC!(4, 6), - VVM = UBVEC!(4, 7), - VIM = UBVEC!(4, 8), - VXM = UBVEC!(4, 9), - VFM = UBVEC!(4, 10), - VS = UBVEC!(4, 11), - VM = UBVEC!(4, 12) + VV = UBVEC!(4, 0), + VI = UBVEC!(4, 1), + VX = UBVEC!(4, 2), + VF = UBVEC!(4, 3), + WV = UBVEC!(4, 4), + WI = UBVEC!(4, 5), + WX = UBVEC!(4, 6), + VVM = UBVEC!(4, 7), + VIM = UBVEC!(4, 8), + VXM = UBVEC!(4, 9), + VFM = UBVEC!(4, 10), + VS = UBVEC!(4, 11), + VM = UBVEC!(4, 12), + NONE = UBVEC!(4, 13) } enum riscv_instr_category_t: ubyte { // 6'b @@ -1669,3 +2247,4 @@ void get_val(string str, out bvec!XLEN val, bool hex = 0) { uvm_info("riscv_instr_pkg", format("imm:%0s -> 0x%0x/%0d", str, val, cast(bvec!XLEN) val), UVM_FULL); } + diff --git a/euvm/riscv/gen/riscv_instr_stream.d b/euvm/riscv/gen/riscv_instr_stream.d index a7842827..8c5eeaf6 100644 --- a/euvm/riscv/gen/riscv_instr_stream.d +++ b/euvm/riscv/gen/riscv_instr_stream.d @@ -418,11 +418,11 @@ class riscv_rand_instr_stream: riscv_instr_stream void add_init_vector_gpr_instr(riscv_vreg_t gpr, ubvec!XLEN val) { riscv_vector_instr instr - = cast(riscv_vector_instr) cfg.instr_registry.get_instr(riscv_instr_name_t.VMV); + = cast(riscv_vector_instr) cfg.instr_registry.get_instr(riscv_instr_name_t.VMV_VX); instr.m_cfg = cfg; instr.avoid_reserved_vregs_c.constraint_mode(false); instr.randomize_with! q{ - va_variant == va_variant_t.VX; + // va_variant == va_variant_t.VX; vd == $0; rs1 == $1; } (gpr, cfg.gpr[0]);