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Main.par
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Release 14.2 par P.28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
CHAITANYA:: Sun Aug 27 18:22:04 2017
par -w -intstyle ise -ol high -mt off Main_map.ncd Main.ncd Main.pcf
Constraints file: Main.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.2\ISE_DS\ISE\.
"Main" is an NCD, version 3.2, device xc6slx9, package csg324, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.22 2012-07-09".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 145 out of 11,440 1%
Number used as Flip Flops: 145
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 192 out of 5,720 3%
Number used as logic: 174 out of 5,720 3%
Number using O6 output only: 130
Number using O5 output only: 31
Number using O5 and O6: 13
Number used as ROM: 0
Number used as Memory: 1 out of 1,440 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 1
Number using O6 output only: 1
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 17
Number with same-slice register load: 2
Number with same-slice carry load: 3
Number with other load: 12
Slice Logic Distribution:
Number of occupied Slices: 80 out of 1,430 5%
Nummber of MUXCYs used: 84 out of 2,860 2%
Number of LUT Flip Flop pairs used: 223
Number with an unused Flip Flop: 86 out of 223 38%
Number with an unused LUT: 31 out of 223 13%
Number of fully used LUT-FF pairs: 106 out of 223 47%
Number of slice register sites lost
to control set restrictions: 0 out of 11,440 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 33 out of 200 16%
Number of LOCed IOBs: 32 out of 33 96%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 2 out of 16 12%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 4 secs
Finished initial Timing Analysis. REAL time: 4 secs
Starting Router
Phase 1 : 1003 unrouted; REAL time: 5 secs
Phase 2 : 673 unrouted; REAL time: 5 secs
Phase 3 : 166 unrouted; REAL time: 6 secs
Phase 4 : 166 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Updating file: Main.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Total REAL time to Router completion: 7 secs
Total CPU time to Router completion: 6 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| CLK_BUFGP | BUFGMUX_X3Y13| No | 49 | 0.095 | 1.163 |
+---------------------+--------------+------+------+------------+-------------+
| XLXI_49/XLXI_42/rst | Local| | 8 | 0.659 | 1.510 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
NET "CLK_BUFGP/IBUFG" PERIOD = 10 ns HIGH | SETUP | 3.560ns| 6.440ns| 0| 0
50% | HOLD | 0.416ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 8 secs
Total CPU time to PAR completion: 7 secs
Peak Memory Usage: 342 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
Writing design to file Main.ncd
PAR done!