[ARM-semantic] Implement carry flag for basic shifters

[W0ni]

Modified instructions:

• ASRS, LSLS, LSRS, RORS, RRXS
• MOVS, MVNS with shifter

For the shift and rotate instructions, the carry flag could be implemented similarly to x86, using another block to handle the zero shift case.

See: https://developer.arm.com/documentation/ddi0597/2023-06/Base-Instructions/MOV--MOVS--register---Move--register--?lang=en

[serpilliere]

Hi @W0ni
Maybe I have missed something, but it seems the flags are present and modified for those instructions:
in miasm/arch/arm/sem.py:

def rors(ir, instr, a, b):
    e = []
    r = ExprOp(">>>", a, b)
    e.append(ExprAssign(a, r))

    e += [ExprAssign(zf, ExprOp('FLAG_EQ', r))]
    e += update_flag_nf(r)

    dst = get_dst(a)
    if dst is not None:
        e.append(ExprAssign(ir.IRDst, r))
    return e, []
...

def asrs(ir, instr, a, b, c=None):
    e = []
    if c is None:
        b, c = a, b
    r = ExprOp("a>>", b, c)
    e.append(ExprAssign(a, r))

    e += [ExprAssign(zf, ExprOp('FLAG_EQ', r))]
    e += update_flag_nf(r)

    dst = get_dst(a)
    if dst is not None:
        e.append(ExprAssign(ir.IRDst, r))
    return e, []
...

[W0ni]

Hey @serpilliere !

Indeed, the N and Z flags are correctly modified by this code. However, these instructions should also modify the C flag according to this documentation: https://developer.arm.com/documentation/ddi0597/2023-06/Base-Instructions/MOV--MOVS--register---Move--register--?lang=en

If the shift is 0, the carry flag is not affected. If it's not 0, a new block is required to compute the carry flag.