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arm64: cmeq too many immediate operands #1629

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ekilmer opened this issue May 8, 2020 · 1 comment · Fixed by #2026
Closed

arm64: cmeq too many immediate operands #1629

ekilmer opened this issue May 8, 2020 · 1 comment · Fixed by #2026

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@ekilmer
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ekilmer commented May 8, 2020

On next branch (f7efa08), there are too many IMM operands:

./cstool -d arm64 '\x20\x98\xe0\x5e'
 0  20 98 e0 5e  cmeq   d0, d1, #0
        ID: 97 (cmeq)
        op_count: 4
                operands[0].type: REG = d0
                operands[0].access: WRITE
                operands[1].type: REG = d1
                operands[1].access: READ
                operands[2].type: IMM = 0x0
                operands[3].type: IMM = 0x0
        Registers read: d1
        Registers modified: d0
        Groups: neon

From v4.0.1

cstool -d arm64 '\x20\x98\xe0\x5e'
 0  20 98 e0 5e  cmeq   d0, d1, #0
        op_count: 3
                operands[0].type: REG = d0
                operands[0].access: WRITE
                operands[1].type: REG = d1
                operands[1].access: READ
                operands[2].type: IMM = 0x0
        Registers read: d1
        Registers modified: d0
        Groups: neon
@ekilmer
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ekilmer commented May 10, 2020

I think this is where the problem is https://github.com/aquynh/capstone/blob/1766485c0c32419e9a17d6ad31f9e218ef4f018f/arch/AArch64/AArch64GenAsmWriter.inc#L11036-L11039

That file says not to edit directly, but I'm not sure how op_addImm(MI, 0); got in there? It doesn't appear in the entry above it https://github.com/aquynh/capstone/blob/1766485c0c32419e9a17d6ad31f9e218ef4f018f/arch/AArch64/AArch64GenAsmWriter.inc#L11029-L11032 or any of the other entries close to it in the file.

Removing op_addImm(MI, 0); works for me.

From LLVM-10 disassembler:

$ echo "0x20 0x98 0xe0 0x5e" | llvm-mc --disassemble --show-encoding --show-inst-operands --show-inst --arch=aarch64
        .text
        cmeq    d0, d1, #0              // encoding: [0x20,0x98,0xe0,0x5e]
                                        // <MCInst #556 CMEQv1i64rz
                                        //  <MCOperand Reg:41>
                                        //  <MCOperand Reg:42>>

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