From 51bd0f85533df668047219e9f52e80a4fc6f99ce Mon Sep 17 00:00:00 2001 From: Afonso Bordado Date: Thu, 31 Aug 2023 17:36:56 +0100 Subject: [PATCH] riscv64: Strenghten pattern matching when emitting Load's --- cranelift/codegen/src/isa/riscv64/inst/emit.rs | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs index 4bd293a8fad3..063d5a9b2cb4 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs @@ -626,7 +626,10 @@ impl MachInstEmit for Inst { // If the offset fits into an imm12 we can directly encode it. (Some(base), Some(imm12), _) => (base, imm12), - (_, _, Some(label)) => { + // If the amode contains a label we can emit an internal relocation to it. + (None, Some(imm), Some(label)) => { + debug_assert_eq!(imm.as_i16(), 0); + // Get the current PC. sink.use_label_at_offset(sink.cur_offset(), label, LabelUse::PCRelHi20); Inst::Auipc { @@ -643,11 +646,13 @@ impl MachInstEmit for Inst { } // Otherwise load the address it into a reg and load from it. - _ => { + (_, _, None) => { let tmp = writable_spilltmp_reg(); Inst::LoadAddr { rd: tmp, mem: from }.emit(&[], sink, emit_info, state); (tmp.to_reg(), Imm12::zero()) } + + _ => unreachable!("Invalid load address"), }; let srcloc = state.cur_srcloc();