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SyncInSyncOut currently crucially depends on the last FPGA in the demo rig to be the last FPGA to have its HITL VIO start probe asserted. This prevents us from implementing parallel test start assertion.
TODO
Amend SyncInSyncOut
Check whether there are any other tests that depend on this
Remove ordering (add scrambling?) from test infrastructure
SyncInSyncOut
currently crucially depends on the last FPGA in the demo rig to be the last FPGA to have its HITL VIO start probe asserted. This prevents us from implementing parallel test start assertion.TODO
SyncInSyncOut
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