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Basic support for bluepill board with at86rf233 radio
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The bluepill board[1] is a tiny arduino-like developer board
that is equipped with a powerful STM32F103 MCU. The chip
is officially an STM32F103C8T6 model that in fact appears
to have 128 KiB flash (cf. [2]). Thus it is recommended to
use the patched stlink[3] to flash the firmware.

[1] http://wiki.stm32duino.com/index.php?title=Blue_Pill
[2] stlink-org/stlink#305
[3] https://github.com/cabo/stlink
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obgm authored and nmeum committed Dec 16, 2016
1 parent 93f405d commit 0a09042
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3 changes: 3 additions & 0 deletions boards/bluepill/Makefile
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MODULE = board

include $(RIOTBASE)/Makefile.base
13 changes: 13 additions & 0 deletions boards/bluepill/Makefile.features
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

# Various other features (if any)
FEATURES_PROVIDED += cpp

# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m3_2
20 changes: 20 additions & 0 deletions boards/bluepill/Makefile.include
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## the cpu to build for
export CPU = stm32f1
export CPU_MODEL = stm32f103cb

# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

# setup serial terminal
include $(RIOTBOARD)/Makefile.include.serial

# st-flash
export FLASHER = st-flash
export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh
export DEBUGSERVER = st-util

# define st-flash parameters
export OFLAGS = -O binary
export FFLAGS = write bin/$(BOARD)/$(APPLICATION).hex 0x8000000
export DEBUGGER_FLAGS = $(RIOTBOARD)/$(BOARD)/dist/gdb.conf $(BINDIR)/$(APPLICATION).elf
32 changes: 32 additions & 0 deletions boards/bluepill/board.c
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/*
* Copyright (C) 2015 TriaGnoSys GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/

/**
* @ingroup boards_nucleo-f103
* @{
*
* @file
* @brief Board specific implementations for the nucleo-f103 board
*
* @author Víctor Ariño <[email protected]>
*
* @}
*/

#include "cpu.h"
#include "board.h"
#include "periph/gpio.h"

void board_init(void)
{
/* initialize the CPU */
cpu_init();

/* initialize the boards LEDs */
gpio_init(LED0_PIN, GPIO_OUT);
}
4 changes: 4 additions & 0 deletions boards/bluepill/dist/debug.sh
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#!/bin/sh

echo "Debugging $1"
arm-none-eabi-gdb -tui -command=$1 $2
1 change: 1 addition & 0 deletions boards/bluepill/dist/gdb.conf
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tar extended-remote :4242
2 changes: 2 additions & 0 deletions boards/bluepill/dist/openocd.cfg
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source [find interface/stlink-v2.cfg]
source [find board/stm3210b_eval.cfg]
94 changes: 94 additions & 0 deletions boards/bluepill/include/board.h
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/*
* Copyright (C) 2015 TriaGnoSys GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/

/**
* @defgroup boards_nucleo-f103 Nucleo-F103
* @ingroup boards
* @brief Board specific files for the nucleo-f103 board
* @{
*
* @file
* @brief Board specific definitions for the nucleo-f103 board
*
* @author Víctor Ariño <[email protected]>
*/

#ifndef BOARD_H_
#define BOARD_H_

#include "periph_conf.h"
#include "periph/spi.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
* @brief LED pin definitions and handlers
* @{
*/
#define LED0_PIN GPIO_PIN(PORT_C , 13)

#define LED0_MASK (1 << 13)

#if defined(CPU_FAM_STM32F4)
#define LED_CREG BSRRH
#else
#define LED_CREG BRR
#endif
#if defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
#define LED_SREG BSRRL
#else
#define LED_SREG BSRR
#endif

#define LED0_ON (GPIOC->LED_SREG = LED0_MASK)
#define LED0_OFF (GPIOC->LED_CREG = LED0_MASK)
#define LED0_TOGGLE (GPIOC->ODR ^= LED0_MASK)
/** @} */

/**
* @brief SPI definitions for Openlabs board
* @{
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
.cs_pin = GPIO_PIN(PORT_A, 4), \
.int_pin = GPIO_PIN(PORT_B, 0), \
.sleep_pin = GPIO_PIN(PORT_B, 1), \
.reset_pin = GPIO_PIN(PORT_A, 3)}
/** @} */

/**
* @brief User button
*/
#define BTN_B1_PIN GPIO_PIN(PORT_C, 13)

/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);

/**
* @brief Use the 2nd UART for STDIO on this board
*/
#define UART_STDIO_DEV UART_DEV(1)

/**
* @name xtimer configuration
*/
#define XTIMER_WIDTH (16)
#define XTIMER_BACKOFF 5
/** @} */

#ifdef __cplusplus
}
#endif

#endif /* BOARD_H_ */
/** @} */
203 changes: 203 additions & 0 deletions boards/bluepill/include/periph_conf.h
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/*
* Copyright (C) 2015 TriaGnoSys GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/

/**
* @ingroup boards_nucleo-f103
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo-f103 board
*
* @author Víctor Ariño <[email protected]>
*/

#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_

#include "periph_cpu.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
* @name Clock system configuration
* @{
*/
#define CLOCK_HSE (8000000U) /* external oscillator */
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */

/* the actual PLL values are automatically generated */
#define CLOCK_PLL_DIV (1)
#define CLOCK_PLL_MUL (9)

/* AHB, APB1, APB2 dividers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36 MHz (!) */

/* resulting bus clocks */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2 (CLOCK_CORECLOCK)

/* Flash latency */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2 /* for >= 72 MHz */
/** @} */

/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */

/**
* @brief DAC configuration
* @{
*/
#define DAC_NUMOF (0)
/** @} */

/**
* @brief Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
},
{
.dev = TIM3,
.rcc_mask = RCC_APB1ENR_TIM3EN,
.bus = APB1,
.irqn = TIM3_IRQn
}
};

#define TIMER_0_ISR isr_tim2
#define TIMER_1_ISR isr_tim3

#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */

/**
* @brief UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rcc_pin = RCC_APB1ENR_USART2EN,
.bus = APB1,
.irqn = USART2_IRQn
},
{
.dev = USART1,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rcc_pin = RCC_APB2ENR_USART1EN,
.bus = APB2,
.irqn = USART1_IRQn
},
{
.dev = USART3,
.rx_pin = GPIO_PIN(PORT_B, 11),
.tx_pin = GPIO_PIN(PORT_B, 10),
.rcc_pin = RCC_APB1ENR_USART3EN,
.bus = APB1,
.irqn = USART3_IRQn
}
};

#define UART_0_ISR isr_usart2
#define UART_1_ISR isr_usart1
#define UART_2_ISR isr_usart3

#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */

/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (2U)
#define I2C_0_EN 1
#define I2C_1_EN 0
#define I2C_IRQ_PRIO 1
#define I2C_APBCLK (36000000U)

/* I2C 0 device configuration */
#define I2C_0_DEV I2C1
#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define I2C_0_EVT_IRQ I2C1_EV_IRQn
#define I2C_0_EVT_ISR isr_i2c1_ev
#define I2C_0_ERR_IRQ I2C1_ER_IRQn
#define I2C_0_ERR_ISR isr_i2c1_er
/* I2C 0 pin configuration */
#define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 8) /* remapped */
#define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 9) /* remapped */

/* I2C 1 device configuration */
#define I2C_1_DEV I2C2
#define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
#define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define I2C_1_EVT_IRQ I2C2_EV_IRQn
#define I2C_1_EVT_ISR isr_i2c2_ev
#define I2C_1_ERR_IRQ I2C2_ER_IRQn
#define I2C_1_ERR_ISR isr_i2c2_er
/* I2C 1 pin configuration */
#define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10)
#define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11)
/** @} */

/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 0
#define SPI_IRQ_PRIO 1

/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
#define SPI_0_BUS_DIV 1

/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_A, 5)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_A, 6)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A, 7)

/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_IRQ_HANDLER isr_spi2
#define SPI_1_BUS_DIV 1
/* SPI 1 pin configuration */
#define SPI_1_CLK_PIN GPIO_PIN(PORT_B, 13)
#define SPI_1_MISO_PIN GPIO_PIN(PORT_B, 14)
#define SPI_1_MOSI_PIN GPIO_PIN(PORT_B, 15)
/** @} */

#ifdef __cplusplus
}
#endif

#endif /* PERIPH_CONF_H_ */

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