From 8f4fd25a6849db8315f7da0a183d72eeac5f9909 Mon Sep 17 00:00:00 2001 From: Ted Pudlik Date: Tue, 28 Feb 2023 17:02:22 -0800 Subject: [PATCH] Add RISC-V extension constraints --- cpu/BUILD | 14 + cpu/riscv/extensions/BUILD | 972 +++++++++++++++++++++++++++++ cpu/riscv/extensions/shorthand.bzl | 21 + 3 files changed, 1007 insertions(+) create mode 100644 cpu/riscv/extensions/BUILD create mode 100644 cpu/riscv/extensions/shorthand.bzl diff --git a/cpu/BUILD b/cpu/BUILD index 50e462b..43bd1bb 100644 --- a/cpu/BUILD +++ b/cpu/BUILD @@ -153,12 +153,26 @@ constraint_value( constraint_setting = ":cpu", ) +# Base integer instruction set, 32-bit. constraint_value( name = "riscv32", constraint_setting = ":cpu", ) +# Base integer instruction set, 32-bit, 16 registers. +constraint_value( + name = "riscv32e", + constraint_setting = ":cpu", +) + +# Base integer instruction set, 64-bit. constraint_value( name = "riscv64", constraint_setting = ":cpu", ) + +# Base integer instruction set, 64-bit, 16 registers. +constraint_value( + name = "riscv64e", + constraint_setting = ":cpu", +) diff --git a/cpu/riscv/extensions/BUILD b/cpu/riscv/extensions/BUILD new file mode 100644 index 0000000..15cff4d --- /dev/null +++ b/cpu/riscv/extensions/BUILD @@ -0,0 +1,972 @@ +# Constraint settings describing RISC-V extensions. +licenses(["notice"]) + +package( + default_visibility = ["//visibility:public"], +) + +# Does the CPU possess extension M (multiplication and division)? +constraint_setting( + name = "M_setting", + default_constraint_value = ":no_M", +) + +# CPU does possess the M extension +constraint_value( + name = "M", + constraint_setting = "M_setting", +) + +# CPU does not possess the M extension +constraint_value( + name = "no_M", + constraint_setting = "M_setting", +) + +# Does the CPU possess extension A (atomic instructions)? +constraint_setting( + name = "A_setting", + default_constraint_value = ":no_A", +) + +# CPU does possess the A extension +constraint_value( + name = "A", + constraint_setting = "A_setting", +) + +# CPU does not possess the A extension +constraint_value( + name = "no_A", + constraint_setting = "A_setting", +) + +# Does the CPU possess extension F (single-precision floating point)? +constraint_setting( + name = "F_setting", + default_constraint_value = ":no_F", +) + +# CPU does possess the F extension +constraint_value( + name = "F", + constraint_setting = "F_setting", +) + +# CPU does not possess the F extension +constraint_value( + name = "no_F", + constraint_setting = "F_setting", +) + +# Does the CPU possess extension D (double-precision floating point)? +constraint_setting( + name = "D_setting", + default_constraint_value = ":no_D", +) + +# CPU does possess the D extension +constraint_value( + name = "D", + constraint_setting = "D_setting", +) + +# CPU does not possess the D extension +constraint_value( + name = "no_D", + constraint_setting = "D_setting", +) + +# Does the CPU possess extension Zicsr (Control and Status Register)? +constraint_setting( + name = "Zicsr_setting", + default_constraint_value = ":no_Zicsr", +) + +# CPU does possess the Zicsr extension +constraint_value( + name = "Zicsr", + constraint_setting = "Zicsr_setting", +) + +# CPU does not possess the Zicsr extension +constraint_value( + name = "no_Zicsr", + constraint_setting = "Zicsr_setting", +) + +# Does the CPU possess extension Zifencei (Control and Status Register)? +constraint_setting( + name = "Zifencei_setting", + default_constraint_value = ":no_Zifencei", +) + +# CPU does possess the Zifencei extension +constraint_value( + name = "Zifencei", + constraint_setting = "Zifencei_setting", +) + +# CPU does not possess the Zifencei extension +constraint_value( + name = "no_Zifencei", + constraint_setting = "Zifencei_setting", +) + +# Does the CPU possess extension Q (quad precision floating point)? +constraint_setting( + name = "Q_setting", + default_constraint_value = ":no_Q", +) + +# CPU does possess the Q extension +constraint_value( + name = "Q", + constraint_setting = "Q_setting", +) + +# CPU does not possess the Q extension +constraint_value( + name = "no_Q", + constraint_setting = "Q_setting", +) + +# Does the CPU possess extension C (compressed instructions)? +constraint_setting( + name = "C_setting", + default_constraint_value = ":no_C", +) + +# CPU does possess the C extension +constraint_value( + name = "C", + constraint_setting = "C_setting", +) + +# CPU does not possess the C extension +constraint_value( + name = "no_C", + constraint_setting = "C_setting", +) + +# Does the CPU possess extension Zba (bit manipulation a)? +constraint_setting( + name = "Zba_setting", + default_constraint_value = ":no_Zba", +) + +# CPU does possess the B extension +constraint_value( + name = "Zba", + constraint_setting = "Zba_setting", +) + +# CPU does not possess the B extension +constraint_value( + name = "no_Zba", + constraint_setting = "Zba_setting", +) + +# Does the CPU possess extension Zbb (bit manipulation b)? +constraint_setting( + name = "Zbb_setting", + default_constraint_value = ":no_Zbb", +) + +# CPU does possess the B extension +constraint_value( + name = "Zbb", + constraint_setting = "Zbb_setting", +) + +# CPU does not possess the B extension +constraint_value( + name = "no_Zbb", + constraint_setting = "Zbb_setting", +) + +# Does the CPU possess extension Zbc (bit manipulation c)? +constraint_setting( + name = "Zbc_setting", + default_constraint_value = ":no_Zbc", +) + +# CPU does possess the B extension +constraint_value( + name = "Zbc", + constraint_setting = "Zbc_setting", +) + +# CPU does not possess the B extension +constraint_value( + name = "no_Zbc", + constraint_setting = "Zbc_setting", +) + +# Does the CPU possess extension Zbc (bit manipulation s)? +constraint_setting( + name = "Zbs_setting", + default_constraint_value = ":no_Zbs", +) + +# CPU does possess the B extension +constraint_value( + name = "Zbs", + constraint_setting = "Zbs_setting", +) + +# CPU does not possess the B extension +constraint_value( + name = "no_Zbs", + constraint_setting = "Zbs_setting", +) + +# Does the CPU possess extension V (vector operations)? +constraint_setting( + name = "V_setting", + default_constraint_value = ":no_V", +) + +# CPU does possess the V extension +constraint_value( + name = "V", + constraint_setting = "V_setting", +) + +# CPU does not possess the V extension +constraint_value( + name = "no_V", + constraint_setting = "V_setting", +) + +# Does the CPU possess extension Zvl32b? +constraint_setting( + name = "Zvl32b_setting", + default_constraint_value = ":no_Zvl32b", +) + +# CPU does possess the Zvl32b extension +constraint_value( + name = "Zvl32b", + constraint_setting = "Zvl32b_setting", +) + +# CPU does not possess the Zvl32b extension +constraint_value( + name = "no_Zvl32b", + constraint_setting = "Zvl32b_setting", +) + + +# Does the CPU possess extension Zvl64b? +constraint_setting( + name = "Zvl64b_setting", + default_constraint_value = ":no_Zvl64b", +) + +# CPU does possess the Zvl64b extension +constraint_value( + name = "Zvl64b", + constraint_setting = "Zvl64b_setting", +) + +# CPU does not possess the Zvl64b extension +constraint_value( + name = "no_Zvl64b", + constraint_setting = "Zvl64b_setting", +) + + +# Does the CPU possess extension Zvl128b? +constraint_setting( + name = "Zvl128b_setting", + default_constraint_value = ":no_Zvl128b", +) + +# CPU does possess the Zvl128b extension +constraint_value( + name = "Zvl128b", + constraint_setting = "Zvl128b_setting", +) + +# CPU does not possess the Zvl128b extension +constraint_value( + name = "no_Zvl128b", + constraint_setting = "Zvl128b_setting", +) + + +# Does the CPU possess extension Zvl256b? +constraint_setting( + name = "Zvl256b_setting", + default_constraint_value = ":no_Zvl256b", +) + +# CPU does possess the Zvl256b extension +constraint_value( + name = "Zvl256b", + constraint_setting = "Zvl256b_setting", +) + +# CPU does not possess the Zvl256b extension +constraint_value( + name = "no_Zvl256b", + constraint_setting = "Zvl256b_setting", +) + + +# Does the CPU possess extension Zvl512b? +constraint_setting( + name = "Zvl512b_setting", + default_constraint_value = ":no_Zvl512b", +) + +# CPU does possess the Zvl512b extension +constraint_value( + name = "Zvl512b", + constraint_setting = "Zvl512b_setting", +) + +# CPU does not possess the Zvl512b extension +constraint_value( + name = "no_Zvl512b", + constraint_setting = "Zvl512b_setting", +) + + +# Does the CPU possess extension Zvl1024b? +constraint_setting( + name = "Zvl1024b_setting", + default_constraint_value = ":no_Zvl1024b", +) + +# CPU does possess the Zvl1024b extension +constraint_value( + name = "Zvl1024b", + constraint_setting = "Zvl1024b_setting", +) + +# CPU does not possess the Zvl1024b extension +constraint_value( + name = "no_Zvl1024b", + constraint_setting = "Zvl1024b_setting", +) + + +# Does the CPU possess extension Zve32x? +constraint_setting( + name = "Zve32x_setting", + default_constraint_value = ":no_Zve32x", +) + +# CPU does possess the Zve32x extension +constraint_value( + name = "Zve32x", + constraint_setting = "Zve32x_setting", +) + +# CPU does not possess the Zve32x extension +constraint_value( + name = "no_Zve32x", + constraint_setting = "Zve32x_setting", +) + + +# Does the CPU possess extension Zve32f? +constraint_setting( + name = "Zve32f_setting", + default_constraint_value = ":no_Zve32f", +) + +# CPU does possess the Zve32f extension +constraint_value( + name = "Zve32f", + constraint_setting = "Zve32f_setting", +) + +# CPU does not possess the Zve32f extension +constraint_value( + name = "no_Zve32f", + constraint_setting = "Zve32f_setting", +) + + +# Does the CPU possess extension Zve64x? +constraint_setting( + name = "Zve64x_setting", + default_constraint_value = ":no_Zve64x", +) + +# CPU does possess the Zve64x extension +constraint_value( + name = "Zve64x", + constraint_setting = "Zve64x_setting", +) + +# CPU does not possess the Zve64x extension +constraint_value( + name = "no_Zve64x", + constraint_setting = "Zve64x_setting", +) + + +# Does the CPU possess extension Zve64f? +constraint_setting( + name = "Zve64f_setting", + default_constraint_value = ":no_Zve64f", +) + +# CPU does possess the Zve64f extension +constraint_value( + name = "Zve64f", + constraint_setting = "Zve64f_setting", +) + +# CPU does not possess the Zve64f extension +constraint_value( + name = "no_Zve64f", + constraint_setting = "Zve64f_setting", +) + + +# Does the CPU possess extension Zve64d? +constraint_setting( + name = "Zve64d_setting", + default_constraint_value = ":no_Zve64d", +) + +# CPU does possess the Zve64d extension +constraint_value( + name = "Zve64d", + constraint_setting = "Zve64d_setting", +) + +# CPU does not possess the Zve64d extension +constraint_value( + name = "no_Zve64d", + constraint_setting = "Zve64d_setting", +) + + +# Does the CPU possess extension Zbkb (bitmanip instructions for cryptography)? +constraint_setting( + name = "Zbkb_setting", + default_constraint_value = ":no_Zbkb", +) + +# CPU does possess the Zbkb extension +constraint_value( + name = "Zbkb", + constraint_setting = "Zbkb_setting", +) + +# CPU does not possess the Zbkb extension +constraint_value( + name = "no_Zbkb", + constraint_setting = "Zbkb_setting", +) + +# Does the CPU possess extension Zbkc (carry-less multiply instructions)? +constraint_setting( + name = "Zbkc_setting", + default_constraint_value = ":no_Zbkc", +) + +# CPU does possess the Zbkc extension +constraint_value( + name = "Zbkc", + constraint_setting = "Zbkc_setting", +) + +# CPU does not possess the Zbkc extension +constraint_value( + name = "no_Zbkc", + constraint_setting = "Zbkc_setting", +) + +# Does the CPU possess extension Zbkx (crossbar permutation instructions)? +constraint_setting( + name = "Zbkx_setting", + default_constraint_value = ":no_Zbkx", +) + +# CPU does possess the Zbkx extension +constraint_value( + name = "Zbkx", + constraint_setting = "Zbkx_setting", +) + +# CPU does not possess the Zbkx extension +constraint_value( + name = "no_Zbkx", + constraint_setting = "Zbkx_setting", +) + +# Does the CPU possess extension Zknd (NIST suite: AES decryption)? +constraint_setting( + name = "Zknd_setting", + default_constraint_value = ":no_Zknd", +) + +# CPU does possess the Zknd extension +constraint_value( + name = "Zknd", + constraint_setting = "Zknd_setting", +) + +# CPU does not possess the Zknd extension +constraint_value( + name = "no_Zknd", + constraint_setting = "Zknd_setting", +) + +# Does the CPU possess extension Zkne (NIST suite: AES encryption)? +constraint_setting( + name = "Zkne_setting", + default_constraint_value = ":no_Zkne", +) + +# CPU does possess the Zkne extension +constraint_value( + name = "Zkne", + constraint_setting = "Zkne_setting", +) + +# CPU does not possess the Zkne extension +constraint_value( + name = "no_Zkne", + constraint_setting = "Zkne_setting", +) + +# Does the CPU possess extension Zknh (NIST suite: hash function instructions)? +constraint_setting( + name = "Zknh_setting", + default_constraint_value = ":no_Zknh", +) + +# CPU does possess the Zknh extension +constraint_value( + name = "Zknh", + constraint_setting = "Zknh_setting", +) + +# CPU does not possess the Zknh extension +constraint_value( + name = "no_Zknh", + constraint_setting = "Zknh_setting", +) + +# Does the CPU possess extension Zksed (ShangMi suite: SM4 block cipher instructions)? +constraint_setting( + name = "Zksed_setting", + default_constraint_value = ":no_Zksed", +) + +# CPU does possess the Zksed extension +constraint_value( + name = "Zksed", + constraint_setting = "Zksed_setting", +) + +# CPU does not possess the Zksed extension +constraint_value( + name = "no_Zksed", + constraint_setting = "Zksed_setting", +) + +# Does the CPU possess extension Zksh (ShangMi suite: SM3 hash function instructions)? +constraint_setting( + name = "Zksh_setting", + default_constraint_value = ":no_Zksh", +) + +# CPU does possess the Zksh extension +constraint_value( + name = "Zksh", + constraint_setting = "Zksh_setting", +) + +# CPU does not possess the Zksh extension +constraint_value( + name = "no_Zksh", + constraint_setting = "Zksh_setting", +) + +# Does the CPU possess extension Zkr (entropy source extension)? +constraint_setting( + name = "Zkr_setting", + default_constraint_value = ":no_Zkr", +) + +# CPU does possess the Zkr extension +constraint_value( + name = "Zkr", + constraint_setting = "Zkr_setting", +) + +# CPU does not possess the Zkr extension +constraint_value( + name = "no_Zkr", + constraint_setting = "Zkr_setting", +) + +# Does the CPU possess extension Zkt (data independent execution latency)? +constraint_setting( + name = "Zkt_setting", + default_constraint_value = ":no_Zkt", +) + +# CPU does possess the Zkt extension +constraint_value( + name = "Zkt", + constraint_setting = "Zkt_setting", +) + +# CPU does not possess the Zkt extension +constraint_value( + name = "no_Zkt", + constraint_setting = "Zkt_setting", +) + +# Does the CPU possess extension H (hypervisor)? +constraint_setting( + name = "H_setting", + default_constraint_value = ":no_H", +) + +# CPU does possess the H extension +constraint_value( + name = "H", + constraint_setting = "H_setting", +) + +# CPU does not possess the H extension +constraint_value( + name = "no_H", + constraint_setting = "H_setting", +) + +# Does the CPU possess extension S (supervisor-level instructions)? +constraint_setting( + name = "S_setting", + default_constraint_value = ":no_S", +) + +# CPU does possess the S extension +constraint_value( + name = "S", + constraint_setting = "S_setting", +) + +# CPU does not possess the S extension +constraint_value( + name = "no_S", + constraint_setting = "S_setting", +) + +# Does the CPU possess extension Zmmul? +constraint_setting( + name = "Zmmul_setting", + default_constraint_value = ":no_Zmmul", +) + +# CPU does possess the Zmmul extension +constraint_value( + name = "Zmmul", + constraint_setting = "Zmmul_setting", +) + +# CPU does not possess the Zmmul extension +constraint_value( + name = "no_Zmmul", + constraint_setting = "Zmmul_setting", +) + +# Does the CPU possess extension Ztso (total store ordering)? +constraint_setting( + name = "Ztso_setting", + default_constraint_value = ":no_Ztso", +) + +# CPU does possess the Ztso extension +constraint_value( + name = "Ztso", + constraint_setting = "Ztso_setting", +) + +# CPU does not possess the Ztso extension +constraint_value( + name = "no_Ztso", + constraint_setting = "Ztso_setting", +) + +# Does the CPU possess extension Zawrs (wait-on-reservation-set)? +constraint_setting( + name = "Zawrs_setting", + default_constraint_value = ":no_Zawrs", +) + +# CPU does possess the Zawrs extension +constraint_value( + name = "Zawrs", + constraint_setting = "Zawrs_setting", +) + +# CPU does not possess the Zawrs extension +constraint_value( + name = "no_Zawrs", + constraint_setting = "Zawrs_setting", +) + +# Does the CPU possess extension Smepmp? +constraint_setting( + name = "Smepmp_setting", + default_constraint_value = ":no_Smepmp", +) + +# CPU does possess the Smepmp extension +constraint_value( + name = "Smepmp", + constraint_setting = "Smepmp_setting", +) + +# CPU does not possess the Smepmp extension +constraint_value( + name = "no_Smepmp", + constraint_setting = "Smepmp_setting", +) + +# Does the CPU possess extension Zicbom? +constraint_setting( + name = "Zicbom_setting", + default_constraint_value = ":no_Zicbom", +) + +# CPU does possess the Zicbom extension +constraint_value( + name = "Zicbom", + constraint_setting = "Zicbom_setting", +) + +# CPU does not possess the Zicbom extension +constraint_value( + name = "no_Zicbom", + constraint_setting = "Zicbom_setting", +) + +# Does the CPU possess extension Zicbop? +constraint_setting( + name = "Zicbop_setting", + default_constraint_value = ":no_Zicbop", +) + +# CPU does possess the Zicbop extension +constraint_value( + name = "Zicbop", + constraint_setting = "Zicbop_setting", +) + +# CPU does not possess the Zicbop extension +constraint_value( + name = "no_Zicbop", + constraint_setting = "Zicbop_setting", +) + +# Does the CPU possess extension Zicboz? +constraint_setting( + name = "Zicboz_setting", + default_constraint_value = ":no_Zicboz", +) + +# CPU does possess the Zicboz extension +constraint_value( + name = "Zicboz", + constraint_setting = "Zicboz_setting", +) + +# CPU does not possess the Zicboz extension +constraint_value( + name = "no_Zicboz", + constraint_setting = "Zicboz_setting", +) + +# Does the CPU possess extension Sscofmpf (count overflow and mode-based +# filtering)? +constraint_setting( + name = "Sscofmpf_setting", + default_constraint_value = ":no_Sscofmpf", +) + +# CPU does possess the Sscofmpf extension +constraint_value( + name = "Sscofmpf", + constraint_setting = "Sscofmpf_setting", +) + +# CPU does not possess the Sscofmpf extension +constraint_value( + name = "no_Sscofmpf", + constraint_setting = "Sscofmpf_setting", +) + +# Does the CPU possess extension Smstateen (state enable)? +constraint_setting( + name = "Smstateen_setting", + default_constraint_value = ":no_Smstateen", +) + +# CPU does possess the Smstateen extension +constraint_value( + name = "Smstateen", + constraint_setting = "Smstateen_setting", +) + +# CPU does not possess the Smstateen extension +constraint_value( + name = "no_Smstateen", + constraint_setting = "Smstateen_setting", +) + +# Does the CPU possess extension Sstc (stimecmp/vstimecmp)? +constraint_setting( + name = "Sstc_setting", + default_constraint_value = ":no_Sstc", +) + +# CPU does possess the Sstc extension +constraint_value( + name = "Sstc", + constraint_setting = "Sstc_setting", +) + +# CPU does not possess the Sstc extension +constraint_value( + name = "no_Sstc", + constraint_setting = "Sstc_setting", +) + +# Does the CPU possess extension Zfh (half-precision floating point)? +constraint_setting( + name = "Zfh_setting", + default_constraint_value = ":no_Zfh", +) + +# CPU does possess the Zfh extension +constraint_value( + name = "Zfh", + constraint_setting = "Zfh_setting", +) + +# CPU does not possess the Zfh extension +constraint_value( + name = "no_Zfh", + constraint_setting = "Zfh_setting", +) + +# Does the CPU possess extension Zfhmin (minimal half-precision floating point)? +constraint_setting( + name = "Zfhmin_setting", + default_constraint_value = ":no_Zfhmin", +) + +# CPU does possess the Zfhmin extension +constraint_value( + name = "Zfhmin", + constraint_setting = "Zfhmin_setting", +) + +# CPU does not possess the Zfhmin extension +constraint_value( + name = "no_Zfhmin", + constraint_setting = "Zfhmin_setting", +) + +# Does the CPU possess extension Zfinx? +constraint_setting( + name = "Zfinx_setting", + default_constraint_value = ":no_Zfinx", +) + +# CPU does possess the Zfinx extension +constraint_value( + name = "Zfinx", + constraint_setting = "Zfinx_setting", +) + +# CPU does not possess the Zfinx extension +constraint_value( + name = "no_Zfinx", + constraint_setting = "Zfinx_setting", +) + +# Does the CPU possess extension Zdinx? +constraint_setting( + name = "Zdinx_setting", + default_constraint_value = ":no_Zdinx", +) + +# CPU does possess the Zdinx extension +constraint_value( + name = "Zdinx", + constraint_setting = "Zdinx_setting", +) + +# CPU does not possess the Zdinx extension +constraint_value( + name = "no_Zdinx", + constraint_setting = "Zdinx_setting", +) + +# Does the CPU possess extension Zhinx? +constraint_setting( + name = "Zhinx_setting", + default_constraint_value = ":no_Zhinx", +) + +# CPU does possess the Zhinx extension +constraint_value( + name = "Zhinx", + constraint_setting = "Zhinx_setting", +) + +# CPU does not possess the Zhinx extension +constraint_value( + name = "no_Zhinx", + constraint_setting = "Zhinx_setting", +) + +# Does the CPU possess extension Zhinxmin? +constraint_setting( + name = "Zhinxmin_setting", + default_constraint_value = ":no_Zhinxmin", +) + +# CPU does possess the Zhinxmin extension +constraint_value( + name = "Zhinxmin", + constraint_setting = "Zhinxmin_setting", +) + +# CPU does not possess the Zhinxmin extension +constraint_value( + name = "no_Zhinxmin", + constraint_setting = "Zhinxmin_setting", +) + +# Does the CPU possess extension Zihintpause? +constraint_setting( + name = "Zihintpause_setting", + default_constraint_value = ":no_Zihintpause", +) + +# CPU does possess the Zihintpause extension +constraint_value( + name = "Zihintpause", + constraint_setting = "Zihintpause_setting", +) + +# CPU does not possess the Zihintpause extension +constraint_value( + name = "no_Zihintpause", + constraint_setting = "Zihintpause_setting", +) diff --git a/cpu/riscv/extensions/shorthand.bzl b/cpu/riscv/extensions/shorthand.bzl new file mode 100644 index 0000000..25d4eeb --- /dev/null +++ b/cpu/riscv/extensions/shorthand.bzl @@ -0,0 +1,21 @@ +"""RISC-V shorthand extensions + +These are official shorthands for commonly combined sets of extensions. +""" + +ZKN = [ + "@platforms//cpu/riscv/extensions:Zbkb", + "@platforms//cpu/riscv/extensions:Zbkc", + "@platforms//cpu/riscv/extensions:Zbkx", + "@platforms//cpu/riscv/extensions:Zkne", + "@platforms//cpu/riscv/extensions:Zknd", + "@platforms//cpu/riscv/extensions:Zknh", +] +ZKS = [ + "@platforms//cpu/riscv/extensions:Zbkb", + "@platforms//cpu/riscv/extensions:Zbkc", + "@platforms//cpu/riscv/extensions:Zbkx", + "@platforms//cpu/riscv/extensions:Zksed", + "@platforms//cpu/riscv/extensions:Zksh", +] +ZK = ZKN + ZKS + ["@platforms//cpu/riscv/extensions:Zkt"]