From fc0b9bf7fb558ea49718317eb0623184d60b6fd6 Mon Sep 17 00:00:00 2001 From: John Harrison Date: Thu, 8 Feb 2024 16:00:10 -0800 Subject: [PATCH] Switch non-alt ARM X25519 to unsaturated code following Lenngren This completely changes the implementation of ARM curve25519_x25519 and curve25519_x25519_byte (not the _alt forms, which remain faster on their target microarchitectures) to a base-25.5 unsaturated version with interleaved integer and SIMD operations, the inner loop closely following Emil Lenngren's implementation described in the paper https://github.com/Emill/X25519-AArch64/blob/master/X25519_AArch64.pdf and available here: https://github.com/Emill/X25519-AArch64 A version of this code was generated by SLOTHY from the reorganized implementation by Abdulrahman, Becker, Kannwischer and Klein here: https://github.com/slothy-optimizer/slothy/blob/main/paper/clean/neon/X25519-AArch64-simple.s as described in the associated paper https://eprint.iacr.org/2022/1303.pdf with some additional annotations for use in the formal proof. The final modular inverse computation reverts to the usual saturated representation and s2n-bignum's divstep-based inverse function. --- arm/curve25519/curve25519_x25519.S | 2312 ++-- arm/curve25519/curve25519_x25519_byte.S | 2440 +++-- arm/proofs/curve25519_x25519.ml | 12062 ++++++++------------- arm/proofs/curve25519_x25519_byte.ml | 12314 ++++++++-------------- 4 files changed, 11787 insertions(+), 17341 deletions(-) diff --git a/arm/curve25519/curve25519_x25519.S b/arm/curve25519/curve25519_x25519.S index 5aaaaa0f..28dd2f69 100644 --- a/arm/curve25519/curve25519_x25519.S +++ b/arm/curve25519/curve25519_x25519.S @@ -1,6 +1,18 @@ // Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved. // SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT-0 +// ********************************************************************** +// This code is substantially derived from Emil Lenngren's implementation +// +// https://github.com/Emill/X25519-AArch64/blob/master/X25519_AArch64.pdf +// https://github.com/Emill/X25519-AArch64 +// +// and the SLOTHY-based re-engineering of that code by Hanno Becker: +// +// https://eprint.iacr.org/2022/1303.pdf +// https://github.com/slothy-optimizer/slothy/tree/main/paper +// ********************************************************************** + // ---------------------------------------------------------------------------- // The x25519 function for curve25519 // Inputs scalar[4], point[4]; output res[4] @@ -26,833 +38,1309 @@ .text .balign 4 -// Size of individual field elements - -#define NUMSIZE 32 - -// Stable homes for the input result argument during the whole body -// and other variables that are only needed prior to the modular inverse. - -#define res x23 -#define i x20 -#define swap x21 - -// Pointers to result x coord to be written - -#define resx res, #0 - -// Pointer-offset pairs for temporaries on stack with some aliasing. - -#define scalar sp, #(0*NUMSIZE) +// Pointer-offset pairs for temporaries on stack -#define pointx sp, #(1*NUMSIZE) +#define scalar sp, #0 +#define pointx sp, #32 +#define mask1 sp, #72 +#define mask2 sp, #80 +#define tmpa sp, #88 +#define tmpb sp, #128 +#define xn sp, #128 +#define zn sp, #160 -#define zm sp, #(2*NUMSIZE) -#define sm sp, #(2*NUMSIZE) -#define dpro sp, #(2*NUMSIZE) - -#define sn sp, #(3*NUMSIZE) - -#define dm sp, #(4*NUMSIZE) - -#define zn sp, #(5*NUMSIZE) -#define dn sp, #(5*NUMSIZE) -#define e sp, #(5*NUMSIZE) - -#define dmsn sp, #(6*NUMSIZE) -#define p sp, #(6*NUMSIZE) - -#define xm sp, #(7*NUMSIZE) -#define dnsm sp, #(7*NUMSIZE) -#define spro sp, #(7*NUMSIZE) - -#define d sp, #(8*NUMSIZE) - -#define xn sp, #(9*NUMSIZE) -#define s sp, #(9*NUMSIZE) +#define res sp, #192 +#define i sp, #200 +#define swap sp, #208 // Total size to reserve on the stack -#define NSPACE (10*NUMSIZE) - -// Macro wrapping up the basic field operation bignum_mul_p25519, only -// trivially different from a pure function call to that subroutine. - -#define mul_p25519(P0,P1,P2) \ - ldp x3, x4, [P1]; \ - ldp x5, x6, [P2]; \ - umull x7, w3, w5; \ - lsr x0, x3, #32; \ - umull x15, w0, w5; \ - lsr x16, x5, #32; \ - umull x8, w16, w0; \ - umull x16, w3, w16; \ - adds x7, x7, x15, lsl #32; \ - lsr x15, x15, #32; \ - adc x8, x8, x15; \ - adds x7, x7, x16, lsl #32; \ - lsr x16, x16, #32; \ - adc x8, x8, x16; \ - mul x9, x4, x6; \ - umulh x10, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x16, cc; \ - adds x9, x9, x8; \ - adc x10, x10, xzr; \ - subs x3, x5, x6; \ - cneg x3, x3, cc; \ - cinv x16, x16, cc; \ - mul x15, x4, x3; \ - umulh x3, x4, x3; \ - adds x8, x7, x9; \ - adcs x9, x9, x10; \ - adc x10, x10, xzr; \ - cmn x16, #0x1; \ - eor x15, x15, x16; \ - adcs x8, x15, x8; \ - eor x3, x3, x16; \ - adcs x9, x3, x9; \ - adc x10, x10, x16; \ - ldp x3, x4, [P1+16]; \ - ldp x5, x6, [P2+16]; \ - umull x11, w3, w5; \ - lsr x0, x3, #32; \ - umull x15, w0, w5; \ - lsr x16, x5, #32; \ - umull x12, w16, w0; \ - umull x16, w3, w16; \ - adds x11, x11, x15, lsl #32; \ - lsr x15, x15, #32; \ - adc x12, x12, x15; \ - adds x11, x11, x16, lsl #32; \ - lsr x16, x16, #32; \ - adc x12, x12, x16; \ - mul x13, x4, x6; \ - umulh x14, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x16, cc; \ - adds x13, x13, x12; \ - adc x14, x14, xzr; \ - subs x3, x5, x6; \ - cneg x3, x3, cc; \ - cinv x16, x16, cc; \ - mul x15, x4, x3; \ - umulh x3, x4, x3; \ - adds x12, x11, x13; \ - adcs x13, x13, x14; \ - adc x14, x14, xzr; \ - cmn x16, #0x1; \ - eor x15, x15, x16; \ - adcs x12, x15, x12; \ - eor x3, x3, x16; \ - adcs x13, x3, x13; \ - adc x14, x14, x16; \ - ldp x3, x4, [P1+16]; \ - ldp x15, x16, [P1]; \ - subs x3, x3, x15; \ - sbcs x4, x4, x16; \ - csetm x16, cc; \ - ldp x15, x0, [P2]; \ - subs x5, x15, x5; \ - sbcs x6, x0, x6; \ - csetm x0, cc; \ - eor x3, x3, x16; \ - subs x3, x3, x16; \ - eor x4, x4, x16; \ - sbc x4, x4, x16; \ - eor x5, x5, x0; \ - subs x5, x5, x0; \ - eor x6, x6, x0; \ - sbc x6, x6, x0; \ - eor x16, x0, x16; \ - adds x11, x11, x9; \ - adcs x12, x12, x10; \ - adcs x13, x13, xzr; \ - adc x14, x14, xzr; \ - mul x2, x3, x5; \ - umulh x0, x3, x5; \ - mul x15, x4, x6; \ - umulh x1, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x9, cc; \ - adds x15, x15, x0; \ - adc x1, x1, xzr; \ - subs x6, x5, x6; \ - cneg x6, x6, cc; \ - cinv x9, x9, cc; \ - mul x5, x4, x6; \ - umulh x6, x4, x6; \ - adds x0, x2, x15; \ - adcs x15, x15, x1; \ - adc x1, x1, xzr; \ - cmn x9, #0x1; \ - eor x5, x5, x9; \ - adcs x0, x5, x0; \ - eor x6, x6, x9; \ - adcs x15, x6, x15; \ - adc x1, x1, x9; \ - adds x9, x11, x7; \ - adcs x10, x12, x8; \ - adcs x11, x13, x11; \ - adcs x12, x14, x12; \ - adcs x13, x13, xzr; \ - adc x14, x14, xzr; \ - cmn x16, #0x1; \ - eor x2, x2, x16; \ - adcs x9, x2, x9; \ - eor x0, x0, x16; \ - adcs x10, x0, x10; \ - eor x15, x15, x16; \ - adcs x11, x15, x11; \ - eor x1, x1, x16; \ - adcs x12, x1, x12; \ - adcs x13, x13, x16; \ - adc x14, x14, x16; \ - mov x3, #0x26; \ - umull x4, w11, w3; \ - add x4, x4, w7, uxtw; \ - lsr x7, x7, #32; \ - lsr x11, x11, #32; \ - umaddl x11, w11, w3, x7; \ - mov x7, x4; \ - umull x4, w12, w3; \ - add x4, x4, w8, uxtw; \ - lsr x8, x8, #32; \ - lsr x12, x12, #32; \ - umaddl x12, w12, w3, x8; \ - mov x8, x4; \ - umull x4, w13, w3; \ - add x4, x4, w9, uxtw; \ - lsr x9, x9, #32; \ - lsr x13, x13, #32; \ - umaddl x13, w13, w3, x9; \ - mov x9, x4; \ - umull x4, w14, w3; \ - add x4, x4, w10, uxtw; \ - lsr x10, x10, #32; \ - lsr x14, x14, #32; \ - umaddl x14, w14, w3, x10; \ - mov x10, x4; \ - lsr x0, x14, #31; \ - mov x5, #0x13; \ - umaddl x5, w5, w0, x5; \ - add x7, x7, x5; \ - adds x7, x7, x11, lsl #32; \ - extr x3, x12, x11, #32; \ - adcs x8, x8, x3; \ - extr x3, x13, x12, #32; \ - adcs x9, x9, x3; \ - extr x3, x14, x13, #32; \ - lsl x5, x0, #63; \ - eor x10, x10, x5; \ - adc x10, x10, x3; \ - mov x3, #0x13; \ - tst x10, #0x8000000000000000; \ - csel x3, x3, xzr, pl; \ - subs x7, x7, x3; \ - sbcs x8, x8, xzr; \ - sbcs x9, x9, xzr; \ - sbc x10, x10, xzr; \ - and x10, x10, #0x7fffffffffffffff; \ - stp x7, x8, [P0]; \ - stp x9, x10, [P0+16] - -// A version of multiplication that only guarantees output < 2 * p_25519. -// This basically skips the +1 and final correction in quotient estimation. - -#define mul_4(P0,P1,P2) \ - ldp x3, x4, [P1]; \ - ldp x5, x6, [P2]; \ - umull x7, w3, w5; \ - lsr x0, x3, #32; \ - umull x15, w0, w5; \ - lsr x16, x5, #32; \ - umull x8, w16, w0; \ - umull x16, w3, w16; \ - adds x7, x7, x15, lsl #32; \ - lsr x15, x15, #32; \ - adc x8, x8, x15; \ - adds x7, x7, x16, lsl #32; \ - lsr x16, x16, #32; \ - adc x8, x8, x16; \ - mul x9, x4, x6; \ - umulh x10, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x16, cc; \ - adds x9, x9, x8; \ - adc x10, x10, xzr; \ - subs x3, x5, x6; \ - cneg x3, x3, cc; \ - cinv x16, x16, cc; \ - mul x15, x4, x3; \ - umulh x3, x4, x3; \ - adds x8, x7, x9; \ - adcs x9, x9, x10; \ - adc x10, x10, xzr; \ - cmn x16, #0x1; \ - eor x15, x15, x16; \ - adcs x8, x15, x8; \ - eor x3, x3, x16; \ - adcs x9, x3, x9; \ - adc x10, x10, x16; \ - ldp x3, x4, [P1+16]; \ - ldp x5, x6, [P2+16]; \ - umull x11, w3, w5; \ - lsr x0, x3, #32; \ - umull x15, w0, w5; \ - lsr x16, x5, #32; \ - umull x12, w16, w0; \ - umull x16, w3, w16; \ - adds x11, x11, x15, lsl #32; \ - lsr x15, x15, #32; \ - adc x12, x12, x15; \ - adds x11, x11, x16, lsl #32; \ - lsr x16, x16, #32; \ - adc x12, x12, x16; \ - mul x13, x4, x6; \ - umulh x14, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x16, cc; \ - adds x13, x13, x12; \ - adc x14, x14, xzr; \ - subs x3, x5, x6; \ - cneg x3, x3, cc; \ - cinv x16, x16, cc; \ - mul x15, x4, x3; \ - umulh x3, x4, x3; \ - adds x12, x11, x13; \ - adcs x13, x13, x14; \ - adc x14, x14, xzr; \ - cmn x16, #0x1; \ - eor x15, x15, x16; \ - adcs x12, x15, x12; \ - eor x3, x3, x16; \ - adcs x13, x3, x13; \ - adc x14, x14, x16; \ - ldp x3, x4, [P1+16]; \ - ldp x15, x16, [P1]; \ - subs x3, x3, x15; \ - sbcs x4, x4, x16; \ - csetm x16, cc; \ - ldp x15, x0, [P2]; \ - subs x5, x15, x5; \ - sbcs x6, x0, x6; \ - csetm x0, cc; \ - eor x3, x3, x16; \ - subs x3, x3, x16; \ - eor x4, x4, x16; \ - sbc x4, x4, x16; \ - eor x5, x5, x0; \ - subs x5, x5, x0; \ - eor x6, x6, x0; \ - sbc x6, x6, x0; \ - eor x16, x0, x16; \ - adds x11, x11, x9; \ - adcs x12, x12, x10; \ - adcs x13, x13, xzr; \ - adc x14, x14, xzr; \ - mul x2, x3, x5; \ - umulh x0, x3, x5; \ - mul x15, x4, x6; \ - umulh x1, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x9, cc; \ - adds x15, x15, x0; \ - adc x1, x1, xzr; \ - subs x6, x5, x6; \ - cneg x6, x6, cc; \ - cinv x9, x9, cc; \ - mul x5, x4, x6; \ - umulh x6, x4, x6; \ - adds x0, x2, x15; \ - adcs x15, x15, x1; \ - adc x1, x1, xzr; \ - cmn x9, #0x1; \ - eor x5, x5, x9; \ - adcs x0, x5, x0; \ - eor x6, x6, x9; \ - adcs x15, x6, x15; \ - adc x1, x1, x9; \ - adds x9, x11, x7; \ - adcs x10, x12, x8; \ - adcs x11, x13, x11; \ - adcs x12, x14, x12; \ - adcs x13, x13, xzr; \ - adc x14, x14, xzr; \ - cmn x16, #0x1; \ - eor x2, x2, x16; \ - adcs x9, x2, x9; \ - eor x0, x0, x16; \ - adcs x10, x0, x10; \ - eor x15, x15, x16; \ - adcs x11, x15, x11; \ - eor x1, x1, x16; \ - adcs x12, x1, x12; \ - adcs x13, x13, x16; \ - adc x14, x14, x16; \ - mov x3, #0x26; \ - umull x4, w11, w3; \ - add x4, x4, w7, uxtw; \ - lsr x7, x7, #32; \ - lsr x11, x11, #32; \ - umaddl x11, w11, w3, x7; \ - mov x7, x4; \ - umull x4, w12, w3; \ - add x4, x4, w8, uxtw; \ - lsr x8, x8, #32; \ - lsr x12, x12, #32; \ - umaddl x12, w12, w3, x8; \ - mov x8, x4; \ - umull x4, w13, w3; \ - add x4, x4, w9, uxtw; \ - lsr x9, x9, #32; \ - lsr x13, x13, #32; \ - umaddl x13, w13, w3, x9; \ - mov x9, x4; \ - umull x4, w14, w3; \ - add x4, x4, w10, uxtw; \ - lsr x10, x10, #32; \ - lsr x14, x14, #32; \ - umaddl x14, w14, w3, x10; \ - mov x10, x4; \ - lsr x0, x14, #31; \ - mov x5, #0x13; \ - umull x5, w5, w0; \ - add x7, x7, x5; \ - adds x7, x7, x11, lsl #32; \ - extr x3, x12, x11, #32; \ - adcs x8, x8, x3; \ - extr x3, x13, x12, #32; \ - adcs x9, x9, x3; \ - extr x3, x14, x13, #32; \ - lsl x5, x0, #63; \ - eor x10, x10, x5; \ - adc x10, x10, x3; \ - stp x7, x8, [P0]; \ - stp x9, x10, [P0+16] - -// Squaring just giving a result < 2 * p_25519, which is done by -// basically skipping the +1 in the quotient estimate and the final -// optional correction. - -#define sqr_4(P0,P1) \ - ldp x10, x11, [P1]; \ - ldp x12, x13, [P1+16]; \ - umull x2, w10, w10; \ - lsr x14, x10, #32; \ - umull x3, w14, w14; \ - umull x14, w10, w14; \ - adds x2, x2, x14, lsl #33; \ - lsr x14, x14, #31; \ - adc x3, x3, x14; \ - umull x4, w11, w11; \ - lsr x14, x11, #32; \ - umull x5, w14, w14; \ - umull x14, w11, w14; \ - mul x15, x10, x11; \ - umulh x16, x10, x11; \ - adds x4, x4, x14, lsl #33; \ - lsr x14, x14, #31; \ - adc x5, x5, x14; \ - adds x15, x15, x15; \ - adcs x16, x16, x16; \ - adc x5, x5, xzr; \ - adds x3, x3, x15; \ - adcs x4, x4, x16; \ - adc x5, x5, xzr; \ - umull x6, w12, w12; \ - lsr x14, x12, #32; \ - umull x7, w14, w14; \ - umull x14, w12, w14; \ - adds x6, x6, x14, lsl #33; \ - lsr x14, x14, #31; \ - adc x7, x7, x14; \ - umull x8, w13, w13; \ - lsr x14, x13, #32; \ - umull x9, w14, w14; \ - umull x14, w13, w14; \ - mul x15, x12, x13; \ - umulh x16, x12, x13; \ - adds x8, x8, x14, lsl #33; \ - lsr x14, x14, #31; \ - adc x9, x9, x14; \ - adds x15, x15, x15; \ - adcs x16, x16, x16; \ - adc x9, x9, xzr; \ - adds x7, x7, x15; \ - adcs x8, x8, x16; \ - adc x9, x9, xzr; \ - subs x10, x10, x12; \ - sbcs x11, x11, x13; \ - csetm x16, cc; \ - eor x10, x10, x16; \ - subs x10, x10, x16; \ - eor x11, x11, x16; \ - sbc x11, x11, x16; \ - adds x6, x6, x4; \ - adcs x7, x7, x5; \ - adcs x8, x8, xzr; \ - adc x9, x9, xzr; \ - umull x12, w10, w10; \ - lsr x5, x10, #32; \ - umull x13, w5, w5; \ - umull x5, w10, w5; \ - adds x12, x12, x5, lsl #33; \ - lsr x5, x5, #31; \ - adc x13, x13, x5; \ - umull x15, w11, w11; \ - lsr x5, x11, #32; \ - umull x14, w5, w5; \ - umull x5, w11, w5; \ - mul x4, x10, x11; \ - umulh x16, x10, x11; \ - adds x15, x15, x5, lsl #33; \ - lsr x5, x5, #31; \ - adc x14, x14, x5; \ - adds x4, x4, x4; \ - adcs x16, x16, x16; \ - adc x14, x14, xzr; \ - adds x13, x13, x4; \ - adcs x15, x15, x16; \ - adc x14, x14, xzr; \ - adds x4, x2, x6; \ - adcs x5, x3, x7; \ - adcs x6, x6, x8; \ - adcs x7, x7, x9; \ - csetm x16, cc; \ - subs x4, x4, x12; \ - sbcs x5, x5, x13; \ - sbcs x6, x6, x15; \ - sbcs x7, x7, x14; \ - adcs x8, x8, x16; \ - adc x9, x9, x16; \ - mov x10, #0x26; \ - umull x12, w6, w10; \ - add x12, x12, w2, uxtw; \ - lsr x2, x2, #32; \ - lsr x6, x6, #32; \ - umaddl x6, w6, w10, x2; \ - mov x2, x12; \ - umull x12, w7, w10; \ - add x12, x12, w3, uxtw; \ - lsr x3, x3, #32; \ - lsr x7, x7, #32; \ - umaddl x7, w7, w10, x3; \ - mov x3, x12; \ - umull x12, w8, w10; \ - add x12, x12, w4, uxtw; \ - lsr x4, x4, #32; \ - lsr x8, x8, #32; \ - umaddl x8, w8, w10, x4; \ - mov x4, x12; \ - umull x12, w9, w10; \ - add x12, x12, w5, uxtw; \ - lsr x5, x5, #32; \ - lsr x9, x9, #32; \ - umaddl x9, w9, w10, x5; \ - mov x5, x12; \ - lsr x13, x9, #31; \ - mov x11, #0x13; \ - umull x11, w11, w13; \ - add x2, x2, x11; \ - adds x2, x2, x6, lsl #32; \ - extr x10, x7, x6, #32; \ - adcs x3, x3, x10; \ - extr x10, x8, x7, #32; \ - adcs x4, x4, x10; \ - extr x10, x9, x8, #32; \ - lsl x11, x13, #63; \ - eor x5, x5, x11; \ - adc x5, x5, x10; \ - stp x2, x3, [P0]; \ - stp x4, x5, [P0+16] - -// Modular addition with double modulus 2 * p_25519 = 2^256 - 38. -// This only ensures that the result fits in 4 digits, not that it is reduced -// even w.r.t. double modulus. The result is always correct modulo provided -// the sum of the inputs is < 2^256 + 2^256 - 38, so in particular provided -// at least one of them is reduced double modulo. - -#define add_twice4(P0,P1,P2) \ - ldp x3, x4, [P1]; \ - ldp x7, x8, [P2]; \ - adds x3, x3, x7; \ - adcs x4, x4, x8; \ - ldp x5, x6, [P1+16]; \ - ldp x7, x8, [P2+16]; \ - adcs x5, x5, x7; \ - adcs x6, x6, x8; \ - mov x9, #38; \ - csel x9, x9, xzr, cs; \ - adds x3, x3, x9; \ - adcs x4, x4, xzr; \ - adcs x5, x5, xzr; \ - adc x6, x6, xzr; \ - stp x3, x4, [P0]; \ - stp x5, x6, [P0+16] - -// Modular subtraction with double modulus 2 * p_25519 = 2^256 - 38 - -#define sub_twice4(p0,p1,p2) \ - ldp x5, x6, [p1]; \ - ldp x4, x3, [p2]; \ - subs x5, x5, x4; \ - sbcs x6, x6, x3; \ - ldp x7, x8, [p1+16]; \ - ldp x4, x3, [p2+16]; \ - sbcs x7, x7, x4; \ - sbcs x8, x8, x3; \ - mov x4, #38; \ - csel x3, x4, xzr, lo; \ - subs x5, x5, x3; \ - sbcs x6, x6, xzr; \ - sbcs x7, x7, xzr; \ - sbc x8, x8, xzr; \ - stp x5, x6, [p0]; \ - stp x7, x8, [p0+16] - -// Combined z = c * x + y with reduction only < 2 * p_25519 -// where c is initially in the X1 register. It is assumed -// that 19 * (c * x + y) < 2^60 * 2^256 so we don't need a -// high mul in the final part. - -#define cmadd_4(p0,p2,p3) \ - ldp x7, x8, [p2]; \ - ldp x9, x10, [p2+16]; \ - mul x3, x1, x7; \ - mul x4, x1, x8; \ - mul x5, x1, x9; \ - mul x6, x1, x10; \ - umulh x7, x1, x7; \ - umulh x8, x1, x8; \ - umulh x9, x1, x9; \ - umulh x10, x1, x10; \ - adds x4, x4, x7; \ - adcs x5, x5, x8; \ - adcs x6, x6, x9; \ - adc x10, x10, xzr; \ - ldp x7, x8, [p3]; \ - adds x3, x3, x7; \ - adcs x4, x4, x8; \ - ldp x7, x8, [p3+16]; \ - adcs x5, x5, x7; \ - adcs x6, x6, x8; \ - adc x10, x10, xzr; \ - cmn x6, x6; \ - bic x6, x6, #0x8000000000000000; \ - adc x8, x10, x10; \ - mov x9, #19; \ - mul x7, x8, x9; \ - adds x3, x3, x7; \ - adcs x4, x4, xzr; \ - adcs x5, x5, xzr; \ - adc x6, x6, xzr; \ - stp x3, x4, [p0]; \ - stp x5, x6, [p0+16] - -// Multiplex: z := if NZ then x else y - -#define mux_4(p0,p1,p2) \ - ldp x0, x1, [p1]; \ - ldp x2, x3, [p2]; \ - csel x0, x0, x2, ne; \ - csel x1, x1, x3, ne; \ - stp x0, x1, [p0]; \ - ldp x0, x1, [p1+16]; \ - ldp x2, x3, [p2+16]; \ - csel x0, x0, x2, ne; \ - csel x1, x1, x3, ne; \ - stp x0, x1, [p0+16] +#define NSPACE 224 +#define regsave sp, #NSPACE S2N_BN_SYMBOL(curve25519_x25519): -// Save regs and make room for temporaries - - stp x19, x20, [sp, -16]! - stp x21, x22, [sp, -16]! - stp x23, x24, [sp, -16]! - sub sp, sp, #NSPACE +// Save registers and make additional room NSPACE for temporaries. +// We only need to save the low 64-bits of the Q8...Q15 registers +// according to the ABI, so we use a save of the D8...D15 forms. + + sub sp, sp, #NSPACE+160 + stp d8, d9, [regsave+0] + stp d10, d11, [regsave+16] + stp d12, d13, [regsave+32] + stp d14, d15, [regsave+48] + stp x19, x20, [regsave+64] + stp x21, x22, [regsave+80] + stp x23, x24, [regsave+96] + stp x25, x26, [regsave+112] + stp x27, x28, [regsave+128] + stp x29, x30, [regsave+144] // Move the output pointer to a stable place - mov res, x0 + str x0, [res] -// Copy the inputs to the local variables with minimal mangling: -// -// - The scalar is in principle turned into 01xxx...xxx000 but -// in the structure below the special handling of these bits is -// explicit in the main computation; the scalar is just copied. -// -// - The point x coord is reduced mod 2^255 by masking off the -// top bit. In the main loop we only need reduction < 2 * p_25519. +// Copy the scalar to the corresponding local variable while +// mangling it. In principle it becomes 01xxx...xxx000 where +// the xxx are the corresponding bits of the original input +// scalar. We actually don't bother forcing the MSB to zero, +// but rather start the main loop below at 254 instead of 255. ldp x10, x11, [x1] + bic x10, x10, #7 stp x10, x11, [scalar] ldp x12, x13, [x1, #16] + orr x13, x13, #0x4000000000000000 stp x12, x13, [scalar+16] - ldp x10, x11, [x2] - stp x10, x11, [pointx] - ldp x12, x13, [x2, #16] - and x13, x13, #0x7fffffffffffffff +// Discard the MSB of the point X coordinate (this is in +// accordance with the RFC, mod 2^255, *not* 2^255-19). +// Then recode it into the unsaturated base 25.5 form. + + ldp x0, x1, [x2] + ldp x2, x3, [x2, #16] + + lsr x12, x0, #51 + lsr x17, x2, #51 + orr x12, x12, x1, lsl #13 + orr x17, x17, x3, lsl #13 + ubfx x8, x3, #12, #26 + ubfx x9, x3, #38, #25 + ubfx x11, x0, #26, #25 + ubfx x13, x1, #13, #25 + lsr x14, x1, #38 + ubfx x16, x2, #25, #26 + and x10, x0, #0x3ffffff + and x12, x12, #0x3ffffff + and x15, x2, #0x1ffffff + and x17, x17, #0x1ffffff + orr x10, x10, x11, lsl #32 + orr x11, x12, x13, lsl #32 + orr x12, x14, x15, lsl #32 + orr x13, x16, x17, lsl #32 + orr x14, x8, x9, lsl #32 + + stp x10, x11, [pointx+0] stp x12, x13, [pointx+16] + str x14, [pointx+32] + +// Initialize (X2,Z2) = (1,0), the identity (projective point at infinity) + + mov x1, #1 + mov v0.d[0], x1 + mov v2.d[0], xzr + mov v4.d[0], xzr + mov v6.d[0], xzr + mov v8.d[0], xzr + + mov v1.d[0], xzr + mov v3.d[0], xzr + mov v5.d[0], xzr + mov v7.d[0], xzr + mov v9.d[0], xzr + +// Initialize (X3,Z3) = (X,1), projective representation of X + + mov v10.d[0], x10 + mov v12.d[0], x11 + mov v14.d[0], x12 + mov v16.d[0], x13 + mov v18.d[0], x14 + + mov v11.d[0], x1 + mov v13.d[0], xzr + mov v15.d[0], xzr + mov v17.d[0], xzr + mov v19.d[0], xzr + +// Set up some constants used repeatedly in the main loop: +// +// Q31 = 0x1300000013 (two 32-bit copies of 19) +// Q30 = 0x3ffffff0000000003ffffff (two 64-bit copies of 2^26-1) +// Q29 = mask1 = (0x07ffffc,0x07fffffe) +// Q28 = mask2 = (0x07ffffb4,0x07fffffe) -// Initialize with explicit doubling in order to handle set bit 254. -// Set swap = 1 and (xm,zm) = (x,1) then double as (xn,zn) = 2 * (x,1). -// We use the fact that the point x coordinate is still in registers. -// Since zm = 1 we could do the doubling with an operation count of -// 2 * S + M instead of 2 * S + 2 * M, but it doesn't seem worth -// the slight complication arising from a different linear combination. - - mov swap, #1 - stp x10, x11, [xm] - stp x12, x13, [xm+16] - stp swap, xzr, [zm] - stp xzr, xzr, [zm+16] - - sub_twice4(d,xm,zm) - add_twice4(s,xm,zm) - sqr_4(d,d) - sqr_4(s,s) - sub_twice4(p,s,d) - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - mul_4(xn,s,d) - mul_4(zn,p,e) - -// The main loop over unmodified bits from i = 253, ..., i = 3 (inclusive). -// This is a classic Montgomery ladder, with the main coordinates only -// reduced mod 2 * p_25519, some intermediate results even more loosely. + mov w0, #19 + add x0, x0, x0, lsl #32 + mov v31.d[0], x0 + mov v31.d[1], xzr - mov i, #253 + mov x0, #(1<<26)-1 + mov v30.d[0], x0 + mov v30.d[1], x0 -curve25519_x25519_scalarloop: + mov x0, #0x07fffffe07fffffe + sub x1, x0, #0xfe-0xb4 + sub x0, x0, #2 -// sm = xm + zm; sn = xn + zn; dm = xm - zm; dn = xn - zn + stp x0, x1, [mask1] + ldp d29, d28, [mask1] - sub_twice4(dm,xm,zm) - add_twice4(sn,xn,zn) - sub_twice4(dn,xn,zn) - add_twice4(sm,xm,zm) +// The main loop over (modified) bits from i = 254, ..., i = 0 (inclusive); +// we explicitly skip bit 255 because it should be forced to zero initially. +// This is a classic Montgomery ladder using a "swap" variable. +// It's assumed x0 = i at the start of the loop, but that is volatile and +// needs to be reloaded from memory at the end of the loop. -// ADDING: dmsn = dm * sn -// DOUBLING: mux d = xt - zt and s = xt + zt for appropriate choice of (xt,zt) + str xzr, [swap] + mov x0, #254 + str x0, [i] - mul_4(dmsn,sn,dm) +curve25519_x25519_scalarloop: - lsr x0, i, #6 - ldr x2, [sp, x0, lsl #3] // Exploiting scalar = sp exactly - lsr x2, x2, i + lsr x1, x0, #6 + ldr x2, [sp, x1, lsl #3] // Exploiting scalar = sp exactly + lsr x2, x2, x0 and x2, x2, #1 - cmp swap, x2 - mov swap, x2 - - mux_4(d,dm,dn) - mux_4(s,sm,sn) - -// ADDING: dnsm = sm * dn - - mul_4(dnsm,sm,dn) - -// DOUBLING: d = (xt - zt)^2 - - sqr_4(d,d) - -// ADDING: dpro = (dmsn - dnsm)^2, spro = (dmsn + dnsm)^2 -// DOUBLING: s = (xt + zt)^2 - - sub_twice4(dpro,dmsn,dnsm) - sqr_4(s,s) - add_twice4(spro,dmsn,dnsm) - sqr_4(dpro,dpro) - -// DOUBLING: p = 4 * xt * zt = s - d - - sub_twice4(p,s,d) - -// ADDING: xm' = (dmsn + dnsm)^2 - - sqr_4(xm,spro) - -// DOUBLING: e = 121666 * p + d - - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - -// DOUBLING: xn' = (xt + zt)^2 * (xt - zt)^2 = s * d - - mul_4(xn,s,d) - -// ADDING: zm' = x * (dmsn - dnsm)^2 - - mul_4(zm,dpro,pointx) - -// DOUBLING: zn' = (4 * xt * zt) * ((xt - zt)^2 + 121666 * (4 * xt * zt)) -// = p * (d + 121666 * p) - - mul_4(zn,p,e) - -// Loop down as far as 3 (inclusive) - - sub i, i, #1 - cmp i, #3 + ldr x0, [swap] + cmp x0, x2 + str x2, [swap] + +// The following inner loop code is derived closely following Lenngren's +// implementation available at "https://github.com/Emill/X25519-AArch64". +// In particular, the basic dataflow and the organization between integer +// and SIMD units is identical, with only a few minor changes to some +// individual instructions (for miscellaneous reasons). The scheduling +// was redone from scratch by SLOTHY starting from Hanno Becker's +// un-interleaved form and using the same scripts as in Becker et al's +// paper. +// +// The intermediate value annotations were added to provide data that +// is used in the formal proof, indicating which lines assign specific +// digits of the various intermediate results (mainly of field +// operations, sometimes other transformations). The names used for +// the intermediate results are similar but not identical to those in +// the abstract Algorithm 1 description in Lenngren's paper. Almost +// all equations are to be interpreted as field operations, i.e. as +// arithmetic modulo 2^255-19, not simple numeric equalities. +// +// b = x2 - z2 +// d = x3 - z3 +// a = x2 + z2 +// c = x3 + z3 +// f = if flip then c else a +// g = if flip then d else b +// aa = f^2 +// bb = g^2 +// bbalt = bb (change of representation) +// e = aa - bb +// bce = bbalt + 121666 * e +// z4 = bce * e +// bc = b * c +// ad = a * d +// t1 = ad + bc +// t2 = ad - bc +// x5 = t1^2 +// t3 = t2^2 +// x4 = aa * bb +// z5 = x * t3 +// +// Then the main variables are updated for the next iteration as +// +// (x2',z2') = (x4,z4) +// (x3',z3') = (x5,z5) + + add v22.2S, v2.2S, v3.2S // ubignum_of_qreglist 1 // INTERMEDIATE a + sub v21.2S, v28.2S, v1.2S + add v25.2S, v0.2S, v1.2S // ubignum_of_qreglist 0 // INTERMEDIATE a + sub v24.2S, v29.2S, v3.2S + add v3.2S, v18.2S, v19.2S // ubignum_of_qreglist 4 // INTERMEDIATE c + add v0.2S, v0.2S, v21.2S // ubignum_of_qreglist 0 // INTERMEDIATE b + sub v20.2S, v29.2S, v15.2S + sub v1.2S, v29.2S, v5.2S + sub v26.2S, v28.2S, v11.2S + sub v21.2S, v29.2S, v19.2S + add v19.2S, v10.2S, v11.2S // ubignum_of_qreglist 0 // INTERMEDIATE c + add v11.2S, v14.2S, v20.2S // ubignum_of_qreglist 2 // INTERMEDIATE d + add v21.2S, v18.2S, v21.2S // ubignum_of_qreglist 4 // INTERMEDIATE d + sub v20.2S, v29.2S, v17.2S + add v18.2S, v2.2S, v24.2S // ubignum_of_qreglist 1 // INTERMEDIATE b + add v14.2S, v14.2S, v15.2S // ubignum_of_qreglist 2 // INTERMEDIATE c + add v15.2S, v16.2S, v17.2S // ubignum_of_qreglist 3 // INTERMEDIATE c + add v2.2S, v16.2S, v20.2S // ubignum_of_qreglist 3 // INTERMEDIATE d + add v24.2S, v12.2S, v13.2S // ubignum_of_qreglist 1 // INTERMEDIATE c + add v26.2S, v10.2S, v26.2S // ubignum_of_qreglist 0 // INTERMEDIATE d + sub v10.2S, v29.2S, v13.2S + sub v13.2S, v29.2S, v7.2S + add v23.2S, v6.2S, v7.2S // ubignum_of_qreglist 3 // INTERMEDIATE a + sub v7.2S, v29.2S, v9.2S + add v27.2S, v12.2S, v10.2S // ubignum_of_qreglist 1 // INTERMEDIATE d + fcsel d20, d22, d24, eq // ubignum_of_qreglist 1 // INTERMEDIATE f + add v28.2S, v4.2S, v5.2S // ubignum_of_qreglist 2 // INTERMEDIATE a + fcsel d12, d23, d15, eq // ubignum_of_qreglist 3 // INTERMEDIATE f + add v7.2S, v8.2S, v7.2S // ubignum_of_qreglist 4 // INTERMEDIATE b + fcsel d16, d25, d19, eq // ubignum_of_qreglist 0 // INTERMEDIATE f + mov x0, v20.d[0] + fcsel d5, d28, d14, eq // ubignum_of_qreglist 2 // INTERMEDIATE f + mov x21, v12.d[0] + fcsel d29, d7, d21, eq // ubignum_of_qreglist 4 // INTERMEDIATE g + mov x5, v16.d[0] + lsr x26, x0, #32 + add x29, x21, x21 + umull x15, w5, w29 + add v13.2S, v6.2S, v13.2S // ubignum_of_qreglist 3 // INTERMEDIATE b + add x12, x26, x26 + mov x30, v5.d[0] + fcsel d10, d18, d27, eq // ubignum_of_qreglist 1 // INTERMEDIATE g + lsr x11, x5, #32 + lsr x10, x30, #32 + trn2 v20.2S, v21.2S, v3.2S + add v9.2S, v8.2S, v9.2S // ubignum_of_qreglist 4 // INTERMEDIATE a + add x14, x11, x11 + trn2 v6.2S, v2.2S, v15.2S + trn1 v12.2S, v25.2S, v0.2S + add v1.2S, v4.2S, v1.2S // ubignum_of_qreglist 2 // INTERMEDIATE b + trn1 v16.2S, v23.2S, v13.2S + fcsel d8, d13, d2, eq // ubignum_of_qreglist 3 // INTERMEDIATE g + trn2 v17.2S, v27.2S, v24.2S + str d29, [tmpb+32] + add x17, x10, x10 + trn2 v4.2S, v28.2S, v1.2S + trn1 v5.2S, v28.2S, v1.2S + trn1 v28.2S, v2.2S, v15.2S + trn1 v2.2S, v22.2S, v18.2S + fcsel d29, d0, d26, eq // ubignum_of_qreglist 0 // INTERMEDIATE g + trn2 v15.2S, v22.2S, v18.2S + umull v22.2D, v12.2S, v20.2S + umull x22, w30, w17 + stp d29, d10, [tmpb+0] + trn2 v10.2S, v23.2S, v13.2S + trn2 v23.2S, v11.2S, v14.2S + trn1 v13.2S, v27.2S, v24.2S + fcsel d27, d1, d11, eq // ubignum_of_qreglist 2 // INTERMEDIATE g + trn1 v14.2S, v11.2S, v14.2S + umlal v22.2D, v2.2S, v6.2S + umull x25, w30, w30 + umlal v22.2D, v5.2S, v23.2S + add x3, x30, x30 + umlal v22.2D, v16.2S, v17.2S + add w30, w21, w21, lsl #1; + stp d27, d8, [tmpb+16] + add w30, w30, w21, lsl #4 + trn1 v11.2S, v26.2S, v19.2S + trn2 v8.2S, v26.2S, v19.2S + trn2 v19.2S, v25.2S, v0.2S + mul v29.2S, v20.2S, v31.2S + ldr x20, [tmpb+24] + umull v25.2D, v19.2S, v6.2S + add x1, x0, x0 + umull v27.2D, v19.2S, v23.2S + umull x9, w5, w1 + umull v0.2D, v12.2S, v23.2S + lsr x24, x20, #32 + mul v20.2S, v23.2S, v31.2S + lsr x16, x21, #32 + umlal v25.2D, v15.2S, v23.2S + umaddl x13, w11, w14, x9 + umlal v25.2D, v4.2S, v17.2S + umaddl x9, w14, w17, x15 + umull v24.2D, v12.2S, v6.2S + add w2, w16, w16, lsl #1; + fcsel d26, d9, d3, eq // ubignum_of_qreglist 4 // INTERMEDIATE f + add w2, w2, w16, lsl #4 + trn1 v18.2S, v21.2S, v3.2S + umull v3.2D, v19.2S, v29.2S + umull x28, w5, w3 + mul v1.2S, v6.2S, v31.2S + umull x8, w5, w5 + umlal v24.2D, v2.2S, v23.2S + umaddl x13, w21, w30, x13 + mul v23.2S, v17.2S, v31.2S + umaddl x27, w14, w12, x28 + trn2 v6.2S, v9.2S, v7.2S + mov x6, v26.d[0] + umlal v3.2D, v15.2S, v1.2S + add x16, x16, x16 + umlal v3.2D, v4.2S, v20.2S + lsr x4, x6, #32 + umlal v3.2D, v10.2S, v23.2S + add x7, x6, x6 + umull v26.2D, v19.2S, v8.2S + add x23, x4, x4 + umaddl x28, w5, w23, x22 + trn1 v7.2S, v9.2S, v7.2S + umlal v27.2D, v15.2S, v17.2S + add w15, w4, w4, lsl #1; + umlal v27.2D, v4.2S, v8.2S + add w15, w15, w4, lsl #4 + add w22, w10, w10, lsl #1; + umlal v24.2D, v5.2S, v17.2S + add w22, w22, w10, lsl #4 + umaddl x10, w11, w7, x28 + umlal v25.2D, v10.2S, v8.2S + umull x21, w5, w16 + umlal v25.2D, v6.2S, v29.2S + umaddl x23, w15, w23, x25 + umlal v27.2D, v10.2S, v29.2S + umull x19, w5, w12 + umlal v27.2D, v6.2S, v1.2S + umaddl x25, w11, w29, x21 + umlal v0.2D, v2.2S, v17.2S + umaddl x28, w0, w3, x9 + shl v21.2D, v25.2D, #1 + umaddl x4, w11, w1, x19 + umaddl x21, w2, w29, x4 + mul v25.2S, v8.2S, v31.2S + umlal v24.2D, v16.2S, v8.2S + umaddl x19, w0, w17, x25 + umlal v24.2D, v7.2S, v29.2S + umull x25, w5, w17 + umlal v24.2D, v19.2S, v28.2S + umaddl x4, w0, w16, x10 + umull v9.2D, v12.2S, v8.2S + umaddl x23, w5, w7, x23 + umlal v21.2D, v12.2S, v18.2S + add w10, w6, w6, lsl #1; + shl v27.2D, v27.2D, #1 + add w10, w10, w6, lsl #4 + umaddl x28, w26, w12, x28 + umlal v26.2D, v15.2S, v29.2S + umaddl x9, w14, w16, x23 + umlal v9.2D, v2.2S, v29.2S + umaddl x22, w22, w17, x8 + umlal v21.2D, v2.2S, v28.2S + umaddl x28, w6, w10, x28 + umaddl x27, w0, w0, x27 + add x8, x14, x14 + umlal v0.2D, v5.2S, v8.2S + umull x5, w5, w14 + umlal v9.2D, v5.2S, v1.2S + umaddl x14, w0, w29, x9 + umlal v26.2D, v4.2S, v1.2S + umaddl x6, w2, w16, x27 + umlal v22.2D, v7.2S, v8.2S + umaddl x5, w30, w17, x5 + umaddl x5, w2, w3, x5 + add x23, x17, x17 + umlal v27.2D, v12.2S, v28.2S + umaddl x13, w2, w23, x13 + umlal v26.2D, v10.2S, v20.2S + add x9, x12, x12 + umlal v9.2D, v16.2S, v20.2S + umaddl x27, w10, w29, x6 + umlal v0.2D, v16.2S, v29.2S + umaddl x6, w11, w3, x25 + umlal v22.2D, v19.2S, v18.2S + umaddl x19, w26, w3, x19 + mul v18.2S, v18.2S, v31.2S + umaddl x23, w15, w23, x27 + umlal v3.2D, v6.2S, v25.2S + umaddl x0, w0, w12, x6 + umlal v0.2D, v7.2S, v1.2S + add x11, x16, x16 + umlal v9.2D, v7.2S, v23.2S + umaddl x6, w12, w17, x14 + umlal v9.2D, v19.2S, v11.2S + umaddl x25, w26, w29, x4 + umlal v9.2D, v15.2S, v18.2S + umaddl x14, w10, w3, x13 + umull v25.2D, v12.2S, v17.2S + umaddl x27, w10, w16, x0 + umlal v26.2D, v6.2S, v23.2S + add x0, x25, x6, lsr #26 + mul v23.2S, v28.2S, v31.2S + umaddl x12, w10, w12, x5 + shl v3.2D, v3.2D, #1 + add x16, x22, x0, lsr #25 + umlal v21.2D, v5.2S, v14.2S + bic x22, x0, #0x1ffffff + umlal v3.2D, v12.2S, v11.2S + add x26, x16, x22, lsr #24 + umlal v3.2D, v2.2S, v18.2S + umaddl x16, w10, w17, x21 + umlal v3.2D, v5.2S, v23.2S + add x22, x26, x22, lsr #21 + umlal v9.2D, v4.2S, v23.2S + umaddl x5, w15, w29, x27 + umull v17.2D, v19.2S, v17.2S + umaddl x17, w30, w3, x22 + umlal v25.2D, v2.2S, v8.2S + umaddl x25, w15, w3, x16 + umlal v25.2D, v5.2S, v29.2S + umaddl x26, w15, w7, x19 + umlal v0.2D, v19.2S, v14.2S + umaddl x17, w2, w9, x17 + umlal v17.2D, v15.2S, v8.2S + ldr x19, [tmpb+0] + umlal v17.2D, v4.2S, v29.2S + ldr x7, [tmpb+8] + shl v29.2D, v26.2D, #1 + umaddl x13, w10, w1, x17 + umlal v0.2D, v15.2S, v13.2S + lsr x2, x19, #32 + umlal v29.2D, v12.2S, v13.2S + umaddl x27, w15, w1, x12 + umlal v29.2D, v2.2S, v11.2S + umaddl x30, w15, w8, x13 + umlal v29.2D, v5.2S, v18.2S + add x4, x7, x7 + umlal v29.2D, v16.2S, v23.2S + umaddl x29, w15, w9, x14 + umlal v0.2D, v4.2S, v11.2S + add x17, x27, x30, lsr #26 + umlal v0.2D, v10.2S, v18.2S + umaddl x16, w15, w11, x28 + umlal v0.2D, v6.2S, v23.2S + add x1, x29, x17, lsr #25 + umlal v25.2D, v16.2S, v1.2S + umull x11, w19, w4 + ldr x8, [tmpb+32] + mul v26.2S, v14.2S, v31.2S + umlal v17.2D, v10.2S, v1.2S + ldr x15, [tmpb+16] + umlal v17.2D, v6.2S, v20.2S + and x9, x30, #0x3ffffff + bfi x9, x17, #32, #25 // ubignum_of_preglist 0 // INTERMEDIATE aa + add x17, x2, x2 + lsr x10, x15, #32 + add x27, x25, x1, lsr #26 + umlal v25.2D, v7.2S, v20.2S + add x13, x10, x10 + umlal v25.2D, v19.2S, v13.2S + add x29, x23, x27, lsr #25 + umlal v25.2D, v15.2S, v11.2S + lsr x30, x8, #32 + umlal v25.2D, v4.2S, v18.2S + add x23, x5, x29, lsr #26 + umlal v25.2D, v10.2S, v23.2S + and x14, x29, #0x3ffffff + umlal v25.2D, v6.2S, v26.2S + add x5, x16, x23, lsr #25 + shl v8.2D, v17.2D, #1 + umaddl x12, w2, w17, x11 + and x29, x5, #0x3ffffff + umull x21, w19, w19 + umlal v29.2D, v7.2S, v26.2S + add w16, w10, w10, lsl #1; + umlal v3.2D, v16.2S, v26.2S + add w16, w16, w10, lsl #4 + bfi x14, x23, #32, #25 // ubignum_of_preglist 2 // INTERMEDIATE aa + add w10, w24, w24, lsl #1; + add x22, x26, x5, lsr #26 + add w10, w10, w24, lsl #4 + umlal v8.2D, v12.2S, v14.2S + umaddl x25, w16, w13, x21 + umlal v8.2D, v2.2S, v13.2S + bfi x29, x22, #32, #25 // ubignum_of_preglist 3 // INTERMEDIATE aa + umlal v8.2D, v5.2S, v11.2S + add x26, x24, x24 + umlal v8.2D, v16.2S, v18.2S + stp x14, x29, [tmpa+16] + umlal v8.2D, v7.2S, v23.2S + add w24, w30, w30, lsl #1; + usra v25.2D, v29.2D, #26 + add w24, w24, w30, lsl #4 + umull x29, w15, w15 + umlal v27.2D, v2.2S, v14.2S + umull x3, w15, w13 + umlal v27.2D, v5.2S, v13.2S + add x21, x20, x20 + umlal v24.2D, v15.2S, v14.2S + umull x5, w19, w21 + umlal v24.2D, v4.2S, v13.2S + and x11, x1, #0x3ffffff + usra v8.2D, v25.2D, #25 + and x1, x0, #0x1ffffff + umlal v27.2D, v16.2S, v11.2S + umaddl x23, w17, w13, x5 + umlal v27.2D, v7.2S, v18.2S + add x5, x30, x30 + usra v0.2D, v8.2D, #26 + add x0, x15, x15 + umlal v24.2D, v10.2S, v11.2S + umaddl x23, w7, w0, x23 + umlal v24.2D, v6.2S, v18.2S + lsr x30, x7, #32 + usra v27.2D, v0.2D, #25 + add x16, x30, x30 + and v20.16B, v8.16B, v30.16B // ubignum_of_hreglist 4 + ubignum_of_lreglist 4 // INTERMEDIATE H|L = bc|ad + umaddl x15, w30, w16, x23 + ushr v23.2D, v30.2D, #1 + add w23, w8, w8, lsl #1; + usra v24.2D, v27.2D, #26 + add w23, w23, w8, lsl #4 + umaddl x14, w19, w5, x3 + and v8.16B, v27.16B, v30.16B // ubignum_of_hreglist 6 + ubignum_of_lreglist 6 // INTERMEDIATE H|L = bc|ad + add x28, x8, x8 + and v27.16B, v0.16B, v23.16B // ubignum_of_hreglist 5 + ubignum_of_lreglist 5 // INTERMEDIATE H|L = bc|ad + umaddl x8, w8, w23, x15 + and v5.16B, v24.16B, v23.16B // ubignum_of_hreglist 7 + ubignum_of_lreglist 7 // INTERMEDIATE H|L = bc|ad + umaddl x3, w2, w28, x14 + umlal v22.2D, v15.2S, v28.2S + bfi x11, x27, #32, #25 // ubignum_of_preglist 1 // INTERMEDIATE aa + uzp1 v5.4S, v8.4S, v5.4S + umaddl x14, w24, w5, x29 + umaddl x5, w19, w28, x14 + ldr d18, [mask1] + mov v18.d[1], v18.d[0] + umaddl x15, w7, w26, x3 + mul v12.2S, v13.2S, v31.2S + umlal v21.2D, v16.2S, v13.2S + stp x9, x11, [tmpa+0] + umlal v21.2D, v7.2S, v11.2S + umaddl x29, w17, w26, x5 + umlal v22.2D, v4.2S, v14.2S + add w14, w20, w20, lsl #1; + umlal v22.2D, v10.2S, v13.2S + add w14, w14, w20, lsl #4 + umull x3, w19, w0 + umlal v22.2D, v6.2S, v11.2S + umaddl x29, w7, w21, x29 + usra v21.2D, v24.2D, #25 + umaddl x11, w20, w14, x12 + and v0.16B, v25.16B, v23.16B + umaddl x5, w30, w21, x15 + and v14.16B, v29.16B, v30.16B + umaddl x12, w16, w13, x29 + usra v22.2D, v21.2D, #26 + umaddl x29, w17, w16, x3 + umlal v3.2D, v7.2S, v12.2S + add x9, x26, x26 + and v1.16B, v21.16B, v30.16B // ubignum_of_hreglist 8 + ubignum_of_lreglist 8 // INTERMEDIATE H|L = bc|ad + add x27, x5, x12, lsr #26 + bic v8.16B, v22.16B, v23.16B + umaddl x29, w7, w7, x29 + and v17.16B, v22.16B, v23.16B // ubignum_of_hreglist 9 + ubignum_of_lreglist 9 // INTERMEDIATE H|L = bc|ad + add x5, x25, x27, lsr #25 + usra v3.2D, v8.2D, #25 + umaddl x25, w24, w9, x8 + umlal v9.2D, v10.2S, v26.2S + add x8, x13, x13 + trn1 v22.4S, v1.4S, v17.4S + umaddl x11, w10, w8, x11 + usra v3.2D, v8.2D, #24 + umull x20, w19, w16 + add v26.2S, v22.2S, v18.2S + ldr d28, [mask2] + umlal v9.2D, v6.2S, v12.2S + umaddl x3, w23, w0, x11 + usra v3.2D, v8.2D, #21 + umaddl x29, w10, w26, x29 + uzp1 v11.4S, v20.4S, v27.4S + umaddl x20, w2, w4, x20 + umaddl x9, w10, w21, x20 + mov v17.d[0], v22.d[1] + usra v9.2D, v3.2D, #26 + umull x15, w19, w13 + and v7.16B, v3.16B, v30.16B // ubignum_of_hreglist 0 + ubignum_of_lreglist 0 // INTERMEDIATE H|L = bc|ad + add x11, x16, x16 + uzp2 v1.4S, v11.4S, v5.4S + umaddl x20, w23, w13, x9 + and v8.16B, v9.16B, v23.16B // ubignum_of_hreglist 1 + ubignum_of_lreglist 1 // INTERMEDIATE H|L = bc|ad + umaddl x9, w2, w0, x15 + usra v14.2D, v9.2D, #25 + and x6, x6, #0x3ffffff + uzp1 v7.4S, v7.4S, v8.4S + umaddl x29, w23, w21, x29 + uzp1 v27.4S, v11.4S, v5.4S + umull x15, w19, w26 + usra v0.2D, v14.2D, #26 // ubignum_of_hreglist 3 + ubignum_of_lreglist 3 // INTERMEDIATE H|L = bc|ad + add x6, x6, x22, lsr #25 + and v3.16B, v14.16B, v30.16B // ubignum_of_hreglist 2 + ubignum_of_lreglist 2 // INTERMEDIATE H|L = bc|ad + bic x22, x27, #0x1ffffff + sub v2.2S, v26.2S, v17.2S + add v9.2S, v22.2S, v17.2S + uzp1 v14.4S, v3.4S, v0.4S + umaddl x2, w2, w21, x15 + add v5.4S, v27.4S, v18.4S + add x5, x5, x22, lsr #24 + zip1 v22.2S, v2.2S, v9.2S // ubignum_of_h32reglist 8 + ubignum_of_l32reglist 8 // INTERMEDIATE H|L = t1|t2 + mov v18.b[0], v28.b[0] + uzp1 v8.4S, v7.4S, v14.4S + add x22, x5, x22, lsr #21 + uzp2 v3.4S, v7.4S, v14.4S + umaddl x5, w7, w16, x9 + add v25.4S, v8.4S, v18.4S + umaddl x15, w14, w0, x22 + add v12.4S, v27.4S, v1.4S + add x9, x17, x17 + sub v14.4S, v5.4S, v1.4S + umull x19, w19, w17 + sub v18.4S, v25.4S, v3.4S + ldr x22, [tmpa+8] + add v20.4S, v8.4S, v3.4S + umaddl x15, w10, w11, x15 + zip1 v16.4S, v14.4S, v12.4S // ubignum_of_h32reglist 4 + ubignum_of_l32reglist 4 // INTERMEDIATE H|L = t1|t2 + umaddl x14, w14, w13, x19 + zip2 v14.4S, v14.4S, v12.4S // ubignum_of_h32reglist 6 + ubignum_of_l32reglist 6 // INTERMEDIATE H|L = t1|t2 + and x17, x27, #0x1ffffff + zip2 v0.4S, v18.4S, v20.4S // ubignum_of_h32reglist 2 + ubignum_of_l32reglist 2 // INTERMEDIATE H|L = t1|t2 + umaddl x15, w23, w4, x15 + zip1 v1.4S, v18.4S, v20.4S // ubignum_of_h32reglist 0 + ubignum_of_l32reglist 0 // INTERMEDIATE H|L = t1|t2 + umaddl x10, w10, w0, x14 + zip2 v5.2S, v2.2S, v9.2S // ubignum_of_h32reglist 9 + ubignum_of_l32reglist 9 // INTERMEDIATE H|L = t1|t2 + shl v24.2S, v0.2S, #1 + mov v19.d[0], v1.d[1] // ubignum_of_h32reglist 1 + ubignum_of_l32reglist 1 // INTERMEDIATE H|L = t1|t2 + shl v26.2S, v22.2S, #1 + shl v17.2S, v16.2S, #1 + mov v15.d[0], v0.d[1] // ubignum_of_h32reglist 3 + ubignum_of_l32reglist 3 // INTERMEDIATE H|L = t1|t2 + shl v7.2S, v5.2S, #1 + shl v18.2S, v19.2S, #1 + umull v11.2D, v1.2S, v24.2S + umaddl x19, w23, w16, x10 + umull v6.2D, v1.2S, v17.2S + umaddl x10, w7, w13, x2 + mov v4.d[0], v16.d[1] // ubignum_of_h32reglist 5 + ubignum_of_l32reglist 5 // INTERMEDIATE H|L = t1|t2 + mov v10.d[0], v14.d[1] // ubignum_of_h32reglist 7 + ubignum_of_l32reglist 7 // INTERMEDIATE H|L = t1|t2 + umull v9.2D, v1.2S, v26.2S + ldr x13, [tmpa+0] + shl v28.2S, v15.2S, #1 + shl v3.2S, v10.2S, #1 + ldr x14, [tmpa+16] + mul v12.2S, v10.2S, v31.2S + umull v25.2D, v1.2S, v7.2S + ldr x2, [tmpa+24] + umlal v6.2D, v18.2S, v28.2S + umaddl x27, w30, w0, x10 + umaddl x16, w24, w0, x20 + shl v13.2S, v14.2S, #1 + umaddl x5, w23, w26, x5 + mul v2.2S, v22.2S, v31.2S + umull v21.2D, v1.2S, v13.2S + umaddl x23, w24, w8, x29 + umlal v11.2D, v18.2S, v19.2S + mov x10, #0x07fffffe07fffffe + sub x10, x10, #2 + umaddl x26, w24, w21, x5 + mul v29.2S, v14.2S, v31.2S + umlal v25.2D, v19.2S, v26.2S + add x7, x1, x6, lsr #26 + mul v20.2S, v4.2S, v31.2S + and x6, x6, #0x3ffffff + shl v8.2S, v18.2S, #1 + shl v4.2S, v4.2S, #1 + umlal v11.2D, v29.2S, v14.2S + bfi x6, x7, #32, #26 // ubignum_of_preglist 4 // INTERMEDIATE aa + umlal v25.2D, v0.2S, v3.2S + umaddl x0, w24, w4, x19 + umlal v25.2D, v15.2S, v13.2S + str x6, [tmpa+32] + umlal v21.2D, v18.2S, v4.2S + umaddl x8, w24, w11, x3 + umlal v21.2D, v0.2S, v17.2S + ldr x30, [tmpa+32] + mul v14.2S, v5.2S, v31.2S + add x2, x2, x10 + shl v5.2S, v28.2S, #1 + shl v27.2S, v4.2S, #1 + umlal v6.2D, v0.2S, v0.2S + umaddl x11, w24, w9, x15 + umlal v6.2D, v12.2S, v3.2S + add x4, x30, x10 + umlal v11.2D, v14.2S, v5.2S + add x3, x22, x10 + umlal v11.2D, v2.2S, v17.2S + add x6, x0, x11, lsr #26 + umlal v11.2D, v12.2S, v27.2S + add x14, x14, x10 + umlal v6.2D, v14.2S, v27.2S + add x8, x8, x6, lsr #25 + umlal v6.2D, v2.2S, v13.2S + movk x10, #0xffb4 + umlal v25.2D, v16.2S, v4.2S + add x29, x16, x8, lsr #26 + umull v27.2D, v1.2S, v3.2S + and x11, x11, #0x3ffffff + umlal v9.2D, v18.2S, v3.2S + add x19, x13, x10 + umlal v9.2D, v0.2S, v13.2S + and x5, x8, #0x3ffffff + umlal v9.2D, v28.2S, v4.2S + bfi x11, x6, #32, #25 // ubignum_of_preglist 0 // INTERMEDIATE bb + umlal v9.2D, v16.2S, v16.2S + umaddl x30, w24, w28, x27 + umlal v9.2D, v14.2S, v7.2S + sub x13, x19, x11 + umull v10.2D, v1.2S, v18.2S + add x7, x23, x29, lsr #25 + umlal v21.2D, v28.2S, v15.2S + lsr x16, x13, #32 // ubignum_of_wreglist 1 + ubignum_of_wreglist 0 // INTERMEDIATE e + umlal v21.2D, v2.2S, v22.2S + add x0, x26, x7, lsr #26 + usra v25.2D, v9.2D, #26 + and x20, x7, #0x3ffffff + umull v22.2D, v1.2S, v1.2S + add x8, x25, x0, lsr #25 + umull v7.2D, v1.2S, v28.2S + and x1, x29, #0x1ffffff // ubignum_of_xreglist 3 // INTERMEDIATE bbalt + bic v18.16B, v25.16B, v23.16B + and x19, x8, #0x3ffffff + and v16.16B, v9.16B, v30.16B + and x7, x12, #0x3ffffff + usra v22.2D, v18.2D, #25 + add x10, x30, x8, lsr #26 + umlal v7.2D, v19.2S, v24.2S + bfi x5, x29, #32, #25 // ubignum_of_preglist 1 // INTERMEDIATE bb + and v9.16B, v25.16B, v23.16B + add x27, x7, x10, lsr #25 + usra v22.2D, v18.2D, #24 + mov x21, #60833 + lsl x21, x21, #1 + add x15, x17, x27, lsr #26 + shl v25.2S, v3.2S, #1 + umlal v7.2D, v14.2S, v17.2S + and x29, x27, #0x3ffffff + usra v22.2D, v18.2D, #21 + bfi x29, x15, #32, #26 // ubignum_of_preglist 4 // INTERMEDIATE bb // ***SOURCE*** ubignum_of_xreglist 9 // INTERMEDIATE bbalt + umlal v10.2D, v14.2S, v24.2S + and x17, x6, #0x1ffffff // ubignum_of_xreglist 1 // INTERMEDIATE bbalt + umlal v10.2D, v2.2S, v28.2S + sub x6, x3, x5 + umlal v10.2D, v12.2S, v17.2S + umaddl x25, w16, w21, x17 + umlal v10.2D, v29.2S, v4.2S + mov w12, w5 // ubignum_of_xreglist 2 // INTERMEDIATE bbalt + umlal v22.2D, v20.2S, v4.2S + lsr x26, x6, #32 // ubignum_of_wreglist 3 + ubignum_of_wreglist 2 // INTERMEDIATE e + umlal v22.2D, v14.2S, v8.2S + and x24, x0, #0x1ffffff // ubignum_of_xreglist 5 // INTERMEDIATE bbalt + umlal v22.2D, v2.2S, v24.2S + stp x11, x5, [tmpb+0] + umlal v22.2D, v12.2S, v5.2S + bfi x20, x0, #32, #25 // ubignum_of_preglist 2 // INTERMEDIATE bb + umlal v22.2D, v29.2S, v17.2S + umaddl x12, w6, w21, x12 + umull v18.2D, v1.2S, v4.2S + bfi x19, x10, #32, #25 // ubignum_of_preglist 3 // INTERMEDIATE bb + umlal v7.2D, v2.2S, v4.2S + sub x7, x14, x20 + umlal v27.2D, v19.2S, v13.2S + mov w8, w20 // ubignum_of_xreglist 4 // INTERMEDIATE bbalt + usra v10.2D, v22.2D, #26 + lsr x14, x7, #32 // ubignum_of_wreglist 5 + ubignum_of_wreglist 4 // INTERMEDIATE e + umlal v18.2D, v19.2S, v17.2S + and x28, x10, #0x1ffffff // ubignum_of_xreglist 7 // INTERMEDIATE bbalt + umlal v7.2D, v12.2S, v13.2S + sub x5, x2, x19 + usra v11.2D, v10.2D, #25 + mov w2, w19 // ubignum_of_xreglist 6 // INTERMEDIATE bbalt + umlal v27.2D, v0.2S, v4.2S + umlal v21.2D, v14.2S, v25.2S + sub x23, x4, x29 + usra v7.2D, v11.2D, #26 + mov w0, w29 // ubignum_of_xreglist 8 // INTERMEDIATE bbalt + umlal v18.2D, v0.2S, v28.2S + lsr x22, x23, #32 // ubignum_of_wreglist 9 + ubignum_of_wreglist 8 // INTERMEDIATE e + umlal v27.2D, v15.2S, v17.2S + str x29, [tmpb+32] + usra v6.2D, v7.2D, #25 + mov w17, w11 // ubignum_of_xreglist 0 // INTERMEDIATE bbalt + and v0.16B, v22.16B, v30.16B // ubignum_of_hreglist 0 + ubignum_of_lreglist 0 // INTERMEDIATE H|L = x5|t3 + umaddl x27, w26, w21, x1 + umlal v18.2D, v14.2S, v13.2S + umaddl x30, w23, w21, x0 + umlal v18.2D, v2.2S, v3.2S + lsr x10, x5, #32 // ubignum_of_wreglist 7 + ubignum_of_wreglist 6 // INTERMEDIATE e + and v4.16B, v6.16B, v30.16B // ubignum_of_hreglist 4 + ubignum_of_lreglist 4 // INTERMEDIATE H|L = x5|t3 + and v1.16B, v10.16B, v23.16B // ubignum_of_hreglist 1 + ubignum_of_lreglist 1 // INTERMEDIATE H|L = x5|t3 + umaddl x4, w14, w21, x24 + ldr x0, [tmpa+0] + mov v0.s[1], w0 + lsr x0, x0, #32 + mov v1.s[1], w0 + umaddl x9, w7, w21, x8 + usra v18.2D, v6.2D, #26 + umaddl x24, w10, w21, x28 + and v3.16B, v7.16B, v23.16B // ubignum_of_hreglist 3 + ubignum_of_lreglist 3 // INTERMEDIATE H|L = x5|t3 + umaddl x8, w22, w21, x15 + umlal v27.2D, v14.2S, v26.2S + umaddl x15, w13, w21, x17 + usra v21.2D, v18.2D, #25 + stp x20, x19, [tmpb+16] + and v2.16B, v11.16B, v30.16B // ubignum_of_hreglist 2 + ubignum_of_lreglist 2 // INTERMEDIATE H|L = x5|t3 + lsr x29, x8, #25 + ldr x3, [tmpb+0] + mov v10.s[1], w3 + lsr x3, x3, #32 + mov v11.s[1], w3 + add x17, x15, x29 + usra v27.2D, v21.2D, #26 + add x28, x17, x29, lsl #1 + and v6.16B, v21.16B, v30.16B // ubignum_of_hreglist 6 + ubignum_of_lreglist 6 // INTERMEDIATE H|L = x5|t3 + and x20, x8, #0x1ffffff + and v5.16B, v18.16B, v23.16B // ubignum_of_hreglist 5 + ubignum_of_lreglist 5 // INTERMEDIATE H|L = x5|t3 + add x17, x28, x29, lsl #4 + and v7.16B, v27.16B, v23.16B // ubignum_of_hreglist 7 + ubignum_of_lreglist 7 // INTERMEDIATE H|L = x5|t3 + ldr x3, [tmpb+8] + mov v22.s[1], w3 + lsr x3, x3, #32 + mov v23.s[1], w3 + add x29, x25, x17, lsr #26 + ldr x15, [pointx+0] + mov v10.s[0], w15 + lsr x15, x15, #32 + mov v11.s[0], w15 + and x11, x17, #0x3ffffff // ubignum_of_xreglist 0 // INTERMEDIATE bce + usra v16.2D, v27.2D, #25 + add x8, x12, x29, lsr #25 + ldr x3, [tmpb+16] + mov v14.s[1], w3 + lsr x3, x3, #32 + mov v15.s[1], w3 + and x12, x29, #0x1ffffff // ubignum_of_xreglist 1 // INTERMEDIATE bce + ldr x15, [pointx+8] + mov v22.s[0], w15 + lsr x15, x15, #32 + mov v23.s[0], w15 + add x28, x27, x8, lsr #26 + and v8.16B, v16.16B, v30.16B // ubignum_of_hreglist 8 + ubignum_of_lreglist 8 // INTERMEDIATE H|L = x5|t3 + umull x1, w12, w10 + ldr x3, [tmpb+24] + mov v17.s[1], w3 + lsr x3, x3, #32 + mov v18.s[1], w3 + add x25, x9, x28, lsr #25 + ldr x15, [pointx+16] + mov v14.s[0], w15 + lsr x15, x15, #32 + mov v15.s[0], w15 + umaddl x19, w5, w21, x2 + usra v9.2D, v16.2D, #26 // ubignum_of_hreglist 8 + ubignum_of_lreglist 8 // INTERMEDIATE H|L = x5|t3 + add x2, x4, x25, lsr #26 + ldr x3, [tmpb+32] + mov v24.s[1], w3 + lsr x3, x3, #32 + mov v25.s[1], w3 + umull x3, w12, w23 + ldr x15, [pointx+24] + mov v17.s[0], w15 + lsr x15, x15, #32 + mov v18.s[0], w15 + add x29, x19, x2, lsr #25 + umull v26.2D, v0.2S, v23.2S + and x21, x28, #0x1ffffff // ubignum_of_xreglist 3 // INTERMEDIATE bce + ldr x0, [tmpa+8] + mov v2.s[1], w0 + lsr x0, x0, #32 + mov v3.s[1], w0 + umaddl x27, w21, w5, x3 + ldr x15, [pointx+32] + mov v24.s[0], w15 + lsr x15, x15, #32 + mov v25.s[0], w15 + add x17, x24, x29, lsr #26 + umull v29.2D, v1.2S, v18.2S + and x15, x8, #0x3ffffff // ubignum_of_xreglist 2 // INTERMEDIATE bce + umull v20.2D, v0.2S, v15.2S + add x19, x30, x17, lsr #25 + and x3, x17, #0x1ffffff // ubignum_of_xreglist 7 // INTERMEDIATE bce + mul v12.2S, v25.2S, v31.2S + ldr x0, [tmpa+16] + mov v4.s[1], w0 + lsr x0, x0, #32 + mov v5.s[1], w0 + add x4, x20, x19, lsr #26 // ubignum_of_xreglist 9 // INTERMEDIATE bce + umlal v26.2D, v2.2S, v11.2S + add w28, w3, w3, lsl #1; + umlal v20.2D, v2.2S, v23.2S + add w28, w28, w3, lsl #4 + umull x8, w12, w5 + ldr x0, [tmpa+24] + mov v6.s[1], w0 + lsr x0, x0, #32 + mov v7.s[1], w0 + and x30, x25, #0x3ffffff // ubignum_of_xreglist 4 // INTERMEDIATE bce + mul v16.2S, v18.2S, v31.2S + add w17, w4, w4, lsl #1; + umull v21.2D, v1.2S, v15.2S + add w17, w17, w4, lsl #4 + umaddl x25, w21, w7, x8 + umlal v20.2D, v4.2S, v11.2S + add w8, w21, w21, lsl #1; + ldr x0, [tmpa+32] + add w8, w8, w21, lsl #4 + mov v8.s[1], w0 + lsr x0, x0, #32 + mov v9.s[1], w0 + and x2, x2, #0x1ffffff // ubignum_of_xreglist 5 // INTERMEDIATE bce + umlal v29.2D, v3.2S, v15.2S + umaddl x24, w2, w6, x25 + umull v13.2D, v0.2S, v25.2S + umaddl x25, w2, w7, x27 + umaddl x0, w3, w6, x25 + mul v19.2S, v15.2S, v31.2S + umull v27.2D, v0.2S, v18.2S + umaddl x20, w3, w13, x24 + umlal v20.2D, v6.2S, v12.2S + umaddl x24, w21, w14, x1 + umlal v13.2D, v2.2S, v18.2S + umaddl x9, w4, w13, x0 + umull v25.2D, v0.2S, v11.2S + umaddl x20, w17, w23, x20 + umlal v27.2D, v2.2S, v15.2S + umaddl x0, w2, w26, x24 + umull v28.2D, v1.2S, v11.2S + umull x24, w17, w5 + umlal v29.2D, v5.2S, v23.2S + umaddl x9, w11, w22, x9 + umlal v13.2D, v4.2S, v15.2S + umaddl x27, w3, w16, x0 + umlal v27.2D, v4.2S, v23.2S + umull x0, w17, w14 + umlal v27.2D, v6.2S, v11.2S + umull x4, w12, w14 + umlal v27.2D, v8.2S, v12.2S + umaddl x25, w11, w10, x20 + umlal v27.2D, v1.2S, v17.2S + umaddl x0, w28, w10, x0 + umlal v13.2D, v6.2S, v23.2S + umull x3, w17, w6 + umlal v13.2D, v8.2S, v11.2S + umaddl x1, w21, w26, x4 + umlal v20.2D, v8.2S, v16.2S + umaddl x4, w2, w13, x24 + umlal v28.2D, v3.2S, v12.2S + umaddl x20, w28, w7, x3 + umlal v29.2D, v7.2S, v11.2S + and x3, x19, #0x3ffffff // ubignum_of_xreglist 9 // INTERMEDIATE bce + umlal v29.2D, v9.2S, v12.2S + umaddl x19, w17, w22, x27 + add w27, w2, w2, lsl #1; + mul v18.2S, v24.2S, v31.2S + add w27, w27, w2, lsl #4 + umlal v21.2D, v3.2S, v23.2S + umull x24, w17, w7 + umlal v13.2D, v1.2S, v24.2S + add x19, x19, x19 + shl v29.2D, v29.2D, #1 + umaddl x1, w2, w16, x1 + umull v15.2D, v1.2S, v23.2S + umaddl x0, w27, w22, x0 + umlal v29.2D, v0.2S, v24.2S + umaddl x2, w28, w5, x24 + mul v24.2S, v23.2S, v31.2S + umaddl x4, w28, w23, x4 + umlal v21.2D, v5.2S, v11.2S + umaddl x24, w27, w5, x20 + umlal v20.2D, v1.2S, v14.2S + umaddl x20, w11, w23, x19 + umlal v26.2D, v4.2S, v12.2S + umaddl x19, w27, w23, x2 + umlal v26.2D, v6.2S, v16.2S + umaddl x2, w21, w6, x4 + umlal v29.2D, v2.2S, v17.2S + umaddl x24, w8, w23, x24 + umlal v15.2D, v3.2S, v11.2S + umaddl x0, w21, w16, x0 + umaddl x4, w21, w13, x19 + mul v23.2S, v11.2S, v31.2S + umlal v20.2D, v3.2S, v22.2S + umaddl x2, w12, w7, x2 + umlal v20.2D, v5.2S, v10.2S + umaddl x19, w12, w26, x0 + umlal v29.2D, v4.2S, v14.2S + umaddl x0, w12, w13, x24 + umlal v26.2D, v8.2S, v19.2S + umaddl x20, w15, w5, x20 + umlal v26.2D, v1.2S, v22.2S + umaddl x21, w15, w10, x9 + umlal v26.2D, v3.2S, v10.2S + and x9, x29, #0x3ffffff // ubignum_of_xreglist 6 // INTERMEDIATE bce + umlal v29.2D, v6.2S, v22.2S + umaddl x20, w30, w7, x20 + umaddl x1, w28, w22, x1 + add x24, x19, x19 + umull v11.2D, v1.2S, v12.2S + add w19, w3, w3, lsl #1; + umlal v26.2D, v5.2S, v18.2S + add w19, w19, w3, lsl #4 + umaddl x20, w9, w6, x20 + umlal v29.2D, v8.2S, v10.2S + add w29, w9, w9, lsl #1; + umlal v13.2D, v3.2S, v17.2S + add w29, w29, w9, lsl #4 + umaddl x2, w19, w10, x2 + umlal v11.2D, v3.2S, v16.2S + umaddl x21, w30, w14, x21 + umlal v11.2D, v5.2S, v19.2S + umaddl x20, w3, w13, x20 + umlal v11.2D, v7.2S, v24.2S + umaddl x2, w29, w22, x2 + umlal v11.2D, v9.2S, v23.2S + umaddl x21, w9, w26, x21 + ushr v23.2D, v30.2D, #1 + umaddl x1, w17, w10, x1 + umlal v13.2D, v5.2S, v14.2S + umaddl x24, w19, w5, x24 + umlal v27.2D, v3.2S, v14.2S + umaddl x21, w3, w16, x21 + shl v11.2D, v11.2D, #1 + add w3, w30, w30, lsl #1; + umlal v28.2D, v5.2S, v16.2S + add w3, w3, w30, lsl #4 + umaddl x24, w29, w23, x24 + umlal v28.2D, v7.2S, v19.2S + add x1, x1, x1 + umlal v28.2D, v9.2S, v24.2S + umaddl x1, w11, w5, x1 + umlal v15.2D, v5.2S, v12.2S + umaddl x24, w30, w13, x24 + umlal v15.2D, v7.2S, v16.2S + umaddl x25, w15, w14, x25 + umlal v15.2D, v9.2S, v19.2S + umaddl x1, w15, w7, x1 + shl v28.2D, v28.2D, #1 + umaddl x24, w15, w6, x24 + umlal v21.2D, v7.2S, v12.2S + umaddl x2, w30, w16, x2 + umlal v21.2D, v9.2S, v16.2S + umaddl x25, w30, w26, x25 + shl v15.2D, v15.2D, #1 + umaddl x30, w30, w6, x1 + umlal v28.2D, v0.2S, v22.2S + umaddl x1, w15, w26, x2 + umlal v28.2D, v2.2S, v10.2S + umaddl x2, w9, w16, x25 + shl v21.2D, v21.2D, #1 + umaddl x24, w11, w7, x24 + umlal v15.2D, v0.2S, v14.2S + umaddl x1, w11, w14, x1 + umlal v21.2D, v0.2S, v17.2S + umaddl x25, w9, w13, x30 + umlal v28.2D, v4.2S, v18.2S + umaddl x0, w19, w26, x0 + umlal v25.2D, v2.2S, v12.2S + add x1, x1, x24, lsr #26 + umlal v25.2D, v4.2S, v16.2S + umaddl x30, w19, w22, x2 + umlal v21.2D, v2.2S, v14.2S + umaddl x4, w12, w6, x4 + mul v14.2S, v14.2S, v31.2S + umaddl x25, w19, w23, x25 + and x2, x1, #0x1ffffff + mul v16.2S, v17.2S, v31.2S + umlal v25.2D, v6.2S, v19.2S + umaddl x9, w19, w14, x4 + umlal v13.2D, v7.2S, v22.2S + add x25, x25, x1, lsr #25 + umlal v21.2D, v4.2S, v22.2S + umaddl x0, w29, w14, x0 + umlal v26.2D, v7.2S, v16.2S + add x30, x30, x25, lsr #26 + umlal v26.2D, v9.2S, v14.2S + add w1, w15, w15, lsl #1; + umlal v28.2D, v6.2S, v16.2S + add w1, w1, w15, lsl #4 + add x4, x20, x30, lsr #25 + umlal v28.2D, v8.2S, v14.2S + and x25, x25, #0x3ffffff + umlal v15.2D, v2.2S, v22.2S + add x21, x21, x4, lsr #26 + umlal v11.2D, v0.2S, v10.2S + bfi x25, x30, #32, #25 // ubignum_of_preglist 3 // INTERMEDIATE z4 + umlal v11.2D, v2.2S, v18.2S + bic x30, x21, #0x3ffffff + usra v26.2D, v28.2D, #26 + lsr x20, x30, #26 + umlal v15.2D, v4.2S, v10.2S + add x20, x20, x30, lsr #25 + umlal v15.2D, v6.2S, v18.2S + umaddl x9, w29, w10, x9 + umlal v15.2D, v8.2S, v16.2S + add x30, x20, x30, lsr #22 + umlal v27.2D, v5.2S, v22.2S + umull x20, w17, w26 + umlal v20.2D, v7.2S, v18.2S + umaddl x30, w17, w16, x30 + umlal v20.2D, v9.2S, v16.2S + umaddl x17, w3, w10, x0 + usra v15.2D, v26.2D, #25 + umaddl x0, w28, w14, x20 + umlal v27.2D, v7.2S, v10.2S + umaddl x20, w28, w26, x30 + umlal v27.2D, v9.2S, v18.2S + add w28, w12, w12, lsl #1; + usra v20.2D, v15.2D, #26 + add w28, w28, w12, lsl #4 + umaddl x30, w27, w10, x0 + and v17.16B, v15.16B, v30.16B // ubignum_of_hreglist 4 + ubignum_of_lreglist 4 // INTERMEDIATE H|L = x4|z5 + umaddl x27, w27, w14, x20 + umaddl x0, w8, w10, x27 + mul v12.2S, v22.2S, v31.2S + and v15.16B, v20.16B, v23.16B // ubignum_of_hreglist 5 + ubignum_of_lreglist 5 // INTERMEDIATE H|L = x4|z5 + umaddl x14, w3, w22, x9 + umlal v21.2D, v6.2S, v10.2S + umaddl x27, w8, w22, x30 + trn1 v15.4S, v17.4S, v15.4S // FINAL z3 + umaddl x10, w28, w22, x0 + umlal v11.2D, v4.2S, v16.2S + umaddl x30, w15, w16, x14 + and v26.16B, v26.16B, v23.16B + umaddl x28, w12, w16, x27 + umlal v21.2D, v8.2S, v18.2S + add x10, x10, x10 + umlal v25.2D, v8.2S, v24.2S + umaddl x20, w19, w6, x10 + umlal v25.2D, v1.2S, v10.2S + add x28, x28, x28 + umlal v25.2D, v3.2S, v18.2S + umaddl x28, w19, w7, x28 + usra v21.2D, v20.2D, #25 + umaddl x0, w29, w7, x20 + umlal v11.2D, v6.2S, v14.2S + umaddl x10, w11, w26, x30 + umlal v13.2D, v9.2S, v10.2S + umaddl x19, w29, w5, x28 + usra v27.2D, v21.2D, #26 + umaddl x0, w3, w5, x0 + umlal v25.2D, v5.2S, v16.2S + umaddl x20, w1, w22, x17 + and v20.16B, v28.16B, v30.16B + umaddl x29, w3, w23, x19 + usra v29.2D, v27.2D, #25 + umaddl x3, w1, w23, x0 + and v27.16B, v27.16B, v23.16B // ubignum_of_hreglist 7 + ubignum_of_lreglist 7 // INTERMEDIATE H|L = x4|z5 + umlal v11.2D, v8.2S, v12.2S + umaddl x12, w15, w13, x29 + usra v13.2D, v29.2D, #26 + umaddl x7, w11, w13, x3 + trn1 v6.4S, v6.4S, v7.4S + umaddl x17, w11, w16, x20 + umlal v25.2D, v7.2S, v14.2S + and x23, x4, #0x3ffffff + bic v19.16B, v13.16B, v23.16B + umaddl x19, w11, w6, x12 + and v28.16B, v13.16B, v23.16B // ubignum_of_hreglist 9 + ubignum_of_lreglist 9 // INTERMEDIATE H|L = x4|z5 + add x3, x17, x7, lsr #26 + usra v11.2D, v19.2D, #25 + trn1 v2.4S, v2.4S, v3.4S + add x17, x19, x3, lsr #25 + and v13.16B, v21.16B, v30.16B // ubignum_of_hreglist 6 + ubignum_of_lreglist 6 // INTERMEDIATE H|L = x4|z5 + and x5, x7, #0x3ffffff + usra v11.2D, v19.2D, #24 + add x7, x10, x17, lsr #26 + trn1 v0.4S, v0.4S, v1.4S + and x19, x24, #0x3ffffff + and v21.16B, v29.16B, v30.16B // ubignum_of_hreglist 8 + ubignum_of_lreglist 8 // INTERMEDIATE H|L = x4|z5 + add x29, x19, x7, lsr #25 + usra v11.2D, v19.2D, #21 + bfi x5, x3, #32, #25 // ubignum_of_preglist 0 // INTERMEDIATE z4 + trn1 v17.4S, v13.4S, v27.4S // FINAL z3 + add x19, x2, x29, lsr #26 + trn1 v19.4S, v21.4S, v28.4S // FINAL z3 + and x3, x29, #0x3ffffff + mov v16.d[0], v6.d[1] // FINAL x3 + mov v6.d[0], v17.d[1] // FINAL x2 + trn1 v8.4S, v8.4S, v9.4S + bfi x3, x19, #32, #26 // ubignum_of_preglist 2 // INTERMEDIATE z4 + and v21.16B, v11.16B, v30.16B // ubignum_of_hreglist 0 + ubignum_of_lreglist 0 // INTERMEDIATE H|L = x4|z5 + bfi x23, x21, #32, #26 // ubignum_of_preglist 4 // INTERMEDIATE z4 + mov v18.d[0], v8.d[1] // FINAL x3 + mov v8.d[0], v19.d[1] // FINAL x2 + umlal v25.2D, v9.2S, v12.2S + mov v9.d[0], x23 // FINAL z2 + mov v7.d[0], x25 // FINAL z2 + ldr d29, [mask1] + mov v12.d[0], v2.d[1] // FINAL x3 + trn1 v4.4S, v4.4S, v5.4S + and x17, x17, #0x3ffffff + usra v25.2D, v11.2D, #26 + mov v10.d[0], v0.d[1] // FINAL x3 + mov v14.d[0], v4.d[1] // FINAL x3 + mov v4.d[0], v15.d[1] // FINAL x2 + usra v20.2D, v25.2D, #25 + and v27.16B, v25.16B, v23.16B // ubignum_of_hreglist 1 + ubignum_of_lreglist 1 // INTERMEDIATE H|L = x4|z5 + bfi x17, x7, #32, #25 // ubignum_of_preglist 1 // INTERMEDIATE z4 + mov v5.d[0], x3 // depth 86 + mov v1.d[0], x5 // FINAL z2 + usra v26.2D, v20.2D, #26 // ubignum_of_hreglist 3 + ubignum_of_lreglist 3 // INTERMEDIATE H|L = x4|z5 + and v28.16B, v20.16B, v30.16B // ubignum_of_hreglist 2 + ubignum_of_lreglist 2 // INTERMEDIATE H|L = x4|z5 + trn1 v11.4S, v21.4S, v27.4S // FINAL z3 + trn1 v13.4S, v28.4S, v26.4S // FINAL z3 + mov v0.d[0], v11.d[1] // FINAL x2 + mov v3.d[0], x17 // FINAL z2 + mov v2.d[0], v13.d[1] // FINAL x2 + ldr d28, [mask2] + + ldr x0, [i] + subs x0, x0, #1 + str x0, [i] bcs curve25519_x25519_scalarloop -// Multiplex directly into (xn,zn) then do three pure doubling steps; -// this accounts for the implicit zeroing of the three lowest bits -// of the scalar. On the very last doubling we *fully* reduce zn mod -// p_25519 to ease checking for degeneracy below. - - cmp swap, xzr - mux_4(xn,xm,xn) - mux_4(zn,zm,zn) - - sub_twice4(d,xn,zn) - add_twice4(s,xn,zn) - sqr_4(d,d) - sqr_4(s,s) - sub_twice4(p,s,d) - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - mul_4(xn,s,d) - mul_4(zn,p,e) - - sub_twice4(d,xn,zn) - add_twice4(s,xn,zn) - sqr_4(d,d) - sqr_4(s,s) - sub_twice4(p,s,d) - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - mul_4(xn,s,d) - mul_4(zn,p,e) - - sub_twice4(d,xn,zn) - add_twice4(s,xn,zn) - sqr_4(d,d) - sqr_4(s,s) - sub_twice4(p,s,d) - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - mul_4(xn,s,d) - mul_p25519(zn,p,e) - -// The projective result of the scalar multiplication is now (xn,zn). -// Prepare to call the modular inverse function to get xm = 1/zn +// Repack X2 into the saturated representation as 256-bit value xn. +// This does not fully normalize mod 2^255-19 but stays within 256 bits. + + mov w0, v0.s[0] + mov w1, v0.s[1] + mov w2, v2.s[0] + mov w3, v2.s[1] + mov w4, v4.s[0] + mov w5, v4.s[1] + mov w6, v6.s[0] + mov w7, v6.s[1] + mov w8, v8.s[0] + mov w9, v8.s[1] + + add x0, x0, x1, lsl #26 + add x1, x2, x3, lsl #26 + add x2, x4, x5, lsl #26 + add x3, x6, x7, lsl #26 + add x4, x8, x9, lsl #26 + + adds x0, x0, x1, lsl #51 + lsr x6, x1, #13 + lsl x7, x2, #38 + adcs x1, x6, x7 + lsr x8, x2, #26 + lsl x9, x3, #25 + adcs x2, x8, x9 + lsr x10, x3, #39 + lsl x11, x4, #12 + adc x3, x10, x11 + stp x0, x1, [xn] + stp x2, x3, [xn+16] - add x0, xm +// Repack Z2 into the saturated representation as 256-bit value zn. +// This does not fully normalize mod 2^255-19. However since Z2, +// unlike X2, was not repacked (within the last multiplication) in +// right-to-left order, its top digit can be any 26-bit value, on +// the face of it. To make sure we don't overflow 256 bits here +// we remove b = 25th bit of the 9th digit (now scaled by 2^230 +// giving bit 25 a final weighting of 2^255) and add 19 * b to +// to the bottom of the sum here to compensate mod 2^255-19. + + mov w0, v1.s[0] + mov w1, v1.s[1] + mov w2, v3.s[0] + mov w3, v3.s[1] + mov w4, v5.s[0] + mov w5, v5.s[1] + mov w6, v7.s[0] + mov w7, v7.s[1] + mov w8, v9.s[0] + mov w9, v9.s[1] + + mov w10, #19 + add x0, x0, x1, lsl #26 + tst x9, #0x2000000 + add x1, x2, x3, lsl #26 + csel x10, x10, xzr, ne + add x2, x4, x5, lsl #26 + and x9, x9, #0x1FFFFFF + add x3, x6, x7, lsl #26 + add x0, x0, x10 + add x4, x8, x9, lsl #26 + + adds x0, x0, x1, lsl #51 + lsr x6, x1, #13 + lsl x7, x2, #38 + adcs x1, x6, x7 + lsr x8, x2, #26 + lsl x9, x3, #25 + adcs x2, x8, x9 + lsr x10, x3, #39 + lsl x11, x4, #12 + adc x3, x10, x11 + stp x0, x1, [zn] + stp x2, x3, [zn+16] + +// Because the lowest bit (indeed, the three lowest bits) of the scalar +// were forced to zero, we know that the projective result of the scalar +// multiplication was in (X2,Z2) and is now (xn,zn) in saturated form. +// Prepare to call the modular inverse function to get zn' = 1/zn. + + add x0, zn add x1, zn // Inline copy of bignum_inv_p25519, identical except for stripping out @@ -860,7 +1348,7 @@ curve25519_x25519_scalarloop: // and reclaiming room on the stack. For more details and explanations see // "arm/curve25519/bignum_inv_p25519.S". Note that the stack it uses for // its own temporaries is 128 bytes, so it has no effect on variables -// that are needed in the rest of our computation here: res, xm and zn. +// that are needed in the rest of our computation here: res, xn, and zn. mov x20, x0 mov x10, #0xffffffffffffffed @@ -1891,36 +2379,210 @@ curve25519_x25519_invmidloop: stp x0, x1, [x4] stp x2, x5, [x4, #16] -// Since we eventually want to return 0 when the result is the point at -// infinity, we force xn = 0 whenever zn = 0. This avoids building in a -// dependency on the behavior of modular inverse in out-of-scope cases. - - ldp x0, x1, [zn] - ldp x2, x3, [zn+16] - orr x0, x0, x1 - orr x2, x2, x3 - orr x4, x0, x2 - cmp x4, xzr - ldp x0, x1, [xn] - csel x0, x0, xzr, ne - csel x1, x1, xzr, ne - ldp x2, x3, [xn+16] - stp x0, x1, [xn] - csel x2, x2, xzr, ne - csel x3, x3, xzr, ne - stp x2, x3, [xn+16] - // Now the result is xn * (1/zn), fully reduced modulo p. - - mul_p25519(resx,xn,xm) - -// Restore stack and registers - - add sp, sp, #NSPACE - ldp x23, x24, [sp], 16 - ldp x21, x22, [sp], 16 - ldp x19, x20, [sp], 16 - +// Note that in the degenerate case zn = 0 (mod p_25519), the +// modular inverse code above will produce 1/zn = 0, giving +// the correct overall X25519 result of zero for the point at +// infinity. The multiplication below is just an inlined +// version of bignum_mul_p25519 except for the detailed +// addressing of inputs and outputs + + ldr x17, [res] + + ldp x3, x4, [xn] + ldp x5, x6, [zn] + umull x7, w3, w5 + lsr x0, x3, #32 + umull x15, w0, w5 + lsr x16, x5, #32 + umull x8, w16, w0 + umull x16, w3, w16 + adds x7, x7, x15, lsl #32 + lsr x15, x15, #32 + adc x8, x8, x15 + adds x7, x7, x16, lsl #32 + lsr x16, x16, #32 + adc x8, x8, x16 + mul x9, x4, x6 + umulh x10, x4, x6 + subs x4, x4, x3 + cneg x4, x4, cc + csetm x16, cc + adds x9, x9, x8 + adc x10, x10, xzr + subs x3, x5, x6 + cneg x3, x3, cc + cinv x16, x16, cc + mul x15, x4, x3 + umulh x3, x4, x3 + adds x8, x7, x9 + adcs x9, x9, x10 + adc x10, x10, xzr + cmn x16, #0x1 + eor x15, x15, x16 + adcs x8, x15, x8 + eor x3, x3, x16 + adcs x9, x3, x9 + adc x10, x10, x16 + ldp x3, x4, [xn+16] + ldp x5, x6, [zn+16] + umull x11, w3, w5 + lsr x0, x3, #32 + umull x15, w0, w5 + lsr x16, x5, #32 + umull x12, w16, w0 + umull x16, w3, w16 + adds x11, x11, x15, lsl #32 + lsr x15, x15, #32 + adc x12, x12, x15 + adds x11, x11, x16, lsl #32 + lsr x16, x16, #32 + adc x12, x12, x16 + mul x13, x4, x6 + umulh x14, x4, x6 + subs x4, x4, x3 + cneg x4, x4, cc + csetm x16, cc + adds x13, x13, x12 + adc x14, x14, xzr + subs x3, x5, x6 + cneg x3, x3, cc + cinv x16, x16, cc + mul x15, x4, x3 + umulh x3, x4, x3 + adds x12, x11, x13 + adcs x13, x13, x14 + adc x14, x14, xzr + cmn x16, #0x1 + eor x15, x15, x16 + adcs x12, x15, x12 + eor x3, x3, x16 + adcs x13, x3, x13 + adc x14, x14, x16 + ldp x3, x4, [xn+16] + ldp x15, x16, [xn] + subs x3, x3, x15 + sbcs x4, x4, x16 + csetm x16, cc + ldp x15, x0, [zn] + subs x5, x15, x5 + sbcs x6, x0, x6 + csetm x0, cc + eor x3, x3, x16 + subs x3, x3, x16 + eor x4, x4, x16 + sbc x4, x4, x16 + eor x5, x5, x0 + subs x5, x5, x0 + eor x6, x6, x0 + sbc x6, x6, x0 + eor x16, x0, x16 + adds x11, x11, x9 + adcs x12, x12, x10 + adcs x13, x13, xzr + adc x14, x14, xzr + mul x2, x3, x5 + umulh x0, x3, x5 + mul x15, x4, x6 + umulh x1, x4, x6 + subs x4, x4, x3 + cneg x4, x4, cc + csetm x9, cc + adds x15, x15, x0 + adc x1, x1, xzr + subs x6, x5, x6 + cneg x6, x6, cc + cinv x9, x9, cc + mul x5, x4, x6 + umulh x6, x4, x6 + adds x0, x2, x15 + adcs x15, x15, x1 + adc x1, x1, xzr + cmn x9, #0x1 + eor x5, x5, x9 + adcs x0, x5, x0 + eor x6, x6, x9 + adcs x15, x6, x15 + adc x1, x1, x9 + adds x9, x11, x7 + adcs x10, x12, x8 + adcs x11, x13, x11 + adcs x12, x14, x12 + adcs x13, x13, xzr + adc x14, x14, xzr + cmn x16, #0x1 + eor x2, x2, x16 + adcs x9, x2, x9 + eor x0, x0, x16 + adcs x10, x0, x10 + eor x15, x15, x16 + adcs x11, x15, x11 + eor x1, x1, x16 + adcs x12, x1, x12 + adcs x13, x13, x16 + adc x14, x14, x16 + mov x3, #0x26 + umull x4, w11, w3 + add x4, x4, w7, uxtw + lsr x7, x7, #32 + lsr x11, x11, #32 + umaddl x11, w11, w3, x7 + mov x7, x4 + umull x4, w12, w3 + add x4, x4, w8, uxtw + lsr x8, x8, #32 + lsr x12, x12, #32 + umaddl x12, w12, w3, x8 + mov x8, x4 + umull x4, w13, w3 + add x4, x4, w9, uxtw + lsr x9, x9, #32 + lsr x13, x13, #32 + umaddl x13, w13, w3, x9 + mov x9, x4 + umull x4, w14, w3 + add x4, x4, w10, uxtw + lsr x10, x10, #32 + lsr x14, x14, #32 + umaddl x14, w14, w3, x10 + mov x10, x4 + lsr x0, x14, #31 + mov x5, #0x13 + umaddl x5, w5, w0, x5 + add x7, x7, x5 + adds x7, x7, x11, lsl #32 + extr x3, x12, x11, #32 + adcs x8, x8, x3 + extr x3, x13, x12, #32 + adcs x9, x9, x3 + extr x3, x14, x13, #32 + lsl x5, x0, #63 + eor x10, x10, x5 + adc x10, x10, x3 + mov x3, #0x13 + tst x10, #0x8000000000000000 + csel x3, x3, xzr, pl + subs x7, x7, x3 + sbcs x8, x8, xzr + sbcs x9, x9, xzr + sbc x10, x10, xzr + and x10, x10, #0x7fffffffffffffff + stp x7, x8, [x17] + stp x9, x10, [x17, #16] + +// Restore stack and registers (this will zero the tops of Q8...Q15). + + ldp d8, d9, [regsave+0] + ldp d10, d11, [regsave+16] + ldp d12, d13, [regsave+32] + ldp d14, d15, [regsave+48] + ldp x19, x20, [regsave+64] + ldp x21, x22, [regsave+80] + ldp x23, x24, [regsave+96] + ldp x25, x26, [regsave+112] + ldp x27, x28, [regsave+128] + ldp x29, x30, [regsave+144] + add sp, sp, #NSPACE+160 ret #if defined(__linux__) && defined(__ELF__) diff --git a/arm/curve25519/curve25519_x25519_byte.S b/arm/curve25519/curve25519_x25519_byte.S index 3e3c0337..e6c89128 100644 --- a/arm/curve25519/curve25519_x25519_byte.S +++ b/arm/curve25519/curve25519_x25519_byte.S @@ -1,6 +1,18 @@ // Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved. // SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT-0 +// ********************************************************************** +// This code is substantially derived from Emil Lenngren's implementation +// +// https://github.com/Emill/X25519-AArch64/blob/master/X25519_AArch64.pdf +// https://github.com/Emill/X25519-AArch64 +// +// and the SLOTHY-based re-engineering of that code by Hanno Becker: +// +// https://eprint.iacr.org/2022/1303.pdf +// https://github.com/slothy-optimizer/slothy/tree/main/paper +// ********************************************************************** + // ---------------------------------------------------------------------------- // The x25519 function for curve25519 (byte array arguments) // Inputs scalar[32] (bytes), point[32] (bytes); output res[32] (bytes) @@ -26,671 +38,53 @@ .text .balign 4 -// Size of individual field elements - -#define NUMSIZE 32 - -// Stable homes for the input result argument during the whole body -// and other variables that are only needed prior to the modular inverse. - -#define res x23 -#define i x20 -#define swap x21 - -// Pointers to result x coord to be written - -#define resx res, #0 - -// Pointer-offset pairs for temporaries on stack with some aliasing. - -#define scalar sp, #(0*NUMSIZE) - -#define pointx sp, #(1*NUMSIZE) +// Pointer-offset pairs for temporaries on stack -#define zm sp, #(2*NUMSIZE) -#define sm sp, #(2*NUMSIZE) -#define dpro sp, #(2*NUMSIZE) +#define scalar sp, #0 +#define pointx sp, #32 +#define mask1 sp, #72 +#define mask2 sp, #80 +#define tmpa sp, #88 +#define tmpb sp, #128 +#define xn sp, #128 +#define zn sp, #160 -#define sn sp, #(3*NUMSIZE) - -#define dm sp, #(4*NUMSIZE) - -#define zn sp, #(5*NUMSIZE) -#define dn sp, #(5*NUMSIZE) -#define e sp, #(5*NUMSIZE) - -#define dmsn sp, #(6*NUMSIZE) -#define p sp, #(6*NUMSIZE) - -#define xm sp, #(7*NUMSIZE) -#define dnsm sp, #(7*NUMSIZE) -#define spro sp, #(7*NUMSIZE) - -#define d sp, #(8*NUMSIZE) - -#define xn sp, #(9*NUMSIZE) -#define s sp, #(9*NUMSIZE) +#define res sp, #192 +#define i sp, #200 +#define swap sp, #208 // Total size to reserve on the stack -#define NSPACE (10*NUMSIZE) - -// Macro wrapping up the basic field operation bignum_mul_p25519, only -// trivially different from a pure function call to that subroutine. - -#define mul_p25519(P0,P1,P2) \ - ldp x3, x4, [P1]; \ - ldp x5, x6, [P2]; \ - umull x7, w3, w5; \ - lsr x0, x3, #32; \ - umull x15, w0, w5; \ - lsr x16, x5, #32; \ - umull x8, w16, w0; \ - umull x16, w3, w16; \ - adds x7, x7, x15, lsl #32; \ - lsr x15, x15, #32; \ - adc x8, x8, x15; \ - adds x7, x7, x16, lsl #32; \ - lsr x16, x16, #32; \ - adc x8, x8, x16; \ - mul x9, x4, x6; \ - umulh x10, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x16, cc; \ - adds x9, x9, x8; \ - adc x10, x10, xzr; \ - subs x3, x5, x6; \ - cneg x3, x3, cc; \ - cinv x16, x16, cc; \ - mul x15, x4, x3; \ - umulh x3, x4, x3; \ - adds x8, x7, x9; \ - adcs x9, x9, x10; \ - adc x10, x10, xzr; \ - cmn x16, #0x1; \ - eor x15, x15, x16; \ - adcs x8, x15, x8; \ - eor x3, x3, x16; \ - adcs x9, x3, x9; \ - adc x10, x10, x16; \ - ldp x3, x4, [P1+16]; \ - ldp x5, x6, [P2+16]; \ - umull x11, w3, w5; \ - lsr x0, x3, #32; \ - umull x15, w0, w5; \ - lsr x16, x5, #32; \ - umull x12, w16, w0; \ - umull x16, w3, w16; \ - adds x11, x11, x15, lsl #32; \ - lsr x15, x15, #32; \ - adc x12, x12, x15; \ - adds x11, x11, x16, lsl #32; \ - lsr x16, x16, #32; \ - adc x12, x12, x16; \ - mul x13, x4, x6; \ - umulh x14, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x16, cc; \ - adds x13, x13, x12; \ - adc x14, x14, xzr; \ - subs x3, x5, x6; \ - cneg x3, x3, cc; \ - cinv x16, x16, cc; \ - mul x15, x4, x3; \ - umulh x3, x4, x3; \ - adds x12, x11, x13; \ - adcs x13, x13, x14; \ - adc x14, x14, xzr; \ - cmn x16, #0x1; \ - eor x15, x15, x16; \ - adcs x12, x15, x12; \ - eor x3, x3, x16; \ - adcs x13, x3, x13; \ - adc x14, x14, x16; \ - ldp x3, x4, [P1+16]; \ - ldp x15, x16, [P1]; \ - subs x3, x3, x15; \ - sbcs x4, x4, x16; \ - csetm x16, cc; \ - ldp x15, x0, [P2]; \ - subs x5, x15, x5; \ - sbcs x6, x0, x6; \ - csetm x0, cc; \ - eor x3, x3, x16; \ - subs x3, x3, x16; \ - eor x4, x4, x16; \ - sbc x4, x4, x16; \ - eor x5, x5, x0; \ - subs x5, x5, x0; \ - eor x6, x6, x0; \ - sbc x6, x6, x0; \ - eor x16, x0, x16; \ - adds x11, x11, x9; \ - adcs x12, x12, x10; \ - adcs x13, x13, xzr; \ - adc x14, x14, xzr; \ - mul x2, x3, x5; \ - umulh x0, x3, x5; \ - mul x15, x4, x6; \ - umulh x1, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x9, cc; \ - adds x15, x15, x0; \ - adc x1, x1, xzr; \ - subs x6, x5, x6; \ - cneg x6, x6, cc; \ - cinv x9, x9, cc; \ - mul x5, x4, x6; \ - umulh x6, x4, x6; \ - adds x0, x2, x15; \ - adcs x15, x15, x1; \ - adc x1, x1, xzr; \ - cmn x9, #0x1; \ - eor x5, x5, x9; \ - adcs x0, x5, x0; \ - eor x6, x6, x9; \ - adcs x15, x6, x15; \ - adc x1, x1, x9; \ - adds x9, x11, x7; \ - adcs x10, x12, x8; \ - adcs x11, x13, x11; \ - adcs x12, x14, x12; \ - adcs x13, x13, xzr; \ - adc x14, x14, xzr; \ - cmn x16, #0x1; \ - eor x2, x2, x16; \ - adcs x9, x2, x9; \ - eor x0, x0, x16; \ - adcs x10, x0, x10; \ - eor x15, x15, x16; \ - adcs x11, x15, x11; \ - eor x1, x1, x16; \ - adcs x12, x1, x12; \ - adcs x13, x13, x16; \ - adc x14, x14, x16; \ - mov x3, #0x26; \ - umull x4, w11, w3; \ - add x4, x4, w7, uxtw; \ - lsr x7, x7, #32; \ - lsr x11, x11, #32; \ - umaddl x11, w11, w3, x7; \ - mov x7, x4; \ - umull x4, w12, w3; \ - add x4, x4, w8, uxtw; \ - lsr x8, x8, #32; \ - lsr x12, x12, #32; \ - umaddl x12, w12, w3, x8; \ - mov x8, x4; \ - umull x4, w13, w3; \ - add x4, x4, w9, uxtw; \ - lsr x9, x9, #32; \ - lsr x13, x13, #32; \ - umaddl x13, w13, w3, x9; \ - mov x9, x4; \ - umull x4, w14, w3; \ - add x4, x4, w10, uxtw; \ - lsr x10, x10, #32; \ - lsr x14, x14, #32; \ - umaddl x14, w14, w3, x10; \ - mov x10, x4; \ - lsr x0, x14, #31; \ - mov x5, #0x13; \ - umaddl x5, w5, w0, x5; \ - add x7, x7, x5; \ - adds x7, x7, x11, lsl #32; \ - extr x3, x12, x11, #32; \ - adcs x8, x8, x3; \ - extr x3, x13, x12, #32; \ - adcs x9, x9, x3; \ - extr x3, x14, x13, #32; \ - lsl x5, x0, #63; \ - eor x10, x10, x5; \ - adc x10, x10, x3; \ - mov x3, #0x13; \ - tst x10, #0x8000000000000000; \ - csel x3, x3, xzr, pl; \ - subs x7, x7, x3; \ - sbcs x8, x8, xzr; \ - sbcs x9, x9, xzr; \ - sbc x10, x10, xzr; \ - and x10, x10, #0x7fffffffffffffff; \ - stp x7, x8, [P0]; \ - stp x9, x10, [P0+16] - -// A version of multiplication that only guarantees output < 2 * p_25519. -// This basically skips the +1 and final correction in quotient estimation. - -#define mul_4(P0,P1,P2) \ - ldp x3, x4, [P1]; \ - ldp x5, x6, [P2]; \ - umull x7, w3, w5; \ - lsr x0, x3, #32; \ - umull x15, w0, w5; \ - lsr x16, x5, #32; \ - umull x8, w16, w0; \ - umull x16, w3, w16; \ - adds x7, x7, x15, lsl #32; \ - lsr x15, x15, #32; \ - adc x8, x8, x15; \ - adds x7, x7, x16, lsl #32; \ - lsr x16, x16, #32; \ - adc x8, x8, x16; \ - mul x9, x4, x6; \ - umulh x10, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x16, cc; \ - adds x9, x9, x8; \ - adc x10, x10, xzr; \ - subs x3, x5, x6; \ - cneg x3, x3, cc; \ - cinv x16, x16, cc; \ - mul x15, x4, x3; \ - umulh x3, x4, x3; \ - adds x8, x7, x9; \ - adcs x9, x9, x10; \ - adc x10, x10, xzr; \ - cmn x16, #0x1; \ - eor x15, x15, x16; \ - adcs x8, x15, x8; \ - eor x3, x3, x16; \ - adcs x9, x3, x9; \ - adc x10, x10, x16; \ - ldp x3, x4, [P1+16]; \ - ldp x5, x6, [P2+16]; \ - umull x11, w3, w5; \ - lsr x0, x3, #32; \ - umull x15, w0, w5; \ - lsr x16, x5, #32; \ - umull x12, w16, w0; \ - umull x16, w3, w16; \ - adds x11, x11, x15, lsl #32; \ - lsr x15, x15, #32; \ - adc x12, x12, x15; \ - adds x11, x11, x16, lsl #32; \ - lsr x16, x16, #32; \ - adc x12, x12, x16; \ - mul x13, x4, x6; \ - umulh x14, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x16, cc; \ - adds x13, x13, x12; \ - adc x14, x14, xzr; \ - subs x3, x5, x6; \ - cneg x3, x3, cc; \ - cinv x16, x16, cc; \ - mul x15, x4, x3; \ - umulh x3, x4, x3; \ - adds x12, x11, x13; \ - adcs x13, x13, x14; \ - adc x14, x14, xzr; \ - cmn x16, #0x1; \ - eor x15, x15, x16; \ - adcs x12, x15, x12; \ - eor x3, x3, x16; \ - adcs x13, x3, x13; \ - adc x14, x14, x16; \ - ldp x3, x4, [P1+16]; \ - ldp x15, x16, [P1]; \ - subs x3, x3, x15; \ - sbcs x4, x4, x16; \ - csetm x16, cc; \ - ldp x15, x0, [P2]; \ - subs x5, x15, x5; \ - sbcs x6, x0, x6; \ - csetm x0, cc; \ - eor x3, x3, x16; \ - subs x3, x3, x16; \ - eor x4, x4, x16; \ - sbc x4, x4, x16; \ - eor x5, x5, x0; \ - subs x5, x5, x0; \ - eor x6, x6, x0; \ - sbc x6, x6, x0; \ - eor x16, x0, x16; \ - adds x11, x11, x9; \ - adcs x12, x12, x10; \ - adcs x13, x13, xzr; \ - adc x14, x14, xzr; \ - mul x2, x3, x5; \ - umulh x0, x3, x5; \ - mul x15, x4, x6; \ - umulh x1, x4, x6; \ - subs x4, x4, x3; \ - cneg x4, x4, cc; \ - csetm x9, cc; \ - adds x15, x15, x0; \ - adc x1, x1, xzr; \ - subs x6, x5, x6; \ - cneg x6, x6, cc; \ - cinv x9, x9, cc; \ - mul x5, x4, x6; \ - umulh x6, x4, x6; \ - adds x0, x2, x15; \ - adcs x15, x15, x1; \ - adc x1, x1, xzr; \ - cmn x9, #0x1; \ - eor x5, x5, x9; \ - adcs x0, x5, x0; \ - eor x6, x6, x9; \ - adcs x15, x6, x15; \ - adc x1, x1, x9; \ - adds x9, x11, x7; \ - adcs x10, x12, x8; \ - adcs x11, x13, x11; \ - adcs x12, x14, x12; \ - adcs x13, x13, xzr; \ - adc x14, x14, xzr; \ - cmn x16, #0x1; \ - eor x2, x2, x16; \ - adcs x9, x2, x9; \ - eor x0, x0, x16; \ - adcs x10, x0, x10; \ - eor x15, x15, x16; \ - adcs x11, x15, x11; \ - eor x1, x1, x16; \ - adcs x12, x1, x12; \ - adcs x13, x13, x16; \ - adc x14, x14, x16; \ - mov x3, #0x26; \ - umull x4, w11, w3; \ - add x4, x4, w7, uxtw; \ - lsr x7, x7, #32; \ - lsr x11, x11, #32; \ - umaddl x11, w11, w3, x7; \ - mov x7, x4; \ - umull x4, w12, w3; \ - add x4, x4, w8, uxtw; \ - lsr x8, x8, #32; \ - lsr x12, x12, #32; \ - umaddl x12, w12, w3, x8; \ - mov x8, x4; \ - umull x4, w13, w3; \ - add x4, x4, w9, uxtw; \ - lsr x9, x9, #32; \ - lsr x13, x13, #32; \ - umaddl x13, w13, w3, x9; \ - mov x9, x4; \ - umull x4, w14, w3; \ - add x4, x4, w10, uxtw; \ - lsr x10, x10, #32; \ - lsr x14, x14, #32; \ - umaddl x14, w14, w3, x10; \ - mov x10, x4; \ - lsr x0, x14, #31; \ - mov x5, #0x13; \ - umull x5, w5, w0; \ - add x7, x7, x5; \ - adds x7, x7, x11, lsl #32; \ - extr x3, x12, x11, #32; \ - adcs x8, x8, x3; \ - extr x3, x13, x12, #32; \ - adcs x9, x9, x3; \ - extr x3, x14, x13, #32; \ - lsl x5, x0, #63; \ - eor x10, x10, x5; \ - adc x10, x10, x3; \ - stp x7, x8, [P0]; \ - stp x9, x10, [P0+16] - -// Squaring just giving a result < 2 * p_25519, which is done by -// basically skipping the +1 in the quotient estimate and the final -// optional correction. - -#define sqr_4(P0,P1) \ - ldp x10, x11, [P1]; \ - ldp x12, x13, [P1+16]; \ - umull x2, w10, w10; \ - lsr x14, x10, #32; \ - umull x3, w14, w14; \ - umull x14, w10, w14; \ - adds x2, x2, x14, lsl #33; \ - lsr x14, x14, #31; \ - adc x3, x3, x14; \ - umull x4, w11, w11; \ - lsr x14, x11, #32; \ - umull x5, w14, w14; \ - umull x14, w11, w14; \ - mul x15, x10, x11; \ - umulh x16, x10, x11; \ - adds x4, x4, x14, lsl #33; \ - lsr x14, x14, #31; \ - adc x5, x5, x14; \ - adds x15, x15, x15; \ - adcs x16, x16, x16; \ - adc x5, x5, xzr; \ - adds x3, x3, x15; \ - adcs x4, x4, x16; \ - adc x5, x5, xzr; \ - umull x6, w12, w12; \ - lsr x14, x12, #32; \ - umull x7, w14, w14; \ - umull x14, w12, w14; \ - adds x6, x6, x14, lsl #33; \ - lsr x14, x14, #31; \ - adc x7, x7, x14; \ - umull x8, w13, w13; \ - lsr x14, x13, #32; \ - umull x9, w14, w14; \ - umull x14, w13, w14; \ - mul x15, x12, x13; \ - umulh x16, x12, x13; \ - adds x8, x8, x14, lsl #33; \ - lsr x14, x14, #31; \ - adc x9, x9, x14; \ - adds x15, x15, x15; \ - adcs x16, x16, x16; \ - adc x9, x9, xzr; \ - adds x7, x7, x15; \ - adcs x8, x8, x16; \ - adc x9, x9, xzr; \ - subs x10, x10, x12; \ - sbcs x11, x11, x13; \ - csetm x16, cc; \ - eor x10, x10, x16; \ - subs x10, x10, x16; \ - eor x11, x11, x16; \ - sbc x11, x11, x16; \ - adds x6, x6, x4; \ - adcs x7, x7, x5; \ - adcs x8, x8, xzr; \ - adc x9, x9, xzr; \ - umull x12, w10, w10; \ - lsr x5, x10, #32; \ - umull x13, w5, w5; \ - umull x5, w10, w5; \ - adds x12, x12, x5, lsl #33; \ - lsr x5, x5, #31; \ - adc x13, x13, x5; \ - umull x15, w11, w11; \ - lsr x5, x11, #32; \ - umull x14, w5, w5; \ - umull x5, w11, w5; \ - mul x4, x10, x11; \ - umulh x16, x10, x11; \ - adds x15, x15, x5, lsl #33; \ - lsr x5, x5, #31; \ - adc x14, x14, x5; \ - adds x4, x4, x4; \ - adcs x16, x16, x16; \ - adc x14, x14, xzr; \ - adds x13, x13, x4; \ - adcs x15, x15, x16; \ - adc x14, x14, xzr; \ - adds x4, x2, x6; \ - adcs x5, x3, x7; \ - adcs x6, x6, x8; \ - adcs x7, x7, x9; \ - csetm x16, cc; \ - subs x4, x4, x12; \ - sbcs x5, x5, x13; \ - sbcs x6, x6, x15; \ - sbcs x7, x7, x14; \ - adcs x8, x8, x16; \ - adc x9, x9, x16; \ - mov x10, #0x26; \ - umull x12, w6, w10; \ - add x12, x12, w2, uxtw; \ - lsr x2, x2, #32; \ - lsr x6, x6, #32; \ - umaddl x6, w6, w10, x2; \ - mov x2, x12; \ - umull x12, w7, w10; \ - add x12, x12, w3, uxtw; \ - lsr x3, x3, #32; \ - lsr x7, x7, #32; \ - umaddl x7, w7, w10, x3; \ - mov x3, x12; \ - umull x12, w8, w10; \ - add x12, x12, w4, uxtw; \ - lsr x4, x4, #32; \ - lsr x8, x8, #32; \ - umaddl x8, w8, w10, x4; \ - mov x4, x12; \ - umull x12, w9, w10; \ - add x12, x12, w5, uxtw; \ - lsr x5, x5, #32; \ - lsr x9, x9, #32; \ - umaddl x9, w9, w10, x5; \ - mov x5, x12; \ - lsr x13, x9, #31; \ - mov x11, #0x13; \ - umull x11, w11, w13; \ - add x2, x2, x11; \ - adds x2, x2, x6, lsl #32; \ - extr x10, x7, x6, #32; \ - adcs x3, x3, x10; \ - extr x10, x8, x7, #32; \ - adcs x4, x4, x10; \ - extr x10, x9, x8, #32; \ - lsl x11, x13, #63; \ - eor x5, x5, x11; \ - adc x5, x5, x10; \ - stp x2, x3, [P0]; \ - stp x4, x5, [P0+16] - -// Modular addition with double modulus 2 * p_25519 = 2^256 - 38. -// This only ensures that the result fits in 4 digits, not that it is reduced -// even w.r.t. double modulus. The result is always correct modulo provided -// the sum of the inputs is < 2^256 + 2^256 - 38, so in particular provided -// at least one of them is reduced double modulo. - -#define add_twice4(P0,P1,P2) \ - ldp x3, x4, [P1]; \ - ldp x7, x8, [P2]; \ - adds x3, x3, x7; \ - adcs x4, x4, x8; \ - ldp x5, x6, [P1+16]; \ - ldp x7, x8, [P2+16]; \ - adcs x5, x5, x7; \ - adcs x6, x6, x8; \ - mov x9, #38; \ - csel x9, x9, xzr, cs; \ - adds x3, x3, x9; \ - adcs x4, x4, xzr; \ - adcs x5, x5, xzr; \ - adc x6, x6, xzr; \ - stp x3, x4, [P0]; \ - stp x5, x6, [P0+16] - -// Modular subtraction with double modulus 2 * p_25519 = 2^256 - 38 - -#define sub_twice4(p0,p1,p2) \ - ldp x5, x6, [p1]; \ - ldp x4, x3, [p2]; \ - subs x5, x5, x4; \ - sbcs x6, x6, x3; \ - ldp x7, x8, [p1+16]; \ - ldp x4, x3, [p2+16]; \ - sbcs x7, x7, x4; \ - sbcs x8, x8, x3; \ - mov x4, #38; \ - csel x3, x4, xzr, lo; \ - subs x5, x5, x3; \ - sbcs x6, x6, xzr; \ - sbcs x7, x7, xzr; \ - sbc x8, x8, xzr; \ - stp x5, x6, [p0]; \ - stp x7, x8, [p0+16] - -// Combined z = c * x + y with reduction only < 2 * p_25519 -// where c is initially in the X1 register. It is assumed -// that 19 * (c * x + y) < 2^60 * 2^256 so we don't need a -// high mul in the final part. - -#define cmadd_4(p0,p2,p3) \ - ldp x7, x8, [p2]; \ - ldp x9, x10, [p2+16]; \ - mul x3, x1, x7; \ - mul x4, x1, x8; \ - mul x5, x1, x9; \ - mul x6, x1, x10; \ - umulh x7, x1, x7; \ - umulh x8, x1, x8; \ - umulh x9, x1, x9; \ - umulh x10, x1, x10; \ - adds x4, x4, x7; \ - adcs x5, x5, x8; \ - adcs x6, x6, x9; \ - adc x10, x10, xzr; \ - ldp x7, x8, [p3]; \ - adds x3, x3, x7; \ - adcs x4, x4, x8; \ - ldp x7, x8, [p3+16]; \ - adcs x5, x5, x7; \ - adcs x6, x6, x8; \ - adc x10, x10, xzr; \ - cmn x6, x6; \ - bic x6, x6, #0x8000000000000000; \ - adc x8, x10, x10; \ - mov x9, #19; \ - mul x7, x8, x9; \ - adds x3, x3, x7; \ - adcs x4, x4, xzr; \ - adcs x5, x5, xzr; \ - adc x6, x6, xzr; \ - stp x3, x4, [p0]; \ - stp x5, x6, [p0+16] - -// Multiplex: z := if NZ then x else y - -#define mux_4(p0,p1,p2) \ - ldp x0, x1, [p1]; \ - ldp x2, x3, [p2]; \ - csel x0, x0, x2, ne; \ - csel x1, x1, x3, ne; \ - stp x0, x1, [p0]; \ - ldp x0, x1, [p1+16]; \ - ldp x2, x3, [p2+16]; \ - csel x0, x0, x2, ne; \ - csel x1, x1, x3, ne; \ - stp x0, x1, [p0+16] +#define NSPACE 224 +#define regsave sp, #NSPACE S2N_BN_SYMBOL(curve25519_x25519_byte): -// Save regs and make room for temporaries - - stp x19, x20, [sp, -16]! - stp x21, x22, [sp, -16]! - stp x23, x24, [sp, -16]! - sub sp, sp, #NSPACE +// Save registers and make additional room NSPACE for temporaries. +// We only need to save the low 64-bits of the Q8...Q15 registers +// according to the ABI, so we use a save of the D8...D15 forms. + + sub sp, sp, #NSPACE+160 + stp d8, d9, [regsave+0] + stp d10, d11, [regsave+16] + stp d12, d13, [regsave+32] + stp d14, d15, [regsave+48] + stp x19, x20, [regsave+64] + stp x21, x22, [regsave+80] + stp x23, x24, [regsave+96] + stp x25, x26, [regsave+112] + stp x27, x28, [regsave+128] + stp x29, x30, [regsave+144] // Move the output pointer to a stable place - mov res, x0 + str x0, [res] -// Copy the inputs to the local variables with minimal mangling: -// -// - The scalar is in principle turned into 01xxx...xxx000 but -// in the structure below the special handling of these bits is -// explicit in the main computation; the scalar is just copied. -// -// - The point x coord is reduced mod 2^255 by masking off the -// top bit. In the main loop we only need reduction < 2 * p_25519. +// Copy the scalar to the corresponding local variable while +// mangling it. In principle it becomes 01xxx...xxx000 where +// the xxx are the corresponding bits of the original input +// scalar. We actually don't bother forcing the MSB to zero, +// but rather start the main loop below at 254 instead of 255. ldrb w10, [x1] ldrb w0, [x1, #1] @@ -722,6 +116,7 @@ S2N_BN_SYMBOL(curve25519_x25519_byte): orr x11, x11, x0, lsl #48 ldrb w0, [x1, #15] orr x11, x11, x0, lsl #56 + bic x10, x10, #7 stp x10, x11, [scalar] ldrb w12, [x1, #16] @@ -754,223 +149,1316 @@ S2N_BN_SYMBOL(curve25519_x25519_byte): orr x13, x13, x0, lsl #48 ldrb w0, [x1, #31] orr x13, x13, x0, lsl #56 + orr x13, x13, #0x4000000000000000 stp x12, x13, [scalar+16] - ldrb w10, [x2] +// Discard the MSB of the point X coordinate (this is in +// accordance with the RFC, mod 2^255, *not* 2^255-19). +// Then recode it into the unsaturated base 25.5 form. + + ldrb w4, [x2] ldrb w0, [x2, #1] - orr x10, x10, x0, lsl #8 + orr x4, x4, x0, lsl #8 ldrb w0, [x2, #2] - orr x10, x10, x0, lsl #16 + orr x4, x4, x0, lsl #16 ldrb w0, [x2, #3] - orr x10, x10, x0, lsl #24 + orr x4, x4, x0, lsl #24 ldrb w0, [x2, #4] - orr x10, x10, x0, lsl #32 + orr x4, x4, x0, lsl #32 ldrb w0, [x2, #5] - orr x10, x10, x0, lsl #40 + orr x4, x4, x0, lsl #40 ldrb w0, [x2, #6] - orr x10, x10, x0, lsl #48 + orr x4, x4, x0, lsl #48 ldrb w0, [x2, #7] - orr x10, x10, x0, lsl #56 - ldrb w11, [x2, #8] + orr x4, x4, x0, lsl #56 + ldrb w5, [x2, #8] ldrb w0, [x2, #9] - orr x11, x11, x0, lsl #8 + orr x5, x5, x0, lsl #8 ldrb w0, [x2, #10] - orr x11, x11, x0, lsl #16 + orr x5, x5, x0, lsl #16 ldrb w0, [x2, #11] - orr x11, x11, x0, lsl #24 + orr x5, x5, x0, lsl #24 ldrb w0, [x2, #12] - orr x11, x11, x0, lsl #32 + orr x5, x5, x0, lsl #32 ldrb w0, [x2, #13] - orr x11, x11, x0, lsl #40 + orr x5, x5, x0, lsl #40 ldrb w0, [x2, #14] - orr x11, x11, x0, lsl #48 + orr x5, x5, x0, lsl #48 ldrb w0, [x2, #15] - orr x11, x11, x0, lsl #56 - stp x10, x11, [pointx] + orr x5, x5, x0, lsl #56 - ldrb w12, [x2, #16] + ldrb w6, [x2, #16] ldrb w0, [x2, #17] - orr x12, x12, x0, lsl #8 + orr x6, x6, x0, lsl #8 ldrb w0, [x2, #18] - orr x12, x12, x0, lsl #16 + orr x6, x6, x0, lsl #16 ldrb w0, [x2, #19] - orr x12, x12, x0, lsl #24 + orr x6, x6, x0, lsl #24 ldrb w0, [x2, #20] - orr x12, x12, x0, lsl #32 + orr x6, x6, x0, lsl #32 ldrb w0, [x2, #21] - orr x12, x12, x0, lsl #40 + orr x6, x6, x0, lsl #40 ldrb w0, [x2, #22] - orr x12, x12, x0, lsl #48 + orr x6, x6, x0, lsl #48 ldrb w0, [x2, #23] - orr x12, x12, x0, lsl #56 - ldrb w13, [x2, #24] + orr x6, x6, x0, lsl #56 + ldrb w7, [x2, #24] ldrb w0, [x2, #25] - orr x13, x13, x0, lsl #8 + orr x7, x7, x0, lsl #8 ldrb w0, [x2, #26] - orr x13, x13, x0, lsl #16 + orr x7, x7, x0, lsl #16 ldrb w0, [x2, #27] - orr x13, x13, x0, lsl #24 + orr x7, x7, x0, lsl #24 ldrb w0, [x2, #28] - orr x13, x13, x0, lsl #32 + orr x7, x7, x0, lsl #32 ldrb w0, [x2, #29] - orr x13, x13, x0, lsl #40 + orr x7, x7, x0, lsl #40 ldrb w0, [x2, #30] - orr x13, x13, x0, lsl #48 + orr x7, x7, x0, lsl #48 ldrb w0, [x2, #31] - orr x13, x13, x0, lsl #56 - and x13, x13, #0x7fffffffffffffff + orr x7, x7, x0, lsl #56 + + lsr x12, x4, #51 + lsr x17, x6, #51 + orr x12, x12, x5, lsl #13 + orr x17, x17, x7, lsl #13 + ubfx x8, x7, #12, #26 + ubfx x9, x7, #38, #25 + ubfx x11, x4, #26, #25 + ubfx x13, x5, #13, #25 + lsr x14, x5, #38 + ubfx x16, x6, #25, #26 + and x10, x4, #0x3ffffff + and x12, x12, #0x3ffffff + and x15, x6, #0x1ffffff + and x17, x17, #0x1ffffff + orr x10, x10, x11, lsl #32 + orr x11, x12, x13, lsl #32 + orr x12, x14, x15, lsl #32 + orr x13, x16, x17, lsl #32 + orr x14, x8, x9, lsl #32 + + stp x10, x11, [pointx+0] stp x12, x13, [pointx+16] + str x14, [pointx+32] + +// Initialize (X2,Z2) = (1,0), the identity (projective point at infinity) + + mov x1, #1 + mov v0.d[0], x1 + mov v2.d[0], xzr + mov v4.d[0], xzr + mov v6.d[0], xzr + mov v8.d[0], xzr + + mov v1.d[0], xzr + mov v3.d[0], xzr + mov v5.d[0], xzr + mov v7.d[0], xzr + mov v9.d[0], xzr + +// Initialize (X3,Z3) = (X,1), projective representation of X + + mov v10.d[0], x10 + mov v12.d[0], x11 + mov v14.d[0], x12 + mov v16.d[0], x13 + mov v18.d[0], x14 + + mov v11.d[0], x1 + mov v13.d[0], xzr + mov v15.d[0], xzr + mov v17.d[0], xzr + mov v19.d[0], xzr + +// Set up some constants used repeatedly in the main loop: +// +// Q31 = 0x1300000013 (two 32-bit copies of 19) +// Q30 = 0x3ffffff0000000003ffffff (two 64-bit copies of 2^26-1) +// Q29 = mask1 = (0x07ffffc,0x07fffffe) +// Q28 = mask2 = (0x07ffffb4,0x07fffffe) -// Initialize with explicit doubling in order to handle set bit 254. -// Set swap = 1 and (xm,zm) = (x,1) then double as (xn,zn) = 2 * (x,1). -// We use the fact that the point x coordinate is still in registers. -// Since zm = 1 we could do the doubling with an operation count of -// 2 * S + M instead of 2 * S + 2 * M, but it doesn't seem worth -// the slight complication arising from a different linear combination. - - mov swap, #1 - stp x10, x11, [xm] - stp x12, x13, [xm+16] - stp swap, xzr, [zm] - stp xzr, xzr, [zm+16] - - sub_twice4(d,xm,zm) - add_twice4(s,xm,zm) - sqr_4(d,d) - sqr_4(s,s) - sub_twice4(p,s,d) - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - mul_4(xn,s,d) - mul_4(zn,p,e) - -// The main loop over unmodified bits from i = 253, ..., i = 3 (inclusive). -// This is a classic Montgomery ladder, with the main coordinates only -// reduced mod 2 * p_25519, some intermediate results even more loosely. - - mov i, #253 - -curve25519_x25519_byte_scalarloop: - -// sm = xm + zm; sn = xn + zn; dm = xm - zm; dn = xn - zn - - sub_twice4(dm,xm,zm) - add_twice4(sn,xn,zn) - sub_twice4(dn,xn,zn) - add_twice4(sm,xm,zm) - -// ADDING: dmsn = dm * sn -// DOUBLING: mux d = xt - zt and s = xt + zt for appropriate choice of (xt,zt) - - mul_4(dmsn,sn,dm) - - lsr x0, i, #6 - ldr x2, [sp, x0, lsl #3] // Exploiting scalar = sp exactly - lsr x2, x2, i - and x2, x2, #1 - - cmp swap, x2 - mov swap, x2 - - mux_4(d,dm,dn) - mux_4(s,sm,sn) - -// ADDING: dnsm = sm * dn - - mul_4(dnsm,sm,dn) - -// DOUBLING: d = (xt - zt)^2 - - sqr_4(d,d) - -// ADDING: dpro = (dmsn - dnsm)^2, spro = (dmsn + dnsm)^2 -// DOUBLING: s = (xt + zt)^2 - - sub_twice4(dpro,dmsn,dnsm) - sqr_4(s,s) - add_twice4(spro,dmsn,dnsm) - sqr_4(dpro,dpro) - -// DOUBLING: p = 4 * xt * zt = s - d - - sub_twice4(p,s,d) - -// ADDING: xm' = (dmsn + dnsm)^2 - - sqr_4(xm,spro) - -// DOUBLING: e = 121666 * p + d - - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) + mov w0, #19 + add x0, x0, x0, lsl #32 + mov v31.d[0], x0 + mov v31.d[1], xzr -// DOUBLING: xn' = (xt + zt)^2 * (xt - zt)^2 = s * d + mov x0, #(1<<26)-1 + mov v30.d[0], x0 + mov v30.d[1], x0 - mul_4(xn,s,d) + mov x0, #0x07fffffe07fffffe + sub x1, x0, #0xfe-0xb4 + sub x0, x0, #2 -// ADDING: zm' = x * (dmsn - dnsm)^2 + stp x0, x1, [mask1] + ldp d29, d28, [mask1] - mul_4(zm,dpro,pointx) +// The main loop over (modified) bits from i = 254, ..., i = 0 (inclusive); +// we explicitly skip bit 255 because it should be forced to zero initially. +// This is a classic Montgomery ladder using a "swap" variable. +// It's assumed x0 = i at the start of the loop, but that is volatile and +// needs to be reloaded from memory at the end of the loop. -// DOUBLING: zn' = (4 * xt * zt) * ((xt - zt)^2 + 121666 * (4 * xt * zt)) -// = p * (d + 121666 * p) + str xzr, [swap] + mov x0, #254 + str x0, [i] - mul_4(zn,p,e) +curve25519_x25519_byte_scalarloop: -// Loop down as far as 3 (inclusive) + lsr x1, x0, #6 + ldr x2, [sp, x1, lsl #3] // Exploiting scalar = sp exactly + lsr x2, x2, x0 + and x2, x2, #1 - sub i, i, #1 - cmp i, #3 + ldr x0, [swap] + cmp x0, x2 + str x2, [swap] + +// The following inner loop code is derived closely following Lenngren's +// implementation available at "https://github.com/Emill/X25519-AArch64". +// In particular, the basic dataflow and the organization between integer +// and SIMD units is identical, with only a few minor changes to some +// individual instructions (for miscellaneous reasons). The scheduling +// was redone from scratch by SLOTHY starting from Hanno Becker's +// un-interleaved form and using the same scripts as in Becker et al's +// paper. +// +// The intermediate value annotations were added to provide data that +// is used in the formal proof, indicating which lines assign specific +// digits of the various intermediate results (mainly of field +// operations, sometimes other transformations). The names used for +// the intermediate results are similar but not identical to those in +// the abstract Algorithm 1 description in Lenngren's paper. Almost +// all equations are to be interpreted as field operations, i.e. as +// arithmetic modulo 2^255-19, not simple numeric equalities. +// +// b = x2 - z2 +// d = x3 - z3 +// a = x2 + z2 +// c = x3 + z3 +// f = if flip then c else a +// g = if flip then d else b +// aa = f^2 +// bb = g^2 +// bbalt = bb (change of representation) +// e = aa - bb +// bce = bbalt + 121666 * e +// z4 = bce * e +// bc = b * c +// ad = a * d +// t1 = ad + bc +// t2 = ad - bc +// x5 = t1^2 +// t3 = t2^2 +// x4 = aa * bb +// z5 = x * t3 +// +// Then the main variables are updated for the next iteration as +// +// (x2',z2') = (x4,z4) +// (x3',z3') = (x5,z5) + + add v22.2S, v2.2S, v3.2S // ubignum_of_qreglist 1 // INTERMEDIATE a + sub v21.2S, v28.2S, v1.2S + add v25.2S, v0.2S, v1.2S // ubignum_of_qreglist 0 // INTERMEDIATE a + sub v24.2S, v29.2S, v3.2S + add v3.2S, v18.2S, v19.2S // ubignum_of_qreglist 4 // INTERMEDIATE c + add v0.2S, v0.2S, v21.2S // ubignum_of_qreglist 0 // INTERMEDIATE b + sub v20.2S, v29.2S, v15.2S + sub v1.2S, v29.2S, v5.2S + sub v26.2S, v28.2S, v11.2S + sub v21.2S, v29.2S, v19.2S + add v19.2S, v10.2S, v11.2S // ubignum_of_qreglist 0 // INTERMEDIATE c + add v11.2S, v14.2S, v20.2S // ubignum_of_qreglist 2 // INTERMEDIATE d + add v21.2S, v18.2S, v21.2S // ubignum_of_qreglist 4 // INTERMEDIATE d + sub v20.2S, v29.2S, v17.2S + add v18.2S, v2.2S, v24.2S // ubignum_of_qreglist 1 // INTERMEDIATE b + add v14.2S, v14.2S, v15.2S // ubignum_of_qreglist 2 // INTERMEDIATE c + add v15.2S, v16.2S, v17.2S // ubignum_of_qreglist 3 // INTERMEDIATE c + add v2.2S, v16.2S, v20.2S // ubignum_of_qreglist 3 // INTERMEDIATE d + add v24.2S, v12.2S, v13.2S // ubignum_of_qreglist 1 // INTERMEDIATE c + add v26.2S, v10.2S, v26.2S // ubignum_of_qreglist 0 // INTERMEDIATE d + sub v10.2S, v29.2S, v13.2S + sub v13.2S, v29.2S, v7.2S + add v23.2S, v6.2S, v7.2S // ubignum_of_qreglist 3 // INTERMEDIATE a + sub v7.2S, v29.2S, v9.2S + add v27.2S, v12.2S, v10.2S // ubignum_of_qreglist 1 // INTERMEDIATE d + fcsel d20, d22, d24, eq // ubignum_of_qreglist 1 // INTERMEDIATE f + add v28.2S, v4.2S, v5.2S // ubignum_of_qreglist 2 // INTERMEDIATE a + fcsel d12, d23, d15, eq // ubignum_of_qreglist 3 // INTERMEDIATE f + add v7.2S, v8.2S, v7.2S // ubignum_of_qreglist 4 // INTERMEDIATE b + fcsel d16, d25, d19, eq // ubignum_of_qreglist 0 // INTERMEDIATE f + mov x0, v20.d[0] + fcsel d5, d28, d14, eq // ubignum_of_qreglist 2 // INTERMEDIATE f + mov x21, v12.d[0] + fcsel d29, d7, d21, eq // ubignum_of_qreglist 4 // INTERMEDIATE g + mov x5, v16.d[0] + lsr x26, x0, #32 + add x29, x21, x21 + umull x15, w5, w29 + add v13.2S, v6.2S, v13.2S // ubignum_of_qreglist 3 // INTERMEDIATE b + add x12, x26, x26 + mov x30, v5.d[0] + fcsel d10, d18, d27, eq // ubignum_of_qreglist 1 // INTERMEDIATE g + lsr x11, x5, #32 + lsr x10, x30, #32 + trn2 v20.2S, v21.2S, v3.2S + add v9.2S, v8.2S, v9.2S // ubignum_of_qreglist 4 // INTERMEDIATE a + add x14, x11, x11 + trn2 v6.2S, v2.2S, v15.2S + trn1 v12.2S, v25.2S, v0.2S + add v1.2S, v4.2S, v1.2S // ubignum_of_qreglist 2 // INTERMEDIATE b + trn1 v16.2S, v23.2S, v13.2S + fcsel d8, d13, d2, eq // ubignum_of_qreglist 3 // INTERMEDIATE g + trn2 v17.2S, v27.2S, v24.2S + str d29, [tmpb+32] + add x17, x10, x10 + trn2 v4.2S, v28.2S, v1.2S + trn1 v5.2S, v28.2S, v1.2S + trn1 v28.2S, v2.2S, v15.2S + trn1 v2.2S, v22.2S, v18.2S + fcsel d29, d0, d26, eq // ubignum_of_qreglist 0 // INTERMEDIATE g + trn2 v15.2S, v22.2S, v18.2S + umull v22.2D, v12.2S, v20.2S + umull x22, w30, w17 + stp d29, d10, [tmpb+0] + trn2 v10.2S, v23.2S, v13.2S + trn2 v23.2S, v11.2S, v14.2S + trn1 v13.2S, v27.2S, v24.2S + fcsel d27, d1, d11, eq // ubignum_of_qreglist 2 // INTERMEDIATE g + trn1 v14.2S, v11.2S, v14.2S + umlal v22.2D, v2.2S, v6.2S + umull x25, w30, w30 + umlal v22.2D, v5.2S, v23.2S + add x3, x30, x30 + umlal v22.2D, v16.2S, v17.2S + add w30, w21, w21, lsl #1; + stp d27, d8, [tmpb+16] + add w30, w30, w21, lsl #4 + trn1 v11.2S, v26.2S, v19.2S + trn2 v8.2S, v26.2S, v19.2S + trn2 v19.2S, v25.2S, v0.2S + mul v29.2S, v20.2S, v31.2S + ldr x20, [tmpb+24] + umull v25.2D, v19.2S, v6.2S + add x1, x0, x0 + umull v27.2D, v19.2S, v23.2S + umull x9, w5, w1 + umull v0.2D, v12.2S, v23.2S + lsr x24, x20, #32 + mul v20.2S, v23.2S, v31.2S + lsr x16, x21, #32 + umlal v25.2D, v15.2S, v23.2S + umaddl x13, w11, w14, x9 + umlal v25.2D, v4.2S, v17.2S + umaddl x9, w14, w17, x15 + umull v24.2D, v12.2S, v6.2S + add w2, w16, w16, lsl #1; + fcsel d26, d9, d3, eq // ubignum_of_qreglist 4 // INTERMEDIATE f + add w2, w2, w16, lsl #4 + trn1 v18.2S, v21.2S, v3.2S + umull v3.2D, v19.2S, v29.2S + umull x28, w5, w3 + mul v1.2S, v6.2S, v31.2S + umull x8, w5, w5 + umlal v24.2D, v2.2S, v23.2S + umaddl x13, w21, w30, x13 + mul v23.2S, v17.2S, v31.2S + umaddl x27, w14, w12, x28 + trn2 v6.2S, v9.2S, v7.2S + mov x6, v26.d[0] + umlal v3.2D, v15.2S, v1.2S + add x16, x16, x16 + umlal v3.2D, v4.2S, v20.2S + lsr x4, x6, #32 + umlal v3.2D, v10.2S, v23.2S + add x7, x6, x6 + umull v26.2D, v19.2S, v8.2S + add x23, x4, x4 + umaddl x28, w5, w23, x22 + trn1 v7.2S, v9.2S, v7.2S + umlal v27.2D, v15.2S, v17.2S + add w15, w4, w4, lsl #1; + umlal v27.2D, v4.2S, v8.2S + add w15, w15, w4, lsl #4 + add w22, w10, w10, lsl #1; + umlal v24.2D, v5.2S, v17.2S + add w22, w22, w10, lsl #4 + umaddl x10, w11, w7, x28 + umlal v25.2D, v10.2S, v8.2S + umull x21, w5, w16 + umlal v25.2D, v6.2S, v29.2S + umaddl x23, w15, w23, x25 + umlal v27.2D, v10.2S, v29.2S + umull x19, w5, w12 + umlal v27.2D, v6.2S, v1.2S + umaddl x25, w11, w29, x21 + umlal v0.2D, v2.2S, v17.2S + umaddl x28, w0, w3, x9 + shl v21.2D, v25.2D, #1 + umaddl x4, w11, w1, x19 + umaddl x21, w2, w29, x4 + mul v25.2S, v8.2S, v31.2S + umlal v24.2D, v16.2S, v8.2S + umaddl x19, w0, w17, x25 + umlal v24.2D, v7.2S, v29.2S + umull x25, w5, w17 + umlal v24.2D, v19.2S, v28.2S + umaddl x4, w0, w16, x10 + umull v9.2D, v12.2S, v8.2S + umaddl x23, w5, w7, x23 + umlal v21.2D, v12.2S, v18.2S + add w10, w6, w6, lsl #1; + shl v27.2D, v27.2D, #1 + add w10, w10, w6, lsl #4 + umaddl x28, w26, w12, x28 + umlal v26.2D, v15.2S, v29.2S + umaddl x9, w14, w16, x23 + umlal v9.2D, v2.2S, v29.2S + umaddl x22, w22, w17, x8 + umlal v21.2D, v2.2S, v28.2S + umaddl x28, w6, w10, x28 + umaddl x27, w0, w0, x27 + add x8, x14, x14 + umlal v0.2D, v5.2S, v8.2S + umull x5, w5, w14 + umlal v9.2D, v5.2S, v1.2S + umaddl x14, w0, w29, x9 + umlal v26.2D, v4.2S, v1.2S + umaddl x6, w2, w16, x27 + umlal v22.2D, v7.2S, v8.2S + umaddl x5, w30, w17, x5 + umaddl x5, w2, w3, x5 + add x23, x17, x17 + umlal v27.2D, v12.2S, v28.2S + umaddl x13, w2, w23, x13 + umlal v26.2D, v10.2S, v20.2S + add x9, x12, x12 + umlal v9.2D, v16.2S, v20.2S + umaddl x27, w10, w29, x6 + umlal v0.2D, v16.2S, v29.2S + umaddl x6, w11, w3, x25 + umlal v22.2D, v19.2S, v18.2S + umaddl x19, w26, w3, x19 + mul v18.2S, v18.2S, v31.2S + umaddl x23, w15, w23, x27 + umlal v3.2D, v6.2S, v25.2S + umaddl x0, w0, w12, x6 + umlal v0.2D, v7.2S, v1.2S + add x11, x16, x16 + umlal v9.2D, v7.2S, v23.2S + umaddl x6, w12, w17, x14 + umlal v9.2D, v19.2S, v11.2S + umaddl x25, w26, w29, x4 + umlal v9.2D, v15.2S, v18.2S + umaddl x14, w10, w3, x13 + umull v25.2D, v12.2S, v17.2S + umaddl x27, w10, w16, x0 + umlal v26.2D, v6.2S, v23.2S + add x0, x25, x6, lsr #26 + mul v23.2S, v28.2S, v31.2S + umaddl x12, w10, w12, x5 + shl v3.2D, v3.2D, #1 + add x16, x22, x0, lsr #25 + umlal v21.2D, v5.2S, v14.2S + bic x22, x0, #0x1ffffff + umlal v3.2D, v12.2S, v11.2S + add x26, x16, x22, lsr #24 + umlal v3.2D, v2.2S, v18.2S + umaddl x16, w10, w17, x21 + umlal v3.2D, v5.2S, v23.2S + add x22, x26, x22, lsr #21 + umlal v9.2D, v4.2S, v23.2S + umaddl x5, w15, w29, x27 + umull v17.2D, v19.2S, v17.2S + umaddl x17, w30, w3, x22 + umlal v25.2D, v2.2S, v8.2S + umaddl x25, w15, w3, x16 + umlal v25.2D, v5.2S, v29.2S + umaddl x26, w15, w7, x19 + umlal v0.2D, v19.2S, v14.2S + umaddl x17, w2, w9, x17 + umlal v17.2D, v15.2S, v8.2S + ldr x19, [tmpb+0] + umlal v17.2D, v4.2S, v29.2S + ldr x7, [tmpb+8] + shl v29.2D, v26.2D, #1 + umaddl x13, w10, w1, x17 + umlal v0.2D, v15.2S, v13.2S + lsr x2, x19, #32 + umlal v29.2D, v12.2S, v13.2S + umaddl x27, w15, w1, x12 + umlal v29.2D, v2.2S, v11.2S + umaddl x30, w15, w8, x13 + umlal v29.2D, v5.2S, v18.2S + add x4, x7, x7 + umlal v29.2D, v16.2S, v23.2S + umaddl x29, w15, w9, x14 + umlal v0.2D, v4.2S, v11.2S + add x17, x27, x30, lsr #26 + umlal v0.2D, v10.2S, v18.2S + umaddl x16, w15, w11, x28 + umlal v0.2D, v6.2S, v23.2S + add x1, x29, x17, lsr #25 + umlal v25.2D, v16.2S, v1.2S + umull x11, w19, w4 + ldr x8, [tmpb+32] + mul v26.2S, v14.2S, v31.2S + umlal v17.2D, v10.2S, v1.2S + ldr x15, [tmpb+16] + umlal v17.2D, v6.2S, v20.2S + and x9, x30, #0x3ffffff + bfi x9, x17, #32, #25 // ubignum_of_preglist 0 // INTERMEDIATE aa + add x17, x2, x2 + lsr x10, x15, #32 + add x27, x25, x1, lsr #26 + umlal v25.2D, v7.2S, v20.2S + add x13, x10, x10 + umlal v25.2D, v19.2S, v13.2S + add x29, x23, x27, lsr #25 + umlal v25.2D, v15.2S, v11.2S + lsr x30, x8, #32 + umlal v25.2D, v4.2S, v18.2S + add x23, x5, x29, lsr #26 + umlal v25.2D, v10.2S, v23.2S + and x14, x29, #0x3ffffff + umlal v25.2D, v6.2S, v26.2S + add x5, x16, x23, lsr #25 + shl v8.2D, v17.2D, #1 + umaddl x12, w2, w17, x11 + and x29, x5, #0x3ffffff + umull x21, w19, w19 + umlal v29.2D, v7.2S, v26.2S + add w16, w10, w10, lsl #1; + umlal v3.2D, v16.2S, v26.2S + add w16, w16, w10, lsl #4 + bfi x14, x23, #32, #25 // ubignum_of_preglist 2 // INTERMEDIATE aa + add w10, w24, w24, lsl #1; + add x22, x26, x5, lsr #26 + add w10, w10, w24, lsl #4 + umlal v8.2D, v12.2S, v14.2S + umaddl x25, w16, w13, x21 + umlal v8.2D, v2.2S, v13.2S + bfi x29, x22, #32, #25 // ubignum_of_preglist 3 // INTERMEDIATE aa + umlal v8.2D, v5.2S, v11.2S + add x26, x24, x24 + umlal v8.2D, v16.2S, v18.2S + stp x14, x29, [tmpa+16] + umlal v8.2D, v7.2S, v23.2S + add w24, w30, w30, lsl #1; + usra v25.2D, v29.2D, #26 + add w24, w24, w30, lsl #4 + umull x29, w15, w15 + umlal v27.2D, v2.2S, v14.2S + umull x3, w15, w13 + umlal v27.2D, v5.2S, v13.2S + add x21, x20, x20 + umlal v24.2D, v15.2S, v14.2S + umull x5, w19, w21 + umlal v24.2D, v4.2S, v13.2S + and x11, x1, #0x3ffffff + usra v8.2D, v25.2D, #25 + and x1, x0, #0x1ffffff + umlal v27.2D, v16.2S, v11.2S + umaddl x23, w17, w13, x5 + umlal v27.2D, v7.2S, v18.2S + add x5, x30, x30 + usra v0.2D, v8.2D, #26 + add x0, x15, x15 + umlal v24.2D, v10.2S, v11.2S + umaddl x23, w7, w0, x23 + umlal v24.2D, v6.2S, v18.2S + lsr x30, x7, #32 + usra v27.2D, v0.2D, #25 + add x16, x30, x30 + and v20.16B, v8.16B, v30.16B // ubignum_of_hreglist 4 + ubignum_of_lreglist 4 // INTERMEDIATE H|L = bc|ad + umaddl x15, w30, w16, x23 + ushr v23.2D, v30.2D, #1 + add w23, w8, w8, lsl #1; + usra v24.2D, v27.2D, #26 + add w23, w23, w8, lsl #4 + umaddl x14, w19, w5, x3 + and v8.16B, v27.16B, v30.16B // ubignum_of_hreglist 6 + ubignum_of_lreglist 6 // INTERMEDIATE H|L = bc|ad + add x28, x8, x8 + and v27.16B, v0.16B, v23.16B // ubignum_of_hreglist 5 + ubignum_of_lreglist 5 // INTERMEDIATE H|L = bc|ad + umaddl x8, w8, w23, x15 + and v5.16B, v24.16B, v23.16B // ubignum_of_hreglist 7 + ubignum_of_lreglist 7 // INTERMEDIATE H|L = bc|ad + umaddl x3, w2, w28, x14 + umlal v22.2D, v15.2S, v28.2S + bfi x11, x27, #32, #25 // ubignum_of_preglist 1 // INTERMEDIATE aa + uzp1 v5.4S, v8.4S, v5.4S + umaddl x14, w24, w5, x29 + umaddl x5, w19, w28, x14 + ldr d18, [mask1] + mov v18.d[1], v18.d[0] + umaddl x15, w7, w26, x3 + mul v12.2S, v13.2S, v31.2S + umlal v21.2D, v16.2S, v13.2S + stp x9, x11, [tmpa+0] + umlal v21.2D, v7.2S, v11.2S + umaddl x29, w17, w26, x5 + umlal v22.2D, v4.2S, v14.2S + add w14, w20, w20, lsl #1; + umlal v22.2D, v10.2S, v13.2S + add w14, w14, w20, lsl #4 + umull x3, w19, w0 + umlal v22.2D, v6.2S, v11.2S + umaddl x29, w7, w21, x29 + usra v21.2D, v24.2D, #25 + umaddl x11, w20, w14, x12 + and v0.16B, v25.16B, v23.16B + umaddl x5, w30, w21, x15 + and v14.16B, v29.16B, v30.16B + umaddl x12, w16, w13, x29 + usra v22.2D, v21.2D, #26 + umaddl x29, w17, w16, x3 + umlal v3.2D, v7.2S, v12.2S + add x9, x26, x26 + and v1.16B, v21.16B, v30.16B // ubignum_of_hreglist 8 + ubignum_of_lreglist 8 // INTERMEDIATE H|L = bc|ad + add x27, x5, x12, lsr #26 + bic v8.16B, v22.16B, v23.16B + umaddl x29, w7, w7, x29 + and v17.16B, v22.16B, v23.16B // ubignum_of_hreglist 9 + ubignum_of_lreglist 9 // INTERMEDIATE H|L = bc|ad + add x5, x25, x27, lsr #25 + usra v3.2D, v8.2D, #25 + umaddl x25, w24, w9, x8 + umlal v9.2D, v10.2S, v26.2S + add x8, x13, x13 + trn1 v22.4S, v1.4S, v17.4S + umaddl x11, w10, w8, x11 + usra v3.2D, v8.2D, #24 + umull x20, w19, w16 + add v26.2S, v22.2S, v18.2S + ldr d28, [mask2] + umlal v9.2D, v6.2S, v12.2S + umaddl x3, w23, w0, x11 + usra v3.2D, v8.2D, #21 + umaddl x29, w10, w26, x29 + uzp1 v11.4S, v20.4S, v27.4S + umaddl x20, w2, w4, x20 + umaddl x9, w10, w21, x20 + mov v17.d[0], v22.d[1] + usra v9.2D, v3.2D, #26 + umull x15, w19, w13 + and v7.16B, v3.16B, v30.16B // ubignum_of_hreglist 0 + ubignum_of_lreglist 0 // INTERMEDIATE H|L = bc|ad + add x11, x16, x16 + uzp2 v1.4S, v11.4S, v5.4S + umaddl x20, w23, w13, x9 + and v8.16B, v9.16B, v23.16B // ubignum_of_hreglist 1 + ubignum_of_lreglist 1 // INTERMEDIATE H|L = bc|ad + umaddl x9, w2, w0, x15 + usra v14.2D, v9.2D, #25 + and x6, x6, #0x3ffffff + uzp1 v7.4S, v7.4S, v8.4S + umaddl x29, w23, w21, x29 + uzp1 v27.4S, v11.4S, v5.4S + umull x15, w19, w26 + usra v0.2D, v14.2D, #26 // ubignum_of_hreglist 3 + ubignum_of_lreglist 3 // INTERMEDIATE H|L = bc|ad + add x6, x6, x22, lsr #25 + and v3.16B, v14.16B, v30.16B // ubignum_of_hreglist 2 + ubignum_of_lreglist 2 // INTERMEDIATE H|L = bc|ad + bic x22, x27, #0x1ffffff + sub v2.2S, v26.2S, v17.2S + add v9.2S, v22.2S, v17.2S + uzp1 v14.4S, v3.4S, v0.4S + umaddl x2, w2, w21, x15 + add v5.4S, v27.4S, v18.4S + add x5, x5, x22, lsr #24 + zip1 v22.2S, v2.2S, v9.2S // ubignum_of_h32reglist 8 + ubignum_of_l32reglist 8 // INTERMEDIATE H|L = t1|t2 + mov v18.b[0], v28.b[0] + uzp1 v8.4S, v7.4S, v14.4S + add x22, x5, x22, lsr #21 + uzp2 v3.4S, v7.4S, v14.4S + umaddl x5, w7, w16, x9 + add v25.4S, v8.4S, v18.4S + umaddl x15, w14, w0, x22 + add v12.4S, v27.4S, v1.4S + add x9, x17, x17 + sub v14.4S, v5.4S, v1.4S + umull x19, w19, w17 + sub v18.4S, v25.4S, v3.4S + ldr x22, [tmpa+8] + add v20.4S, v8.4S, v3.4S + umaddl x15, w10, w11, x15 + zip1 v16.4S, v14.4S, v12.4S // ubignum_of_h32reglist 4 + ubignum_of_l32reglist 4 // INTERMEDIATE H|L = t1|t2 + umaddl x14, w14, w13, x19 + zip2 v14.4S, v14.4S, v12.4S // ubignum_of_h32reglist 6 + ubignum_of_l32reglist 6 // INTERMEDIATE H|L = t1|t2 + and x17, x27, #0x1ffffff + zip2 v0.4S, v18.4S, v20.4S // ubignum_of_h32reglist 2 + ubignum_of_l32reglist 2 // INTERMEDIATE H|L = t1|t2 + umaddl x15, w23, w4, x15 + zip1 v1.4S, v18.4S, v20.4S // ubignum_of_h32reglist 0 + ubignum_of_l32reglist 0 // INTERMEDIATE H|L = t1|t2 + umaddl x10, w10, w0, x14 + zip2 v5.2S, v2.2S, v9.2S // ubignum_of_h32reglist 9 + ubignum_of_l32reglist 9 // INTERMEDIATE H|L = t1|t2 + shl v24.2S, v0.2S, #1 + mov v19.d[0], v1.d[1] // ubignum_of_h32reglist 1 + ubignum_of_l32reglist 1 // INTERMEDIATE H|L = t1|t2 + shl v26.2S, v22.2S, #1 + shl v17.2S, v16.2S, #1 + mov v15.d[0], v0.d[1] // ubignum_of_h32reglist 3 + ubignum_of_l32reglist 3 // INTERMEDIATE H|L = t1|t2 + shl v7.2S, v5.2S, #1 + shl v18.2S, v19.2S, #1 + umull v11.2D, v1.2S, v24.2S + umaddl x19, w23, w16, x10 + umull v6.2D, v1.2S, v17.2S + umaddl x10, w7, w13, x2 + mov v4.d[0], v16.d[1] // ubignum_of_h32reglist 5 + ubignum_of_l32reglist 5 // INTERMEDIATE H|L = t1|t2 + mov v10.d[0], v14.d[1] // ubignum_of_h32reglist 7 + ubignum_of_l32reglist 7 // INTERMEDIATE H|L = t1|t2 + umull v9.2D, v1.2S, v26.2S + ldr x13, [tmpa+0] + shl v28.2S, v15.2S, #1 + shl v3.2S, v10.2S, #1 + ldr x14, [tmpa+16] + mul v12.2S, v10.2S, v31.2S + umull v25.2D, v1.2S, v7.2S + ldr x2, [tmpa+24] + umlal v6.2D, v18.2S, v28.2S + umaddl x27, w30, w0, x10 + umaddl x16, w24, w0, x20 + shl v13.2S, v14.2S, #1 + umaddl x5, w23, w26, x5 + mul v2.2S, v22.2S, v31.2S + umull v21.2D, v1.2S, v13.2S + umaddl x23, w24, w8, x29 + umlal v11.2D, v18.2S, v19.2S + mov x10, #0x07fffffe07fffffe + sub x10, x10, #2 + umaddl x26, w24, w21, x5 + mul v29.2S, v14.2S, v31.2S + umlal v25.2D, v19.2S, v26.2S + add x7, x1, x6, lsr #26 + mul v20.2S, v4.2S, v31.2S + and x6, x6, #0x3ffffff + shl v8.2S, v18.2S, #1 + shl v4.2S, v4.2S, #1 + umlal v11.2D, v29.2S, v14.2S + bfi x6, x7, #32, #26 // ubignum_of_preglist 4 // INTERMEDIATE aa + umlal v25.2D, v0.2S, v3.2S + umaddl x0, w24, w4, x19 + umlal v25.2D, v15.2S, v13.2S + str x6, [tmpa+32] + umlal v21.2D, v18.2S, v4.2S + umaddl x8, w24, w11, x3 + umlal v21.2D, v0.2S, v17.2S + ldr x30, [tmpa+32] + mul v14.2S, v5.2S, v31.2S + add x2, x2, x10 + shl v5.2S, v28.2S, #1 + shl v27.2S, v4.2S, #1 + umlal v6.2D, v0.2S, v0.2S + umaddl x11, w24, w9, x15 + umlal v6.2D, v12.2S, v3.2S + add x4, x30, x10 + umlal v11.2D, v14.2S, v5.2S + add x3, x22, x10 + umlal v11.2D, v2.2S, v17.2S + add x6, x0, x11, lsr #26 + umlal v11.2D, v12.2S, v27.2S + add x14, x14, x10 + umlal v6.2D, v14.2S, v27.2S + add x8, x8, x6, lsr #25 + umlal v6.2D, v2.2S, v13.2S + movk x10, #0xffb4 + umlal v25.2D, v16.2S, v4.2S + add x29, x16, x8, lsr #26 + umull v27.2D, v1.2S, v3.2S + and x11, x11, #0x3ffffff + umlal v9.2D, v18.2S, v3.2S + add x19, x13, x10 + umlal v9.2D, v0.2S, v13.2S + and x5, x8, #0x3ffffff + umlal v9.2D, v28.2S, v4.2S + bfi x11, x6, #32, #25 // ubignum_of_preglist 0 // INTERMEDIATE bb + umlal v9.2D, v16.2S, v16.2S + umaddl x30, w24, w28, x27 + umlal v9.2D, v14.2S, v7.2S + sub x13, x19, x11 + umull v10.2D, v1.2S, v18.2S + add x7, x23, x29, lsr #25 + umlal v21.2D, v28.2S, v15.2S + lsr x16, x13, #32 // ubignum_of_wreglist 1 + ubignum_of_wreglist 0 // INTERMEDIATE e + umlal v21.2D, v2.2S, v22.2S + add x0, x26, x7, lsr #26 + usra v25.2D, v9.2D, #26 + and x20, x7, #0x3ffffff + umull v22.2D, v1.2S, v1.2S + add x8, x25, x0, lsr #25 + umull v7.2D, v1.2S, v28.2S + and x1, x29, #0x1ffffff // ubignum_of_xreglist 3 // INTERMEDIATE bbalt + bic v18.16B, v25.16B, v23.16B + and x19, x8, #0x3ffffff + and v16.16B, v9.16B, v30.16B + and x7, x12, #0x3ffffff + usra v22.2D, v18.2D, #25 + add x10, x30, x8, lsr #26 + umlal v7.2D, v19.2S, v24.2S + bfi x5, x29, #32, #25 // ubignum_of_preglist 1 // INTERMEDIATE bb + and v9.16B, v25.16B, v23.16B + add x27, x7, x10, lsr #25 + usra v22.2D, v18.2D, #24 + mov x21, #60833 + lsl x21, x21, #1 + add x15, x17, x27, lsr #26 + shl v25.2S, v3.2S, #1 + umlal v7.2D, v14.2S, v17.2S + and x29, x27, #0x3ffffff + usra v22.2D, v18.2D, #21 + bfi x29, x15, #32, #26 // ubignum_of_preglist 4 // INTERMEDIATE bb // ***SOURCE*** ubignum_of_xreglist 9 // INTERMEDIATE bbalt + umlal v10.2D, v14.2S, v24.2S + and x17, x6, #0x1ffffff // ubignum_of_xreglist 1 // INTERMEDIATE bbalt + umlal v10.2D, v2.2S, v28.2S + sub x6, x3, x5 + umlal v10.2D, v12.2S, v17.2S + umaddl x25, w16, w21, x17 + umlal v10.2D, v29.2S, v4.2S + mov w12, w5 // ubignum_of_xreglist 2 // INTERMEDIATE bbalt + umlal v22.2D, v20.2S, v4.2S + lsr x26, x6, #32 // ubignum_of_wreglist 3 + ubignum_of_wreglist 2 // INTERMEDIATE e + umlal v22.2D, v14.2S, v8.2S + and x24, x0, #0x1ffffff // ubignum_of_xreglist 5 // INTERMEDIATE bbalt + umlal v22.2D, v2.2S, v24.2S + stp x11, x5, [tmpb+0] + umlal v22.2D, v12.2S, v5.2S + bfi x20, x0, #32, #25 // ubignum_of_preglist 2 // INTERMEDIATE bb + umlal v22.2D, v29.2S, v17.2S + umaddl x12, w6, w21, x12 + umull v18.2D, v1.2S, v4.2S + bfi x19, x10, #32, #25 // ubignum_of_preglist 3 // INTERMEDIATE bb + umlal v7.2D, v2.2S, v4.2S + sub x7, x14, x20 + umlal v27.2D, v19.2S, v13.2S + mov w8, w20 // ubignum_of_xreglist 4 // INTERMEDIATE bbalt + usra v10.2D, v22.2D, #26 + lsr x14, x7, #32 // ubignum_of_wreglist 5 + ubignum_of_wreglist 4 // INTERMEDIATE e + umlal v18.2D, v19.2S, v17.2S + and x28, x10, #0x1ffffff // ubignum_of_xreglist 7 // INTERMEDIATE bbalt + umlal v7.2D, v12.2S, v13.2S + sub x5, x2, x19 + usra v11.2D, v10.2D, #25 + mov w2, w19 // ubignum_of_xreglist 6 // INTERMEDIATE bbalt + umlal v27.2D, v0.2S, v4.2S + umlal v21.2D, v14.2S, v25.2S + sub x23, x4, x29 + usra v7.2D, v11.2D, #26 + mov w0, w29 // ubignum_of_xreglist 8 // INTERMEDIATE bbalt + umlal v18.2D, v0.2S, v28.2S + lsr x22, x23, #32 // ubignum_of_wreglist 9 + ubignum_of_wreglist 8 // INTERMEDIATE e + umlal v27.2D, v15.2S, v17.2S + str x29, [tmpb+32] + usra v6.2D, v7.2D, #25 + mov w17, w11 // ubignum_of_xreglist 0 // INTERMEDIATE bbalt + and v0.16B, v22.16B, v30.16B // ubignum_of_hreglist 0 + ubignum_of_lreglist 0 // INTERMEDIATE H|L = x5|t3 + umaddl x27, w26, w21, x1 + umlal v18.2D, v14.2S, v13.2S + umaddl x30, w23, w21, x0 + umlal v18.2D, v2.2S, v3.2S + lsr x10, x5, #32 // ubignum_of_wreglist 7 + ubignum_of_wreglist 6 // INTERMEDIATE e + and v4.16B, v6.16B, v30.16B // ubignum_of_hreglist 4 + ubignum_of_lreglist 4 // INTERMEDIATE H|L = x5|t3 + and v1.16B, v10.16B, v23.16B // ubignum_of_hreglist 1 + ubignum_of_lreglist 1 // INTERMEDIATE H|L = x5|t3 + umaddl x4, w14, w21, x24 + ldr x0, [tmpa+0] + mov v0.s[1], w0 + lsr x0, x0, #32 + mov v1.s[1], w0 + umaddl x9, w7, w21, x8 + usra v18.2D, v6.2D, #26 + umaddl x24, w10, w21, x28 + and v3.16B, v7.16B, v23.16B // ubignum_of_hreglist 3 + ubignum_of_lreglist 3 // INTERMEDIATE H|L = x5|t3 + umaddl x8, w22, w21, x15 + umlal v27.2D, v14.2S, v26.2S + umaddl x15, w13, w21, x17 + usra v21.2D, v18.2D, #25 + stp x20, x19, [tmpb+16] + and v2.16B, v11.16B, v30.16B // ubignum_of_hreglist 2 + ubignum_of_lreglist 2 // INTERMEDIATE H|L = x5|t3 + lsr x29, x8, #25 + ldr x3, [tmpb+0] + mov v10.s[1], w3 + lsr x3, x3, #32 + mov v11.s[1], w3 + add x17, x15, x29 + usra v27.2D, v21.2D, #26 + add x28, x17, x29, lsl #1 + and v6.16B, v21.16B, v30.16B // ubignum_of_hreglist 6 + ubignum_of_lreglist 6 // INTERMEDIATE H|L = x5|t3 + and x20, x8, #0x1ffffff + and v5.16B, v18.16B, v23.16B // ubignum_of_hreglist 5 + ubignum_of_lreglist 5 // INTERMEDIATE H|L = x5|t3 + add x17, x28, x29, lsl #4 + and v7.16B, v27.16B, v23.16B // ubignum_of_hreglist 7 + ubignum_of_lreglist 7 // INTERMEDIATE H|L = x5|t3 + ldr x3, [tmpb+8] + mov v22.s[1], w3 + lsr x3, x3, #32 + mov v23.s[1], w3 + add x29, x25, x17, lsr #26 + ldr x15, [pointx+0] + mov v10.s[0], w15 + lsr x15, x15, #32 + mov v11.s[0], w15 + and x11, x17, #0x3ffffff // ubignum_of_xreglist 0 // INTERMEDIATE bce + usra v16.2D, v27.2D, #25 + add x8, x12, x29, lsr #25 + ldr x3, [tmpb+16] + mov v14.s[1], w3 + lsr x3, x3, #32 + mov v15.s[1], w3 + and x12, x29, #0x1ffffff // ubignum_of_xreglist 1 // INTERMEDIATE bce + ldr x15, [pointx+8] + mov v22.s[0], w15 + lsr x15, x15, #32 + mov v23.s[0], w15 + add x28, x27, x8, lsr #26 + and v8.16B, v16.16B, v30.16B // ubignum_of_hreglist 8 + ubignum_of_lreglist 8 // INTERMEDIATE H|L = x5|t3 + umull x1, w12, w10 + ldr x3, [tmpb+24] + mov v17.s[1], w3 + lsr x3, x3, #32 + mov v18.s[1], w3 + add x25, x9, x28, lsr #25 + ldr x15, [pointx+16] + mov v14.s[0], w15 + lsr x15, x15, #32 + mov v15.s[0], w15 + umaddl x19, w5, w21, x2 + usra v9.2D, v16.2D, #26 // ubignum_of_hreglist 8 + ubignum_of_lreglist 8 // INTERMEDIATE H|L = x5|t3 + add x2, x4, x25, lsr #26 + ldr x3, [tmpb+32] + mov v24.s[1], w3 + lsr x3, x3, #32 + mov v25.s[1], w3 + umull x3, w12, w23 + ldr x15, [pointx+24] + mov v17.s[0], w15 + lsr x15, x15, #32 + mov v18.s[0], w15 + add x29, x19, x2, lsr #25 + umull v26.2D, v0.2S, v23.2S + and x21, x28, #0x1ffffff // ubignum_of_xreglist 3 // INTERMEDIATE bce + ldr x0, [tmpa+8] + mov v2.s[1], w0 + lsr x0, x0, #32 + mov v3.s[1], w0 + umaddl x27, w21, w5, x3 + ldr x15, [pointx+32] + mov v24.s[0], w15 + lsr x15, x15, #32 + mov v25.s[0], w15 + add x17, x24, x29, lsr #26 + umull v29.2D, v1.2S, v18.2S + and x15, x8, #0x3ffffff // ubignum_of_xreglist 2 // INTERMEDIATE bce + umull v20.2D, v0.2S, v15.2S + add x19, x30, x17, lsr #25 + and x3, x17, #0x1ffffff // ubignum_of_xreglist 7 // INTERMEDIATE bce + mul v12.2S, v25.2S, v31.2S + ldr x0, [tmpa+16] + mov v4.s[1], w0 + lsr x0, x0, #32 + mov v5.s[1], w0 + add x4, x20, x19, lsr #26 // ubignum_of_xreglist 9 // INTERMEDIATE bce + umlal v26.2D, v2.2S, v11.2S + add w28, w3, w3, lsl #1; + umlal v20.2D, v2.2S, v23.2S + add w28, w28, w3, lsl #4 + umull x8, w12, w5 + ldr x0, [tmpa+24] + mov v6.s[1], w0 + lsr x0, x0, #32 + mov v7.s[1], w0 + and x30, x25, #0x3ffffff // ubignum_of_xreglist 4 // INTERMEDIATE bce + mul v16.2S, v18.2S, v31.2S + add w17, w4, w4, lsl #1; + umull v21.2D, v1.2S, v15.2S + add w17, w17, w4, lsl #4 + umaddl x25, w21, w7, x8 + umlal v20.2D, v4.2S, v11.2S + add w8, w21, w21, lsl #1; + ldr x0, [tmpa+32] + add w8, w8, w21, lsl #4 + mov v8.s[1], w0 + lsr x0, x0, #32 + mov v9.s[1], w0 + and x2, x2, #0x1ffffff // ubignum_of_xreglist 5 // INTERMEDIATE bce + umlal v29.2D, v3.2S, v15.2S + umaddl x24, w2, w6, x25 + umull v13.2D, v0.2S, v25.2S + umaddl x25, w2, w7, x27 + umaddl x0, w3, w6, x25 + mul v19.2S, v15.2S, v31.2S + umull v27.2D, v0.2S, v18.2S + umaddl x20, w3, w13, x24 + umlal v20.2D, v6.2S, v12.2S + umaddl x24, w21, w14, x1 + umlal v13.2D, v2.2S, v18.2S + umaddl x9, w4, w13, x0 + umull v25.2D, v0.2S, v11.2S + umaddl x20, w17, w23, x20 + umlal v27.2D, v2.2S, v15.2S + umaddl x0, w2, w26, x24 + umull v28.2D, v1.2S, v11.2S + umull x24, w17, w5 + umlal v29.2D, v5.2S, v23.2S + umaddl x9, w11, w22, x9 + umlal v13.2D, v4.2S, v15.2S + umaddl x27, w3, w16, x0 + umlal v27.2D, v4.2S, v23.2S + umull x0, w17, w14 + umlal v27.2D, v6.2S, v11.2S + umull x4, w12, w14 + umlal v27.2D, v8.2S, v12.2S + umaddl x25, w11, w10, x20 + umlal v27.2D, v1.2S, v17.2S + umaddl x0, w28, w10, x0 + umlal v13.2D, v6.2S, v23.2S + umull x3, w17, w6 + umlal v13.2D, v8.2S, v11.2S + umaddl x1, w21, w26, x4 + umlal v20.2D, v8.2S, v16.2S + umaddl x4, w2, w13, x24 + umlal v28.2D, v3.2S, v12.2S + umaddl x20, w28, w7, x3 + umlal v29.2D, v7.2S, v11.2S + and x3, x19, #0x3ffffff // ubignum_of_xreglist 9 // INTERMEDIATE bce + umlal v29.2D, v9.2S, v12.2S + umaddl x19, w17, w22, x27 + add w27, w2, w2, lsl #1; + mul v18.2S, v24.2S, v31.2S + add w27, w27, w2, lsl #4 + umlal v21.2D, v3.2S, v23.2S + umull x24, w17, w7 + umlal v13.2D, v1.2S, v24.2S + add x19, x19, x19 + shl v29.2D, v29.2D, #1 + umaddl x1, w2, w16, x1 + umull v15.2D, v1.2S, v23.2S + umaddl x0, w27, w22, x0 + umlal v29.2D, v0.2S, v24.2S + umaddl x2, w28, w5, x24 + mul v24.2S, v23.2S, v31.2S + umaddl x4, w28, w23, x4 + umlal v21.2D, v5.2S, v11.2S + umaddl x24, w27, w5, x20 + umlal v20.2D, v1.2S, v14.2S + umaddl x20, w11, w23, x19 + umlal v26.2D, v4.2S, v12.2S + umaddl x19, w27, w23, x2 + umlal v26.2D, v6.2S, v16.2S + umaddl x2, w21, w6, x4 + umlal v29.2D, v2.2S, v17.2S + umaddl x24, w8, w23, x24 + umlal v15.2D, v3.2S, v11.2S + umaddl x0, w21, w16, x0 + umaddl x4, w21, w13, x19 + mul v23.2S, v11.2S, v31.2S + umlal v20.2D, v3.2S, v22.2S + umaddl x2, w12, w7, x2 + umlal v20.2D, v5.2S, v10.2S + umaddl x19, w12, w26, x0 + umlal v29.2D, v4.2S, v14.2S + umaddl x0, w12, w13, x24 + umlal v26.2D, v8.2S, v19.2S + umaddl x20, w15, w5, x20 + umlal v26.2D, v1.2S, v22.2S + umaddl x21, w15, w10, x9 + umlal v26.2D, v3.2S, v10.2S + and x9, x29, #0x3ffffff // ubignum_of_xreglist 6 // INTERMEDIATE bce + umlal v29.2D, v6.2S, v22.2S + umaddl x20, w30, w7, x20 + umaddl x1, w28, w22, x1 + add x24, x19, x19 + umull v11.2D, v1.2S, v12.2S + add w19, w3, w3, lsl #1; + umlal v26.2D, v5.2S, v18.2S + add w19, w19, w3, lsl #4 + umaddl x20, w9, w6, x20 + umlal v29.2D, v8.2S, v10.2S + add w29, w9, w9, lsl #1; + umlal v13.2D, v3.2S, v17.2S + add w29, w29, w9, lsl #4 + umaddl x2, w19, w10, x2 + umlal v11.2D, v3.2S, v16.2S + umaddl x21, w30, w14, x21 + umlal v11.2D, v5.2S, v19.2S + umaddl x20, w3, w13, x20 + umlal v11.2D, v7.2S, v24.2S + umaddl x2, w29, w22, x2 + umlal v11.2D, v9.2S, v23.2S + umaddl x21, w9, w26, x21 + ushr v23.2D, v30.2D, #1 + umaddl x1, w17, w10, x1 + umlal v13.2D, v5.2S, v14.2S + umaddl x24, w19, w5, x24 + umlal v27.2D, v3.2S, v14.2S + umaddl x21, w3, w16, x21 + shl v11.2D, v11.2D, #1 + add w3, w30, w30, lsl #1; + umlal v28.2D, v5.2S, v16.2S + add w3, w3, w30, lsl #4 + umaddl x24, w29, w23, x24 + umlal v28.2D, v7.2S, v19.2S + add x1, x1, x1 + umlal v28.2D, v9.2S, v24.2S + umaddl x1, w11, w5, x1 + umlal v15.2D, v5.2S, v12.2S + umaddl x24, w30, w13, x24 + umlal v15.2D, v7.2S, v16.2S + umaddl x25, w15, w14, x25 + umlal v15.2D, v9.2S, v19.2S + umaddl x1, w15, w7, x1 + shl v28.2D, v28.2D, #1 + umaddl x24, w15, w6, x24 + umlal v21.2D, v7.2S, v12.2S + umaddl x2, w30, w16, x2 + umlal v21.2D, v9.2S, v16.2S + umaddl x25, w30, w26, x25 + shl v15.2D, v15.2D, #1 + umaddl x30, w30, w6, x1 + umlal v28.2D, v0.2S, v22.2S + umaddl x1, w15, w26, x2 + umlal v28.2D, v2.2S, v10.2S + umaddl x2, w9, w16, x25 + shl v21.2D, v21.2D, #1 + umaddl x24, w11, w7, x24 + umlal v15.2D, v0.2S, v14.2S + umaddl x1, w11, w14, x1 + umlal v21.2D, v0.2S, v17.2S + umaddl x25, w9, w13, x30 + umlal v28.2D, v4.2S, v18.2S + umaddl x0, w19, w26, x0 + umlal v25.2D, v2.2S, v12.2S + add x1, x1, x24, lsr #26 + umlal v25.2D, v4.2S, v16.2S + umaddl x30, w19, w22, x2 + umlal v21.2D, v2.2S, v14.2S + umaddl x4, w12, w6, x4 + mul v14.2S, v14.2S, v31.2S + umaddl x25, w19, w23, x25 + and x2, x1, #0x1ffffff + mul v16.2S, v17.2S, v31.2S + umlal v25.2D, v6.2S, v19.2S + umaddl x9, w19, w14, x4 + umlal v13.2D, v7.2S, v22.2S + add x25, x25, x1, lsr #25 + umlal v21.2D, v4.2S, v22.2S + umaddl x0, w29, w14, x0 + umlal v26.2D, v7.2S, v16.2S + add x30, x30, x25, lsr #26 + umlal v26.2D, v9.2S, v14.2S + add w1, w15, w15, lsl #1; + umlal v28.2D, v6.2S, v16.2S + add w1, w1, w15, lsl #4 + add x4, x20, x30, lsr #25 + umlal v28.2D, v8.2S, v14.2S + and x25, x25, #0x3ffffff + umlal v15.2D, v2.2S, v22.2S + add x21, x21, x4, lsr #26 + umlal v11.2D, v0.2S, v10.2S + bfi x25, x30, #32, #25 // ubignum_of_preglist 3 // INTERMEDIATE z4 + umlal v11.2D, v2.2S, v18.2S + bic x30, x21, #0x3ffffff + usra v26.2D, v28.2D, #26 + lsr x20, x30, #26 + umlal v15.2D, v4.2S, v10.2S + add x20, x20, x30, lsr #25 + umlal v15.2D, v6.2S, v18.2S + umaddl x9, w29, w10, x9 + umlal v15.2D, v8.2S, v16.2S + add x30, x20, x30, lsr #22 + umlal v27.2D, v5.2S, v22.2S + umull x20, w17, w26 + umlal v20.2D, v7.2S, v18.2S + umaddl x30, w17, w16, x30 + umlal v20.2D, v9.2S, v16.2S + umaddl x17, w3, w10, x0 + usra v15.2D, v26.2D, #25 + umaddl x0, w28, w14, x20 + umlal v27.2D, v7.2S, v10.2S + umaddl x20, w28, w26, x30 + umlal v27.2D, v9.2S, v18.2S + add w28, w12, w12, lsl #1; + usra v20.2D, v15.2D, #26 + add w28, w28, w12, lsl #4 + umaddl x30, w27, w10, x0 + and v17.16B, v15.16B, v30.16B // ubignum_of_hreglist 4 + ubignum_of_lreglist 4 // INTERMEDIATE H|L = x4|z5 + umaddl x27, w27, w14, x20 + umaddl x0, w8, w10, x27 + mul v12.2S, v22.2S, v31.2S + and v15.16B, v20.16B, v23.16B // ubignum_of_hreglist 5 + ubignum_of_lreglist 5 // INTERMEDIATE H|L = x4|z5 + umaddl x14, w3, w22, x9 + umlal v21.2D, v6.2S, v10.2S + umaddl x27, w8, w22, x30 + trn1 v15.4S, v17.4S, v15.4S // FINAL z3 + umaddl x10, w28, w22, x0 + umlal v11.2D, v4.2S, v16.2S + umaddl x30, w15, w16, x14 + and v26.16B, v26.16B, v23.16B + umaddl x28, w12, w16, x27 + umlal v21.2D, v8.2S, v18.2S + add x10, x10, x10 + umlal v25.2D, v8.2S, v24.2S + umaddl x20, w19, w6, x10 + umlal v25.2D, v1.2S, v10.2S + add x28, x28, x28 + umlal v25.2D, v3.2S, v18.2S + umaddl x28, w19, w7, x28 + usra v21.2D, v20.2D, #25 + umaddl x0, w29, w7, x20 + umlal v11.2D, v6.2S, v14.2S + umaddl x10, w11, w26, x30 + umlal v13.2D, v9.2S, v10.2S + umaddl x19, w29, w5, x28 + usra v27.2D, v21.2D, #26 + umaddl x0, w3, w5, x0 + umlal v25.2D, v5.2S, v16.2S + umaddl x20, w1, w22, x17 + and v20.16B, v28.16B, v30.16B + umaddl x29, w3, w23, x19 + usra v29.2D, v27.2D, #25 + umaddl x3, w1, w23, x0 + and v27.16B, v27.16B, v23.16B // ubignum_of_hreglist 7 + ubignum_of_lreglist 7 // INTERMEDIATE H|L = x4|z5 + umlal v11.2D, v8.2S, v12.2S + umaddl x12, w15, w13, x29 + usra v13.2D, v29.2D, #26 + umaddl x7, w11, w13, x3 + trn1 v6.4S, v6.4S, v7.4S + umaddl x17, w11, w16, x20 + umlal v25.2D, v7.2S, v14.2S + and x23, x4, #0x3ffffff + bic v19.16B, v13.16B, v23.16B + umaddl x19, w11, w6, x12 + and v28.16B, v13.16B, v23.16B // ubignum_of_hreglist 9 + ubignum_of_lreglist 9 // INTERMEDIATE H|L = x4|z5 + add x3, x17, x7, lsr #26 + usra v11.2D, v19.2D, #25 + trn1 v2.4S, v2.4S, v3.4S + add x17, x19, x3, lsr #25 + and v13.16B, v21.16B, v30.16B // ubignum_of_hreglist 6 + ubignum_of_lreglist 6 // INTERMEDIATE H|L = x4|z5 + and x5, x7, #0x3ffffff + usra v11.2D, v19.2D, #24 + add x7, x10, x17, lsr #26 + trn1 v0.4S, v0.4S, v1.4S + and x19, x24, #0x3ffffff + and v21.16B, v29.16B, v30.16B // ubignum_of_hreglist 8 + ubignum_of_lreglist 8 // INTERMEDIATE H|L = x4|z5 + add x29, x19, x7, lsr #25 + usra v11.2D, v19.2D, #21 + bfi x5, x3, #32, #25 // ubignum_of_preglist 0 // INTERMEDIATE z4 + trn1 v17.4S, v13.4S, v27.4S // FINAL z3 + add x19, x2, x29, lsr #26 + trn1 v19.4S, v21.4S, v28.4S // FINAL z3 + and x3, x29, #0x3ffffff + mov v16.d[0], v6.d[1] // FINAL x3 + mov v6.d[0], v17.d[1] // FINAL x2 + trn1 v8.4S, v8.4S, v9.4S + bfi x3, x19, #32, #26 // ubignum_of_preglist 2 // INTERMEDIATE z4 + and v21.16B, v11.16B, v30.16B // ubignum_of_hreglist 0 + ubignum_of_lreglist 0 // INTERMEDIATE H|L = x4|z5 + bfi x23, x21, #32, #26 // ubignum_of_preglist 4 // INTERMEDIATE z4 + mov v18.d[0], v8.d[1] // FINAL x3 + mov v8.d[0], v19.d[1] // FINAL x2 + umlal v25.2D, v9.2S, v12.2S + mov v9.d[0], x23 // FINAL z2 + mov v7.d[0], x25 // FINAL z2 + ldr d29, [mask1] + mov v12.d[0], v2.d[1] // FINAL x3 + trn1 v4.4S, v4.4S, v5.4S + and x17, x17, #0x3ffffff + usra v25.2D, v11.2D, #26 + mov v10.d[0], v0.d[1] // FINAL x3 + mov v14.d[0], v4.d[1] // FINAL x3 + mov v4.d[0], v15.d[1] // FINAL x2 + usra v20.2D, v25.2D, #25 + and v27.16B, v25.16B, v23.16B // ubignum_of_hreglist 1 + ubignum_of_lreglist 1 // INTERMEDIATE H|L = x4|z5 + bfi x17, x7, #32, #25 // ubignum_of_preglist 1 // INTERMEDIATE z4 + mov v5.d[0], x3 // depth 86 + mov v1.d[0], x5 // FINAL z2 + usra v26.2D, v20.2D, #26 // ubignum_of_hreglist 3 + ubignum_of_lreglist 3 // INTERMEDIATE H|L = x4|z5 + and v28.16B, v20.16B, v30.16B // ubignum_of_hreglist 2 + ubignum_of_lreglist 2 // INTERMEDIATE H|L = x4|z5 + trn1 v11.4S, v21.4S, v27.4S // FINAL z3 + trn1 v13.4S, v28.4S, v26.4S // FINAL z3 + mov v0.d[0], v11.d[1] // FINAL x2 + mov v3.d[0], x17 // FINAL z2 + mov v2.d[0], v13.d[1] // FINAL x2 + ldr d28, [mask2] + + ldr x0, [i] + subs x0, x0, #1 + str x0, [i] bcs curve25519_x25519_byte_scalarloop -// Multiplex directly into (xn,zn) then do three pure doubling steps; -// this accounts for the implicit zeroing of the three lowest bits -// of the scalar. On the very last doubling we *fully* reduce zn mod -// p_25519 to ease checking for degeneracy below. - - cmp swap, xzr - mux_4(xn,xm,xn) - mux_4(zn,zm,zn) - - sub_twice4(d,xn,zn) - add_twice4(s,xn,zn) - sqr_4(d,d) - sqr_4(s,s) - sub_twice4(p,s,d) - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - mul_4(xn,s,d) - mul_4(zn,p,e) - - sub_twice4(d,xn,zn) - add_twice4(s,xn,zn) - sqr_4(d,d) - sqr_4(s,s) - sub_twice4(p,s,d) - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - mul_4(xn,s,d) - mul_4(zn,p,e) - - sub_twice4(d,xn,zn) - add_twice4(s,xn,zn) - sqr_4(d,d) - sqr_4(s,s) - sub_twice4(p,s,d) - mov x1, 0xdb42 - orr x1, x1, 0x10000 - cmadd_4(e,p,d) - mul_4(xn,s,d) - mul_p25519(zn,p,e) - -// The projective result of the scalar multiplication is now (xn,zn). -// Prepare to call the modular inverse function to get xm = 1/zn - - add x0, xm +// Repack X2 into the saturated representation as 256-bit value xn. +// This does not fully normalize mod 2^255-19 but stays within 256 bits. + + mov w0, v0.s[0] + mov w1, v0.s[1] + mov w2, v2.s[0] + mov w3, v2.s[1] + mov w4, v4.s[0] + mov w5, v4.s[1] + mov w6, v6.s[0] + mov w7, v6.s[1] + mov w8, v8.s[0] + mov w9, v8.s[1] + + add x0, x0, x1, lsl #26 + add x1, x2, x3, lsl #26 + add x2, x4, x5, lsl #26 + add x3, x6, x7, lsl #26 + add x4, x8, x9, lsl #26 + + adds x0, x0, x1, lsl #51 + lsr x6, x1, #13 + lsl x7, x2, #38 + adcs x1, x6, x7 + lsr x8, x2, #26 + lsl x9, x3, #25 + adcs x2, x8, x9 + lsr x10, x3, #39 + lsl x11, x4, #12 + adc x3, x10, x11 + stp x0, x1, [xn] + stp x2, x3, [xn+16] + +// Repack Z2 into the saturated representation as 256-bit value zn. +// This does not fully normalize mod 2^255-19. However since Z2, +// unlike X2, was not repacked (within the last multiplication) in +// right-to-left order, its top digit can be any 26-bit value, on +// the face of it. To make sure we don't overflow 256 bits here +// we remove b = 25th bit of the 9th digit (now scaled by 2^230 +// giving bit 25 a final weighting of 2^255) and add 19 * b to +// to the bottom of the sum here to compensate mod 2^255-19. + + mov w0, v1.s[0] + mov w1, v1.s[1] + mov w2, v3.s[0] + mov w3, v3.s[1] + mov w4, v5.s[0] + mov w5, v5.s[1] + mov w6, v7.s[0] + mov w7, v7.s[1] + mov w8, v9.s[0] + mov w9, v9.s[1] + + mov w10, #19 + add x0, x0, x1, lsl #26 + tst x9, #0x2000000 + add x1, x2, x3, lsl #26 + csel x10, x10, xzr, ne + add x2, x4, x5, lsl #26 + and x9, x9, #0x1FFFFFF + add x3, x6, x7, lsl #26 + add x0, x0, x10 + add x4, x8, x9, lsl #26 + + adds x0, x0, x1, lsl #51 + lsr x6, x1, #13 + lsl x7, x2, #38 + adcs x1, x6, x7 + lsr x8, x2, #26 + lsl x9, x3, #25 + adcs x2, x8, x9 + lsr x10, x3, #39 + lsl x11, x4, #12 + adc x3, x10, x11 + stp x0, x1, [zn] + stp x2, x3, [zn+16] + +// Because the lowest bit (indeed, the three lowest bits) of the scalar +// were forced to zero, we know that the projective result of the scalar +// multiplication was in (X2,Z2) and is now (xn,zn) in saturated form. +// Prepare to call the modular inverse function to get zn' = 1/zn. + + add x0, zn add x1, zn // Inline copy of bignum_inv_p25519, identical except for stripping out @@ -978,7 +1466,7 @@ curve25519_x25519_byte_scalarloop: // and reclaiming room on the stack. For more details and explanations see // "arm/curve25519/bignum_inv_p25519.S". Note that the stack it uses for // its own temporaries is 128 bytes, so it has no effect on variables -// that are needed in the rest of our computation here: res, xm and zn. +// that are needed in the rest of our computation here: res, xn, and zn. mov x20, x0 mov x10, #0xffffffffffffffed @@ -2009,102 +2497,278 @@ curve25519_x25519_byte_invmidloop: stp x0, x1, [x4] stp x2, x5, [x4, #16] -// Since we eventually want to return 0 when the result is the point at -// infinity, we force xn = 0 whenever zn = 0. This avoids building in a -// dependency on the behavior of modular inverse in out-of-scope cases. - - ldp x0, x1, [zn] - ldp x2, x3, [zn+16] - orr x0, x0, x1 - orr x2, x2, x3 - orr x4, x0, x2 - cmp x4, xzr - ldp x0, x1, [xn] - csel x0, x0, xzr, ne - csel x1, x1, xzr, ne - ldp x2, x3, [xn+16] - stp x0, x1, [xn] - csel x2, x2, xzr, ne - csel x3, x3, xzr, ne - stp x2, x3, [xn+16] - // Now the result is xn * (1/zn), fully reduced modulo p. +// Note that in the degenerate case zn = 0 (mod p_25519), the +// modular inverse code above will produce 1/zn = 0, giving +// the correct overall X25519 result of zero for the point at +// infinity. The multiplication below is just an inlined +// version of bignum_mul_p25519 except for the detailed +// addressing of inputs and outputs + + ldp x3, x4, [xn] + ldp x5, x6, [zn] + umull x7, w3, w5 + lsr x0, x3, #32 + umull x15, w0, w5 + lsr x16, x5, #32 + umull x8, w16, w0 + umull x16, w3, w16 + adds x7, x7, x15, lsl #32 + lsr x15, x15, #32 + adc x8, x8, x15 + adds x7, x7, x16, lsl #32 + lsr x16, x16, #32 + adc x8, x8, x16 + mul x9, x4, x6 + umulh x10, x4, x6 + subs x4, x4, x3 + cneg x4, x4, cc + csetm x16, cc + adds x9, x9, x8 + adc x10, x10, xzr + subs x3, x5, x6 + cneg x3, x3, cc + cinv x16, x16, cc + mul x15, x4, x3 + umulh x3, x4, x3 + adds x8, x7, x9 + adcs x9, x9, x10 + adc x10, x10, xzr + cmn x16, #0x1 + eor x15, x15, x16 + adcs x8, x15, x8 + eor x3, x3, x16 + adcs x9, x3, x9 + adc x10, x10, x16 + ldp x3, x4, [xn+16] + ldp x5, x6, [zn+16] + umull x11, w3, w5 + lsr x0, x3, #32 + umull x15, w0, w5 + lsr x16, x5, #32 + umull x12, w16, w0 + umull x16, w3, w16 + adds x11, x11, x15, lsl #32 + lsr x15, x15, #32 + adc x12, x12, x15 + adds x11, x11, x16, lsl #32 + lsr x16, x16, #32 + adc x12, x12, x16 + mul x13, x4, x6 + umulh x14, x4, x6 + subs x4, x4, x3 + cneg x4, x4, cc + csetm x16, cc + adds x13, x13, x12 + adc x14, x14, xzr + subs x3, x5, x6 + cneg x3, x3, cc + cinv x16, x16, cc + mul x15, x4, x3 + umulh x3, x4, x3 + adds x12, x11, x13 + adcs x13, x13, x14 + adc x14, x14, xzr + cmn x16, #0x1 + eor x15, x15, x16 + adcs x12, x15, x12 + eor x3, x3, x16 + adcs x13, x3, x13 + adc x14, x14, x16 + ldp x3, x4, [xn+16] + ldp x15, x16, [xn] + subs x3, x3, x15 + sbcs x4, x4, x16 + csetm x16, cc + ldp x15, x0, [zn] + subs x5, x15, x5 + sbcs x6, x0, x6 + csetm x0, cc + eor x3, x3, x16 + subs x3, x3, x16 + eor x4, x4, x16 + sbc x4, x4, x16 + eor x5, x5, x0 + subs x5, x5, x0 + eor x6, x6, x0 + sbc x6, x6, x0 + eor x16, x0, x16 + adds x11, x11, x9 + adcs x12, x12, x10 + adcs x13, x13, xzr + adc x14, x14, xzr + mul x2, x3, x5 + umulh x0, x3, x5 + mul x15, x4, x6 + umulh x1, x4, x6 + subs x4, x4, x3 + cneg x4, x4, cc + csetm x9, cc + adds x15, x15, x0 + adc x1, x1, xzr + subs x6, x5, x6 + cneg x6, x6, cc + cinv x9, x9, cc + mul x5, x4, x6 + umulh x6, x4, x6 + adds x0, x2, x15 + adcs x15, x15, x1 + adc x1, x1, xzr + cmn x9, #0x1 + eor x5, x5, x9 + adcs x0, x5, x0 + eor x6, x6, x9 + adcs x15, x6, x15 + adc x1, x1, x9 + adds x9, x11, x7 + adcs x10, x12, x8 + adcs x11, x13, x11 + adcs x12, x14, x12 + adcs x13, x13, xzr + adc x14, x14, xzr + cmn x16, #0x1 + eor x2, x2, x16 + adcs x9, x2, x9 + eor x0, x0, x16 + adcs x10, x0, x10 + eor x15, x15, x16 + adcs x11, x15, x11 + eor x1, x1, x16 + adcs x12, x1, x12 + adcs x13, x13, x16 + adc x14, x14, x16 + mov x3, #0x26 + umull x4, w11, w3 + add x4, x4, w7, uxtw + lsr x7, x7, #32 + lsr x11, x11, #32 + umaddl x11, w11, w3, x7 + mov x7, x4 + umull x4, w12, w3 + add x4, x4, w8, uxtw + lsr x8, x8, #32 + lsr x12, x12, #32 + umaddl x12, w12, w3, x8 + mov x8, x4 + umull x4, w13, w3 + add x4, x4, w9, uxtw + lsr x9, x9, #32 + lsr x13, x13, #32 + umaddl x13, w13, w3, x9 + mov x9, x4 + umull x4, w14, w3 + add x4, x4, w10, uxtw + lsr x10, x10, #32 + lsr x14, x14, #32 + umaddl x14, w14, w3, x10 + mov x10, x4 + lsr x0, x14, #31 + mov x5, #0x13 + umaddl x5, w5, w0, x5 + add x7, x7, x5 + adds x7, x7, x11, lsl #32 + extr x3, x12, x11, #32 + adcs x8, x8, x3 + extr x3, x13, x12, #32 + adcs x9, x9, x3 + extr x3, x14, x13, #32 + lsl x5, x0, #63 + eor x10, x10, x5 + adc x10, x10, x3 + mov x3, #0x13 + tst x10, #0x8000000000000000 + csel x3, x3, xzr, pl + subs x7, x7, x3 + sbcs x8, x8, xzr + sbcs x9, x9, xzr + sbc x10, x10, xzr + and x10, x10, #0x7fffffffffffffff + stp x7, x8, [zn] + stp x9, x10, [zn+16] + +// Now copy bytewise to the output - mul_p25519(zn,xn,xm) + ldr x17, [res] ldp x10, x11, [zn] - strb w10, [resx] + strb w10, [x17] lsr x10, x10, #8 - strb w10, [resx+1] + strb w10, [x17, #1] lsr x10, x10, #8 - strb w10, [resx+2] + strb w10, [x17, #2] lsr x10, x10, #8 - strb w10, [resx+3] + strb w10, [x17, #3] lsr x10, x10, #8 - strb w10, [resx+4] + strb w10, [x17, #4] lsr x10, x10, #8 - strb w10, [resx+5] + strb w10, [x17, #5] lsr x10, x10, #8 - strb w10, [resx+6] + strb w10, [x17, #6] lsr x10, x10, #8 - strb w10, [resx+7] + strb w10, [x17, #7] - strb w11, [resx+8] + strb w11, [x17, #8] lsr x11, x11, #8 - strb w11, [resx+9] + strb w11, [x17, #9] lsr x11, x11, #8 - strb w11, [resx+10] + strb w11, [x17, #10] lsr x11, x11, #8 - strb w11, [resx+11] + strb w11, [x17, #11] lsr x11, x11, #8 - strb w11, [resx+12] + strb w11, [x17, #12] lsr x11, x11, #8 - strb w11, [resx+13] + strb w11, [x17, #13] lsr x11, x11, #8 - strb w11, [resx+14] + strb w11, [x17, #14] lsr x11, x11, #8 - strb w11, [resx+15] + strb w11, [x17, #15] ldp x12, x13, [zn+16] - strb w12, [resx+16] + strb w12, [x17, #16] lsr x12, x12, #8 - strb w12, [resx+17] + strb w12, [x17, #17] lsr x12, x12, #8 - strb w12, [resx+18] + strb w12, [x17, #18] lsr x12, x12, #8 - strb w12, [resx+19] + strb w12, [x17, #19] lsr x12, x12, #8 - strb w12, [resx+20] + strb w12, [x17, #20] lsr x12, x12, #8 - strb w12, [resx+21] + strb w12, [x17, #21] lsr x12, x12, #8 - strb w12, [resx+22] + strb w12, [x17, #22] lsr x12, x12, #8 - strb w12, [resx+23] + strb w12, [x17, #23] - strb w13, [resx+24] + strb w13, [x17, #24] lsr x13, x13, #8 - strb w13, [resx+25] + strb w13, [x17, #25] lsr x13, x13, #8 - strb w13, [resx+26] + strb w13, [x17, #26] lsr x13, x13, #8 - strb w13, [resx+27] + strb w13, [x17, #27] lsr x13, x13, #8 - strb w13, [resx+28] + strb w13, [x17, #28] lsr x13, x13, #8 - strb w13, [resx+29] + strb w13, [x17, #29] lsr x13, x13, #8 - strb w13, [resx+30] + strb w13, [x17, #30] lsr x13, x13, #8 - strb w13, [resx+31] - -// Restore stack and registers - - add sp, sp, #NSPACE - ldp x23, x24, [sp], 16 - ldp x21, x22, [sp], 16 - ldp x19, x20, [sp], 16 - + strb w13, [x17, #31] + +// Restore stack and registers (this will zero the tops of Q8...Q15). + + ldp d8, d9, [regsave+0] + ldp d10, d11, [regsave+16] + ldp d12, d13, [regsave+32] + ldp d14, d15, [regsave+48] + ldp x19, x20, [regsave+64] + ldp x21, x22, [regsave+80] + ldp x23, x24, [regsave+96] + ldp x25, x26, [regsave+112] + ldp x27, x28, [regsave+128] + ldp x29, x30, [regsave+144] + add sp, sp, #NSPACE+160 ret #if defined(__linux__) && defined(__ELF__) diff --git a/arm/proofs/curve25519_x25519.ml b/arm/proofs/curve25519_x25519.ml index 251943a7..e851492f 100644 --- a/arm/proofs/curve25519_x25519.ml +++ b/arm/proofs/curve25519_x25519.ml @@ -12,6 +12,8 @@ needs "arm/proofs/bignum_inv_p25519.ml";; needs "common/ecencoding.ml";; do_list hide_constant ["X1";"X2";"X3";"X4";"X5"];; +needs "EC/curve25519.ml";; +needs "EC/formulary_xzprojective.ml";; needs "EC/x25519.ml";; do_list unhide_constant ["X1";"X2";"X3";"X4";"X5"];; @@ -19,6226 +21,3402 @@ prioritize_int();; prioritize_real();; prioritize_num();; +(* ------------------------------------------------------------------------- *) +(* The code. *) +(* ------------------------------------------------------------------------- *) + (**** print_literal_from_elf "arm/curve25519/curve25519_x25519.o";; ****) let curve25519_x25519_mc = define_assert_from_elf "curve25519_x25519_mc" "arm/curve25519/curve25519_x25519.o" [ - 0xa9bf53f3; (* arm_STP X19 X20 SP (Preimmediate_Offset (iword (-- &16))) *) - 0xa9bf5bf5; (* arm_STP X21 X22 SP (Preimmediate_Offset (iword (-- &16))) *) - 0xa9bf63f7; (* arm_STP X23 X24 SP (Preimmediate_Offset (iword (-- &16))) *) - 0xd10503ff; (* arm_SUB SP SP (rvalue (word 320)) *) - 0xaa0003f7; (* arm_MOV X23 X0 *) + 0xd10603ff; (* arm_SUB SP SP (rvalue (word 384)) *) + 0x6d0e27e8; (* arm_STP D8 D9 SP (Immediate_Offset (iword (&224))) *) + 0x6d0f2fea; (* arm_STP D10 D11 SP (Immediate_Offset (iword (&240))) *) + 0x6d1037ec; (* arm_STP D12 D13 SP (Immediate_Offset (iword (&256))) *) + 0x6d113fee; (* arm_STP D14 D15 SP (Immediate_Offset (iword (&272))) *) + 0xa91253f3; (* arm_STP X19 X20 SP (Immediate_Offset (iword (&288))) *) + 0xa9135bf5; (* arm_STP X21 X22 SP (Immediate_Offset (iword (&304))) *) + 0xa91463f7; (* arm_STP X23 X24 SP (Immediate_Offset (iword (&320))) *) + 0xa9156bf9; (* arm_STP X25 X26 SP (Immediate_Offset (iword (&336))) *) + 0xa91673fb; (* arm_STP X27 X28 SP (Immediate_Offset (iword (&352))) *) + 0xa9177bfd; (* arm_STP X29 X30 SP (Immediate_Offset (iword (&368))) *) + 0xf90063e0; (* arm_STR X0 SP (Immediate_Offset (word 192)) *) 0xa9402c2a; (* arm_LDP X10 X11 X1 (Immediate_Offset (iword (&0))) *) + 0x927df14a; (* arm_AND X10 X10 (rvalue (word 18446744073709551608)) *) 0xa9002fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&0))) *) 0xa941342c; (* arm_LDP X12 X13 X1 (Immediate_Offset (iword (&16))) *) + 0xb24201ad; (* arm_ORR X13 X13 (rvalue (word 4611686018427387904)) *) 0xa90137ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&16))) *) - 0xa9402c4a; (* arm_LDP X10 X11 X2 (Immediate_Offset (iword (&0))) *) + 0xa9400440; (* arm_LDP X0 X1 X2 (Immediate_Offset (iword (&0))) *) + 0xa9410c42; (* arm_LDP X2 X3 X2 (Immediate_Offset (iword (&16))) *) + 0xd373fc0c; (* arm_LSR X12 X0 51 *) + 0xd373fc51; (* arm_LSR X17 X2 51 *) + 0xaa01358c; (* arm_ORR X12 X12 (Shiftedreg X1 LSL 13) *) + 0xaa033631; (* arm_ORR X17 X17 (Shiftedreg X3 LSL 13) *) + 0xd34c9468; (* arm_UBFM X8 X3 12 37 *) + 0xd366f869; (* arm_UBFM X9 X3 38 62 *) + 0xd35ac80b; (* arm_UBFM X11 X0 26 50 *) + 0xd34d942d; (* arm_UBFM X13 X1 13 37 *) + 0xd366fc2e; (* arm_LSR X14 X1 38 *) + 0xd359c850; (* arm_UBFM X16 X2 25 50 *) + 0x9240640a; (* arm_AND X10 X0 (rvalue (word 67108863)) *) + 0x9240658c; (* arm_AND X12 X12 (rvalue (word 67108863)) *) + 0x9240604f; (* arm_AND X15 X2 (rvalue (word 33554431)) *) + 0x92406231; (* arm_AND X17 X17 (rvalue (word 33554431)) *) + 0xaa0b814a; (* arm_ORR X10 X10 (Shiftedreg X11 LSL 32) *) + 0xaa0d818b; (* arm_ORR X11 X12 (Shiftedreg X13 LSL 32) *) + 0xaa0f81cc; (* arm_ORR X12 X14 (Shiftedreg X15 LSL 32) *) + 0xaa11820d; (* arm_ORR X13 X16 (Shiftedreg X17 LSL 32) *) + 0xaa09810e; (* arm_ORR X14 X8 (Shiftedreg X9 LSL 32) *) 0xa9022fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&32))) *) - 0xa941344c; (* arm_LDP X12 X13 X2 (Immediate_Offset (iword (&16))) *) - 0x9240f9ad; (* arm_AND X13 X13 (rvalue (word 9223372036854775807)) *) 0xa90337ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&48))) *) - 0xd2800035; (* arm_MOV X21 (rvalue (word 1)) *) - 0xa90e2fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&224))) *) - 0xa90f37ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&240))) *) - 0xa9047ff5; (* arm_STP X21 XZR SP (Immediate_Offset (iword (&64))) *) - 0xa9057fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&80))) *) - 0xa94e1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&224))) *) - 0xa9440fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&64))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa94f23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&240))) *) - 0xa9450fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&80))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9101be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0xa91123e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xa94e13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&224))) *) - 0xa94423e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&64))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa94f1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&240))) *) - 0xa94523e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&80))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa91213e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9131be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) + 0xf90023ee; (* arm_STR X14 SP (Immediate_Offset (word 64)) *) + 0xd2800021; (* arm_MOV X1 (rvalue (word 1)) *) + 0x4e081c20; (* arm_INS_GEN Q0 X1 0 64 *) + 0x4e081fe2; (* arm_INS_GEN Q2 XZR 0 64 *) + 0x4e081fe4; (* arm_INS_GEN Q4 XZR 0 64 *) + 0x4e081fe6; (* arm_INS_GEN Q6 XZR 0 64 *) + 0x4e081fe8; (* arm_INS_GEN Q8 XZR 0 64 *) + 0x4e081fe1; (* arm_INS_GEN Q1 XZR 0 64 *) + 0x4e081fe3; (* arm_INS_GEN Q3 XZR 0 64 *) + 0x4e081fe5; (* arm_INS_GEN Q5 XZR 0 64 *) + 0x4e081fe7; (* arm_INS_GEN Q7 XZR 0 64 *) + 0x4e081fe9; (* arm_INS_GEN Q9 XZR 0 64 *) + 0x4e081d4a; (* arm_INS_GEN Q10 X10 0 64 *) + 0x4e081d6c; (* arm_INS_GEN Q12 X11 0 64 *) + 0x4e081d8e; (* arm_INS_GEN Q14 X12 0 64 *) + 0x4e081db0; (* arm_INS_GEN Q16 X13 0 64 *) + 0x4e081dd2; (* arm_INS_GEN Q18 X14 0 64 *) + 0x4e081c2b; (* arm_INS_GEN Q11 X1 0 64 *) + 0x4e081fed; (* arm_INS_GEN Q13 XZR 0 64 *) + 0x4e081fef; (* arm_INS_GEN Q15 XZR 0 64 *) + 0x4e081ff1; (* arm_INS_GEN Q17 XZR 0 64 *) + 0x4e081ff3; (* arm_INS_GEN Q19 XZR 0 64 *) + 0x52800260; (* arm_MOV W0 (rvalue (word 19)) *) + 0x8b008000; (* arm_ADD X0 X0 (Shiftedreg X0 LSL 32) *) + 0x4e081c1f; (* arm_INS_GEN Q31 X0 0 64 *) + 0x4e181fff; (* arm_INS_GEN Q31 XZR 64 64 *) + 0xb24067e0; (* arm_MOV X0 (rvalue (word 67108863)) *) + 0x4e081c1e; (* arm_INS_GEN Q30 X0 0 64 *) + 0x4e181c1e; (* arm_INS_GEN Q30 X0 64 64 *) + 0xb21f67e0; (* arm_MOV X0 (rvalue (word 576460743847706622)) *) + 0xd1012801; (* arm_SUB X1 X0 (rvalue (word 74)) *) + 0xd1000800; (* arm_SUB X0 X0 (rvalue (word 2)) *) + 0xa90487e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&72))) *) + 0x6d44f3fd; (* arm_LDP D29 D28 SP (Immediate_Offset (iword (&72))) *) + 0xf9006bff; (* arm_STR XZR SP (Immediate_Offset (word 208)) *) + 0xd2801fc0; (* arm_MOV X0 (rvalue (word 254)) *) + 0xf90067e0; (* arm_STR X0 SP (Immediate_Offset (word 200)) *) + 0xd346fc01; (* arm_LSR X1 X0 6 *) + 0xf8617be2; (* arm_LDR X2 SP (Shiftreg_Offset X1 3) *) + 0x9ac02442; (* arm_LSRV X2 X2 X0 *) + 0x92400042; (* arm_AND X2 X2 (rvalue (word 1)) *) + 0xf9406be0; (* arm_LDR X0 SP (Immediate_Offset (word 208)) *) + 0xeb02001f; (* arm_CMP X0 X2 *) + 0xf9006be2; (* arm_STR X2 SP (Immediate_Offset (word 208)) *) + 0x0ea38456; (* arm_ADD_VEC Q22 Q2 Q3 32 64 *) + 0x2ea18795; (* arm_SUB_VEC Q21 Q28 Q1 32 64 *) + 0x0ea18419; (* arm_ADD_VEC Q25 Q0 Q1 32 64 *) + 0x2ea387b8; (* arm_SUB_VEC Q24 Q29 Q3 32 64 *) + 0x0eb38643; (* arm_ADD_VEC Q3 Q18 Q19 32 64 *) + 0x0eb58400; (* arm_ADD_VEC Q0 Q0 Q21 32 64 *) + 0x2eaf87b4; (* arm_SUB_VEC Q20 Q29 Q15 32 64 *) + 0x2ea587a1; (* arm_SUB_VEC Q1 Q29 Q5 32 64 *) + 0x2eab879a; (* arm_SUB_VEC Q26 Q28 Q11 32 64 *) + 0x2eb387b5; (* arm_SUB_VEC Q21 Q29 Q19 32 64 *) + 0x0eab8553; (* arm_ADD_VEC Q19 Q10 Q11 32 64 *) + 0x0eb485cb; (* arm_ADD_VEC Q11 Q14 Q20 32 64 *) + 0x0eb58655; (* arm_ADD_VEC Q21 Q18 Q21 32 64 *) + 0x2eb187b4; (* arm_SUB_VEC Q20 Q29 Q17 32 64 *) + 0x0eb88452; (* arm_ADD_VEC Q18 Q2 Q24 32 64 *) + 0x0eaf85ce; (* arm_ADD_VEC Q14 Q14 Q15 32 64 *) + 0x0eb1860f; (* arm_ADD_VEC Q15 Q16 Q17 32 64 *) + 0x0eb48602; (* arm_ADD_VEC Q2 Q16 Q20 32 64 *) + 0x0ead8598; (* arm_ADD_VEC Q24 Q12 Q13 32 64 *) + 0x0eba855a; (* arm_ADD_VEC Q26 Q10 Q26 32 64 *) + 0x2ead87aa; (* arm_SUB_VEC Q10 Q29 Q13 32 64 *) + 0x2ea787ad; (* arm_SUB_VEC Q13 Q29 Q7 32 64 *) + 0x0ea784d7; (* arm_ADD_VEC Q23 Q6 Q7 32 64 *) + 0x2ea987a7; (* arm_SUB_VEC Q7 Q29 Q9 32 64 *) + 0x0eaa859b; (* arm_ADD_VEC Q27 Q12 Q10 32 64 *) + 0x1e780ed4; (* arm_FCSEL Q20 Q22 Q24 Condition_EQ 64 *) + 0x0ea5849c; (* arm_ADD_VEC Q28 Q4 Q5 32 64 *) + 0x1e6f0eec; (* arm_FCSEL Q12 Q23 Q15 Condition_EQ 64 *) + 0x0ea78507; (* arm_ADD_VEC Q7 Q8 Q7 32 64 *) + 0x1e730f30; (* arm_FCSEL Q16 Q25 Q19 Condition_EQ 64 *) + 0x4e083e80; (* arm_UMOV X0 Q20 0 8 *) + 0x1e6e0f85; (* arm_FCSEL Q5 Q28 Q14 Condition_EQ 64 *) + 0x4e083d95; (* arm_UMOV X21 Q12 0 8 *) + 0x1e750cfd; (* arm_FCSEL Q29 Q7 Q21 Condition_EQ 64 *) + 0x4e083e05; (* arm_UMOV X5 Q16 0 8 *) + 0xd360fc1a; (* arm_LSR X26 X0 32 *) + 0x8b1502bd; (* arm_ADD X29 X21 X21 *) + 0x9bbd7caf; (* arm_UMULL X15 W5 W29 *) + 0x0ead84cd; (* arm_ADD_VEC Q13 Q6 Q13 32 64 *) + 0x8b1a034c; (* arm_ADD X12 X26 X26 *) + 0x4e083cbe; (* arm_UMOV X30 Q5 0 8 *) + 0x1e7b0e4a; (* arm_FCSEL Q10 Q18 Q27 Condition_EQ 64 *) + 0xd360fcab; (* arm_LSR X11 X5 32 *) + 0xd360ffca; (* arm_LSR X10 X30 32 *) + 0x0e836ab4; (* arm_TRN2 Q20 Q21 Q3 32 64 *) + 0x0ea98509; (* arm_ADD_VEC Q9 Q8 Q9 32 64 *) + 0x8b0b016e; (* arm_ADD X14 X11 X11 *) + 0x0e8f6846; (* arm_TRN2 Q6 Q2 Q15 32 64 *) + 0x0e802b2c; (* arm_TRN1 Q12 Q25 Q0 32 64 *) + 0x0ea18481; (* arm_ADD_VEC Q1 Q4 Q1 32 64 *) + 0x0e8d2af0; (* arm_TRN1 Q16 Q23 Q13 32 64 *) + 0x1e620da8; (* arm_FCSEL Q8 Q13 Q2 Condition_EQ 64 *) + 0x0e986b71; (* arm_TRN2 Q17 Q27 Q24 32 64 *) + 0xfd0053fd; (* arm_STR D29 SP (Immediate_Offset (word 160)) *) + 0x8b0a0151; (* arm_ADD X17 X10 X10 *) + 0x0e816b84; (* arm_TRN2 Q4 Q28 Q1 32 64 *) + 0x0e812b85; (* arm_TRN1 Q5 Q28 Q1 32 64 *) + 0x0e8f285c; (* arm_TRN1 Q28 Q2 Q15 32 64 *) + 0x0e922ac2; (* arm_TRN1 Q2 Q22 Q18 32 64 *) + 0x1e7a0c1d; (* arm_FCSEL Q29 Q0 Q26 Condition_EQ 64 *) + 0x0e926acf; (* arm_TRN2 Q15 Q22 Q18 32 64 *) + 0x2eb4c196; (* arm_UMULL_VEC Q22 Q12 Q20 32 *) + 0x9bb17fd6; (* arm_UMULL X22 W30 W17 *) + 0x6d082bfd; (* arm_STP D29 D10 SP (Immediate_Offset (iword (&128))) *) + 0x0e8d6aea; (* arm_TRN2 Q10 Q23 Q13 32 64 *) + 0x0e8e6977; (* arm_TRN2 Q23 Q11 Q14 32 64 *) + 0x0e982b6d; (* arm_TRN1 Q13 Q27 Q24 32 64 *) + 0x1e6b0c3b; (* arm_FCSEL Q27 Q1 Q11 Condition_EQ 64 *) + 0x0e8e296e; (* arm_TRN1 Q14 Q11 Q14 32 64 *) + 0x2ea68056; (* arm_UMLAL_VEC Q22 Q2 Q6 32 *) + 0x9bbe7fd9; (* arm_UMULL X25 W30 W30 *) + 0x2eb780b6; (* arm_UMLAL_VEC Q22 Q5 Q23 32 *) + 0x8b1e03c3; (* arm_ADD X3 X30 X30 *) + 0x2eb18216; (* arm_UMLAL_VEC Q22 Q16 Q17 32 *) + 0x0b1506be; (* arm_ADD W30 W21 (Shiftedreg W21 LSL 1) *) + 0x6d0923fb; (* arm_STP D27 D8 SP (Immediate_Offset (iword (&144))) *) + 0x0b1513de; (* arm_ADD W30 W30 (Shiftedreg W21 LSL 4) *) + 0x0e932b4b; (* arm_TRN1 Q11 Q26 Q19 32 64 *) + 0x0e936b48; (* arm_TRN2 Q8 Q26 Q19 32 64 *) + 0x0e806b33; (* arm_TRN2 Q19 Q25 Q0 32 64 *) + 0x0ebf9e9d; (* arm_MUL_VEC Q29 Q20 Q31 32 64 *) + 0xf9404ff4; (* arm_LDR X20 SP (Immediate_Offset (word 152)) *) + 0x2ea6c279; (* arm_UMULL_VEC Q25 Q19 Q6 32 *) + 0x8b000001; (* arm_ADD X1 X0 X0 *) + 0x2eb7c27b; (* arm_UMULL_VEC Q27 Q19 Q23 32 *) + 0x9ba17ca9; (* arm_UMULL X9 W5 W1 *) + 0x2eb7c180; (* arm_UMULL_VEC Q0 Q12 Q23 32 *) + 0xd360fe98; (* arm_LSR X24 X20 32 *) + 0x0ebf9ef4; (* arm_MUL_VEC Q20 Q23 Q31 32 64 *) + 0xd360feb0; (* arm_LSR X16 X21 32 *) + 0x2eb781f9; (* arm_UMLAL_VEC Q25 Q15 Q23 32 *) + 0x9bae256d; (* arm_UMADDL X13 W11 W14 X9 *) + 0x2eb18099; (* arm_UMLAL_VEC Q25 Q4 Q17 32 *) + 0x9bb13dc9; (* arm_UMADDL X9 W14 W17 X15 *) + 0x2ea6c198; (* arm_UMULL_VEC Q24 Q12 Q6 32 *) + 0x0b100602; (* arm_ADD W2 W16 (Shiftedreg W16 LSL 1) *) + 0x1e630d3a; (* arm_FCSEL Q26 Q9 Q3 Condition_EQ 64 *) + 0x0b101042; (* arm_ADD W2 W2 (Shiftedreg W16 LSL 4) *) + 0x0e832ab2; (* arm_TRN1 Q18 Q21 Q3 32 64 *) + 0x2ebdc263; (* arm_UMULL_VEC Q3 Q19 Q29 32 *) + 0x9ba37cbc; (* arm_UMULL X28 W5 W3 *) + 0x0ebf9cc1; (* arm_MUL_VEC Q1 Q6 Q31 32 64 *) + 0x9ba57ca8; (* arm_UMULL X8 W5 W5 *) + 0x2eb78058; (* arm_UMLAL_VEC Q24 Q2 Q23 32 *) + 0x9bbe36ad; (* arm_UMADDL X13 W21 W30 X13 *) + 0x0ebf9e37; (* arm_MUL_VEC Q23 Q17 Q31 32 64 *) + 0x9bac71db; (* arm_UMADDL X27 W14 W12 X28 *) + 0x0e876926; (* arm_TRN2 Q6 Q9 Q7 32 64 *) + 0x4e083f46; (* arm_UMOV X6 Q26 0 8 *) + 0x2ea181e3; (* arm_UMLAL_VEC Q3 Q15 Q1 32 *) + 0x8b100210; (* arm_ADD X16 X16 X16 *) + 0x2eb48083; (* arm_UMLAL_VEC Q3 Q4 Q20 32 *) + 0xd360fcc4; (* arm_LSR X4 X6 32 *) + 0x2eb78143; (* arm_UMLAL_VEC Q3 Q10 Q23 32 *) + 0x8b0600c7; (* arm_ADD X7 X6 X6 *) + 0x2ea8c27a; (* arm_UMULL_VEC Q26 Q19 Q8 32 *) + 0x8b040097; (* arm_ADD X23 X4 X4 *) + 0x9bb758bc; (* arm_UMADDL X28 W5 W23 X22 *) + 0x0e872927; (* arm_TRN1 Q7 Q9 Q7 32 64 *) + 0x2eb181fb; (* arm_UMLAL_VEC Q27 Q15 Q17 32 *) + 0x0b04048f; (* arm_ADD W15 W4 (Shiftedreg W4 LSL 1) *) + 0x2ea8809b; (* arm_UMLAL_VEC Q27 Q4 Q8 32 *) + 0x0b0411ef; (* arm_ADD W15 W15 (Shiftedreg W4 LSL 4) *) + 0x0b0a0556; (* arm_ADD W22 W10 (Shiftedreg W10 LSL 1) *) + 0x2eb180b8; (* arm_UMLAL_VEC Q24 Q5 Q17 32 *) + 0x0b0a12d6; (* arm_ADD W22 W22 (Shiftedreg W10 LSL 4) *) + 0x9ba7716a; (* arm_UMADDL X10 W11 W7 X28 *) + 0x2ea88159; (* arm_UMLAL_VEC Q25 Q10 Q8 32 *) + 0x9bb07cb5; (* arm_UMULL X21 W5 W16 *) + 0x2ebd80d9; (* arm_UMLAL_VEC Q25 Q6 Q29 32 *) + 0x9bb765f7; (* arm_UMADDL X23 W15 W23 X25 *) + 0x2ebd815b; (* arm_UMLAL_VEC Q27 Q10 Q29 32 *) + 0x9bac7cb3; (* arm_UMULL X19 W5 W12 *) + 0x2ea180db; (* arm_UMLAL_VEC Q27 Q6 Q1 32 *) + 0x9bbd5579; (* arm_UMADDL X25 W11 W29 X21 *) + 0x2eb18040; (* arm_UMLAL_VEC Q0 Q2 Q17 32 *) + 0x9ba3241c; (* arm_UMADDL X28 W0 W3 X9 *) + 0x4f415735; (* arm_SHL_VEC Q21 Q25 1 64 128 *) + 0x9ba14d64; (* arm_UMADDL X4 W11 W1 X19 *) + 0x9bbd1055; (* arm_UMADDL X21 W2 W29 X4 *) + 0x0ebf9d19; (* arm_MUL_VEC Q25 Q8 Q31 32 64 *) + 0x2ea88218; (* arm_UMLAL_VEC Q24 Q16 Q8 32 *) + 0x9bb16413; (* arm_UMADDL X19 W0 W17 X25 *) + 0x2ebd80f8; (* arm_UMLAL_VEC Q24 Q7 Q29 32 *) + 0x9bb17cb9; (* arm_UMULL X25 W5 W17 *) + 0x2ebc8278; (* arm_UMLAL_VEC Q24 Q19 Q28 32 *) + 0x9bb02804; (* arm_UMADDL X4 W0 W16 X10 *) + 0x2ea8c189; (* arm_UMULL_VEC Q9 Q12 Q8 32 *) + 0x9ba75cb7; (* arm_UMADDL X23 W5 W7 X23 *) + 0x2eb28195; (* arm_UMLAL_VEC Q21 Q12 Q18 32 *) + 0x0b0604ca; (* arm_ADD W10 W6 (Shiftedreg W6 LSL 1) *) + 0x4f41577b; (* arm_SHL_VEC Q27 Q27 1 64 128 *) + 0x0b06114a; (* arm_ADD W10 W10 (Shiftedreg W6 LSL 4) *) + 0x9bac735c; (* arm_UMADDL X28 W26 W12 X28 *) + 0x2ebd81fa; (* arm_UMLAL_VEC Q26 Q15 Q29 32 *) + 0x9bb05dc9; (* arm_UMADDL X9 W14 W16 X23 *) + 0x2ebd8049; (* arm_UMLAL_VEC Q9 Q2 Q29 32 *) + 0x9bb122d6; (* arm_UMADDL X22 W22 W17 X8 *) + 0x2ebc8055; (* arm_UMLAL_VEC Q21 Q2 Q28 32 *) + 0x9baa70dc; (* arm_UMADDL X28 W6 W10 X28 *) + 0x9ba06c1b; (* arm_UMADDL X27 W0 W0 X27 *) + 0x8b0e01c8; (* arm_ADD X8 X14 X14 *) + 0x2ea880a0; (* arm_UMLAL_VEC Q0 Q5 Q8 32 *) + 0x9bae7ca5; (* arm_UMULL X5 W5 W14 *) + 0x2ea180a9; (* arm_UMLAL_VEC Q9 Q5 Q1 32 *) + 0x9bbd240e; (* arm_UMADDL X14 W0 W29 X9 *) + 0x2ea1809a; (* arm_UMLAL_VEC Q26 Q4 Q1 32 *) + 0x9bb06c46; (* arm_UMADDL X6 W2 W16 X27 *) + 0x2ea880f6; (* arm_UMLAL_VEC Q22 Q7 Q8 32 *) + 0x9bb117c5; (* arm_UMADDL X5 W30 W17 X5 *) + 0x9ba31445; (* arm_UMADDL X5 W2 W3 X5 *) + 0x8b110237; (* arm_ADD X23 X17 X17 *) + 0x2ebc819b; (* arm_UMLAL_VEC Q27 Q12 Q28 32 *) + 0x9bb7344d; (* arm_UMADDL X13 W2 W23 X13 *) + 0x2eb4815a; (* arm_UMLAL_VEC Q26 Q10 Q20 32 *) + 0x8b0c0189; (* arm_ADD X9 X12 X12 *) + 0x2eb48209; (* arm_UMLAL_VEC Q9 Q16 Q20 32 *) + 0x9bbd195b; (* arm_UMADDL X27 W10 W29 X6 *) + 0x2ebd8200; (* arm_UMLAL_VEC Q0 Q16 Q29 32 *) + 0x9ba36566; (* arm_UMADDL X6 W11 W3 X25 *) + 0x2eb28276; (* arm_UMLAL_VEC Q22 Q19 Q18 32 *) + 0x9ba34f53; (* arm_UMADDL X19 W26 W3 X19 *) + 0x0ebf9e52; (* arm_MUL_VEC Q18 Q18 Q31 32 64 *) + 0x9bb76df7; (* arm_UMADDL X23 W15 W23 X27 *) + 0x2eb980c3; (* arm_UMLAL_VEC Q3 Q6 Q25 32 *) + 0x9bac1800; (* arm_UMADDL X0 W0 W12 X6 *) + 0x2ea180e0; (* arm_UMLAL_VEC Q0 Q7 Q1 32 *) + 0x8b10020b; (* arm_ADD X11 X16 X16 *) + 0x2eb780e9; (* arm_UMLAL_VEC Q9 Q7 Q23 32 *) + 0x9bb13986; (* arm_UMADDL X6 W12 W17 X14 *) + 0x2eab8269; (* arm_UMLAL_VEC Q9 Q19 Q11 32 *) + 0x9bbd1359; (* arm_UMADDL X25 W26 W29 X4 *) + 0x2eb281e9; (* arm_UMLAL_VEC Q9 Q15 Q18 32 *) + 0x9ba3354e; (* arm_UMADDL X14 W10 W3 X13 *) + 0x2eb1c199; (* arm_UMULL_VEC Q25 Q12 Q17 32 *) + 0x9bb0015b; (* arm_UMADDL X27 W10 W16 X0 *) + 0x2eb780da; (* arm_UMLAL_VEC Q26 Q6 Q23 32 *) + 0x8b466b20; (* arm_ADD X0 X25 (Shiftedreg X6 LSR 26) *) + 0x0ebf9f97; (* arm_MUL_VEC Q23 Q28 Q31 32 64 *) + 0x9bac154c; (* arm_UMADDL X12 W10 W12 X5 *) + 0x4f415463; (* arm_SHL_VEC Q3 Q3 1 64 128 *) + 0x8b4066d0; (* arm_ADD X16 X22 (Shiftedreg X0 LSR 25) *) + 0x2eae80b5; (* arm_UMLAL_VEC Q21 Q5 Q14 32 *) + 0x92679816; (* arm_AND X22 X0 (rvalue (word 18446744073675997184)) *) + 0x2eab8183; (* arm_UMLAL_VEC Q3 Q12 Q11 32 *) + 0x8b56621a; (* arm_ADD X26 X16 (Shiftedreg X22 LSR 24) *) + 0x2eb28043; (* arm_UMLAL_VEC Q3 Q2 Q18 32 *) + 0x9bb15550; (* arm_UMADDL X16 W10 W17 X21 *) + 0x2eb780a3; (* arm_UMLAL_VEC Q3 Q5 Q23 32 *) + 0x8b565756; (* arm_ADD X22 X26 (Shiftedreg X22 LSR 21) *) + 0x2eb78089; (* arm_UMLAL_VEC Q9 Q4 Q23 32 *) + 0x9bbd6de5; (* arm_UMADDL X5 W15 W29 X27 *) + 0x2eb1c271; (* arm_UMULL_VEC Q17 Q19 Q17 32 *) + 0x9ba35bd1; (* arm_UMADDL X17 W30 W3 X22 *) + 0x2ea88059; (* arm_UMLAL_VEC Q25 Q2 Q8 32 *) + 0x9ba341f9; (* arm_UMADDL X25 W15 W3 X16 *) + 0x2ebd80b9; (* arm_UMLAL_VEC Q25 Q5 Q29 32 *) + 0x9ba74dfa; (* arm_UMADDL X26 W15 W7 X19 *) + 0x2eae8260; (* arm_UMLAL_VEC Q0 Q19 Q14 32 *) + 0x9ba94451; (* arm_UMADDL X17 W2 W9 X17 *) + 0x2ea881f1; (* arm_UMLAL_VEC Q17 Q15 Q8 32 *) + 0xf94043f3; (* arm_LDR X19 SP (Immediate_Offset (word 128)) *) + 0x2ebd8091; (* arm_UMLAL_VEC Q17 Q4 Q29 32 *) + 0xf94047e7; (* arm_LDR X7 SP (Immediate_Offset (word 136)) *) + 0x4f41575d; (* arm_SHL_VEC Q29 Q26 1 64 128 *) + 0x9ba1454d; (* arm_UMADDL X13 W10 W1 X17 *) + 0x2ead81e0; (* arm_UMLAL_VEC Q0 Q15 Q13 32 *) + 0xd360fe62; (* arm_LSR X2 X19 32 *) + 0x2ead819d; (* arm_UMLAL_VEC Q29 Q12 Q13 32 *) + 0x9ba131fb; (* arm_UMADDL X27 W15 W1 X12 *) + 0x2eab805d; (* arm_UMLAL_VEC Q29 Q2 Q11 32 *) + 0x9ba835fe; (* arm_UMADDL X30 W15 W8 X13 *) + 0x2eb280bd; (* arm_UMLAL_VEC Q29 Q5 Q18 32 *) + 0x8b0700e4; (* arm_ADD X4 X7 X7 *) + 0x2eb7821d; (* arm_UMLAL_VEC Q29 Q16 Q23 32 *) + 0x9ba939fd; (* arm_UMADDL X29 W15 W9 X14 *) + 0x2eab8080; (* arm_UMLAL_VEC Q0 Q4 Q11 32 *) + 0x8b5e6b71; (* arm_ADD X17 X27 (Shiftedreg X30 LSR 26) *) + 0x2eb28140; (* arm_UMLAL_VEC Q0 Q10 Q18 32 *) + 0x9bab71f0; (* arm_UMADDL X16 W15 W11 X28 *) + 0x2eb780c0; (* arm_UMLAL_VEC Q0 Q6 Q23 32 *) + 0x8b5167a1; (* arm_ADD X1 X29 (Shiftedreg X17 LSR 25) *) + 0x2ea18219; (* arm_UMLAL_VEC Q25 Q16 Q1 32 *) + 0x9ba47e6b; (* arm_UMULL X11 W19 W4 *) + 0xf94053e8; (* arm_LDR X8 SP (Immediate_Offset (word 160)) *) + 0x0ebf9dda; (* arm_MUL_VEC Q26 Q14 Q31 32 64 *) + 0x2ea18151; (* arm_UMLAL_VEC Q17 Q10 Q1 32 *) + 0xf9404bef; (* arm_LDR X15 SP (Immediate_Offset (word 144)) *) + 0x2eb480d1; (* arm_UMLAL_VEC Q17 Q6 Q20 32 *) + 0x924067c9; (* arm_AND X9 X30 (rvalue (word 67108863)) *) + 0xb3606229; (* arm_BFM X9 X17 32 24 *) + 0x8b020051; (* arm_ADD X17 X2 X2 *) + 0xd360fdea; (* arm_LSR X10 X15 32 *) + 0x8b416b3b; (* arm_ADD X27 X25 (Shiftedreg X1 LSR 26) *) + 0x2eb480f9; (* arm_UMLAL_VEC Q25 Q7 Q20 32 *) + 0x8b0a014d; (* arm_ADD X13 X10 X10 *) + 0x2ead8279; (* arm_UMLAL_VEC Q25 Q19 Q13 32 *) + 0x8b5b66fd; (* arm_ADD X29 X23 (Shiftedreg X27 LSR 25) *) + 0x2eab81f9; (* arm_UMLAL_VEC Q25 Q15 Q11 32 *) + 0xd360fd1e; (* arm_LSR X30 X8 32 *) + 0x2eb28099; (* arm_UMLAL_VEC Q25 Q4 Q18 32 *) + 0x8b5d68b7; (* arm_ADD X23 X5 (Shiftedreg X29 LSR 26) *) + 0x2eb78159; (* arm_UMLAL_VEC Q25 Q10 Q23 32 *) + 0x924067ae; (* arm_AND X14 X29 (rvalue (word 67108863)) *) + 0x2eba80d9; (* arm_UMLAL_VEC Q25 Q6 Q26 32 *) + 0x8b576605; (* arm_ADD X5 X16 (Shiftedreg X23 LSR 25) *) + 0x4f415628; (* arm_SHL_VEC Q8 Q17 1 64 128 *) + 0x9bb12c4c; (* arm_UMADDL X12 W2 W17 X11 *) + 0x924064bd; (* arm_AND X29 X5 (rvalue (word 67108863)) *) + 0x9bb37e75; (* arm_UMULL X21 W19 W19 *) + 0x2eba80fd; (* arm_UMLAL_VEC Q29 Q7 Q26 32 *) + 0x0b0a0550; (* arm_ADD W16 W10 (Shiftedreg W10 LSL 1) *) + 0x2eba8203; (* arm_UMLAL_VEC Q3 Q16 Q26 32 *) + 0x0b0a1210; (* arm_ADD W16 W16 (Shiftedreg W10 LSL 4) *) + 0xb36062ee; (* arm_BFM X14 X23 32 24 *) + 0x0b18070a; (* arm_ADD W10 W24 (Shiftedreg W24 LSL 1) *) + 0x8b456b56; (* arm_ADD X22 X26 (Shiftedreg X5 LSR 26) *) + 0x0b18114a; (* arm_ADD W10 W10 (Shiftedreg W24 LSL 4) *) + 0x2eae8188; (* arm_UMLAL_VEC Q8 Q12 Q14 32 *) + 0x9bad5619; (* arm_UMADDL X25 W16 W13 X21 *) + 0x2ead8048; (* arm_UMLAL_VEC Q8 Q2 Q13 32 *) + 0xb36062dd; (* arm_BFM X29 X22 32 24 *) + 0x2eab80a8; (* arm_UMLAL_VEC Q8 Q5 Q11 32 *) + 0x8b18031a; (* arm_ADD X26 X24 X24 *) + 0x2eb28208; (* arm_UMLAL_VEC Q8 Q16 Q18 32 *) + 0xa906f7ee; (* arm_STP X14 X29 SP (Immediate_Offset (iword (&104))) *) + 0x2eb780e8; (* arm_UMLAL_VEC Q8 Q7 Q23 32 *) + 0x0b1e07d8; (* arm_ADD W24 W30 (Shiftedreg W30 LSL 1) *) + 0x6f6617b9; (* arm_USRA_VEC Q25 Q29 26 64 128 *) + 0x0b1e1318; (* arm_ADD W24 W24 (Shiftedreg W30 LSL 4) *) + 0x9baf7dfd; (* arm_UMULL X29 W15 W15 *) + 0x2eae805b; (* arm_UMLAL_VEC Q27 Q2 Q14 32 *) + 0x9bad7de3; (* arm_UMULL X3 W15 W13 *) + 0x2ead80bb; (* arm_UMLAL_VEC Q27 Q5 Q13 32 *) + 0x8b140295; (* arm_ADD X21 X20 X20 *) + 0x2eae81f8; (* arm_UMLAL_VEC Q24 Q15 Q14 32 *) + 0x9bb57e65; (* arm_UMULL X5 W19 W21 *) + 0x2ead8098; (* arm_UMLAL_VEC Q24 Q4 Q13 32 *) + 0x9240642b; (* arm_AND X11 X1 (rvalue (word 67108863)) *) + 0x6f671728; (* arm_USRA_VEC Q8 Q25 25 64 128 *) + 0x92406001; (* arm_AND X1 X0 (rvalue (word 33554431)) *) + 0x2eab821b; (* arm_UMLAL_VEC Q27 Q16 Q11 32 *) + 0x9bad1637; (* arm_UMADDL X23 W17 W13 X5 *) + 0x2eb280fb; (* arm_UMLAL_VEC Q27 Q7 Q18 32 *) + 0x8b1e03c5; (* arm_ADD X5 X30 X30 *) + 0x6f661500; (* arm_USRA_VEC Q0 Q8 26 64 128 *) + 0x8b0f01e0; (* arm_ADD X0 X15 X15 *) + 0x2eab8158; (* arm_UMLAL_VEC Q24 Q10 Q11 32 *) + 0x9ba05cf7; (* arm_UMADDL X23 W7 W0 X23 *) + 0x2eb280d8; (* arm_UMLAL_VEC Q24 Q6 Q18 32 *) + 0xd360fcfe; (* arm_LSR X30 X7 32 *) + 0x6f67141b; (* arm_USRA_VEC Q27 Q0 25 64 128 *) + 0x8b1e03d0; (* arm_ADD X16 X30 X30 *) + 0x4e3e1d14; (* arm_AND_VEC Q20 Q8 Q30 128 *) + 0x9bb05fcf; (* arm_UMADDL X15 W30 W16 X23 *) + 0x6f7f07d7; (* arm_USHR_VEC Q23 Q30 1 64 128 *) + 0x0b080517; (* arm_ADD W23 W8 (Shiftedreg W8 LSL 1) *) + 0x6f661778; (* arm_USRA_VEC Q24 Q27 26 64 128 *) + 0x0b0812f7; (* arm_ADD W23 W23 (Shiftedreg W8 LSL 4) *) + 0x9ba50e6e; (* arm_UMADDL X14 W19 W5 X3 *) + 0x4e3e1f68; (* arm_AND_VEC Q8 Q27 Q30 128 *) + 0x8b08011c; (* arm_ADD X28 X8 X8 *) + 0x4e371c1b; (* arm_AND_VEC Q27 Q0 Q23 128 *) + 0x9bb73d08; (* arm_UMADDL X8 W8 W23 X15 *) + 0x4e371f05; (* arm_AND_VEC Q5 Q24 Q23 128 *) + 0x9bbc3843; (* arm_UMADDL X3 W2 W28 X14 *) + 0x2ebc81f6; (* arm_UMLAL_VEC Q22 Q15 Q28 32 *) + 0xb360636b; (* arm_BFM X11 X27 32 24 *) + 0x4e851905; (* arm_UZP1 Q5 Q8 Q5 32 *) + 0x9ba5770e; (* arm_UMADDL X14 W24 W5 X29 *) + 0x9bbc3a65; (* arm_UMADDL X5 W19 W28 X14 *) + 0xfd4027f2; (* arm_LDR D18 SP (Immediate_Offset (word 72)) *) + 0x6e180652; (* arm_INS Q18 Q18 64 0 64 64 *) + 0x9bba0cef; (* arm_UMADDL X15 W7 W26 X3 *) + 0x0ebf9dac; (* arm_MUL_VEC Q12 Q13 Q31 32 64 *) + 0x2ead8215; (* arm_UMLAL_VEC Q21 Q16 Q13 32 *) + 0xa905afe9; (* arm_STP X9 X11 SP (Immediate_Offset (iword (&88))) *) + 0x2eab80f5; (* arm_UMLAL_VEC Q21 Q7 Q11 32 *) + 0x9bba163d; (* arm_UMADDL X29 W17 W26 X5 *) + 0x2eae8096; (* arm_UMLAL_VEC Q22 Q4 Q14 32 *) + 0x0b14068e; (* arm_ADD W14 W20 (Shiftedreg W20 LSL 1) *) + 0x2ead8156; (* arm_UMLAL_VEC Q22 Q10 Q13 32 *) + 0x0b1411ce; (* arm_ADD W14 W14 (Shiftedreg W20 LSL 4) *) + 0x9ba07e63; (* arm_UMULL X3 W19 W0 *) + 0x2eab80d6; (* arm_UMLAL_VEC Q22 Q6 Q11 32 *) + 0x9bb574fd; (* arm_UMADDL X29 W7 W21 X29 *) + 0x6f671715; (* arm_USRA_VEC Q21 Q24 25 64 128 *) + 0x9bae328b; (* arm_UMADDL X11 W20 W14 X12 *) + 0x4e371f20; (* arm_AND_VEC Q0 Q25 Q23 128 *) + 0x9bb53fc5; (* arm_UMADDL X5 W30 W21 X15 *) + 0x4e3e1fae; (* arm_AND_VEC Q14 Q29 Q30 128 *) + 0x9bad760c; (* arm_UMADDL X12 W16 W13 X29 *) + 0x6f6616b6; (* arm_USRA_VEC Q22 Q21 26 64 128 *) + 0x9bb00e3d; (* arm_UMADDL X29 W17 W16 X3 *) + 0x2eac80e3; (* arm_UMLAL_VEC Q3 Q7 Q12 32 *) + 0x8b1a0349; (* arm_ADD X9 X26 X26 *) + 0x4e3e1ea1; (* arm_AND_VEC Q1 Q21 Q30 128 *) + 0x8b4c68bb; (* arm_ADD X27 X5 (Shiftedreg X12 LSR 26) *) + 0x4e771ec8; (* arm_BIC_VEC Q8 Q22 Q23 128 *) + 0x9ba774fd; (* arm_UMADDL X29 W7 W7 X29 *) + 0x4e371ed1; (* arm_AND_VEC Q17 Q22 Q23 128 *) + 0x8b5b6725; (* arm_ADD X5 X25 (Shiftedreg X27 LSR 25) *) + 0x6f671503; (* arm_USRA_VEC Q3 Q8 25 64 128 *) + 0x9ba92319; (* arm_UMADDL X25 W24 W9 X8 *) + 0x2eba8149; (* arm_UMLAL_VEC Q9 Q10 Q26 32 *) + 0x8b0d01a8; (* arm_ADD X8 X13 X13 *) + 0x4e912836; (* arm_TRN1 Q22 Q1 Q17 32 128 *) + 0x9ba82d4b; (* arm_UMADDL X11 W10 W8 X11 *) + 0x6f681503; (* arm_USRA_VEC Q3 Q8 24 64 128 *) + 0x9bb07e74; (* arm_UMULL X20 W19 W16 *) + 0x0eb286da; (* arm_ADD_VEC Q26 Q22 Q18 32 64 *) + 0xfd402bfc; (* arm_LDR D28 SP (Immediate_Offset (word 80)) *) + 0x2eac80c9; (* arm_UMLAL_VEC Q9 Q6 Q12 32 *) + 0x9ba02ee3; (* arm_UMADDL X3 W23 W0 X11 *) + 0x6f6b1503; (* arm_USRA_VEC Q3 Q8 21 64 128 *) + 0x9bba755d; (* arm_UMADDL X29 W10 W26 X29 *) + 0x4e9b1a8b; (* arm_UZP1 Q11 Q20 Q27 32 *) + 0x9ba45054; (* arm_UMADDL X20 W2 W4 X20 *) + 0x9bb55149; (* arm_UMADDL X9 W10 W21 X20 *) + 0x6e0846d1; (* arm_INS Q17 Q22 0 64 64 128 *) + 0x6f661469; (* arm_USRA_VEC Q9 Q3 26 64 128 *) + 0x9bad7e6f; (* arm_UMULL X15 W19 W13 *) + 0x4e3e1c67; (* arm_AND_VEC Q7 Q3 Q30 128 *) + 0x8b10020b; (* arm_ADD X11 X16 X16 *) + 0x4e855961; (* arm_UZP2 Q1 Q11 Q5 32 *) + 0x9bad26f4; (* arm_UMADDL X20 W23 W13 X9 *) + 0x4e371d28; (* arm_AND_VEC Q8 Q9 Q23 128 *) + 0x9ba03c49; (* arm_UMADDL X9 W2 W0 X15 *) + 0x6f67152e; (* arm_USRA_VEC Q14 Q9 25 64 128 *) + 0x924064c6; (* arm_AND X6 X6 (rvalue (word 67108863)) *) + 0x4e8818e7; (* arm_UZP1 Q7 Q7 Q8 32 *) + 0x9bb576fd; (* arm_UMADDL X29 W23 W21 X29 *) + 0x4e85197b; (* arm_UZP1 Q27 Q11 Q5 32 *) + 0x9bba7e6f; (* arm_UMULL X15 W19 W26 *) + 0x6f6615c0; (* arm_USRA_VEC Q0 Q14 26 64 128 *) + 0x8b5664c6; (* arm_ADD X6 X6 (Shiftedreg X22 LSR 25) *) + 0x4e3e1dc3; (* arm_AND_VEC Q3 Q14 Q30 128 *) + 0x92679b76; (* arm_AND X22 X27 (rvalue (word 18446744073675997184)) *) + 0x2eb18742; (* arm_SUB_VEC Q2 Q26 Q17 32 64 *) + 0x0eb186c9; (* arm_ADD_VEC Q9 Q22 Q17 32 64 *) + 0x4e80186e; (* arm_UZP1 Q14 Q3 Q0 32 *) + 0x9bb53c42; (* arm_UMADDL X2 W2 W21 X15 *) + 0x4eb28765; (* arm_ADD_VEC Q5 Q27 Q18 32 128 *) + 0x8b5660a5; (* arm_ADD X5 X5 (Shiftedreg X22 LSR 24) *) + 0x0e893856; (* arm_ZIP1 Q22 Q2 Q9 32 64 *) + 0x6e010792; (* arm_INS Q18 Q28 0 0 8 64 *) + 0x4e8e18e8; (* arm_UZP1 Q8 Q7 Q14 32 *) + 0x8b5654b6; (* arm_ADD X22 X5 (Shiftedreg X22 LSR 21) *) + 0x4e8e58e3; (* arm_UZP2 Q3 Q7 Q14 32 *) + 0x9bb024e5; (* arm_UMADDL X5 W7 W16 X9 *) + 0x4eb28519; (* arm_ADD_VEC Q25 Q8 Q18 32 128 *) + 0x9ba059cf; (* arm_UMADDL X15 W14 W0 X22 *) + 0x4ea1876c; (* arm_ADD_VEC Q12 Q27 Q1 32 128 *) + 0x8b110229; (* arm_ADD X9 X17 X17 *) + 0x6ea184ae; (* arm_SUB_VEC Q14 Q5 Q1 32 128 *) + 0x9bb17e73; (* arm_UMULL X19 W19 W17 *) + 0x6ea38732; (* arm_SUB_VEC Q18 Q25 Q3 32 128 *) + 0xf94033f6; (* arm_LDR X22 SP (Immediate_Offset (word 96)) *) + 0x4ea38514; (* arm_ADD_VEC Q20 Q8 Q3 32 128 *) + 0x9bab3d4f; (* arm_UMADDL X15 W10 W11 X15 *) + 0x4e8c39d0; (* arm_ZIP1 Q16 Q14 Q12 32 128 *) + 0x9bad4dce; (* arm_UMADDL X14 W14 W13 X19 *) + 0x4e8c79ce; (* arm_ZIP2 Q14 Q14 Q12 32 128 *) + 0x92406371; (* arm_AND X17 X27 (rvalue (word 33554431)) *) + 0x4e947a40; (* arm_ZIP2 Q0 Q18 Q20 32 128 *) + 0x9ba43eef; (* arm_UMADDL X15 W23 W4 X15 *) + 0x4e943a41; (* arm_ZIP1 Q1 Q18 Q20 32 128 *) + 0x9ba0394a; (* arm_UMADDL X10 W10 W0 X14 *) + 0x0e897845; (* arm_ZIP2 Q5 Q2 Q9 32 64 *) + 0x0f215418; (* arm_SHL_VEC Q24 Q0 1 32 64 *) + 0x6e084433; (* arm_INS Q19 Q1 0 64 64 128 *) + 0x0f2156da; (* arm_SHL_VEC Q26 Q22 1 32 64 *) + 0x0f215611; (* arm_SHL_VEC Q17 Q16 1 32 64 *) + 0x6e08440f; (* arm_INS Q15 Q0 0 64 64 128 *) + 0x0f2154a7; (* arm_SHL_VEC Q7 Q5 1 32 64 *) + 0x0f215672; (* arm_SHL_VEC Q18 Q19 1 32 64 *) + 0x2eb8c02b; (* arm_UMULL_VEC Q11 Q1 Q24 32 *) + 0x9bb02af3; (* arm_UMADDL X19 W23 W16 X10 *) + 0x2eb1c026; (* arm_UMULL_VEC Q6 Q1 Q17 32 *) + 0x9bad08ea; (* arm_UMADDL X10 W7 W13 X2 *) + 0x6e084604; (* arm_INS Q4 Q16 0 64 64 128 *) + 0x6e0845ca; (* arm_INS Q10 Q14 0 64 64 128 *) + 0x2ebac029; (* arm_UMULL_VEC Q9 Q1 Q26 32 *) + 0xf9402fed; (* arm_LDR X13 SP (Immediate_Offset (word 88)) *) + 0x0f2155fc; (* arm_SHL_VEC Q28 Q15 1 32 64 *) + 0x0f215543; (* arm_SHL_VEC Q3 Q10 1 32 64 *) + 0xf94037ee; (* arm_LDR X14 SP (Immediate_Offset (word 104)) *) + 0x0ebf9d4c; (* arm_MUL_VEC Q12 Q10 Q31 32 64 *) + 0x2ea7c039; (* arm_UMULL_VEC Q25 Q1 Q7 32 *) + 0xf9403be2; (* arm_LDR X2 SP (Immediate_Offset (word 112)) *) + 0x2ebc8246; (* arm_UMLAL_VEC Q6 Q18 Q28 32 *) + 0x9ba02bdb; (* arm_UMADDL X27 W30 W0 X10 *) + 0x9ba05310; (* arm_UMADDL X16 W24 W0 X20 *) + 0x0f2155cd; (* arm_SHL_VEC Q13 Q14 1 32 64 *) + 0x9bba16e5; (* arm_UMADDL X5 W23 W26 X5 *) + 0x0ebf9ec2; (* arm_MUL_VEC Q2 Q22 Q31 32 64 *) + 0x2eadc035; (* arm_UMULL_VEC Q21 Q1 Q13 32 *) + 0x9ba87717; (* arm_UMADDL X23 W24 W8 X29 *) + 0x2eb3824b; (* arm_UMLAL_VEC Q11 Q18 Q19 32 *) + 0xb21f67ea; (* arm_MOV X10 (rvalue (word 576460743847706622)) *) + 0xd100094a; (* arm_SUB X10 X10 (rvalue (word 2)) *) + 0x9bb5171a; (* arm_UMADDL X26 W24 W21 X5 *) + 0x0ebf9ddd; (* arm_MUL_VEC Q29 Q14 Q31 32 64 *) + 0x2eba8279; (* arm_UMLAL_VEC Q25 Q19 Q26 32 *) + 0x8b466827; (* arm_ADD X7 X1 (Shiftedreg X6 LSR 26) *) + 0x0ebf9c94; (* arm_MUL_VEC Q20 Q4 Q31 32 64 *) + 0x924064c6; (* arm_AND X6 X6 (rvalue (word 67108863)) *) + 0x0f215648; (* arm_SHL_VEC Q8 Q18 1 32 64 *) + 0x0f215484; (* arm_SHL_VEC Q4 Q4 1 32 64 *) + 0x2eae83ab; (* arm_UMLAL_VEC Q11 Q29 Q14 32 *) + 0xb36064e6; (* arm_BFM X6 X7 32 25 *) + 0x2ea38019; (* arm_UMLAL_VEC Q25 Q0 Q3 32 *) + 0x9ba44f00; (* arm_UMADDL X0 W24 W4 X19 *) + 0x2ead81f9; (* arm_UMLAL_VEC Q25 Q15 Q13 32 *) + 0xf9003fe6; (* arm_STR X6 SP (Immediate_Offset (word 120)) *) + 0x2ea48255; (* arm_UMLAL_VEC Q21 Q18 Q4 32 *) + 0x9bab0f08; (* arm_UMADDL X8 W24 W11 X3 *) + 0x2eb18015; (* arm_UMLAL_VEC Q21 Q0 Q17 32 *) + 0xf9403ffe; (* arm_LDR X30 SP (Immediate_Offset (word 120)) *) + 0x0ebf9cae; (* arm_MUL_VEC Q14 Q5 Q31 32 64 *) + 0x8b0a0042; (* arm_ADD X2 X2 X10 *) + 0x0f215785; (* arm_SHL_VEC Q5 Q28 1 32 64 *) + 0x0f21549b; (* arm_SHL_VEC Q27 Q4 1 32 64 *) + 0x2ea08006; (* arm_UMLAL_VEC Q6 Q0 Q0 32 *) + 0x9ba93f0b; (* arm_UMADDL X11 W24 W9 X15 *) + 0x2ea38186; (* arm_UMLAL_VEC Q6 Q12 Q3 32 *) + 0x8b0a03c4; (* arm_ADD X4 X30 X10 *) + 0x2ea581cb; (* arm_UMLAL_VEC Q11 Q14 Q5 32 *) + 0x8b0a02c3; (* arm_ADD X3 X22 X10 *) + 0x2eb1804b; (* arm_UMLAL_VEC Q11 Q2 Q17 32 *) + 0x8b4b6806; (* arm_ADD X6 X0 (Shiftedreg X11 LSR 26) *) + 0x2ebb818b; (* arm_UMLAL_VEC Q11 Q12 Q27 32 *) + 0x8b0a01ce; (* arm_ADD X14 X14 X10 *) + 0x2ebb81c6; (* arm_UMLAL_VEC Q6 Q14 Q27 32 *) + 0x8b466508; (* arm_ADD X8 X8 (Shiftedreg X6 LSR 25) *) + 0x2ead8046; (* arm_UMLAL_VEC Q6 Q2 Q13 32 *) + 0xf29ff68a; (* arm_MOVK X10 (word 65460) 0 *) + 0x2ea48219; (* arm_UMLAL_VEC Q25 Q16 Q4 32 *) + 0x8b486a1d; (* arm_ADD X29 X16 (Shiftedreg X8 LSR 26) *) + 0x2ea3c03b; (* arm_UMULL_VEC Q27 Q1 Q3 32 *) + 0x9240656b; (* arm_AND X11 X11 (rvalue (word 67108863)) *) + 0x2ea38249; (* arm_UMLAL_VEC Q9 Q18 Q3 32 *) + 0x8b0a01b3; (* arm_ADD X19 X13 X10 *) + 0x2ead8009; (* arm_UMLAL_VEC Q9 Q0 Q13 32 *) + 0x92406505; (* arm_AND X5 X8 (rvalue (word 67108863)) *) + 0x2ea48389; (* arm_UMLAL_VEC Q9 Q28 Q4 32 *) + 0xb36060cb; (* arm_BFM X11 X6 32 24 *) + 0x2eb08209; (* arm_UMLAL_VEC Q9 Q16 Q16 32 *) + 0x9bbc6f1e; (* arm_UMADDL X30 W24 W28 X27 *) + 0x2ea781c9; (* arm_UMLAL_VEC Q9 Q14 Q7 32 *) + 0xcb0b026d; (* arm_SUB X13 X19 X11 *) + 0x2eb2c02a; (* arm_UMULL_VEC Q10 Q1 Q18 32 *) + 0x8b5d66e7; (* arm_ADD X7 X23 (Shiftedreg X29 LSR 25) *) + 0x2eaf8395; (* arm_UMLAL_VEC Q21 Q28 Q15 32 *) + 0xd360fdb0; (* arm_LSR X16 X13 32 *) + 0x2eb68055; (* arm_UMLAL_VEC Q21 Q2 Q22 32 *) + 0x8b476b40; (* arm_ADD X0 X26 (Shiftedreg X7 LSR 26) *) + 0x6f661539; (* arm_USRA_VEC Q25 Q9 26 64 128 *) + 0x924064f4; (* arm_AND X20 X7 (rvalue (word 67108863)) *) + 0x2ea1c036; (* arm_UMULL_VEC Q22 Q1 Q1 32 *) + 0x8b406728; (* arm_ADD X8 X25 (Shiftedreg X0 LSR 25) *) + 0x2ebcc027; (* arm_UMULL_VEC Q7 Q1 Q28 32 *) + 0x924063a1; (* arm_AND X1 X29 (rvalue (word 33554431)) *) + 0x4e771f32; (* arm_BIC_VEC Q18 Q25 Q23 128 *) + 0x92406513; (* arm_AND X19 X8 (rvalue (word 67108863)) *) + 0x4e3e1d30; (* arm_AND_VEC Q16 Q9 Q30 128 *) + 0x92406587; (* arm_AND X7 X12 (rvalue (word 67108863)) *) + 0x6f671656; (* arm_USRA_VEC Q22 Q18 25 64 128 *) + 0x8b486bca; (* arm_ADD X10 X30 (Shiftedreg X8 LSR 26) *) + 0x2eb88267; (* arm_UMLAL_VEC Q7 Q19 Q24 32 *) + 0xb36063a5; (* arm_BFM X5 X29 32 24 *) + 0x4e371f29; (* arm_AND_VEC Q9 Q25 Q23 128 *) + 0x8b4a64fb; (* arm_ADD X27 X7 (Shiftedreg X10 LSR 25) *) + 0x6f681656; (* arm_USRA_VEC Q22 Q18 24 64 128 *) + 0xd29db435; (* arm_MOV X21 (rvalue (word 60833)) *) + 0xd37ffab5; (* arm_LSL X21 X21 1 *) + 0x8b5b6a2f; (* arm_ADD X15 X17 (Shiftedreg X27 LSR 26) *) + 0x0f215479; (* arm_SHL_VEC Q25 Q3 1 32 64 *) + 0x2eb181c7; (* arm_UMLAL_VEC Q7 Q14 Q17 32 *) + 0x9240677d; (* arm_AND X29 X27 (rvalue (word 67108863)) *) + 0x6f6b1656; (* arm_USRA_VEC Q22 Q18 21 64 128 *) + 0xb36065fd; (* arm_BFM X29 X15 32 25 *) + 0x2eb881ca; (* arm_UMLAL_VEC Q10 Q14 Q24 32 *) + 0x924060d1; (* arm_AND X17 X6 (rvalue (word 33554431)) *) + 0x2ebc804a; (* arm_UMLAL_VEC Q10 Q2 Q28 32 *) + 0xcb050066; (* arm_SUB X6 X3 X5 *) + 0x2eb1818a; (* arm_UMLAL_VEC Q10 Q12 Q17 32 *) + 0x9bb54619; (* arm_UMADDL X25 W16 W21 X17 *) + 0x2ea483aa; (* arm_UMLAL_VEC Q10 Q29 Q4 32 *) + 0x2a0503ec; (* arm_MOV W12 W5 *) + 0x2ea48296; (* arm_UMLAL_VEC Q22 Q20 Q4 32 *) + 0xd360fcda; (* arm_LSR X26 X6 32 *) + 0x2ea881d6; (* arm_UMLAL_VEC Q22 Q14 Q8 32 *) + 0x92406018; (* arm_AND X24 X0 (rvalue (word 33554431)) *) + 0x2eb88056; (* arm_UMLAL_VEC Q22 Q2 Q24 32 *) + 0xa90817eb; (* arm_STP X11 X5 SP (Immediate_Offset (iword (&128))) *) + 0x2ea58196; (* arm_UMLAL_VEC Q22 Q12 Q5 32 *) + 0xb3606014; (* arm_BFM X20 X0 32 24 *) + 0x2eb183b6; (* arm_UMLAL_VEC Q22 Q29 Q17 32 *) + 0x9bb530cc; (* arm_UMADDL X12 W6 W21 X12 *) + 0x2ea4c032; (* arm_UMULL_VEC Q18 Q1 Q4 32 *) + 0xb3606153; (* arm_BFM X19 X10 32 24 *) + 0x2ea48047; (* arm_UMLAL_VEC Q7 Q2 Q4 32 *) + 0xcb1401c7; (* arm_SUB X7 X14 X20 *) + 0x2ead827b; (* arm_UMLAL_VEC Q27 Q19 Q13 32 *) + 0x2a1403e8; (* arm_MOV W8 W20 *) + 0x6f6616ca; (* arm_USRA_VEC Q10 Q22 26 64 128 *) + 0xd360fcee; (* arm_LSR X14 X7 32 *) + 0x2eb18272; (* arm_UMLAL_VEC Q18 Q19 Q17 32 *) + 0x9240615c; (* arm_AND X28 X10 (rvalue (word 33554431)) *) + 0x2ead8187; (* arm_UMLAL_VEC Q7 Q12 Q13 32 *) + 0xcb130045; (* arm_SUB X5 X2 X19 *) + 0x6f67154b; (* arm_USRA_VEC Q11 Q10 25 64 128 *) + 0x2a1303e2; (* arm_MOV W2 W19 *) + 0x2ea4801b; (* arm_UMLAL_VEC Q27 Q0 Q4 32 *) + 0x2eb981d5; (* arm_UMLAL_VEC Q21 Q14 Q25 32 *) + 0xcb1d0097; (* arm_SUB X23 X4 X29 *) + 0x6f661567; (* arm_USRA_VEC Q7 Q11 26 64 128 *) + 0x2a1d03e0; (* arm_MOV W0 W29 *) + 0x2ebc8012; (* arm_UMLAL_VEC Q18 Q0 Q28 32 *) + 0xd360fef6; (* arm_LSR X22 X23 32 *) + 0x2eb181fb; (* arm_UMLAL_VEC Q27 Q15 Q17 32 *) + 0xf90053fd; (* arm_STR X29 SP (Immediate_Offset (word 160)) *) + 0x6f6714e6; (* arm_USRA_VEC Q6 Q7 25 64 128 *) + 0x2a0b03f1; (* arm_MOV W17 W11 *) + 0x4e3e1ec0; (* arm_AND_VEC Q0 Q22 Q30 128 *) + 0x9bb5075b; (* arm_UMADDL X27 W26 W21 X1 *) + 0x2ead81d2; (* arm_UMLAL_VEC Q18 Q14 Q13 32 *) + 0x9bb502fe; (* arm_UMADDL X30 W23 W21 X0 *) + 0x2ea38052; (* arm_UMLAL_VEC Q18 Q2 Q3 32 *) + 0xd360fcaa; (* arm_LSR X10 X5 32 *) + 0x4e3e1cc4; (* arm_AND_VEC Q4 Q6 Q30 128 *) + 0x4e371d41; (* arm_AND_VEC Q1 Q10 Q23 128 *) + 0x9bb561c4; (* arm_UMADDL X4 W14 W21 X24 *) + 0xf9402fe0; (* arm_LDR X0 SP (Immediate_Offset (word 88)) *) + 0x4e0c1c00; (* arm_INS_GEN Q0 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c01; (* arm_INS_GEN Q1 W0 32 32 *) + 0x9bb520e9; (* arm_UMADDL X9 W7 W21 X8 *) + 0x6f6614d2; (* arm_USRA_VEC Q18 Q6 26 64 128 *) + 0x9bb57158; (* arm_UMADDL X24 W10 W21 X28 *) + 0x4e371ce3; (* arm_AND_VEC Q3 Q7 Q23 128 *) + 0x9bb53ec8; (* arm_UMADDL X8 W22 W21 X15 *) + 0x2eba81db; (* arm_UMLAL_VEC Q27 Q14 Q26 32 *) + 0x9bb545af; (* arm_UMADDL X15 W13 W21 X17 *) + 0x6f671655; (* arm_USRA_VEC Q21 Q18 25 64 128 *) + 0xa9094ff4; (* arm_STP X20 X19 SP (Immediate_Offset (iword (&144))) *) + 0x4e3e1d62; (* arm_AND_VEC Q2 Q11 Q30 128 *) + 0xd359fd1d; (* arm_LSR X29 X8 25 *) + 0xf94043e3; (* arm_LDR X3 SP (Immediate_Offset (word 128)) *) + 0x4e0c1c6a; (* arm_INS_GEN Q10 W3 32 32 *) 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) + 0x4e0c1c6b; (* arm_INS_GEN Q11 W3 32 32 *) + 0x8b1d01f1; (* arm_ADD X17 X15 X29 *) + 0x6f6616bb; (* arm_USRA_VEC Q27 Q21 26 64 128 *) + 0x8b1d063c; (* arm_ADD X28 X17 (Shiftedreg X29 LSL 1) *) + 0x4e3e1ea6; (* arm_AND_VEC Q6 Q21 Q30 128 *) + 0x92406114; (* arm_AND X20 X8 (rvalue (word 33554431)) *) + 0x4e371e45; (* arm_AND_VEC Q5 Q18 Q23 128 *) + 0x8b1d1391; (* arm_ADD X17 X28 (Shiftedreg X29 LSL 4) *) + 0x4e371f67; (* arm_AND_VEC Q7 Q27 Q23 128 *) + 0xf94047e3; (* arm_LDR X3 SP (Immediate_Offset (word 136)) *) + 0x4e0c1c76; (* arm_INS_GEN Q22 W3 32 32 *) 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) + 0x4e0c1c77; (* arm_INS_GEN Q23 W3 32 32 *) + 0x8b516b3d; (* arm_ADD X29 X25 (Shiftedreg X17 LSR 26) *) + 0xf94013ef; (* arm_LDR X15 SP (Immediate_Offset (word 32)) *) + 0x4e041dea; (* arm_INS_GEN Q10 W15 0 32 *) 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) + 0x4e041deb; (* arm_INS_GEN Q11 W15 0 32 *) + 0x9240662b; (* arm_AND X11 X17 (rvalue (word 67108863)) *) + 0x6f671770; (* arm_USRA_VEC Q16 Q27 25 64 128 *) + 0x8b5d6588; (* arm_ADD X8 X12 (Shiftedreg X29 LSR 25) *) + 0xf9404be3; (* arm_LDR X3 SP (Immediate_Offset (word 144)) *) + 0x4e0c1c6e; (* arm_INS_GEN Q14 W3 32 32 *) + 0xd360fc63; (* arm_LSR X3 X3 32 *) + 0x4e0c1c6f; (* arm_INS_GEN Q15 W3 32 32 *) + 0x924063ac; (* arm_AND X12 X29 (rvalue (word 33554431)) *) + 0xf94017ef; (* arm_LDR X15 SP (Immediate_Offset (word 40)) *) + 0x4e041df6; (* arm_INS_GEN Q22 W15 0 32 *) 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) + 0x4e041df7; (* arm_INS_GEN Q23 W15 0 32 *) + 0x8b486b7c; (* arm_ADD X28 X27 (Shiftedreg X8 LSR 26) *) + 0x4e3e1e08; (* arm_AND_VEC Q8 Q16 Q30 128 *) + 0x9baa7d81; (* arm_UMULL X1 W12 W10 *) + 0xf9404fe3; (* arm_LDR X3 SP (Immediate_Offset (word 152)) *) + 0x4e0c1c71; (* arm_INS_GEN Q17 W3 32 32 *) + 0xd360fc63; (* arm_LSR X3 X3 32 *) + 0x4e0c1c72; (* arm_INS_GEN Q18 W3 32 32 *) + 0x8b5c6539; (* arm_ADD X25 X9 (Shiftedreg X28 LSR 25) *) + 0xf9401bef; (* arm_LDR X15 SP (Immediate_Offset (word 48)) *) + 0x4e041dee; (* arm_INS_GEN Q14 W15 0 32 *) 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) + 0x4e041def; (* arm_INS_GEN Q15 W15 0 32 *) + 0x9bb508b3; (* arm_UMADDL X19 W5 W21 X2 *) + 0x6f661609; (* arm_USRA_VEC Q9 Q16 26 64 128 *) + 0x8b596882; (* arm_ADD X2 X4 (Shiftedreg X25 LSR 26) *) + 0xf94053e3; (* arm_LDR X3 SP (Immediate_Offset (word 160)) *) + 0x4e0c1c78; (* arm_INS_GEN Q24 W3 32 32 *) + 0xd360fc63; (* arm_LSR X3 X3 32 *) + 0x4e0c1c79; (* arm_INS_GEN Q25 W3 32 32 *) + 0x9bb77d83; (* arm_UMULL X3 W12 W23 *) + 0xf9401fef; (* arm_LDR X15 SP (Immediate_Offset (word 56)) *) + 0x4e041df1; (* arm_INS_GEN Q17 W15 0 32 *) 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xd2801fb4; (* arm_MOV X20 (rvalue (word 253)) *) - 0xa94e1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&224))) *) - 0xa9440fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&64))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa94f23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&240))) *) - 0xa9450fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&80))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9081be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&128))) *) - 0xa90923e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&144))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94a23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa9531be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa94b23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90613e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&96))) *) - 0xa9071be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&112))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa94a0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&160))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa94b0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&176))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90a1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0xa90b23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xa94e13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&224))) *) - 0xa94423e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&64))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa94f1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&240))) *) - 0xa94523e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&80))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) + 0x4e041df2; (* arm_INS_GEN Q18 W15 0 32 *) + 0x8b42667d; (* arm_ADD X29 X19 (Shiftedreg X2 LSR 25) *) + 0x2eb7c01a; (* arm_UMULL_VEC Q26 Q0 Q23 32 *) + 0x92406395; (* arm_AND X21 X28 (rvalue (word 33554431)) *) + 0xf94033e0; (* arm_LDR X0 SP (Immediate_Offset (word 96)) *) + 0x4e0c1c02; (* arm_INS_GEN Q2 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c03; (* arm_INS_GEN Q3 W0 32 32 *) + 0x9ba50ebb; (* arm_UMADDL X27 W21 W5 X3 *) + 0xf94023ef; (* arm_LDR X15 SP (Immediate_Offset (word 64)) *) + 0x4e041df8; (* arm_INS_GEN Q24 W15 0 32 *) + 0xd360fdef; (* arm_LSR X15 X15 32 *) + 0x4e041df9; (* arm_INS_GEN Q25 W15 0 32 *) + 0x8b5d6b11; (* arm_ADD X17 X24 (Shiftedreg X29 LSR 26) *) + 0x2eb2c03d; (* arm_UMULL_VEC Q29 Q1 Q18 32 *) + 0x9240650f; (* arm_AND X15 X8 (rvalue (word 67108863)) *) + 0x2eafc014; (* arm_UMULL_VEC Q20 Q0 Q15 32 *) + 0x8b5167d3; (* arm_ADD X19 X30 (Shiftedreg X17 LSR 25) *) + 0x92406223; (* arm_AND X3 X17 (rvalue (word 33554431)) *) + 0x0ebf9f2c; (* arm_MUL_VEC Q12 Q25 Q31 32 64 *) + 0xf94037e0; (* arm_LDR X0 SP (Immediate_Offset (word 104)) *) + 0x4e0c1c04; (* arm_INS_GEN Q4 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c05; (* arm_INS_GEN Q5 W0 32 32 *) + 0x8b536a84; (* arm_ADD X4 X20 (Shiftedreg X19 LSR 26) *) + 0x2eab805a; (* arm_UMLAL_VEC Q26 Q2 Q11 32 *) + 0x0b03047c; (* arm_ADD W28 W3 (Shiftedreg W3 LSL 1) *) + 0x2eb78054; (* arm_UMLAL_VEC Q20 Q2 Q23 32 *) + 0x0b03139c; (* arm_ADD W28 W28 (Shiftedreg W3 LSL 4) *) + 0x9ba57d88; (* arm_UMULL X8 W12 W5 *) + 0xf9403be0; (* arm_LDR X0 SP (Immediate_Offset (word 112)) *) + 0x4e0c1c06; (* arm_INS_GEN Q6 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c07; (* arm_INS_GEN Q7 W0 32 32 *) + 0x9240673e; (* arm_AND X30 X25 (rvalue (word 67108863)) *) + 0x0ebf9e50; (* arm_MUL_VEC Q16 Q18 Q31 32 64 *) + 0x0b040491; (* arm_ADD W17 W4 (Shiftedreg W4 LSL 1) *) + 0x2eafc035; (* arm_UMULL_VEC Q21 Q1 Q15 32 *) + 0x0b041231; (* arm_ADD W17 W17 (Shiftedreg W4 LSL 4) *) + 0x9ba722b9; (* arm_UMADDL X25 W21 W7 X8 *) + 0x2eab8094; (* arm_UMLAL_VEC Q20 Q4 Q11 32 *) + 0x0b1506a8; (* arm_ADD W8 W21 (Shiftedreg W21 LSL 1) *) + 0xf9403fe0; (* arm_LDR X0 SP (Immediate_Offset (word 120)) *) + 0x0b151108; (* arm_ADD W8 W8 (Shiftedreg W21 LSL 4) *) + 0x4e0c1c08; (* arm_INS_GEN Q8 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c09; (* arm_INS_GEN Q9 W0 32 32 *) + 0x92406042; (* arm_AND X2 X2 (rvalue (word 33554431)) *) + 0x2eaf807d; (* arm_UMLAL_VEC Q29 Q3 Q15 32 *) + 0x9ba66458; (* arm_UMADDL X24 W2 W6 X25 *) + 0x2eb9c00d; (* arm_UMULL_VEC Q13 Q0 Q25 32 *) + 0x9ba76c59; (* arm_UMADDL X25 W2 W7 X27 *) + 0x9ba66460; (* arm_UMADDL X0 W3 W6 X25 *) + 0x0ebf9df3; (* arm_MUL_VEC Q19 Q15 Q31 32 64 *) + 0x2eb2c01b; (* arm_UMULL_VEC Q27 Q0 Q18 32 *) + 0x9bad6074; (* arm_UMADDL X20 W3 W13 X24 *) + 0x2eac80d4; (* arm_UMLAL_VEC Q20 Q6 Q12 32 *) + 0x9bae06b8; (* arm_UMADDL X24 W21 W14 X1 *) + 0x2eb2804d; (* arm_UMLAL_VEC Q13 Q2 Q18 32 *) + 0x9bad0089; (* arm_UMADDL X9 W4 W13 X0 *) + 0x2eabc019; (* arm_UMULL_VEC Q25 Q0 Q11 32 *) + 0x9bb75234; (* arm_UMADDL X20 W17 W23 X20 *) + 0x2eaf805b; (* arm_UMLAL_VEC Q27 Q2 Q15 32 *) + 0x9bba6040; (* arm_UMADDL X0 W2 W26 X24 *) + 0x2eabc03c; (* arm_UMULL_VEC Q28 Q1 Q11 32 *) + 0x9ba57e38; (* arm_UMULL X24 W17 W5 *) + 0x2eb780bd; (* arm_UMLAL_VEC Q29 Q5 Q23 32 *) + 0x9bb62569; (* arm_UMADDL X9 W11 W22 X9 *) + 0x2eaf808d; (* arm_UMLAL_VEC Q13 Q4 Q15 32 *) + 0x9bb0007b; (* arm_UMADDL X27 W3 W16 X0 *) + 0x2eb7809b; (* arm_UMLAL_VEC Q27 Q4 Q23 32 *) + 0x9bae7e20; (* arm_UMULL X0 W17 W14 *) + 0x2eab80db; (* arm_UMLAL_VEC Q27 Q6 Q11 32 *) + 0x9bae7d84; (* arm_UMULL X4 W12 W14 *) + 0x2eac811b; (* arm_UMLAL_VEC Q27 Q8 Q12 32 *) + 0x9baa5179; (* arm_UMADDL X25 W11 W10 X20 *) + 0x2eb1803b; (* arm_UMLAL_VEC Q27 Q1 Q17 32 *) + 0x9baa0380; (* arm_UMADDL X0 W28 W10 X0 *) + 0x2eb780cd; (* arm_UMLAL_VEC Q13 Q6 Q23 32 *) + 0x9ba67e23; (* arm_UMULL X3 W17 W6 *) + 0x2eab810d; (* arm_UMLAL_VEC Q13 Q8 Q11 32 *) + 0x9bba12a1; (* arm_UMADDL X1 W21 W26 X4 *) + 0x2eb08114; (* arm_UMLAL_VEC Q20 Q8 Q16 32 *) + 0x9bad6044; (* arm_UMADDL X4 W2 W13 X24 *) + 0x2eac807c; (* arm_UMLAL_VEC Q28 Q3 Q12 32 *) + 0x9ba70f94; (* arm_UMADDL X20 W28 W7 X3 *) + 0x2eab80fd; (* arm_UMLAL_VEC Q29 Q7 Q11 32 *) + 0x92406663; (* arm_AND X3 X19 (rvalue (word 67108863)) *) + 0x2eac813d; (* arm_UMLAL_VEC Q29 Q9 Q12 32 *) + 0x9bb66e33; (* arm_UMADDL X19 W17 W22 X27 *) + 0x0b02045b; (* arm_ADD W27 W2 (Shiftedreg W2 LSL 1) *) + 0x0ebf9f12; (* arm_MUL_VEC Q18 Q24 Q31 32 64 *) + 0x0b02137b; (* arm_ADD W27 W27 (Shiftedreg W2 LSL 4) *) + 0x2eb78075; (* arm_UMLAL_VEC Q21 Q3 Q23 32 *) + 0x9ba77e38; (* arm_UMULL X24 W17 W7 *) + 0x2eb8802d; (* arm_UMLAL_VEC Q13 Q1 Q24 32 *) + 0x8b130273; (* arm_ADD X19 X19 X19 *) + 0x4f4157bd; (* arm_SHL_VEC Q29 Q29 1 64 128 *) + 0x9bb00441; (* arm_UMADDL X1 W2 W16 X1 *) + 0x2eb7c02f; (* arm_UMULL_VEC Q15 Q1 Q23 32 *) + 0x9bb60360; (* arm_UMADDL X0 W27 W22 X0 *) + 0x2eb8801d; (* arm_UMLAL_VEC Q29 Q0 Q24 32 *) + 0x9ba56382; (* arm_UMADDL X2 W28 W5 X24 *) + 0x0ebf9ef8; (* arm_MUL_VEC Q24 Q23 Q31 32 64 *) + 0x9bb71384; (* arm_UMADDL X4 W28 W23 X4 *) + 0x2eab80b5; (* arm_UMLAL_VEC Q21 Q5 Q11 32 *) + 0x9ba55378; (* arm_UMADDL X24 W27 W5 X20 *) + 0x2eae8034; (* arm_UMLAL_VEC Q20 Q1 Q14 32 *) + 0x9bb74d74; (* arm_UMADDL X20 W11 W23 X19 *) + 0x2eac809a; (* arm_UMLAL_VEC Q26 Q4 Q12 32 *) + 0x9bb70b73; (* arm_UMADDL X19 W27 W23 X2 *) + 0x2eb080da; (* arm_UMLAL_VEC Q26 Q6 Q16 32 *) + 0x9ba612a2; (* arm_UMADDL X2 W21 W6 X4 *) + 0x2eb1805d; (* arm_UMLAL_VEC Q29 Q2 Q17 32 *) + 0x9bb76118; (* arm_UMADDL X24 W8 W23 X24 *) + 0x2eab806f; (* arm_UMLAL_VEC Q15 Q3 Q11 32 *) + 0x9bb002a0; (* arm_UMADDL X0 W21 W16 X0 *) + 0x9bad4ea4; (* arm_UMADDL X4 W21 W13 X19 *) + 0x0ebf9d77; (* arm_MUL_VEC Q23 Q11 Q31 32 64 *) + 0x2eb68074; (* arm_UMLAL_VEC Q20 Q3 Q22 32 *) + 0x9ba70982; (* arm_UMADDL X2 W12 W7 X2 *) + 0x2eaa80b4; (* arm_UMLAL_VEC Q20 Q5 Q10 32 *) + 0x9bba0193; (* arm_UMADDL X19 W12 W26 X0 *) + 0x2eae809d; (* arm_UMLAL_VEC Q29 Q4 Q14 32 *) + 0x9bad6180; (* arm_UMADDL X0 W12 W13 X24 *) + 0x2eb3811a; (* arm_UMLAL_VEC Q26 Q8 Q19 32 *) + 0x9ba551f4; (* arm_UMADDL X20 W15 W5 X20 *) + 0x2eb6803a; (* arm_UMLAL_VEC Q26 Q1 Q22 32 *) + 0x9baa25f5; (* arm_UMADDL X21 W15 W10 X9 *) + 0x2eaa807a; (* arm_UMLAL_VEC Q26 Q3 Q10 32 *) + 0x924067a9; (* arm_AND X9 X29 (rvalue (word 67108863)) *) + 0x2eb680dd; (* arm_UMLAL_VEC Q29 Q6 Q22 32 *) + 0x9ba753d4; (* arm_UMADDL X20 W30 W7 X20 *) + 0x9bb60781; (* arm_UMADDL X1 W28 W22 X1 *) + 0x8b130278; (* arm_ADD X24 X19 X19 *) + 0x2eacc02b; (* arm_UMULL_VEC Q11 Q1 Q12 32 *) + 0x0b030473; (* arm_ADD W19 W3 (Shiftedreg W3 LSL 1) *) + 0x2eb280ba; (* arm_UMLAL_VEC Q26 Q5 Q18 32 *) + 0x0b031273; (* arm_ADD W19 W19 (Shiftedreg W3 LSL 4) *) + 0x9ba65134; (* arm_UMADDL X20 W9 W6 X20 *) + 0x2eaa811d; (* arm_UMLAL_VEC Q29 Q8 Q10 32 *) + 0x0b09053d; (* arm_ADD W29 W9 (Shiftedreg W9 LSL 1) *) + 0x2eb1806d; (* arm_UMLAL_VEC Q13 Q3 Q17 32 *) + 0x0b0913bd; (* arm_ADD W29 W29 (Shiftedreg W9 LSL 4) *) + 0x9baa0a62; (* arm_UMADDL X2 W19 W10 X2 *) + 0x2eb0806b; (* arm_UMLAL_VEC Q11 Q3 Q16 32 *) + 0x9bae57d5; (* arm_UMADDL X21 W30 W14 X21 *) + 0x2eb380ab; (* arm_UMLAL_VEC Q11 Q5 Q19 32 *) + 0x9bad5074; (* arm_UMADDL X20 W3 W13 X20 *) + 0x2eb880eb; (* arm_UMLAL_VEC Q11 Q7 Q24 32 *) + 0x9bb60ba2; (* arm_UMADDL X2 W29 W22 X2 *) + 0x2eb7812b; (* arm_UMLAL_VEC Q11 Q9 Q23 32 *) + 0x9bba5535; (* arm_UMADDL X21 W9 W26 X21 *) + 0x6f7f07d7; (* arm_USHR_VEC Q23 Q30 1 64 128 *) + 0x9baa0621; (* arm_UMADDL X1 W17 W10 X1 *) + 0x2eae80ad; (* arm_UMLAL_VEC Q13 Q5 Q14 32 *) + 0x9ba56278; (* arm_UMADDL X24 W19 W5 X24 *) + 0x2eae807b; (* arm_UMLAL_VEC Q27 Q3 Q14 32 *) + 0x9bb05475; (* arm_UMADDL X21 W3 W16 X21 *) + 0x4f41556b; (* arm_SHL_VEC Q11 Q11 1 64 128 *) + 0x0b1e07c3; (* arm_ADD W3 W30 (Shiftedreg W30 LSL 1) *) + 0x2eb080bc; (* arm_UMLAL_VEC Q28 Q5 Q16 32 *) + 0x0b1e1063; (* arm_ADD W3 W3 (Shiftedreg W30 LSL 4) *) + 0x9bb763b8; (* arm_UMADDL X24 W29 W23 X24 *) + 0x2eb380fc; (* arm_UMLAL_VEC Q28 Q7 Q19 32 *) + 0x8b010021; (* arm_ADD X1 X1 X1 *) + 0x2eb8813c; (* arm_UMLAL_VEC Q28 Q9 Q24 32 *) + 0x9ba50561; (* arm_UMADDL X1 W11 W5 X1 *) + 0x2eac80af; (* arm_UMLAL_VEC Q15 Q5 Q12 32 *) + 0x9bad63d8; (* arm_UMADDL X24 W30 W13 X24 *) + 0x2eb080ef; (* arm_UMLAL_VEC Q15 Q7 Q16 32 *) + 0x9bae65f9; (* arm_UMADDL X25 W15 W14 X25 *) + 0x2eb3812f; (* arm_UMLAL_VEC Q15 Q9 Q19 32 *) + 0x9ba705e1; (* arm_UMADDL X1 W15 W7 X1 *) + 0x4f41579c; (* arm_SHL_VEC Q28 Q28 1 64 128 *) + 0x9ba661f8; (* arm_UMADDL X24 W15 W6 X24 *) + 0x2eac80f5; (* arm_UMLAL_VEC Q21 Q7 Q12 32 *) + 0x9bb00bc2; (* arm_UMADDL X2 W30 W16 X2 *) + 0x2eb08135; (* arm_UMLAL_VEC Q21 Q9 Q16 32 *) + 0x9bba67d9; (* arm_UMADDL X25 W30 W26 X25 *) + 0x4f4155ef; (* arm_SHL_VEC Q15 Q15 1 64 128 *) + 0x9ba607de; (* arm_UMADDL X30 W30 W6 X1 *) + 0x2eb6801c; (* arm_UMLAL_VEC Q28 Q0 Q22 32 *) + 0x9bba09e1; (* arm_UMADDL X1 W15 W26 X2 *) + 0x2eaa805c; (* arm_UMLAL_VEC Q28 Q2 Q10 32 *) + 0x9bb06522; (* arm_UMADDL X2 W9 W16 X25 *) + 0x4f4156b5; (* arm_SHL_VEC Q21 Q21 1 64 128 *) + 0x9ba76178; (* arm_UMADDL X24 W11 W7 X24 *) + 0x2eae800f; (* arm_UMLAL_VEC Q15 Q0 Q14 32 *) + 0x9bae0561; (* arm_UMADDL X1 W11 W14 X1 *) + 0x2eb18015; (* arm_UMLAL_VEC Q21 Q0 Q17 32 *) + 0x9bad7939; (* arm_UMADDL X25 W9 W13 X30 *) + 0x2eb2809c; (* arm_UMLAL_VEC Q28 Q4 Q18 32 *) + 0x9bba0260; (* arm_UMADDL X0 W19 W26 X0 *) + 0x2eac8059; (* arm_UMLAL_VEC Q25 Q2 Q12 32 *) + 0x8b586821; (* arm_ADD X1 X1 (Shiftedreg X24 LSR 26) *) + 0x2eb08099; (* arm_UMLAL_VEC Q25 Q4 Q16 32 *) + 0x9bb60a7e; (* arm_UMADDL X30 W19 W22 X2 *) + 0x2eae8055; (* arm_UMLAL_VEC Q21 Q2 Q14 32 *) + 0x9ba61184; (* arm_UMADDL X4 W12 W6 X4 *) + 0x0ebf9dce; (* arm_MUL_VEC Q14 Q14 Q31 32 64 *) + 0x9bb76679; (* arm_UMADDL X25 W19 W23 X25 *) + 0x92406022; (* arm_AND X2 X1 (rvalue (word 33554431)) *) + 0x0ebf9e30; (* arm_MUL_VEC Q16 Q17 Q31 32 64 *) + 0x2eb380d9; (* arm_UMLAL_VEC Q25 Q6 Q19 32 *) + 0x9bae1269; (* arm_UMADDL X9 W19 W14 X4 *) + 0x2eb680ed; (* arm_UMLAL_VEC Q13 Q7 Q22 32 *) + 0x8b416739; (* arm_ADD X25 X25 (Shiftedreg X1 LSR 25) *) + 0x2eb68095; (* arm_UMLAL_VEC Q21 Q4 Q22 32 *) + 0x9bae03a0; (* arm_UMADDL X0 W29 W14 X0 *) + 0x2eb080fa; (* arm_UMLAL_VEC Q26 Q7 Q16 32 *) + 0x8b596bde; (* arm_ADD X30 X30 (Shiftedreg X25 LSR 26) *) + 0x2eae813a; (* arm_UMLAL_VEC Q26 Q9 Q14 32 *) + 0x0b0f05e1; (* arm_ADD W1 W15 (Shiftedreg W15 LSL 1) *) + 0x2eb080dc; (* arm_UMLAL_VEC Q28 Q6 Q16 32 *) + 0x0b0f1021; (* arm_ADD W1 W1 (Shiftedreg W15 LSL 4) *) + 0x8b5e6684; (* arm_ADD X4 X20 (Shiftedreg X30 LSR 25) *) + 0x2eae811c; (* arm_UMLAL_VEC Q28 Q8 Q14 32 *) + 0x92406739; (* arm_AND X25 X25 (rvalue (word 67108863)) *) + 0x2eb6804f; (* arm_UMLAL_VEC Q15 Q2 Q22 32 *) + 0x8b446ab5; (* arm_ADD X21 X21 (Shiftedreg X4 LSR 26) *) + 0x2eaa800b; (* arm_UMLAL_VEC Q11 Q0 Q10 32 *) + 0xb36063d9; (* arm_BFM X25 X30 32 24 *) + 0x2eb2804b; (* arm_UMLAL_VEC Q11 Q2 Q18 32 *) + 0x926696be; (* arm_AND X30 X21 (rvalue (word 18446744073642442752)) *) + 0x6f66179a; (* arm_USRA_VEC Q26 Q28 26 64 128 *) + 0xd35affd4; (* arm_LSR X20 X30 26 *) + 0x2eaa808f; (* arm_UMLAL_VEC Q15 Q4 Q10 32 *) + 0x8b5e6694; (* arm_ADD X20 X20 (Shiftedreg X30 LSR 25) *) + 0x2eb280cf; (* arm_UMLAL_VEC Q15 Q6 Q18 32 *) + 0x9baa27a9; (* arm_UMADDL X9 W29 W10 X9 *) + 0x2eb0810f; (* arm_UMLAL_VEC Q15 Q8 Q16 32 *) + 0x8b5e5a9e; (* arm_ADD X30 X20 (Shiftedreg X30 LSR 22) *) + 0x2eb680bb; (* arm_UMLAL_VEC Q27 Q5 Q22 32 *) + 0x9bba7e34; (* arm_UMULL X20 W17 W26 *) + 0x2eb280f4; (* arm_UMLAL_VEC Q20 Q7 Q18 32 *) + 0x9bb07a3e; (* arm_UMADDL X30 W17 W16 X30 *) + 0x2eb08134; (* arm_UMLAL_VEC Q20 Q9 Q16 32 *) + 0x9baa0071; (* arm_UMADDL X17 W3 W10 X0 *) + 0x6f67174f; (* arm_USRA_VEC Q15 Q26 25 64 128 *) + 0x9bae5380; (* arm_UMADDL X0 W28 W14 X20 *) + 0x2eaa80fb; (* arm_UMLAL_VEC Q27 Q7 Q10 32 *) + 0x9bba7b94; (* arm_UMADDL X20 W28 W26 X30 *) + 0x2eb2813b; (* arm_UMLAL_VEC Q27 Q9 Q18 32 *) + 0x0b0c059c; (* arm_ADD W28 W12 (Shiftedreg W12 LSL 1) *) + 0x6f6615f4; (* arm_USRA_VEC Q20 Q15 26 64 128 *) + 0x0b0c139c; (* arm_ADD W28 W28 (Shiftedreg W12 LSL 4) *) + 0x9baa037e; (* arm_UMADDL X30 W27 W10 X0 *) + 0x4e3e1df1; (* arm_AND_VEC Q17 Q15 Q30 128 *) + 0x9bae537b; (* arm_UMADDL X27 W27 W14 X20 *) + 0x9baa6d00; (* arm_UMADDL X0 W8 W10 X27 *) + 0x0ebf9ecc; (* arm_MUL_VEC Q12 Q22 Q31 32 64 *) + 0x4e371e8f; (* arm_AND_VEC Q15 Q20 Q23 128 *) + 0x9bb6246e; (* arm_UMADDL X14 W3 W22 X9 *) + 0x2eaa80d5; (* arm_UMLAL_VEC Q21 Q6 Q10 32 *) + 0x9bb6791b; (* arm_UMADDL X27 W8 W22 X30 *) + 0x4e8f2a2f; (* arm_TRN1 Q15 Q17 Q15 32 128 *) + 0x9bb6038a; (* arm_UMADDL X10 W28 W22 X0 *) + 0x2eb0808b; (* arm_UMLAL_VEC Q11 Q4 Q16 32 *) + 0x9bb039fe; (* arm_UMADDL X30 W15 W16 X14 *) + 0x4e371f5a; (* arm_AND_VEC Q26 Q26 Q23 128 *) + 0x9bb06d9c; (* arm_UMADDL X28 W12 W16 X27 *) + 0x2eb28115; (* arm_UMLAL_VEC Q21 Q8 Q18 32 *) + 0x8b0a014a; (* arm_ADD X10 X10 X10 *) + 0x2eb88119; (* arm_UMLAL_VEC Q25 Q8 Q24 32 *) + 0x9ba62a74; (* arm_UMADDL X20 W19 W6 X10 *) + 0x2eaa8039; (* arm_UMLAL_VEC Q25 Q1 Q10 32 *) + 0x8b1c039c; (* arm_ADD X28 X28 X28 *) + 0x2eb28079; (* arm_UMLAL_VEC Q25 Q3 Q18 32 *) + 0x9ba7727c; (* arm_UMADDL X28 W19 W7 X28 *) + 0x6f671695; (* arm_USRA_VEC Q21 Q20 25 64 128 *) + 0x9ba753a0; (* arm_UMADDL X0 W29 W7 X20 *) + 0x2eae80cb; (* arm_UMLAL_VEC Q11 Q6 Q14 32 *) + 0x9bba796a; (* arm_UMADDL X10 W11 W26 X30 *) + 0x2eaa812d; (* arm_UMLAL_VEC Q13 Q9 Q10 32 *) + 0x9ba573b3; (* arm_UMADDL X19 W29 W5 X28 *) + 0x6f6616bb; (* arm_USRA_VEC Q27 Q21 26 64 128 *) + 0x9ba50060; (* arm_UMADDL X0 W3 W5 X0 *) + 0x2eb080b9; (* arm_UMLAL_VEC Q25 Q5 Q16 32 *) + 0x9bb64434; (* arm_UMADDL X20 W1 W22 X17 *) + 0x4e3e1f94; (* arm_AND_VEC Q20 Q28 Q30 128 *) + 0x9bb74c7d; (* arm_UMADDL X29 W3 W23 X19 *) + 0x6f67177d; (* arm_USRA_VEC Q29 Q27 25 64 128 *) + 0x9bb70023; (* arm_UMADDL X3 W1 W23 X0 *) + 0x4e371f7b; (* arm_AND_VEC Q27 Q27 Q23 128 *) + 0x2eac810b; (* arm_UMLAL_VEC Q11 Q8 Q12 32 *) + 0x9bad75ec; (* arm_UMADDL X12 W15 W13 X29 *) + 0x6f6617ad; (* arm_USRA_VEC Q13 Q29 26 64 128 *) + 0x9bad0d67; (* arm_UMADDL X7 W11 W13 X3 *) + 0x4e8728c6; (* arm_TRN1 Q6 Q6 Q7 32 128 *) + 0x9bb05171; (* arm_UMADDL X17 W11 W16 X20 *) + 0x2eae80f9; (* arm_UMLAL_VEC Q25 Q7 Q14 32 *) + 0x92406497; (* arm_AND X23 X4 (rvalue (word 67108863)) *) + 0x4e771db3; (* arm_BIC_VEC Q19 Q13 Q23 128 *) + 0x9ba63173; (* arm_UMADDL X19 W11 W6 X12 *) + 0x4e371dbc; (* arm_AND_VEC Q28 Q13 Q23 128 *) + 0x8b476a23; (* arm_ADD X3 X17 (Shiftedreg X7 LSR 26) *) + 0x6f67166b; (* arm_USRA_VEC Q11 Q19 25 64 128 *) + 0x4e832842; (* arm_TRN1 Q2 Q2 Q3 32 128 *) + 0x8b436671; (* arm_ADD X17 X19 (Shiftedreg X3 LSR 25) *) + 0x4e3e1ead; (* arm_AND_VEC Q13 Q21 Q30 128 *) + 0x924064e5; (* arm_AND X5 X7 (rvalue (word 67108863)) *) + 0x6f68166b; (* arm_USRA_VEC Q11 Q19 24 64 128 *) + 0x8b516947; (* arm_ADD X7 X10 (Shiftedreg X17 LSR 26) *) + 0x4e812800; (* arm_TRN1 Q0 Q0 Q1 32 128 *) + 0x92406713; (* arm_AND X19 X24 (rvalue (word 67108863)) *) + 0x4e3e1fb5; (* arm_AND_VEC Q21 Q29 Q30 128 *) + 0x8b47667d; (* arm_ADD X29 X19 (Shiftedreg X7 LSR 25) *) + 0x6f6b166b; (* arm_USRA_VEC Q11 Q19 21 64 128 *) + 0xb3606065; (* arm_BFM X5 X3 32 24 *) + 0x4e9b29b1; (* arm_TRN1 Q17 Q13 Q27 32 128 *) + 0x8b5d6853; (* arm_ADD X19 X2 (Shiftedreg X29 LSR 26) *) + 0x4e9c2ab3; (* arm_TRN1 Q19 Q21 Q28 32 128 *) + 0x924067a3; (* arm_AND X3 X29 (rvalue (word 67108863)) *) + 0x6e0844d0; (* arm_INS Q16 Q6 0 64 64 128 *) + 0x6e084626; (* arm_INS Q6 Q17 0 64 64 128 *) + 0x4e892908; (* arm_TRN1 Q8 Q8 Q9 32 128 *) + 0xb3606663; (* arm_BFM X3 X19 32 25 *) + 0x4e3e1d75; (* arm_AND_VEC Q21 Q11 Q30 128 *) + 0xb36066b7; (* arm_BFM X23 X21 32 25 *) + 0x6e084512; (* arm_INS Q18 Q8 0 64 64 128 *) + 0x6e084668; (* arm_INS Q8 Q19 0 64 64 128 *) + 0x2eac8139; (* arm_UMLAL_VEC Q25 Q9 Q12 32 *) + 0x4e081ee9; (* arm_INS_GEN Q9 X23 0 64 *) + 0x4e081f27; (* arm_INS_GEN Q7 X25 0 64 *) + 0xfd4027fd; (* arm_LDR D29 SP (Immediate_Offset (word 72)) *) + 0x6e08444c; (* arm_INS Q12 Q2 0 64 64 128 *) + 0x4e852884; (* arm_TRN1 Q4 Q4 Q5 32 128 *) + 0x92406631; (* arm_AND X17 X17 (rvalue (word 67108863)) *) + 0x6f661579; (* arm_USRA_VEC Q25 Q11 26 64 128 *) + 0x6e08440a; (* arm_INS Q10 Q0 0 64 64 128 *) + 0x6e08448e; (* arm_INS Q14 Q4 0 64 64 128 *) + 0x6e0845e4; (* arm_INS Q4 Q15 0 64 64 128 *) + 0x6f671734; (* arm_USRA_VEC Q20 Q25 25 64 128 *) + 0x4e371f3b; (* arm_AND_VEC Q27 Q25 Q23 128 *) + 0xb36060f1; (* arm_BFM X17 X7 32 24 *) + 0x4e081c65; (* arm_INS_GEN Q5 X3 0 64 *) + 0x4e081ca1; (* arm_INS_GEN Q1 X5 0 64 *) + 0x6f66169a; (* arm_USRA_VEC Q26 Q20 26 64 128 *) + 0x4e3e1e9c; (* arm_AND_VEC Q28 Q20 Q30 128 *) + 0x4e9b2aab; (* arm_TRN1 Q11 Q21 Q27 32 128 *) + 0x4e9a2b8d; (* arm_TRN1 Q13 Q28 Q26 32 128 *) + 0x6e084560; (* arm_INS Q0 Q11 0 64 64 128 *) + 0x4e081e23; (* arm_INS_GEN Q3 X17 0 64 *) + 0x6e0845a2; (* arm_INS Q2 Q13 0 64 64 128 *) + 0xfd402bfc; (* arm_LDR D28 SP (Immediate_Offset (word 80)) *) + 0xf94067e0; (* arm_LDR X0 SP (Immediate_Offset (word 200)) *) + 0xf1000400; (* arm_SUBS X0 X0 (rvalue (word 1)) *) + 0xf90067e0; (* arm_STR X0 SP (Immediate_Offset (word 200)) *) + 0x54ff8062; (* arm_BCS (word 2093068) *) + 0x0e043c00; (* arm_UMOV W0 Q0 0 4 *) + 0x0e0c3c01; (* arm_UMOV W1 Q0 1 4 *) + 0x0e043c42; (* arm_UMOV W2 Q2 0 4 *) + 0x0e0c3c43; (* arm_UMOV W3 Q2 1 4 *) + 0x0e043c84; (* arm_UMOV W4 Q4 0 4 *) + 0x0e0c3c85; (* arm_UMOV W5 Q4 1 4 *) + 0x0e043cc6; (* arm_UMOV W6 Q6 0 4 *) + 0x0e0c3cc7; (* arm_UMOV W7 Q6 1 4 *) + 0x0e043d08; (* arm_UMOV W8 Q8 0 4 *) + 0x0e0c3d09; (* arm_UMOV W9 Q8 1 4 *) + 0x8b016800; (* arm_ADD X0 X0 (Shiftedreg X1 LSL 26) *) + 0x8b036841; (* arm_ADD X1 X2 (Shiftedreg X3 LSL 26) *) + 0x8b056882; (* arm_ADD X2 X4 (Shiftedreg X5 LSL 26) *) + 0x8b0768c3; (* arm_ADD X3 X6 (Shiftedreg X7 LSL 26) *) + 0x8b096904; (* arm_ADD X4 X8 (Shiftedreg X9 LSL 26) *) + 0xab01cc00; (* arm_ADDS X0 X0 (Shiftedreg X1 LSL 51) *) + 0xd34dfc26; (* arm_LSR X6 X1 13 *) + 0xd35a6447; (* arm_LSL X7 X2 38 *) + 0xba0700c1; (* arm_ADCS X1 X6 X7 *) + 0xd35afc48; (* arm_LSR X8 X2 26 *) + 0xd3679869; (* arm_LSL X9 X3 25 *) + 0xba090102; (* arm_ADCS X2 X8 X9 *) + 0xd367fc6a; (* arm_LSR X10 X3 39 *) + 0xd374cc8b; (* arm_LSL X11 X4 12 *) + 0x9a0b0143; (* arm_ADC X3 X10 X11 *) + 0xa90807e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&128))) *) + 0xa9090fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&144))) *) + 0x0e043c20; (* arm_UMOV W0 Q1 0 4 *) + 0x0e0c3c21; (* arm_UMOV W1 Q1 1 4 *) + 0x0e043c62; (* arm_UMOV W2 Q3 0 4 *) + 0x0e0c3c63; (* arm_UMOV W3 Q3 1 4 *) + 0x0e043ca4; (* arm_UMOV W4 Q5 0 4 *) + 0x0e0c3ca5; (* arm_UMOV W5 Q5 1 4 *) + 0x0e043ce6; (* arm_UMOV W6 Q7 0 4 *) + 0x0e0c3ce7; (* arm_UMOV W7 Q7 1 4 *) + 0x0e043d28; (* arm_UMOV W8 Q9 0 4 *) + 0x0e0c3d29; (* arm_UMOV W9 Q9 1 4 *) + 0x5280026a; (* arm_MOV W10 (rvalue (word 19)) *) + 0x8b016800; (* arm_ADD X0 X0 (Shiftedreg X1 LSL 26) *) + 0xf267013f; (* arm_TST X9 (rvalue (word 33554432)) *) + 0x8b036841; (* arm_ADD X1 X2 (Shiftedreg X3 LSL 26) *) + 0x9a9f114a; (* arm_CSEL X10 X10 XZR Condition_NE *) + 0x8b056882; (* arm_ADD X2 X4 (Shiftedreg X5 LSL 26) *) + 0x92406129; (* arm_AND X9 X9 (rvalue (word 33554431)) *) + 0x8b0768c3; (* arm_ADD X3 X6 (Shiftedreg X7 LSL 26) *) + 0x8b0a0000; (* arm_ADD X0 X0 X10 *) + 0x8b096904; (* arm_ADD X4 X8 (Shiftedreg X9 LSL 26) *) + 0xab01cc00; (* arm_ADDS X0 X0 (Shiftedreg X1 LSL 51) *) + 0xd34dfc26; (* arm_LSR X6 X1 13 *) + 0xd35a6447; (* arm_LSL X7 X2 38 *) + 0xba0700c1; (* arm_ADCS X1 X6 X7 *) + 0xd35afc48; (* arm_LSR X8 X2 26 *) + 0xd3679869; (* arm_LSL X9 X3 25 *) + 0xba090102; (* arm_ADCS X2 X8 X9 *) + 0xd367fc6a; (* arm_LSR X10 X3 39 *) + 0xd374cc8b; (* arm_LSL X11 X4 12 *) + 0x9a0b0143; (* arm_ADC X3 X10 X11 *) + 0xa90a07e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&160))) *) + 0xa90b0fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&176))) *) + 0x910283e0; (* arm_ADD X0 SP (rvalue (word 160)) *) + 0x910283e1; (* arm_ADD X1 SP (rvalue (word 160)) *) + 0xaa0003f4; (* arm_MOV X20 X0 *) + 0x9280024a; (* arm_MOVN X10 (word 18) 0 *) + 0x9280000b; (* arm_MOVN X11 (word 0) 0 *) + 0xa9002fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&0))) *) + 0x92f0000c; (* arm_MOVN X12 (word 32768) 48 *) + 0xa90133eb; (* arm_STP X11 X12 SP (Immediate_Offset (iword (&16))) *) + 0xa9400c22; (* arm_LDP X2 X3 X1 (Immediate_Offset (iword (&0))) *) + 0xa9411424; (* arm_LDP X4 X5 X1 (Immediate_Offset (iword (&16))) *) + 0xd2800267; (* arm_MOV X7 (rvalue (word 19)) *) + 0xd37ffca6; (* arm_LSR X6 X5 63 *) + 0x9b061ce6; (* arm_MADD X6 X7 X6 X7 *) + 0xab060042; (* arm_ADDS X2 X2 X6 *) + 0xba1f0063; (* arm_ADCS X3 X3 XZR *) 0xba1f0084; (* arm_ADCS X4 X4 XZR *) + 0xb24100a5; (* arm_ORR X5 X5 (rvalue (word 9223372036854775808)) *) 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90413e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&64))) *) - 0xa9051be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&80))) *) - 0xa94613e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&96))) *) - 0xa9481be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&128))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94713e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&112))) *) - 0xa9491be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&144))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94713e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&112))) *) - 0xa94643ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&96))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94803ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&128))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90c23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa90d2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0xd346fe80; (* arm_LSR X0 X20 6 *) - 0xf8607be2; (* arm_LDR X2 SP (Shiftreg_Offset X0 3) *) - 0x9ad42442; (* arm_LSRV X2 X2 X20 *) - 0x92400042; (* arm_AND X2 X2 (rvalue (word 1)) *) - 0xeb0202bf; (* arm_CMP X21 X2 *) - 0xaa0203f5; (* arm_MOV X21 X2 *) - 0xa94807e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&128))) *) - 0xa94a0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&160))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91007e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&256))) *) - 0xa94907e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&144))) *) - 0xa94b0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&176))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91107e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&272))) *) - 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0xa9460fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&96))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91207e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&288))) *) - 0xa94507e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&80))) *) - 0xa9470fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&112))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91307e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&304))) *) - 0xa94413e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&64))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94513e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&80))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94513e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&80))) *) - 0xa94443ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&64))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90e23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&224))) *) - 0xa90f2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&240))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa94c1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa94e0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&224))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa94d23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xa94f0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&240))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9041be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&64))) *) - 0xa90523e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&80))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94e23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&224))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa94d1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&208))) *) - 0xa94f23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&240))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90e13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&224))) *) - 0xa90f1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&240))) *) - 0xa9442fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&64))) *) - 0xa94537ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&80))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9040fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&64))) *) - 0xa90517e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&80))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xa94e2fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&224))) *) - 0xa94f37ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&240))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa90e0fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&224))) *) - 0xa90f17e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&240))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94413e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&64))) *) - 0xa9421be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&32))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94513e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&80))) *) - 0xa9431be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&48))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94513e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&80))) *) - 0xa94443ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&64))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94203ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&32))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90423e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&64))) *) - 0xa9052be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&80))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xd1000694; (* arm_SUB X20 X20 (rvalue (word 1)) *) - 0xf1000e9f; (* arm_CMP X20 (rvalue (word 3)) *) - 0x54ff3dc2; (* arm_BCS (word 2090936) *) - 0xeb1f02bf; (* arm_CMP X21 XZR *) - 0xa94e07e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&224))) *) - 0xa9520fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91207e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&288))) *) - 0xa94f07e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&240))) *) - 0xa9530fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&304))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91307e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&304))) *) - 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0xa94a0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&160))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa90a07e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&160))) *) - 0xa94507e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&80))) *) - 0xa94b0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&176))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa90b07e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&176))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa94a0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&160))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa94b0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&176))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9101be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0xa91123e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94a23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa9531be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa94b23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa91213e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9131be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa94a0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&160))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa94b0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&176))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9101be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0xa91123e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94a23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa9531be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa94b23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa91213e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9131be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa94a0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&160))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa94b0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&176))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9101be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0xa91123e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94a23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa9531be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa94b23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa91213e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9131be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba014a5; (* arm_UMADDL X5 W5 W0 X5 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) - 0xf241015f; (* arm_TST X10 (rvalue (word 9223372036854775808)) *) - 0x9a9f5063; (* arm_CSEL X3 X3 XZR Condition_PL *) - 0xeb0300e7; (* arm_SUBS X7 X7 X3 *) - 0xfa1f0108; (* arm_SBCS X8 X8 XZR *) - 0xfa1f0129; (* arm_SBCS X9 X9 XZR *) - 0xda1f014a; (* arm_SBC X10 X10 XZR *) - 0x9240f94a; (* arm_AND X10 X10 (rvalue (word 9223372036854775807)) *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0x910383e0; (* arm_ADD X0 SP (rvalue (word 224)) *) - 0x910283e1; (* arm_ADD X1 SP (rvalue (word 160)) *) - 0xaa0003f4; (* arm_MOV X20 X0 *) - 0x9280024a; (* arm_MOVN X10 (word 18) 0 *) - 0x9280000b; (* arm_MOVN X11 (word 0) 0 *) - 0xa9002fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&0))) *) - 0x92f0000c; (* arm_MOVN X12 (word 32768) 48 *) - 0xa90133eb; (* arm_STP X11 X12 SP (Immediate_Offset (iword (&16))) *) - 0xa9400c22; (* arm_LDP X2 X3 X1 (Immediate_Offset (iword (&0))) *) - 0xa9411424; (* arm_LDP X4 X5 X1 (Immediate_Offset (iword (&16))) *) - 0xd2800267; (* arm_MOV X7 (rvalue (word 19)) *) - 0xd37ffca6; (* arm_LSR X6 X5 63 *) - 0x9b061ce6; (* arm_MADD X6 X7 X6 X7 *) - 0xab060042; (* arm_ADDS X2 X2 X6 *) - 0xba1f0063; (* arm_ADCS X3 X3 XZR *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xb24100a5; (* arm_ORR X5 X5 (rvalue (word 9223372036854775808)) *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a9f30e6; (* arm_CSEL X6 X7 XZR Condition_CC *) - 0xeb060042; (* arm_SUBS X2 X2 X6 *) - 0xfa1f0063; (* arm_SBCS X3 X3 XZR *) - 0xfa1f0084; (* arm_SBCS X4 X4 XZR *) - 0xda1f00a5; (* arm_SBC X5 X5 XZR *) - 0x9240f8a5; (* arm_AND X5 X5 (rvalue (word 9223372036854775807)) *) - 0xa9020fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&32))) *) - 0xa90317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&48))) *) - 0xa9047fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&64))) *) - 0xa9057fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&80))) *) - 0xd284132a; (* arm_MOV X10 (rvalue (word 8345)) *) - 0xf2aea04a; (* arm_MOVK X10 (word 29954) 16 *) - 0xf2d3c46a; (* arm_MOVK X10 (word 40483) 32 *) - 0xf2f41f2a; (* arm_MOVK X10 (word 41209) 48 *) - 0xd284b2ab; (* arm_MOV X11 (rvalue (word 9621)) *) - 0xf2a3a26b; (* arm_MOVK X11 (word 7443) 16 *) - 0xf2d1e7eb; (* arm_MOVK X11 (word 36671) 32 *) - 0xf2f518cb; (* arm_MOVK X11 (word 43206) 48 *) - 0xd28a484c; (* arm_MOV X12 (rvalue (word 21058)) *) - 0xf2a0b58c; (* arm_MOVK X12 (word 1452) 16 *) - 0xf2d1270c; (* arm_MOVK X12 (word 35128) 32 *) - 0xf2ed8d8c; (* arm_MOVK X12 (word 27756) 48 *) - 0xd280c2ad; (* arm_MOV X13 (rvalue (word 1557)) *) - 0xf2a82eed; (* arm_MOVK X13 (word 16759) 16 *) - 0xf2c1164d; (* arm_MOVK X13 (word 2226) 32 *) - 0xf2e4ecad; (* arm_MOVK X13 (word 10085) 48 *) - 0xa9062fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&96))) *) - 0xa90737ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&112))) *) - 0xd2800155; (* arm_MOV X21 (rvalue (word 10)) *) - 0xd2800036; (* arm_MOV X22 (rvalue (word 1)) *) - 0x1400010b; (* arm_B (word 1068) *) - 0xeb1f015f; (* arm_CMP X10 XZR *) - 0xda9f53ee; (* arm_CSETM X14 Condition_MI *) - 0xda8a554a; (* arm_CNEG X10 X10 Condition_MI *) - 0xeb1f017f; (* arm_CMP X11 XZR *) - 0xda9f53ef; (* arm_CSETM X15 Condition_MI *) - 0xda8b556b; (* arm_CNEG X11 X11 Condition_MI *) - 0xeb1f019f; (* arm_CMP X12 XZR *) - 0xda9f53f0; (* arm_CSETM X16 Condition_MI *) - 0xda8c558c; (* arm_CNEG X12 X12 Condition_MI *) - 0xeb1f01bf; (* arm_CMP X13 XZR *) - 0xda9f53f1; (* arm_CSETM X17 Condition_MI *) - 0xda8d55ad; (* arm_CNEG X13 X13 Condition_MI *) - 0x8a0e0140; (* arm_AND X0 X10 X14 *) - 0x8a0f0161; (* arm_AND X1 X11 X15 *) - 0x8b010009; (* arm_ADD X9 X0 X1 *) - 0x8a100180; (* arm_AND X0 X12 X16 *) - 0x8a1101a1; (* arm_AND X1 X13 X17 *) - 0x8b010013; (* arm_ADD X19 X0 X1 *) - 0xf94003e7; (* arm_LDR X7 SP (Immediate_Offset (word 0)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000124; (* arm_ADDS X4 X9 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xf94013e8; (* arm_LDR X8 SP (Immediate_Offset (word 32)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000265; (* arm_ADDS X5 X19 X0 *) - 0x9a0103e3; (* arm_ADC X3 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf94007e7; (* arm_LDR X7 SP (Immediate_Offset (word 8)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0103e6; (* arm_ADC X6 XZR X1 *) - 0xf94017e8; (* arm_LDR X8 SP (Immediate_Offset (word 40)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100c6; (* arm_ADC X6 X6 X1 *) - 0x93c4ec44; (* arm_EXTR X4 X2 X4 59 *) - 0xf90003e4; (* arm_STR X4 SP (Immediate_Offset (word 0)) *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000063; (* arm_ADDS X3 X3 X0 *) - 0x9a0103e4; (* arm_ADC X4 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000063; (* arm_ADDS X3 X3 X0 *) - 0x9a010084; (* arm_ADC X4 X4 X1 *) - 0x93c5ec65; (* arm_EXTR X5 X3 X5 59 *) - 0xf90013e5; (* arm_STR X5 SP (Immediate_Offset (word 32)) *) - 0xf9400be7; (* arm_LDR X7 SP (Immediate_Offset (word 16)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0x9a0103e5; (* arm_ADC X5 XZR X1 *) - 0xf9401be8; (* arm_LDR X8 SP (Immediate_Offset (word 48)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0x93c2ecc2; (* arm_EXTR X2 X6 X2 59 *) - 0xf90007e2; (* arm_STR X2 SP (Immediate_Offset (word 8)) *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0x93c3ec83; (* arm_EXTR X3 X4 X3 59 *) - 0xf90017e3; (* arm_STR X3 SP (Immediate_Offset (word 40)) *) - 0xf9400fe7; (* arm_LDR X7 SP (Immediate_Offset (word 24)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x937ffc23; (* arm_ASR X3 X1 63 *) - 0x8a0a0063; (* arm_AND X3 X3 X10 *) - 0xcb0303e3; (* arm_NEG X3 X3 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf9401fe8; (* arm_LDR X8 SP (Immediate_Offset (word 56)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x937ffc20; (* arm_ASR X0 X1 63 *) - 0x8a0b0000; (* arm_AND X0 X0 X11 *) - 0xcb000063; (* arm_SUB X3 X3 X0 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0x93c6eca6; (* arm_EXTR X6 X5 X6 59 *) - 0xf9000be6; (* arm_STR X6 SP (Immediate_Offset (word 16)) *) - 0x93c5ec65; (* arm_EXTR X5 X3 X5 59 *) - 0xf9000fe5; (* arm_STR X5 SP (Immediate_Offset (word 24)) *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x937ffc25; (* arm_ASR X5 X1 63 *) - 0x8a0c00a5; (* arm_AND X5 X5 X12 *) - 0xcb0503e5; (* arm_NEG X5 X5 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x937ffc20; (* arm_ASR X0 X1 63 *) - 0x8a0d0000; (* arm_AND X0 X0 X13 *) - 0xcb0000a5; (* arm_SUB X5 X5 X0 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0x93c4ec44; (* arm_EXTR X4 X2 X4 59 *) - 0xf9001be4; (* arm_STR X4 SP (Immediate_Offset (word 48)) *) - 0x93c2eca2; (* arm_EXTR X2 X5 X2 59 *) - 0xf9001fe2; (* arm_STR X2 SP (Immediate_Offset (word 56)) *) - 0xf94023e7; (* arm_LDR X7 SP (Immediate_Offset (word 64)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000124; (* arm_ADDS X4 X9 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xf94033e8; (* arm_LDR X8 SP (Immediate_Offset (word 96)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0xf90023e4; (* arm_STR X4 SP (Immediate_Offset (word 64)) *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000265; (* arm_ADDS X5 X19 X0 *) - 0x9a0103e3; (* arm_ADC X3 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0xf90033e5; (* arm_STR X5 SP (Immediate_Offset (word 96)) *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf94027e7; (* arm_LDR X7 SP (Immediate_Offset (word 72)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0103e6; (* arm_ADC X6 XZR X1 *) - 0xf94037e8; (* arm_LDR X8 SP (Immediate_Offset (word 104)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0xf90027e2; (* arm_STR X2 SP (Immediate_Offset (word 72)) *) - 0x9a0100c6; (* arm_ADC X6 X6 X1 *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000063; (* arm_ADDS X3 X3 X0 *) - 0x9a0103e4; (* arm_ADC X4 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000063; (* arm_ADDS X3 X3 X0 *) - 0xf90037e3; (* arm_STR X3 SP (Immediate_Offset (word 104)) *) - 0x9a010084; (* arm_ADC X4 X4 X1 *) - 0xf9402be7; (* arm_LDR X7 SP (Immediate_Offset (word 80)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0x9a0103e5; (* arm_ADC X5 XZR X1 *) - 0xf9403be8; (* arm_LDR X8 SP (Immediate_Offset (word 112)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0xf9002be6; (* arm_STR X6 SP (Immediate_Offset (word 80)) *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0xf9003be4; (* arm_STR X4 SP (Immediate_Offset (word 112)) *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0xf9402fe7; (* arm_LDR X7 SP (Immediate_Offset (word 88)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x8a0a01c3; (* arm_AND X3 X14 X10 *) - 0xcb0303e3; (* arm_NEG X3 X3 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf9403fe8; (* arm_LDR X8 SP (Immediate_Offset (word 120)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x8a0b01e0; (* arm_AND X0 X15 X11 *) - 0xcb000063; (* arm_SUB X3 X3 X0 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0x93c5fc66; (* arm_EXTR X6 X3 X5 63 *) - 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0x8b83fcc6; (* arm_ADD X6 X6 (Shiftedreg X3 ASR 63) *) - 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) - 0x9b037cc4; (* arm_MUL X4 X6 X3 *) - 0x8b06fca5; (* arm_ADD X5 X5 (Shiftedreg X6 LSL 63) *) - 0x9b437cc3; (* arm_SMULH X3 X6 X3 *) - 0xf9402be6; (* arm_LDR X6 SP (Immediate_Offset (word 80)) *) - 0xab040000; (* arm_ADDS X0 X0 X4 *) - 0xba030021; (* arm_ADCS X1 X1 X3 *) - 0x937ffc63; (* arm_ASR X3 X3 63 *) - 0xba0300c6; (* arm_ADCS X6 X6 X3 *) - 0x9a0300a5; (* arm_ADC X5 X5 X3 *) - 0xa90407e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0xa90517e6; (* arm_STP X6 X5 SP (Immediate_Offset (iword (&80))) *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x8a0c0205; (* arm_AND X5 X16 X12 *) - 0xcb0503e5; (* arm_NEG X5 X5 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x8a0d0220; (* arm_AND X0 X17 X13 *) - 0xcb0000a5; (* arm_SUB X5 X5 X0 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0x93c2fca6; (* arm_EXTR X6 X5 X2 63 *) - 0xa94607e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&96))) *) - 0x8b85fcc6; (* arm_ADD X6 X6 (Shiftedreg X5 ASR 63) *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9b057cc4; (* arm_MUL X4 X6 X5 *) - 0x8b06fc42; (* arm_ADD X2 X2 (Shiftedreg X6 LSL 63) *) - 0x9b457cc5; (* arm_SMULH X5 X6 X5 *) - 0xf9403be3; (* arm_LDR X3 SP (Immediate_Offset (word 112)) *) - 0xab040000; (* arm_ADDS X0 X0 X4 *) - 0xba050021; (* arm_ADCS X1 X1 X5 *) - 0x937ffca5; (* arm_ASR X5 X5 63 *) - 0xba050063; (* arm_ADCS X3 X3 X5 *) - 0x9a050042; (* arm_ADC X2 X2 X5 *) - 0xa90607e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&96))) *) - 0xa9070be3; (* arm_STP X3 X2 SP (Immediate_Offset (iword (&112))) *) - 0xaa1603e1; (* arm_MOV X1 X22 *) - 0xf94003e2; (* arm_LDR X2 SP (Immediate_Offset (word 0)) *) - 0xf94013e3; (* arm_LDR X3 SP (Immediate_Offset (word 32)) *) - 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) - 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) - 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) - 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) - 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x91440088; (* arm_ADD X8 X4 (rvalue (word 1048576)) *) - 0x9355a508; (* arm_SBFM X8 X8 21 41 *) - 0xd2a0020b; (* arm_MOVZ X11 (word 16) 16 *) - 0x8b0b556b; (* arm_ADD X11 X11 (Shiftedreg X11 LSL 21) *) - 0x8b0b0089; (* arm_ADD X9 X4 X11 *) - 0x936afd29; (* arm_ASR X9 X9 42 *) - 0x914400aa; (* arm_ADD X10 X5 (rvalue (word 1048576)) *) - 0x9355a54a; (* arm_SBFM X10 X10 21 41 *) - 0x8b0b00ab; (* arm_ADD X11 X5 X11 *) - 0x936afd6b; (* arm_ASR X11 X11 42 *) - 0x9b027d06; (* arm_MUL X6 X8 X2 *) - 0x9b037d27; (* arm_MUL X7 X9 X3 *) - 0x9b027d42; (* arm_MUL X2 X10 X2 *) - 0x9b037d63; (* arm_MUL X3 X11 X3 *) - 0x8b0700c4; (* arm_ADD X4 X6 X7 *) - 0x8b030045; (* arm_ADD X5 X2 X3 *) - 0x9354fc82; (* arm_ASR X2 X4 20 *) - 0x9354fca3; (* arm_ASR X3 X5 20 *) - 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) - 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) - 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) - 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) - 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9144008c; (* arm_ADD X12 X4 (rvalue (word 1048576)) *) - 0x9355a58c; (* arm_SBFM X12 X12 21 41 *) - 0xd2a0020f; (* arm_MOVZ X15 (word 16) 16 *) - 0x8b0f55ef; (* arm_ADD X15 X15 (Shiftedreg X15 LSL 21) *) - 0x8b0f008d; (* arm_ADD X13 X4 X15 *) - 0x936afdad; (* arm_ASR X13 X13 42 *) - 0x914400ae; (* arm_ADD X14 X5 (rvalue (word 1048576)) *) - 0x9355a5ce; (* arm_SBFM X14 X14 21 41 *) - 0x8b0f00af; (* arm_ADD X15 X5 X15 *) - 0x936afdef; (* arm_ASR X15 X15 42 *) - 0x9b027d86; (* arm_MUL X6 X12 X2 *) - 0x9b037da7; (* arm_MUL X7 X13 X3 *) - 0x9b027dc2; (* arm_MUL X2 X14 X2 *) - 0x9b037de3; (* arm_MUL X3 X15 X3 *) - 0x8b0700c4; (* arm_ADD X4 X6 X7 *) - 0x8b030045; (* arm_ADD X5 X2 X3 *) - 0x9354fc82; (* arm_ASR X2 X4 20 *) - 0x9354fca3; (* arm_ASR X3 X5 20 *) - 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) - 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) - 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) - 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) - 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9b087d82; (* arm_MUL X2 X12 X8 *) - 0x9b097d83; (* arm_MUL X3 X12 X9 *) - 0x9b087dc6; (* arm_MUL X6 X14 X8 *) - 0x9b097dc7; (* arm_MUL X7 X14 X9 *) - 0x9b0a09a8; (* arm_MADD X8 X13 X10 X2 *) - 0x9b0b0da9; (* arm_MADD X9 X13 X11 X3 *) - 0x9b0a19f0; (* arm_MADD X16 X15 X10 X6 *) - 0x9b0b1df1; (* arm_MADD X17 X15 X11 X7 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9144008c; (* arm_ADD X12 X4 (rvalue (word 1048576)) *) - 0x9356a98c; (* arm_SBFM X12 X12 22 42 *) - 0xd2a0020f; (* arm_MOVZ X15 (word 16) 16 *) - 0x8b0f55ef; (* arm_ADD X15 X15 (Shiftedreg X15 LSL 21) *) - 0x8b0f008d; (* arm_ADD X13 X4 X15 *) - 0x936bfdad; (* arm_ASR X13 X13 43 *) - 0x914400ae; (* arm_ADD X14 X5 (rvalue (word 1048576)) *) - 0x9356a9ce; (* arm_SBFM X14 X14 22 42 *) - 0x8b0f00af; (* arm_ADD X15 X5 X15 *) - 0x936bfdef; (* arm_ASR X15 X15 43 *) - 0x9b08fd82; (* arm_MNEG X2 X12 X8 *) - 0x9b09fd83; (* arm_MNEG X3 X12 X9 *) - 0x9b08fdc4; (* arm_MNEG X4 X14 X8 *) - 0x9b09fdc5; (* arm_MNEG X5 X14 X9 *) - 0x9b1089aa; (* arm_MSUB X10 X13 X16 X2 *) - 0x9b118dab; (* arm_MSUB X11 X13 X17 X3 *) - 0x9b1091ec; (* arm_MSUB X12 X15 X16 X4 *) - 0x9b1195ed; (* arm_MSUB X13 X15 X17 X5 *) - 0xaa0103f6; (* arm_MOV X22 X1 *) - 0xf10006b5; (* arm_SUBS X21 X21 (rvalue (word 1)) *) - 0x54ff9281; (* arm_BNE (word 2093648) *) - 0xf94003e0; (* arm_LDR X0 SP (Immediate_Offset (word 0)) *) - 0xf94013e1; (* arm_LDR X1 SP (Immediate_Offset (word 32)) *) - 0x9b0a7c00; (* arm_MUL X0 X0 X10 *) - 0x9b0b0021; (* arm_MADD X1 X1 X11 X0 *) - 0x937ffc20; (* arm_ASR X0 X1 63 *) - 0xeb1f015f; (* arm_CMP X10 XZR *) - 0xda9f53ee; (* arm_CSETM X14 Condition_MI *) - 0xda8a554a; (* arm_CNEG X10 X10 Condition_MI *) - 0xca0001ce; (* arm_EOR X14 X14 X0 *) - 0xeb1f017f; (* arm_CMP X11 XZR *) - 0xda9f53ef; (* arm_CSETM X15 Condition_MI *) - 0xda8b556b; (* arm_CNEG X11 X11 Condition_MI *) - 0xca0001ef; (* arm_EOR X15 X15 X0 *) - 0xeb1f019f; (* arm_CMP X12 XZR *) - 0xda9f53f0; (* arm_CSETM X16 Condition_MI *) - 0xda8c558c; (* arm_CNEG X12 X12 Condition_MI *) - 0xca000210; (* arm_EOR X16 X16 X0 *) - 0xeb1f01bf; (* arm_CMP X13 XZR *) - 0xda9f53f1; (* arm_CSETM X17 Condition_MI *) - 0xda8d55ad; (* arm_CNEG X13 X13 Condition_MI *) - 0xca000231; (* arm_EOR X17 X17 X0 *) - 0x8a0e0140; (* arm_AND X0 X10 X14 *) - 0x8a0f0161; (* arm_AND X1 X11 X15 *) - 0x8b010009; (* arm_ADD X9 X0 X1 *) - 0xf94023e7; (* arm_LDR X7 SP (Immediate_Offset (word 64)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000124; (* arm_ADDS X4 X9 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xf94033e8; (* arm_LDR X8 SP (Immediate_Offset (word 96)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0xf90023e4; (* arm_STR X4 SP (Immediate_Offset (word 64)) *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0xf94027e7; (* arm_LDR X7 SP (Immediate_Offset (word 72)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0103e6; (* arm_ADC X6 XZR X1 *) - 0xf94037e8; (* arm_LDR X8 SP (Immediate_Offset (word 104)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0xf90027e2; (* arm_STR X2 SP (Immediate_Offset (word 72)) *) - 0x9a0100c6; (* arm_ADC X6 X6 X1 *) - 0xf9402be7; (* arm_LDR X7 SP (Immediate_Offset (word 80)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0x9a0103e5; (* arm_ADC X5 XZR X1 *) - 0xf9403be8; (* arm_LDR X8 SP (Immediate_Offset (word 112)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0xf9002be6; (* arm_STR X6 SP (Immediate_Offset (word 80)) *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0xf9402fe7; (* arm_LDR X7 SP (Immediate_Offset (word 88)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x8a0a01c3; (* arm_AND X3 X14 X10 *) - 0xcb0303e3; (* arm_NEG X3 X3 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf9403fe8; (* arm_LDR X8 SP (Immediate_Offset (word 120)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x8a0b01e0; (* arm_AND X0 X15 X11 *) - 0xcb000063; (* arm_SUB X3 X3 X0 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0x93c5fc66; (* arm_EXTR X6 X3 X5 63 *) - 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0xea03007f; (* arm_TST X3 X3 *) - 0x9a8644c6; (* arm_CINC X6 X6 Condition_PL *) - 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) - 0x9b037cc4; (* arm_MUL X4 X6 X3 *) - 0x8b06fca5; (* arm_ADD X5 X5 (Shiftedreg X6 LSL 63) *) - 0x9b437cc6; (* arm_SMULH X6 X6 X3 *) - 0xf9402be2; (* arm_LDR X2 SP (Immediate_Offset (word 80)) *) - 0xab040000; (* arm_ADDS X0 X0 X4 *) - 0xba060021; (* arm_ADCS X1 X1 X6 *) - 0x937ffcc6; (* arm_ASR X6 X6 63 *) - 0xba060042; (* arm_ADCS X2 X2 X6 *) - 0xba0600a5; (* arm_ADCS X5 X5 X6 *) - 0x9a9f4063; (* arm_CSEL X3 X3 XZR Condition_MI *) - 0xeb030000; (* arm_SUBS X0 X0 X3 *) - 0xfa1f0021; (* arm_SBCS X1 X1 XZR *) - 0xfa1f0042; (* arm_SBCS X2 X2 XZR *) - 0xda1f00a5; (* arm_SBC X5 X5 XZR *) - 0x9240f8a5; (* arm_AND X5 X5 (rvalue (word 9223372036854775807)) *) - 0xaa1403e4; (* arm_MOV X4 X20 *) - 0xa9000480; (* arm_STP X0 X1 X4 (Immediate_Offset (iword (&0))) *) - 0xa9011482; (* arm_STP X2 X5 X4 (Immediate_Offset (iword (&16))) *) - 0xa94a07e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&160))) *) - 0xa94b0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&176))) *) - 0xaa010000; (* arm_ORR X0 X0 X1 *) - 0xaa030042; (* arm_ORR X2 X2 X3 *) - 0xaa020004; (* arm_ORR X4 X0 X2 *) - 0xeb1f009f; (* arm_CMP X4 XZR *) - 0xa95207e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&288))) *) - 0x9a9f1000; (* arm_CSEL X0 X0 XZR Condition_NE *) - 0x9a9f1021; (* arm_CSEL X1 X1 XZR Condition_NE *) - 0xa9530fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&304))) *) - 0xa91207e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&288))) *) - 0x9a9f1042; (* arm_CSEL X2 X2 XZR Condition_NE *) - 0x9a9f1063; (* arm_CSEL X3 X3 XZR Condition_NE *) - 0xa9130fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&304))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94e1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&224))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa94f1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&240))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94e03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&224))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba014a5; (* arm_UMADDL X5 W5 W0 X5 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) - 0xf241015f; (* arm_TST X10 (rvalue (word 9223372036854775808)) *) - 0x9a9f5063; (* arm_CSEL X3 X3 XZR Condition_PL *) - 0xeb0300e7; (* arm_SUBS X7 X7 X3 *) - 0xfa1f0108; (* arm_SBCS X8 X8 XZR *) - 0xfa1f0129; (* arm_SBCS X9 X9 XZR *) - 0xda1f014a; (* arm_SBC X10 X10 XZR *) - 0x9240f94a; (* arm_AND X10 X10 (rvalue (word 9223372036854775807)) *) - 0xa90022e7; (* arm_STP X7 X8 X23 (Immediate_Offset (iword (&0))) *) - 0xa9012ae9; (* arm_STP X9 X10 X23 (Immediate_Offset (iword (&16))) *) - 0x910503ff; (* arm_ADD SP SP (rvalue (word 320)) *) - 0xa8c163f7; (* arm_LDP X23 X24 SP (Postimmediate_Offset (iword (&16))) *) - 0xa8c15bf5; (* arm_LDP X21 X22 SP (Postimmediate_Offset (iword (&16))) *) - 0xa8c153f3; (* arm_LDP X19 X20 SP (Postimmediate_Offset (iword (&16))) *) - 0xd65f03c0 (* arm_RET X30 *) -];; - -let CURVE25519_X25519_EXEC = ARM_MK_EXEC_RULE curve25519_x25519_mc;; - -(* ------------------------------------------------------------------------- *) -(* Abbreviations used to state the specification. *) -(* ------------------------------------------------------------------------- *) - -let p_25519 = define `p_25519 = 57896044618658097711785492504343953926634992332820282019728792003956564819949`;; - -let curve25519x = define - `curve25519x (f:A ring) = (f,ring_of_num f A_25519,ring_of_num f 1)`;; - -let curve25519x_halfcanonically_represents = new_definition - `curve25519x_halfcanonically_represents (f:A ring) P (X,Z) <=> - X < 2 * p_25519 /\ Z < 2 * p_25519 /\ - montgomery_xz f P (ring_of_num f X,ring_of_num f Z)`;; - -(* ------------------------------------------------------------------------- *) -(* Common lemmas and tactics for the component proofs. *) -(* ------------------------------------------------------------------------- *) - -let lemma0 = prove - (`!x0 x1:int64. - &(val(if val x0 <= val x1 then word_sub x1 x0 - else word_neg(word_sub x1 x0))):real = abs(&(val x1) - &(val x0))`, - REPEAT GEN_TAC THEN REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[WORD_NEG_SUB; REAL_ARITH - `abs(x - y):real = if y <= x then x - y else y - x`] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - RULE_ASSUM_TAC(REWRITE_RULE[REAL_OF_NUM_CLAUSES; NOT_LE]) THEN - ASM_SIMP_TAC[VAL_WORD_SUB_CASES; LT_IMP_LE; REAL_OF_NUM_SUB]);; - -let lemma1 = prove - (`!(x0:num) x1 (y0:num) y1. - (if y0 <= y1 - then if x1 <= x0 then word 0 else word 18446744073709551615 - else word_not - (if x1 <= x0 then word 0 else word 18446744073709551615)):int64 = - word_neg(word(bitval(y0 <= y1 <=> x0 < x1)))`, - REPEAT GEN_TAC THEN REWRITE_TAC[GSYM NOT_LE] THEN - REPEAT(COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES]) THEN - CONV_TAC WORD_REDUCE_CONV);; - -let lemma2 = prove - (`!p x0 x1 y0 y1:real. - (x0 + p * x1) * (y0 + p * y1) = - x0 * y0 + p pow 2 * x1 * y1 + - p * (x0 * y0 + x1 * y1 + - --(&1) pow bitval(y1 <= y0 <=> x1 < x0) * - abs(x1 - x0) * abs(y0 - y1))`, - REPEAT GEN_TAC THEN - MAP_EVERY ASM_CASES_TAC [`y1:real <= y0`; `x1:real < x0`] THEN - ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN ASM_REAL_ARITH_TAC);; - -let VAL_WORD_MADDL_0 = prove - (`!x y. val(word(0 + val(x:int32) * val(y:int32)):int64) = val x * val y`, - REPEAT GEN_TAC THEN REWRITE_TAC[ADD_CLAUSES; VAL_WORD_EQ_EQ] THEN - REWRITE_TAC[DIMINDEX_64; ARITH_RULE `2 EXP 64 = 2 EXP 32 * 2 EXP 32`] THEN - MATCH_MP_TAC LT_MULT2 THEN REWRITE_TAC[GSYM DIMINDEX_32; VAL_BOUND]);; - -let DIVMOD_32_32 = prove - (`!n. (2 EXP 32 * n) MOD 2 EXP 64 = 2 EXP 32 * n MOD 2 EXP 32`, - REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - -let DIVMOD_33_31 = prove - (`!n. (2 EXP 33 * n) MOD 2 EXP 64 = 2 EXP 33 * n MOD 2 EXP 31`, - REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - -let DIVMOD_63_64 = prove - (`!n. (2 EXP 63 * n) MOD 2 EXP 64 = 2 EXP 63 * n MOD 2`, - REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - -let VAL_WORD_SPLIT32 = prove - (`!x. 2 EXP 32 * val(word_zx(word_ushr x 32):int32) + val(word_zx x:int32) = - val(x:int64)`, - REWRITE_TAC[VAL_WORD_USHR; VAL_WORD_ZX_GEN; DIMINDEX_32] THEN - GEN_TAC THEN REWRITE_TAC[GSYM MOD_MULT_MOD; GSYM EXP_ADD] THEN - CONV_TAC(ONCE_DEPTH_CONV NUM_ADD_CONV) THEN - MATCH_MP_TAC MOD_LT THEN REWRITE_TAC[VAL_BOUND_64]);; - -let p25519redlemma32 = prove - (`!h l. h < 2 EXP 256 /\ l < 2 EXP 256 - ==> let q = (38 * h DIV 2 EXP 224 + l DIV 2 EXP 224) DIV 2 EXP 31 in - q <= 77 /\ - q < 2 EXP 64 /\ - (q + 1) * p_25519 <= (38 * h + l) + p_25519 /\ - 38 * h + l < (q + 1) * p_25519 + p_25519`, - CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN - REWRITE_TAC[p_25519] THEN ARITH_TAC);; - -let endp25519redlemma = prove - (`(&z == &2 pow 255 + x) (mod (&2 pow 256)) /\ - --(&p_25519) <= x /\ x < &p_25519 /\ z < 2 EXP 256 - ==> x rem &p_25519 = - if z < 2 EXP 255 then &z - &19 else &z - &2 pow 255`, - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN REPEAT STRIP_TAC THEN - SUBGOAL_THEN `&z:int < &2 pow 255 <=> x:int < &0` SUBST1_TAC THENL - [ALL_TAC; - COND_CASES_TAC THEN MATCH_MP_TAC INT_REM_UNIQ THENL - [EXISTS_TAC `--(&1):int`; EXISTS_TAC `&0:int`]] THEN - FIRST_X_ASSUM(MP_TAC o MATCH_MP - (REWRITE_RULE[IMP_CONJ_ALT] INT_CONG_IMP_EQ)) THEN - REWRITE_TAC[p_25519] THEN - RULE_ASSUM_TAC(REWRITE_RULE[p_25519]) THEN ASM_INT_ARITH_TAC);; - -let KARATSUBA12_TAC = - REWRITE_TAC[REAL_MUL_RZERO; REAL_ADD_RID] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN - ASM_REWRITE_TAC[INTEGER_CLOSED] THEN - REPLICATE_TAC 2 (CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC]) THEN - REWRITE_TAC[lemma2; REAL_OF_NUM_LE; REAL_OF_NUM_LT] THEN - ACCUMULATOR_POP_ASSUM_LIST(fun thl -> - MP_TAC(end_itlist CONJ(rev thl)) THEN - REWRITE_TAC[WORD_XOR_MASK] THEN - REWRITE_TAC[REAL_OF_NUM_LT; REAL_OF_NUM_LE; GSYM NOT_LE] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - REWRITE_TAC[REAL_VAL_WORD_NOT; DIMINDEX_64] THEN - DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN - CONV_TAC(RAND_CONV REAL_POLY_CONV) THEN - REWRITE_TAC(filter(is_ratconst o rand o concl) (DECARRY_RULE thl)) THEN - REAL_INTEGER_TAC);; - -let p25519weakredlemma = prove - (`!n. n <= 2 EXP 62 * 2 EXP 256 - ==> let q = n DIV 2 EXP 255 in - q < 2 EXP 64 /\ - q * p_25519 <= n /\ - n < q * p_25519 + 2 * p_25519`, - CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN REWRITE_TAC[p_25519] THEN ARITH_TAC);; - -let lvs = - ["resx",[`X23`;`0`]; - "x",[`SP`;`32`]; - "zm",[`SP`;`64`]; - "sm",[`SP`;`64`]; - "dpro",[`SP`;`64`]; - "sn",[`SP`;`96`]; - "dm",[`SP`;`128`]; - "zn",[`SP`;`160`]; - "dn",[`SP`;`160`]; - "e",[`SP`;`160`]; - "dmsn",[`SP`;`192`]; - "p",[`SP`;`192`]; - "xm",[`SP`;`224`]; - "dnsm",[`SP`;`224`]; - "spro",[`SP`;`224`]; - "d",[`SP`;`256`]; - "xn",[`SP`;`288`]; - "s",[`SP`;`288`]];; - -(* ------------------------------------------------------------------------- *) -(* Instances of mul_p25519. *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_MUL_P25519_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_mc 180 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x571c) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s = - (m * n) MOD p_25519) - (MAYCHANGE [PC; X0; X1; X2; X3; X4; X5; X6; X7; X8; X9; X10; X11; X12; - X13; X14; X15; X16] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "y_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "x_" o lhand o concl) THEN - - (*** Retrofitted insertion for the 32-bit fiddling (1 of 2) ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC [9;11;12;14] (1--14) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; VAL_WORD_USHR; VAL_WORD_SHL; - DIVMOD_32_32; DIMINDEX_64]) THEN - SUBGOAL_THEN - `&2 pow 64 * &(val(sum_s14:int64)) + &(val(sum_s12:int64)):real = - &(val(x_0:int64)) * &(val(y_0:int64))` - MP_TAC THENL - [MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`128`; `&0:real`] THEN - REPLICATE_TAC 2 (CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC]) THEN - REWRITE_TAC[INTEGER_CLOSED] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`x_0:int64`; `y_0:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN DISCH_TAC THEN - POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - SPEC_TAC(`sum_s12:int64`,`mullo_s3:int64`) THEN - SPEC_TAC(`sum_s14:int64`,`mulhi_s3:int64`) THEN - SPEC_TAC(`s14:armstate`,`s4:armstate`) THEN REPEAT STRIP_TAC] THEN - - (*** First nested block multiplying the lower halves ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [5;10;11;15;17;18;19;22;24;25] (5--25) THEN - RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN - - MAP_EVERY ABBREV_TAC - [`q0 = bignum_of_wordlist[mullo_s3;sum_s22]`; - `q1 = bignum_of_wordlist[sum_s24;sum_s25]`] THEN - SUBGOAL_THEN - `2 EXP 128 * q1 + q0 = - bignum_of_wordlist [x_0;x_1] * bignum_of_wordlist[y_0;y_1]` - ASSUME_TAC THENL - [MAP_EVERY EXPAND_TAC ["q0"; "q1"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - KARATSUBA12_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN - DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN - - (*** Retrofitted insertion for the 32-bit fiddling (2 of 2) ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC [34;36;37;39] (26--39) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; VAL_WORD_USHR; VAL_WORD_SHL; - DIVMOD_32_32; DIMINDEX_64]) THEN - SUBGOAL_THEN - `&2 pow 64 * &(val(sum_s39:int64)) + &(val(sum_s37:int64)):real = - &(val(x_2:int64)) * &(val(y_2:int64))` - MP_TAC THENL - [MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`128`; `&0:real`] THEN - REPLICATE_TAC 2 (CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC]) THEN - REWRITE_TAC[INTEGER_CLOSED] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`x_2:int64`; `y_2:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN DISCH_TAC THEN - POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - SPEC_TAC(`sum_s37:int64`,`mullo_s28:int64`) THEN - SPEC_TAC(`sum_s39:int64`,`mulhi_s28:int64`) THEN - SPEC_TAC(`s39:armstate`,`s29:armstate`) THEN REPEAT STRIP_TAC] THEN - - (*** Second nested block multiplying the upper halves ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [30;35;36;40;42;43;44;47;49;50] (30--50) THEN - RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN - - ABBREV_TAC - `q23 = bignum_of_wordlist[mullo_s28;sum_s47; sum_s49;sum_s50]` THEN - SUBGOAL_THEN - `q23 = bignum_of_wordlist [x_2;x_3] * bignum_of_wordlist[y_2;y_3]` - ASSUME_TAC THENL - [EXPAND_TAC "q23" THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - KARATSUBA12_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN - DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN + 0x9a9f30e6; (* arm_CSEL X6 X7 XZR Condition_CC *) + 0xeb060042; (* arm_SUBS X2 X2 X6 *) + 0xfa1f0063; (* arm_SBCS X3 X3 XZR *) + 0xfa1f0084; (* arm_SBCS X4 X4 XZR *) + 0xda1f00a5; (* arm_SBC X5 X5 XZR *) + 0x9240f8a5; (* arm_AND X5 X5 (rvalue (word 9223372036854775807)) *) + 0xa9020fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&32))) *) + 0xa90317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&48))) *) + 0xa9047fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&64))) *) + 0xa9057fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&80))) *) + 0xd284132a; (* arm_MOV X10 (rvalue (word 8345)) *) + 0xf2aea04a; (* arm_MOVK X10 (word 29954) 16 *) + 0xf2d3c46a; (* arm_MOVK X10 (word 40483) 32 *) + 0xf2f41f2a; (* arm_MOVK X10 (word 41209) 48 *) + 0xd284b2ab; (* arm_MOV X11 (rvalue (word 9621)) *) + 0xf2a3a26b; (* arm_MOVK X11 (word 7443) 16 *) + 0xf2d1e7eb; (* arm_MOVK X11 (word 36671) 32 *) + 0xf2f518cb; (* arm_MOVK X11 (word 43206) 48 *) + 0xd28a484c; (* arm_MOV X12 (rvalue (word 21058)) *) + 0xf2a0b58c; (* arm_MOVK X12 (word 1452) 16 *) + 0xf2d1270c; (* arm_MOVK X12 (word 35128) 32 *) + 0xf2ed8d8c; (* arm_MOVK X12 (word 27756) 48 *) + 0xd280c2ad; (* arm_MOV X13 (rvalue (word 1557)) *) + 0xf2a82eed; (* arm_MOVK X13 (word 16759) 16 *) + 0xf2c1164d; (* arm_MOVK X13 (word 2226) 32 *) + 0xf2e4ecad; (* arm_MOVK X13 (word 10085) 48 *) + 0xa9062fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&96))) *) + 0xa90737ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&112))) *) + 0xd2800155; (* arm_MOV X21 (rvalue (word 10)) *) + 0xd2800036; (* arm_MOV X22 (rvalue (word 1)) *) + 0x1400010b; (* arm_B (word 1068) *) + 0xeb1f015f; (* arm_CMP X10 XZR *) + 0xda9f53ee; (* arm_CSETM X14 Condition_MI *) + 0xda8a554a; (* arm_CNEG X10 X10 Condition_MI *) + 0xeb1f017f; (* arm_CMP X11 XZR *) + 0xda9f53ef; (* arm_CSETM X15 Condition_MI *) + 0xda8b556b; (* arm_CNEG X11 X11 Condition_MI *) + 0xeb1f019f; (* arm_CMP X12 XZR *) + 0xda9f53f0; (* arm_CSETM X16 Condition_MI *) + 0xda8c558c; (* arm_CNEG X12 X12 Condition_MI *) + 0xeb1f01bf; (* arm_CMP X13 XZR *) + 0xda9f53f1; (* arm_CSETM X17 Condition_MI *) + 0xda8d55ad; (* arm_CNEG X13 X13 Condition_MI *) + 0x8a0e0140; (* arm_AND X0 X10 X14 *) + 0x8a0f0161; (* arm_AND X1 X11 X15 *) + 0x8b010009; (* arm_ADD X9 X0 X1 *) + 0x8a100180; (* arm_AND X0 X12 X16 *) + 0x8a1101a1; (* arm_AND X1 X13 X17 *) + 0x8b010013; (* arm_ADD X19 X0 X1 *) + 0xf94003e7; (* arm_LDR X7 SP (Immediate_Offset (word 0)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000124; (* arm_ADDS X4 X9 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xf94013e8; (* arm_LDR X8 SP (Immediate_Offset (word 32)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000265; (* arm_ADDS X5 X19 X0 *) + 0x9a0103e3; (* arm_ADC X3 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf94007e7; (* arm_LDR X7 SP (Immediate_Offset (word 8)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0103e6; (* arm_ADC X6 XZR X1 *) + 0xf94017e8; (* arm_LDR X8 SP (Immediate_Offset (word 40)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100c6; (* arm_ADC X6 X6 X1 *) + 0x93c4ec44; (* arm_EXTR X4 X2 X4 59 *) + 0xf90003e4; (* arm_STR X4 SP (Immediate_Offset (word 0)) *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000063; (* arm_ADDS X3 X3 X0 *) + 0x9a0103e4; (* arm_ADC X4 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000063; (* arm_ADDS X3 X3 X0 *) + 0x9a010084; (* arm_ADC X4 X4 X1 *) + 0x93c5ec65; (* arm_EXTR X5 X3 X5 59 *) + 0xf90013e5; (* arm_STR X5 SP (Immediate_Offset (word 32)) *) + 0xf9400be7; (* arm_LDR X7 SP (Immediate_Offset (word 16)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0x9a0103e5; (* arm_ADC X5 XZR X1 *) + 0xf9401be8; (* arm_LDR X8 SP (Immediate_Offset (word 48)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0x93c2ecc2; (* arm_EXTR X2 X6 X2 59 *) + 0xf90007e2; (* arm_STR X2 SP (Immediate_Offset (word 8)) *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0x93c3ec83; (* arm_EXTR X3 X4 X3 59 *) + 0xf90017e3; (* arm_STR X3 SP (Immediate_Offset (word 40)) *) + 0xf9400fe7; (* arm_LDR X7 SP (Immediate_Offset (word 24)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x937ffc23; (* arm_ASR X3 X1 63 *) + 0x8a0a0063; (* arm_AND X3 X3 X10 *) + 0xcb0303e3; (* arm_NEG X3 X3 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf9401fe8; (* arm_LDR X8 SP (Immediate_Offset (word 56)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x937ffc20; (* arm_ASR X0 X1 63 *) + 0x8a0b0000; (* arm_AND X0 X0 X11 *) + 0xcb000063; (* arm_SUB X3 X3 X0 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0x93c6eca6; (* arm_EXTR X6 X5 X6 59 *) + 0xf9000be6; (* arm_STR X6 SP (Immediate_Offset (word 16)) *) + 0x93c5ec65; (* arm_EXTR X5 X3 X5 59 *) + 0xf9000fe5; (* arm_STR X5 SP (Immediate_Offset (word 24)) *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x937ffc25; (* arm_ASR X5 X1 63 *) + 0x8a0c00a5; (* arm_AND X5 X5 X12 *) + 0xcb0503e5; (* arm_NEG X5 X5 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x937ffc20; (* arm_ASR X0 X1 63 *) + 0x8a0d0000; (* arm_AND X0 X0 X13 *) + 0xcb0000a5; (* arm_SUB X5 X5 X0 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0x93c4ec44; (* arm_EXTR X4 X2 X4 59 *) + 0xf9001be4; (* arm_STR X4 SP (Immediate_Offset (word 48)) *) + 0x93c2eca2; (* arm_EXTR X2 X5 X2 59 *) + 0xf9001fe2; (* arm_STR X2 SP (Immediate_Offset (word 56)) *) + 0xf94023e7; (* arm_LDR X7 SP (Immediate_Offset (word 64)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000124; (* arm_ADDS X4 X9 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xf94033e8; (* arm_LDR X8 SP (Immediate_Offset (word 96)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0xf90023e4; (* arm_STR X4 SP (Immediate_Offset (word 64)) *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000265; (* arm_ADDS X5 X19 X0 *) + 0x9a0103e3; (* arm_ADC X3 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0xf90033e5; (* arm_STR X5 SP (Immediate_Offset (word 96)) *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf94027e7; (* arm_LDR X7 SP (Immediate_Offset (word 72)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0103e6; (* arm_ADC X6 XZR X1 *) + 0xf94037e8; (* arm_LDR X8 SP (Immediate_Offset (word 104)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0xf90027e2; (* arm_STR X2 SP (Immediate_Offset (word 72)) *) + 0x9a0100c6; (* arm_ADC X6 X6 X1 *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000063; (* arm_ADDS X3 X3 X0 *) + 0x9a0103e4; (* arm_ADC X4 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000063; (* arm_ADDS X3 X3 X0 *) + 0xf90037e3; (* arm_STR X3 SP (Immediate_Offset (word 104)) *) + 0x9a010084; (* arm_ADC X4 X4 X1 *) + 0xf9402be7; (* arm_LDR X7 SP (Immediate_Offset (word 80)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0x9a0103e5; (* arm_ADC X5 XZR X1 *) + 0xf9403be8; (* arm_LDR X8 SP (Immediate_Offset (word 112)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0xf9002be6; (* arm_STR X6 SP (Immediate_Offset (word 80)) *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0xf9003be4; (* arm_STR X4 SP (Immediate_Offset (word 112)) *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0xf9402fe7; (* arm_LDR X7 SP (Immediate_Offset (word 88)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x8a0a01c3; (* arm_AND X3 X14 X10 *) + 0xcb0303e3; (* arm_NEG X3 X3 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf9403fe8; (* arm_LDR X8 SP (Immediate_Offset (word 120)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x8a0b01e0; (* arm_AND X0 X15 X11 *) + 0xcb000063; (* arm_SUB X3 X3 X0 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0x93c5fc66; (* arm_EXTR X6 X3 X5 63 *) + 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) + 0x8b83fcc6; (* arm_ADD X6 X6 (Shiftedreg X3 ASR 63) *) + 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) + 0x9b037cc4; (* arm_MUL X4 X6 X3 *) + 0x8b06fca5; (* arm_ADD X5 X5 (Shiftedreg X6 LSL 63) *) + 0x9b437cc3; (* arm_SMULH X3 X6 X3 *) + 0xf9402be6; (* arm_LDR X6 SP (Immediate_Offset (word 80)) *) + 0xab040000; (* arm_ADDS X0 X0 X4 *) + 0xba030021; (* arm_ADCS X1 X1 X3 *) + 0x937ffc63; (* arm_ASR X3 X3 63 *) + 0xba0300c6; (* arm_ADCS X6 X6 X3 *) + 0x9a0300a5; (* arm_ADC X5 X5 X3 *) + 0xa90407e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&64))) *) + 0xa90517e6; (* arm_STP X6 X5 SP (Immediate_Offset (iword (&80))) *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x8a0c0205; (* arm_AND X5 X16 X12 *) + 0xcb0503e5; (* arm_NEG X5 X5 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x8a0d0220; (* arm_AND X0 X17 X13 *) + 0xcb0000a5; (* arm_SUB X5 X5 X0 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0x93c2fca6; (* arm_EXTR X6 X5 X2 63 *) + 0xa94607e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&96))) *) + 0x8b85fcc6; (* arm_ADD X6 X6 (Shiftedreg X5 ASR 63) *) + 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) + 0x9b057cc4; (* arm_MUL X4 X6 X5 *) + 0x8b06fc42; (* arm_ADD X2 X2 (Shiftedreg X6 LSL 63) *) + 0x9b457cc5; (* arm_SMULH X5 X6 X5 *) + 0xf9403be3; (* arm_LDR X3 SP (Immediate_Offset (word 112)) *) + 0xab040000; (* arm_ADDS X0 X0 X4 *) + 0xba050021; (* arm_ADCS X1 X1 X5 *) + 0x937ffca5; (* arm_ASR X5 X5 63 *) + 0xba050063; (* arm_ADCS X3 X3 X5 *) + 0x9a050042; (* arm_ADC X2 X2 X5 *) + 0xa90607e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&96))) *) + 0xa9070be3; (* arm_STP X3 X2 SP (Immediate_Offset (iword (&112))) *) + 0xaa1603e1; (* arm_MOV X1 X22 *) + 0xf94003e2; (* arm_LDR X2 SP (Immediate_Offset (word 0)) *) + 0xf94013e3; (* arm_LDR X3 SP (Immediate_Offset (word 32)) *) + 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) + 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) + 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) + 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) + 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x91440088; (* arm_ADD X8 X4 (rvalue (word 1048576)) *) + 0x9355a508; (* arm_SBFM X8 X8 21 41 *) + 0xd2a0020b; (* arm_MOVZ X11 (word 16) 16 *) + 0x8b0b556b; (* arm_ADD X11 X11 (Shiftedreg X11 LSL 21) *) + 0x8b0b0089; (* arm_ADD X9 X4 X11 *) + 0x936afd29; (* arm_ASR X9 X9 42 *) + 0x914400aa; (* arm_ADD X10 X5 (rvalue (word 1048576)) *) + 0x9355a54a; (* arm_SBFM X10 X10 21 41 *) + 0x8b0b00ab; (* arm_ADD X11 X5 X11 *) + 0x936afd6b; (* arm_ASR X11 X11 42 *) + 0x9b027d06; (* arm_MUL X6 X8 X2 *) + 0x9b037d27; (* arm_MUL X7 X9 X3 *) + 0x9b027d42; (* arm_MUL X2 X10 X2 *) + 0x9b037d63; (* arm_MUL X3 X11 X3 *) + 0x8b0700c4; (* arm_ADD X4 X6 X7 *) + 0x8b030045; (* arm_ADD X5 X2 X3 *) + 0x9354fc82; (* arm_ASR X2 X4 20 *) + 0x9354fca3; (* arm_ASR X3 X5 20 *) + 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) + 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) + 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) + 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) + 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9144008c; (* arm_ADD X12 X4 (rvalue (word 1048576)) *) + 0x9355a58c; (* arm_SBFM X12 X12 21 41 *) + 0xd2a0020f; (* arm_MOVZ X15 (word 16) 16 *) + 0x8b0f55ef; (* arm_ADD X15 X15 (Shiftedreg X15 LSL 21) *) + 0x8b0f008d; (* arm_ADD X13 X4 X15 *) + 0x936afdad; (* arm_ASR X13 X13 42 *) + 0x914400ae; (* arm_ADD X14 X5 (rvalue (word 1048576)) *) + 0x9355a5ce; (* arm_SBFM X14 X14 21 41 *) + 0x8b0f00af; (* arm_ADD X15 X5 X15 *) + 0x936afdef; (* arm_ASR X15 X15 42 *) + 0x9b027d86; (* arm_MUL X6 X12 X2 *) + 0x9b037da7; (* arm_MUL X7 X13 X3 *) + 0x9b027dc2; (* arm_MUL X2 X14 X2 *) + 0x9b037de3; (* arm_MUL X3 X15 X3 *) + 0x8b0700c4; (* arm_ADD X4 X6 X7 *) + 0x8b030045; (* arm_ADD X5 X2 X3 *) + 0x9354fc82; (* arm_ASR X2 X4 20 *) + 0x9354fca3; (* arm_ASR X3 X5 20 *) + 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) + 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) + 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) + 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) + 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9b087d82; (* arm_MUL X2 X12 X8 *) + 0x9b097d83; (* arm_MUL X3 X12 X9 *) + 0x9b087dc6; (* arm_MUL X6 X14 X8 *) + 0x9b097dc7; (* arm_MUL X7 X14 X9 *) + 0x9b0a09a8; (* arm_MADD X8 X13 X10 X2 *) + 0x9b0b0da9; (* arm_MADD X9 X13 X11 X3 *) + 0x9b0a19f0; (* arm_MADD X16 X15 X10 X6 *) + 0x9b0b1df1; (* arm_MADD X17 X15 X11 X7 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9144008c; (* arm_ADD X12 X4 (rvalue (word 1048576)) *) + 0x9356a98c; (* arm_SBFM X12 X12 22 42 *) + 0xd2a0020f; (* arm_MOVZ X15 (word 16) 16 *) + 0x8b0f55ef; (* arm_ADD X15 X15 (Shiftedreg X15 LSL 21) *) + 0x8b0f008d; (* arm_ADD X13 X4 X15 *) + 0x936bfdad; (* arm_ASR X13 X13 43 *) + 0x914400ae; (* arm_ADD X14 X5 (rvalue (word 1048576)) *) + 0x9356a9ce; (* arm_SBFM X14 X14 22 42 *) + 0x8b0f00af; (* arm_ADD X15 X5 X15 *) + 0x936bfdef; (* arm_ASR X15 X15 43 *) + 0x9b08fd82; (* arm_MNEG X2 X12 X8 *) + 0x9b09fd83; (* arm_MNEG X3 X12 X9 *) + 0x9b08fdc4; (* arm_MNEG X4 X14 X8 *) + 0x9b09fdc5; (* arm_MNEG X5 X14 X9 *) + 0x9b1089aa; (* arm_MSUB X10 X13 X16 X2 *) + 0x9b118dab; (* arm_MSUB X11 X13 X17 X3 *) + 0x9b1091ec; (* arm_MSUB X12 X15 X16 X4 *) + 0x9b1195ed; (* arm_MSUB X13 X15 X17 X5 *) + 0xaa0103f6; (* arm_MOV X22 X1 *) + 0xf10006b5; (* arm_SUBS X21 X21 (rvalue (word 1)) *) + 0x54ff9281; (* arm_BNE (word 2093648) *) + 0xf94003e0; (* arm_LDR X0 SP (Immediate_Offset (word 0)) *) + 0xf94013e1; (* arm_LDR X1 SP (Immediate_Offset (word 32)) *) + 0x9b0a7c00; (* arm_MUL X0 X0 X10 *) + 0x9b0b0021; (* arm_MADD X1 X1 X11 X0 *) + 0x937ffc20; (* arm_ASR X0 X1 63 *) + 0xeb1f015f; (* arm_CMP X10 XZR *) + 0xda9f53ee; (* arm_CSETM X14 Condition_MI *) + 0xda8a554a; (* arm_CNEG X10 X10 Condition_MI *) + 0xca0001ce; (* arm_EOR X14 X14 X0 *) + 0xeb1f017f; (* arm_CMP X11 XZR *) + 0xda9f53ef; (* arm_CSETM X15 Condition_MI *) + 0xda8b556b; (* arm_CNEG X11 X11 Condition_MI *) + 0xca0001ef; (* arm_EOR X15 X15 X0 *) + 0xeb1f019f; (* arm_CMP X12 XZR *) + 0xda9f53f0; (* arm_CSETM X16 Condition_MI *) + 0xda8c558c; (* arm_CNEG X12 X12 Condition_MI *) + 0xca000210; (* arm_EOR X16 X16 X0 *) + 0xeb1f01bf; (* arm_CMP X13 XZR *) + 0xda9f53f1; (* arm_CSETM X17 Condition_MI *) + 0xda8d55ad; (* arm_CNEG X13 X13 Condition_MI *) + 0xca000231; (* arm_EOR X17 X17 X0 *) + 0x8a0e0140; (* arm_AND X0 X10 X14 *) + 0x8a0f0161; (* arm_AND X1 X11 X15 *) + 0x8b010009; (* arm_ADD X9 X0 X1 *) + 0xf94023e7; (* arm_LDR X7 SP (Immediate_Offset (word 64)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000124; (* arm_ADDS X4 X9 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xf94033e8; (* arm_LDR X8 SP (Immediate_Offset (word 96)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0xf90023e4; (* arm_STR X4 SP (Immediate_Offset (word 64)) *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0xf94027e7; (* arm_LDR X7 SP (Immediate_Offset (word 72)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0103e6; (* arm_ADC X6 XZR X1 *) + 0xf94037e8; (* arm_LDR X8 SP (Immediate_Offset (word 104)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0xf90027e2; (* arm_STR X2 SP (Immediate_Offset (word 72)) *) + 0x9a0100c6; (* arm_ADC X6 X6 X1 *) + 0xf9402be7; (* arm_LDR X7 SP (Immediate_Offset (word 80)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0x9a0103e5; (* arm_ADC X5 XZR X1 *) + 0xf9403be8; (* arm_LDR X8 SP (Immediate_Offset (word 112)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0xf9002be6; (* arm_STR X6 SP (Immediate_Offset (word 80)) *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0xf9402fe7; (* arm_LDR X7 SP (Immediate_Offset (word 88)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x8a0a01c3; (* arm_AND X3 X14 X10 *) + 0xcb0303e3; (* arm_NEG X3 X3 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf9403fe8; (* arm_LDR X8 SP (Immediate_Offset (word 120)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x8a0b01e0; (* arm_AND X0 X15 X11 *) + 0xcb000063; (* arm_SUB X3 X3 X0 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0x93c5fc66; (* arm_EXTR X6 X3 X5 63 *) + 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) + 0xea03007f; (* arm_TST X3 X3 *) + 0x9a8644c6; (* arm_CINC X6 X6 Condition_PL *) + 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) + 0x9b037cc4; (* arm_MUL X4 X6 X3 *) + 0x8b06fca5; (* arm_ADD X5 X5 (Shiftedreg X6 LSL 63) *) + 0x9b437cc6; (* arm_SMULH X6 X6 X3 *) + 0xf9402be2; (* arm_LDR X2 SP (Immediate_Offset (word 80)) *) + 0xab040000; (* arm_ADDS X0 X0 X4 *) + 0xba060021; (* arm_ADCS X1 X1 X6 *) + 0x937ffcc6; (* arm_ASR X6 X6 63 *) + 0xba060042; (* arm_ADCS X2 X2 X6 *) + 0xba0600a5; (* arm_ADCS X5 X5 X6 *) + 0x9a9f4063; (* arm_CSEL X3 X3 XZR Condition_MI *) + 0xeb030000; (* arm_SUBS X0 X0 X3 *) + 0xfa1f0021; (* arm_SBCS X1 X1 XZR *) + 0xfa1f0042; (* arm_SBCS X2 X2 XZR *) + 0xda1f00a5; (* arm_SBC X5 X5 XZR *) + 0x9240f8a5; (* arm_AND X5 X5 (rvalue (word 9223372036854775807)) *) + 0xaa1403e4; (* arm_MOV X4 X20 *) + 0xa9000480; (* arm_STP X0 X1 X4 (Immediate_Offset (iword (&0))) *) + 0xa9011482; (* arm_STP X2 X5 X4 (Immediate_Offset (iword (&16))) *) + 0xf94063f1; (* arm_LDR X17 SP (Immediate_Offset (word 192)) *) + 0xa94813e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&128))) *) + 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) + 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) + 0xd360fc60; (* arm_LSR X0 X3 32 *) + 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) + 0xd360fcb0; (* arm_LSR X16 X5 32 *) + 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) + 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) + 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) + 0xd360fdef; (* arm_LSR X15 X15 32 *) + 0x9a0f0108; (* arm_ADC X8 X8 X15 *) + 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) + 0xd360fe10; (* arm_LSR X16 X16 32 *) + 0x9a100108; (* arm_ADC X8 X8 X16 *) + 0x9b067c89; (* arm_MUL X9 X4 X6 *) + 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) + 0xeb030084; (* arm_SUBS X4 X4 X3 *) + 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) + 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) + 0xab080129; (* arm_ADDS X9 X9 X8 *) + 0x9a1f014a; (* arm_ADC X10 X10 XZR *) + 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) + 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) + 0xda902210; (* arm_CINV X16 X16 Condition_CC *) + 0x9b037c8f; (* arm_MUL X15 X4 X3 *) + 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) + 0xab0900e8; (* arm_ADDS X8 X7 X9 *) + 0xba0a0129; (* arm_ADCS X9 X9 X10 *) + 0x9a1f014a; (* arm_ADC X10 X10 XZR *) + 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) + 0xca1001ef; (* arm_EOR X15 X15 X16 *) + 0xba0801e8; (* arm_ADCS X8 X15 X8 *) + 0xca100063; (* arm_EOR X3 X3 X16 *) + 0xba090069; (* arm_ADCS X9 X3 X9 *) + 0x9a10014a; (* arm_ADC X10 X10 X16 *) + 0xa94913e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&144))) *) + 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) + 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) + 0xd360fc60; (* arm_LSR X0 X3 32 *) + 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) + 0xd360fcb0; (* arm_LSR X16 X5 32 *) + 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) + 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) + 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) + 0xd360fdef; (* arm_LSR X15 X15 32 *) + 0x9a0f018c; (* arm_ADC X12 X12 X15 *) + 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) + 0xd360fe10; (* arm_LSR X16 X16 32 *) + 0x9a10018c; (* arm_ADC X12 X12 X16 *) + 0x9b067c8d; (* arm_MUL X13 X4 X6 *) + 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) + 0xeb030084; (* arm_SUBS X4 X4 X3 *) + 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) + 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) + 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) + 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) + 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) + 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) + 0xda902210; (* arm_CINV X16 X16 Condition_CC *) + 0x9b037c8f; (* arm_MUL X15 X4 X3 *) + 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) + 0xab0d016c; (* arm_ADDS X12 X11 X13 *) + 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) + 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) + 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) + 0xca1001ef; (* arm_EOR X15 X15 X16 *) + 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) + 0xca100063; (* arm_EOR X3 X3 X16 *) + 0xba0d006d; (* arm_ADCS X13 X3 X13 *) + 0x9a1001ce; (* arm_ADC X14 X14 X16 *) + 0xa94913e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&144))) *) + 0xa94843ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&128))) *) + 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) + 0xfa100084; (* arm_SBCS X4 X4 X16 *) + 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) + 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) + 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) + 0xfa060006; (* arm_SBCS X6 X0 X6 *) + 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) + 0xca100063; (* arm_EOR X3 X3 X16 *) + 0xeb100063; (* arm_SUBS X3 X3 X16 *) + 0xca100084; (* arm_EOR X4 X4 X16 *) + 0xda100084; (* arm_SBC X4 X4 X16 *) + 0xca0000a5; (* arm_EOR X5 X5 X0 *) + 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) + 0xca0000c6; (* arm_EOR X6 X6 X0 *) + 0xda0000c6; (* arm_SBC X6 X6 X0 *) + 0xca100010; (* arm_EOR X16 X0 X16 *) + 0xab09016b; (* arm_ADDS X11 X11 X9 *) + 0xba0a018c; (* arm_ADCS X12 X12 X10 *) + 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) + 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) + 0x9b057c62; (* arm_MUL X2 X3 X5 *) + 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) + 0x9b067c8f; (* arm_MUL X15 X4 X6 *) + 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) + 0xeb030084; (* arm_SUBS X4 X4 X3 *) + 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) + 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) + 0xab0001ef; (* arm_ADDS X15 X15 X0 *) + 0x9a1f0021; (* arm_ADC X1 X1 XZR *) + 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) + 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) + 0xda892129; (* arm_CINV X9 X9 Condition_CC *) + 0x9b067c85; (* arm_MUL X5 X4 X6 *) + 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) + 0xab0f0040; (* arm_ADDS X0 X2 X15 *) + 0xba0101ef; (* arm_ADCS X15 X15 X1 *) + 0x9a1f0021; (* arm_ADC X1 X1 XZR *) + 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) + 0xca0900a5; (* arm_EOR X5 X5 X9 *) + 0xba0000a0; (* arm_ADCS X0 X5 X0 *) + 0xca0900c6; (* arm_EOR X6 X6 X9 *) + 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) + 0x9a090021; (* arm_ADC X1 X1 X9 *) + 0xab070169; (* arm_ADDS X9 X11 X7 *) + 0xba08018a; (* arm_ADCS X10 X12 X8 *) + 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) + 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) + 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) + 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) + 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) + 0xca100042; (* arm_EOR X2 X2 X16 *) + 0xba090049; (* arm_ADCS X9 X2 X9 *) + 0xca100000; (* arm_EOR X0 X0 X16 *) + 0xba0a000a; (* arm_ADCS X10 X0 X10 *) + 0xca1001ef; (* arm_EOR X15 X15 X16 *) + 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) + 0xca100021; (* arm_EOR X1 X1 X16 *) + 0xba0c002c; (* arm_ADCS X12 X1 X12 *) + 0xba1001ad; (* arm_ADCS X13 X13 X16 *) + 0x9a1001ce; (* arm_ADC X14 X14 X16 *) + 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) + 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) + 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) + 0xd360fce7; (* arm_LSR X7 X7 32 *) + 0xd360fd6b; (* arm_LSR X11 X11 32 *) + 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) + 0xaa0403e7; (* arm_MOV X7 X4 *) + 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) + 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) + 0xd360fd08; (* arm_LSR X8 X8 32 *) + 0xd360fd8c; (* arm_LSR X12 X12 32 *) + 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) + 0xaa0403e8; (* arm_MOV X8 X4 *) + 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) + 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) + 0xd360fd29; (* arm_LSR X9 X9 32 *) + 0xd360fdad; (* arm_LSR X13 X13 32 *) + 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) + 0xaa0403e9; (* arm_MOV X9 X4 *) + 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) + 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) + 0xd360fd4a; (* arm_LSR X10 X10 32 *) + 0xd360fdce; (* arm_LSR X14 X14 32 *) + 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) + 0xaa0403ea; (* arm_MOV X10 X4 *) + 0xd35ffdc0; (* arm_LSR X0 X14 31 *) + 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) + 0x9ba014a5; (* arm_UMADDL X5 W5 W0 X5 *) + 0x8b0500e7; (* arm_ADD X7 X7 X5 *) + 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) + 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) + 0xba030108; (* arm_ADCS X8 X8 X3 *) + 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) + 0xba030129; (* arm_ADCS X9 X9 X3 *) + 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) + 0xd3410005; (* arm_LSL X5 X0 63 *) + 0xca05014a; (* arm_EOR X10 X10 X5 *) + 0x9a03014a; (* arm_ADC X10 X10 X3 *) + 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) + 0xf241015f; (* arm_TST X10 (rvalue (word 9223372036854775808)) *) + 0x9a9f5063; (* arm_CSEL X3 X3 XZR Condition_PL *) + 0xeb0300e7; (* arm_SUBS X7 X7 X3 *) + 0xfa1f0108; (* arm_SBCS X8 X8 XZR *) + 0xfa1f0129; (* arm_SBCS X9 X9 XZR *) + 0xda1f014a; (* arm_SBC X10 X10 XZR *) + 0x9240f94a; (* arm_AND X10 X10 (rvalue (word 9223372036854775807)) *) + 0xa9002227; (* arm_STP X7 X8 X17 (Immediate_Offset (iword (&0))) *) + 0xa9012a29; (* arm_STP X9 X10 X17 (Immediate_Offset (iword (&16))) *) + 0x6d4e27e8; (* arm_LDP D8 D9 SP (Immediate_Offset (iword (&224))) *) + 0x6d4f2fea; (* arm_LDP D10 D11 SP (Immediate_Offset (iword (&240))) *) + 0x6d5037ec; (* arm_LDP D12 D13 SP (Immediate_Offset (iword (&256))) *) + 0x6d513fee; (* arm_LDP D14 D15 SP (Immediate_Offset (iword (&272))) *) + 0xa95253f3; (* arm_LDP X19 X20 SP (Immediate_Offset (iword (&288))) *) + 0xa9535bf5; (* arm_LDP X21 X22 SP (Immediate_Offset (iword (&304))) *) + 0xa95463f7; (* arm_LDP X23 X24 SP (Immediate_Offset (iword (&320))) *) + 0xa9556bf9; (* arm_LDP X25 X26 SP (Immediate_Offset (iword (&336))) *) + 0xa95673fb; (* arm_LDP X27 X28 SP (Immediate_Offset (iword (&352))) *) + 0xa9577bfd; (* arm_LDP X29 X30 SP (Immediate_Offset (iword (&368))) *) + 0x910603ff; (* arm_ADD SP SP (rvalue (word 384)) *) + 0xd65f03c0 (* arm_RET X30 *) +];; - (*** The sign-magnitude difference computation ***) +let CURVE25519_X25519_EXEC = ARM_MK_EXEC_RULE curve25519_x25519_mc;; - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [53;54; 57;58; 61;63; 65;67] (51--68) THEN - RULE_ASSUM_TAC(REWRITE_RULE[WORD_UNMASK_64]) THEN +(* ------------------------------------------------------------------------- *) +(* Some abbreviations around the base-25.5 representation *) +(* ------------------------------------------------------------------------- *) - MAP_EVERY ABBREV_TAC - [`sgn <=> ~(carry_s58 <=> carry_s54)`; - `xd = bignum_of_wordlist[sum_s61;sum_s63]`; - `yd = bignum_of_wordlist[sum_s65;sum_s67]`] THEN - SUBGOAL_THEN - `(&(bignum_of_wordlist[x_2;x_3]) - - &(bignum_of_wordlist[x_0;x_1])) * - (&(bignum_of_wordlist[y_0;y_1]) - - &(bignum_of_wordlist[y_2;y_3])):real = - --(&1) pow bitval sgn * &xd * &yd` - ASSUME_TAC THENL - [TRANS_TAC EQ_TRANS - `(--(&1) pow bitval carry_s54 * &xd) * - (--(&1) pow bitval carry_s58 * &yd):real` THEN - CONJ_TAC THENL - [ALL_TAC; - EXPAND_TAC "sgn" THEN REWRITE_TAC[BITVAL_NOT; BITVAL_IFF] THEN - POP_ASSUM_LIST(K ALL_TAC) THEN REWRITE_TAC[bitval] THEN - REPEAT(COND_CASES_TAC THEN ASM_REWRITE_TAC[]) THEN - CONV_TAC NUM_REDUCE_CONV THEN REAL_ARITH_TAC] THEN - SUBGOAL_THEN - `(carry_s54 <=> - bignum_of_wordlist[x_2;x_3] < bignum_of_wordlist[x_0;x_1]) /\ - (carry_s58 <=> - bignum_of_wordlist[y_0;y_1] < bignum_of_wordlist[y_2;y_3])` - (CONJUNCTS_THEN SUBST_ALL_TAC) - THENL - [CONJ_TAC THEN MATCH_MP_TAC FLAG_FROM_CARRY_LT THEN EXISTS_TAC `128` THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - REWRITE_TAC[REAL_BITVAL_NOT; REAL_VAL_WORD_MASK; DIMINDEX_64] THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN BOUNDER_TAC[]; - ALL_TAC] THEN - BINOP_TAC THEN REWRITE_TAC[bitval] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[real_pow; REAL_MUL_LID] THEN - REWRITE_TAC[REAL_ARITH `x - y:real = --(&1) pow 1 * z <=> y - x = z`] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`128`; `&0:real`] THEN - (CONJ_TAC THENL - [MATCH_MP_TAC(REAL_ARITH - `y:real <= x /\ (&0 <= x /\ x < e) /\ (&0 <= y /\ y < e) - ==> &0 <= x - y /\ x - y < e`) THEN - ASM_SIMP_TAC[REAL_OF_NUM_CLAUSES; LT_IMP_LE; - ARITH_RULE `~(a:num < b) ==> b <= a`] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - CONJ_TAC THEN BOUNDER_TAC[]; - ALL_TAC] THEN - MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; REWRITE_TAC[INTEGER_CLOSED]]) THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - ASM_REWRITE_TAC[WORD_XOR_MASK] THEN - REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN - DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN +let ubignum_of_list = define + `ubignum_of_list [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9] = + d0 + + 2 EXP 26 * d1 + + 2 EXP 51 * d2 + + 2 EXP 77 * d3 + + 2 EXP 102 * d4 + + 2 EXP 128 * d5 + + 2 EXP 153 * d6 + + 2 EXP 179 * d7 + + 2 EXP 204 * d8 + + 2 EXP 230 * d9`;; + +let ubignum_of_int32list = define + `ubignum_of_int32list (l:int32 list) = ubignum_of_list (MAP val l)`;; + +(*** This is a paired representation using parts of the vector registers ***) + +let ubignum_of_qreglist = define + `ubignum_of_qreglist [q0:(armstate,int128)component;q2;q4;q6;q8] s = + ubignum_of_int32list + [word_subword (read q0 s) (0,32); word_subword (read q0 s) (32,32); + word_subword (read q2 s) (0,32); word_subword (read q2 s) (32,32); + word_subword (read q4 s) (0,32); word_subword (read q4 s) (32,32); + word_subword (read q6 s) (0,32); word_subword (read q6 s) (32,32); + word_subword (read q8 s) (0,32); word_subword (read q8 s) (32,32)]`;; + +(**** This is a pure representation with one GPR per digit ***) + +let ubignum_of_xreglist = define + `ubignum_of_xreglist (l:((armstate,int64)component) list) s = + ubignum_of_list (MAP (\c. val(read c s)) l)`;; + +(**** Similar, but only looking at the W register form, the lowest 32 bits ***) + +let ubignum_of_wreglist = define + `ubignum_of_wreglist (l:((armstate,int64)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (0,32):int32)) l)`;; + +(*** Simular, in the high and low 64-bits of 128-bit registers ***) + +let ubignum_of_hreglist = define + `ubignum_of_hreglist (l:((armstate,int128)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (64,64):int64)) l)`;; + +let ubignum_of_lreglist = define + `ubignum_of_lreglist (l:((armstate,int128)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (0,64):int64)) l)`;; + +(*** Similar again, this time 32-bit chunks, which might be better ***) + +let ubignum_of_h32reglist = define + `ubignum_of_h32reglist (l:((armstate,int128)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (32,32):int32)) l)`;; + +let ubignum_of_l32reglist = define + `ubignum_of_l32reglist (l:((armstate,int128)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (0,32):int32)) l)`;; + +(*** This is how they are sometimes packed in pairs into GPRs ***) + +let ubignum_of_preglist = define + `ubignum_of_preglist [p0:(armstate,int64)component;p2;p4;p6;p8] s = + ubignum_of_int32list + [word_subword (read p0 s) (0,32); word_subword (read p0 s) (32,32); + word_subword (read p2 s) (0,32); word_subword (read p2 s) (32,32); + word_subword (read p4 s) (0,32); word_subword (read p4 s) (32,32); + word_subword (read p6 s) (0,32); word_subword (read p6 s) (32,32); + word_subword (read p8 s) (0,32); word_subword (read p8 s) (32,32)]`;; + +(*** There are two slightly different notions of normalization. + *** The primed one comes up when using the scalar version of + *** multiplication, which does nor repack right-to-left and so + *** can have a larger top digit. Otherwise, the digit bounds + *** are roughly alternating 25 and 26 bits plus a bit extra. + ***) + +let normalized_ubignum_list = define + `normalized_ubignum_list [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9] x <=> + (&(ubignum_of_list [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9]):int == x) + (mod &p_25519) /\ + d0 <= 67108863 /\ d1 <= 34000000 /\ + d2 <= 67108863 /\ d3 <= 34000000 /\ + d4 <= 67108863 /\ d5 <= 34000000 /\ + d6 <= 67108863 /\ d7 <= 34000000 /\ + d8 <= 67108863 /\ d9 <= 34000000`;; + +let normalized_ubignum_int32list = define + `normalized_ubignum_int32list (l:int32 list) x = + normalized_ubignum_list (MAP val l) x`;; + +let normalized_ubignum_preglist = define + `normalized_ubignum_preglist + [p0:(armstate,int64)component;p2;p4;p6;p8] x s = + normalized_ubignum_int32list + [word_subword (read p0 s) (0,32); word_subword (read p0 s) (32,32); + word_subword (read p2 s) (0,32); word_subword (read p2 s) (32,32); + word_subword (read p4 s) (0,32); word_subword (read p4 s) (32,32); + word_subword (read p6 s) (0,32); word_subword (read p6 s) (32,32); + word_subword (read p8 s) (0,32); word_subword (read p8 s) (32,32)] + x`;; + +let normalized_ubignum_qreglist = define + `normalized_ubignum_qreglist + [q0:(armstate,int128)component;q2;q4;q6;q8] x s = + normalized_ubignum_int32list + [word_subword (read q0 s) (0,32); word_subword (read q0 s) (32,32); + word_subword (read q2 s) (0,32); word_subword (read q2 s) (32,32); + word_subword (read q4 s) (0,32); word_subword (read q4 s) (32,32); + word_subword (read q6 s) (0,32); word_subword (read q6 s) (32,32); + word_subword (read q8 s) (0,32); word_subword (read q8 s) (32,32)] + x`;; + +let normalized_ubignum_list' = define + `normalized_ubignum_list' [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9] x <=> + (&(ubignum_of_list [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9]):int == x) + (mod &p_25519) /\ + d0 <= 67108863 /\ d1 <= 34000000 /\ + d2 <= 67108863 /\ d3 <= 34000000 /\ + d4 <= 67108863 /\ d5 <= 34000000 /\ + d6 <= 67108863 /\ d7 <= 34000000 /\ + d8 <= 67108863 /\ d9 <= 67108863`;; + +let normalized_ubignum_int32list' = define + `normalized_ubignum_int32list' (l:int32 list) x = + normalized_ubignum_list' (MAP val l) x`;; + +let normalized_ubignum_preglist' = define + `normalized_ubignum_preglist' + [p0:(armstate,int64)component;p2;p4;p6;p8] x s = + normalized_ubignum_int32list' + [word_subword (read p0 s) (0,32); word_subword (read p0 s) (32,32); + word_subword (read p2 s) (0,32); word_subword (read p2 s) (32,32); + word_subword (read p4 s) (0,32); word_subword (read p4 s) (32,32); + word_subword (read p6 s) (0,32); word_subword (read p6 s) (32,32); + word_subword (read p8 s) (0,32); word_subword (read p8 s) (32,32)] + x`;; + +let normalized_ubignum_qreglist' = define + `normalized_ubignum_qreglist' + [q0:(armstate,int128)component;q2;q4;q6;q8] x s = + normalized_ubignum_int32list' + [word_subword (read q0 s) (0,32); word_subword (read q0 s) (32,32); + word_subword (read q2 s) (0,32); word_subword (read q2 s) (32,32); + word_subword (read q4 s) (0,32); word_subword (read q4 s) (32,32); + word_subword (read q6 s) (0,32); word_subword (read q6 s) (32,32); + word_subword (read q8 s) (0,32); word_subword (read q8 s) (32,32)] + x`;; - (*** Clean up the overall sign ***) +(* ------------------------------------------------------------------------- *) +(* Key state components in inner loop, extracted from code annotations. *) +(* ------------------------------------------------------------------------- *) - FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE RAND_CONV [WORD_XOR_MASKS]) THEN - ASM_REWRITE_TAC[] THEN DISCH_TAC THEN +let named_variables = + [`x = + ubignum_of_list + [val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 32))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 32))) s0) (32,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 40))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 40))) s0) (32,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 48))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 48))) s0) (32,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 56))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 56))) s0) (32,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 64))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 64))) s0) (32,32):int32)]`; + `x2 = + ubignum_of_list + [val(word_subword (read Q0 s0) (0,32):int32); + val(word_subword (read Q0 s0) (32,32):int32); + val(word_subword (read Q2 s0) (0,32):int32); + val(word_subword (read Q2 s0) (32,32):int32); + val(word_subword (read Q4 s0) (0,32):int32); + val(word_subword (read Q4 s0) (32,32):int32); + val(word_subword (read Q6 s0) (0,32):int32); + val(word_subword (read Q6 s0) (32,32):int32); + val(word_subword (read Q8 s0) (0,32):int32); + val(word_subword (read Q8 s0) (32,32):int32)]`; + `x3 = + ubignum_of_list + [val(word_subword (read Q10 s0) (0,32):int32); + val(word_subword (read Q10 s0) (32,32):int32); + val(word_subword (read Q12 s0) (0,32):int32); + val(word_subword (read Q12 s0) (32,32):int32); + val(word_subword (read Q14 s0) (0,32):int32); + val(word_subword (read Q14 s0) (32,32):int32); + val(word_subword (read Q16 s0) (0,32):int32); + val(word_subword (read Q16 s0) (32,32):int32); + val(word_subword (read Q18 s0) (0,32):int32); + val(word_subword (read Q18 s0) (32,32):int32)]`; + `z2 = + ubignum_of_list + [val(word_subword (read Q1 s0) (0,32):int32); + val(word_subword (read Q1 s0) (32,32):int32); + val(word_subword (read Q3 s0) (0,32):int32); + val(word_subword (read Q3 s0) (32,32):int32); + val(word_subword (read Q5 s0) (0,32):int32); + val(word_subword (read Q5 s0) (32,32):int32); + val(word_subword (read Q7 s0) (0,32):int32); + val(word_subword (read Q7 s0) (32,32):int32); + val(word_subword (read Q9 s0) (0,32):int32); + val(word_subword (read Q9 s0) (32,32):int32)]`; + `z3 = + ubignum_of_list + [val(word_subword (read Q11 s0) (0,32):int32); + val(word_subword (read Q11 s0) (32,32):int32); + val(word_subword (read Q13 s0) (0,32):int32); + val(word_subword (read Q13 s0) (32,32):int32); + val(word_subword (read Q15 s0) (0,32):int32); + val(word_subword (read Q15 s0) (32,32):int32); + val(word_subword (read Q17 s0) (0,32):int32); + val(word_subword (read Q17 s0) (32,32):int32); + val(word_subword (read Q19 s0) (0,32):int32); + val(word_subword (read Q19 s0) (32,32):int32)]`; + `a = + ubignum_of_list + [val(word_subword (read Q25 s10) (0,32):int32); + val(word_subword (read Q25 s10) (32,32):int32); + val(word_subword (read Q22 s8) (0,32):int32); + val(word_subword (read Q22 s8) (32,32):int32); + val(word_subword (read Q28 s34) (0,32):int32); + val(word_subword (read Q28 s34) (32,32):int32); + val(word_subword (read Q23 s30) (0,32):int32); + val(word_subword (read Q23 s30) (32,32):int32); + val(word_subword (read Q9 s53) (0,32):int32); + val(word_subword (read Q9 s53) (32,32):int32)]`; + `aa = + ubignum_of_list + [val(word_subword (read X9 s258) (0,32):int32); + val(word_subword (read X9 s258) (32,32):int32); + val(word_subword (read X11 s335) (0,32):int32); + val(word_subword (read X11 s335) (32,32):int32); + val(word_subword (read X14 s282) (0,32):int32); + val(word_subword (read X14 s282) (32,32):int32); + val(word_subword (read X29 s289) (0,32):int32); + val(word_subword (read X29 s289) (32,32):int32); + val(word_subword (read X6 s478) (0,32):int32); + val(word_subword (read X6 s478) (32,32):int32)]`; + `ad = + ubignum_of_list + [val(word_subword (read Q7 s390) (0,64):int64); + val(word_subword (read Q8 s394) (0,64):int64); + val(word_subword (read Q3 s404) (0,64):int64); + val(word_subword (read Q0 s402) (0,64):int64); + val(word_subword (read Q20 s321) (0,64):int64); + val(word_subword (read Q27 s330) (0,64):int64); + val(word_subword (read Q8 s328) (0,64):int64); + val(word_subword (read Q5 s332) (0,64):int64); + val(word_subword (read Q1 s364) (0,64):int64); + val(word_subword (read Q17 s368) (0,64):int64)]`; + `b = + ubignum_of_list + [val(word_subword (read Q0 s13) (0,32):int32); + val(word_subword (read Q0 s13) (32,32):int32); + val(word_subword (read Q18 s22) (0,32):int32); + val(word_subword (read Q18 s22) (32,32):int32); + val(word_subword (read Q1 s57) (0,32):int32); + val(word_subword (read Q1 s57) (32,32):int32); + val(word_subword (read Q13 s46) (0,32):int32); + val(word_subword (read Q13 s46) (32,32):int32); + val(word_subword (read Q7 s36) (0,32):int32); + val(word_subword (read Q7 s36) (32,32):int32)]`; + `bb = + ubignum_of_list + [val(word_subword (read X11 s514) (0,32):int32); + val(word_subword (read X11 s514) (32,32):int32); + val(word_subword (read X5 s538) (0,32):int32); + val(word_subword (read X5 s538) (32,32):int32); + val(word_subword (read X20 s565) (0,32):int32); + val(word_subword (read X20 s565) (32,32):int32); + val(word_subword (read X19 s569) (0,32):int32); + val(word_subword (read X19 s569) (32,32):int32); + val(word_subword (read X29 s549) (0,32):int32); + val(word_subword (read X29 s549) (32,32):int32)]`; + `bbalt = + ubignum_of_list + [val(read X17 s592); val(read X17 s551); val(read X12 s557); + val(read X1 s530); val(read X8 s573); val(read X24 s561); + val(read X2 s581); val(read X28 s577); val(read X0 s586); + val(read X15 s549)]`; + `bc = + ubignum_of_list + [val(word_subword (read Q7 s390) (64,64):int64); + val(word_subword (read Q8 s394) (64,64):int64); + val(word_subword (read Q3 s404) (64,64):int64); + val(word_subword (read Q0 s402) (64,64):int64); + val(word_subword (read Q20 s321) (64,64):int64); + val(word_subword (read Q27 s330) (64,64):int64); + val(word_subword (read Q8 s328) (64,64):int64); + val(word_subword (read Q5 s332) (64,64):int64); + val(word_subword (read Q1 s364) (64,64):int64); + val(word_subword (read Q17 s368) (64,64):int64)]`; + `bce = + ubignum_of_list + [val(read X11 s638); val(read X12 s645); val(read X15 s688); + val(read X21 s676); val(read X30 s707); val(read X2 s720); + val(read X9 s803); val(read X3 s691); val(read X3 s760); + val(read X4 s697)]`; + `c = + ubignum_of_list + [val(word_subword (read Q19 s18) (0,32):int32); + val(word_subword (read Q19 s18) (32,32):int32); + val(word_subword (read Q24 s26) (0,32):int32); + val(word_subword (read Q24 s26) (32,32):int32); + val(word_subword (read Q14 s23) (0,32):int32); + val(word_subword (read Q14 s23) (32,32):int32); + val(word_subword (read Q15 s24) (0,32):int32); + val(word_subword (read Q15 s24) (32,32):int32); + val(word_subword (read Q3 s12) (0,32):int32); + val(word_subword (read Q3 s12) (32,32):int32)]`; + `d = + ubignum_of_list + [val(word_subword (read Q26 s27) (0,32):int32); + val(word_subword (read Q26 s27) (32,32):int32); + val(word_subword (read Q27 s32) (0,32):int32); + val(word_subword (read Q27 s32) (32,32):int32); + val(word_subword (read Q11 s19) (0,32):int32); + val(word_subword (read Q11 s19) (32,32):int32); + val(word_subword (read Q2 s25) (0,32):int32); + val(word_subword (read Q2 s25) (32,32):int32); + val(word_subword (read Q21 s20) (0,32):int32); + val(word_subword (read Q21 s20) (32,32):int32)]`; + `e = + ubignum_of_list + [val(word_subword (read X13 s522) (0,32):int32); + val(word_subword (read X16 s522) (0,32):int32); + val(word_subword (read X6 s559) (0,32):int32); + val(word_subword (read X26 s559) (0,32):int32); + val(word_subword (read X7 s575) (0,32):int32); + val(word_subword (read X14 s575) (0,32):int32); + val(word_subword (read X5 s598) (0,32):int32); + val(word_subword (read X10 s598) (0,32):int32); + val(word_subword (read X23 s588) (0,32):int32); + val(word_subword (read X22 s588) (0,32):int32)]`; + `f = + ubignum_of_list + [val(word_subword (read Q16 s37) (0,32):int32); + val(word_subword (read Q16 s37) (32,32):int32); + val(word_subword (read Q20 s33) (0,32):int32); + val(word_subword (read Q20 s33) (32,32):int32); + val(word_subword (read Q5 s39) (0,32):int32); + val(word_subword (read Q5 s39) (32,32):int32); + val(word_subword (read Q12 s35) (0,32):int32); + val(word_subword (read Q12 s35) (32,32):int32); + val(word_subword (read Q26 s104) (0,32):int32); + val(word_subword (read Q26 s104) (32,32):int32)]`; + `g = + ubignum_of_list + [val(word_subword (read Q29 s67) (0,32):int32); + val(word_subword (read Q29 s67) (32,32):int32); + val(word_subword (read Q10 s49) (0,32):int32); + val(word_subword (read Q10 s49) (32,32):int32); + val(word_subword (read Q27 s75) (0,32):int32); + val(word_subword (read Q27 s75) (32,32):int32); + val(word_subword (read Q8 s59) (0,32):int32); + val(word_subword (read Q8 s59) (32,32):int32); + val(word_subword (read Q29 s41) (0,32):int32); + val(word_subword (read Q29 s41) (32,32):int32)]`; + `t1 = + ubignum_of_list + [val(word_subword (read Q1 s434) (32,32):int32); + val(word_subword (read Q19 s438) (32,32):int32); + val(word_subword (read Q0 s432) (32,32):int32); + val(word_subword (read Q15 s441) (32,32):int32); + val(word_subword (read Q16 s428) (32,32):int32); + val(word_subword (read Q4 s448) (32,32):int32); + val(word_subword (read Q14 s430) (32,32):int32); + val(word_subword (read Q10 s449) (32,32):int32); + val(word_subword (read Q22 s412) (32,32):int32); + val(word_subword (read Q5 s436) (32,32):int32)]`; + `t2 = + ubignum_of_list + [val(word_subword (read Q1 s434) (0,32):int32); + val(word_subword (read Q19 s438) (0,32):int32); + val(word_subword (read Q0 s432) (0,32):int32); + val(word_subword (read Q15 s441) (0,32):int32); + val(word_subword (read Q16 s428) (0,32):int32); + val(word_subword (read Q4 s448) (0,32):int32); + val(word_subword (read Q14 s430) (0,32):int32); + val(word_subword (read Q10 s449) (0,32):int32); + val(word_subword (read Q22 s412) (0,32):int32); + val(word_subword (read Q5 s436) (0,32):int32)]`; + `t3 = + ubignum_of_list + [val(word_subword (read Q0 s593) (0,64):int64); + val(word_subword (read Q1 s600) (0,64):int64); + val(word_subword (read Q2 s615) (0,64):int64); + val(word_subword (read Q3 s609) (0,64):int64); + val(word_subword (read Q4 s599) (0,64):int64); + val(word_subword (read Q5 s626) (0,64):int64); + val(word_subword (read Q6 s624) (0,64):int64); + val(word_subword (read Q7 s628) (0,64):int64); + val(word_subword (read Q8 s651) (0,64):int64); + val(word_subword (read Q9 s663) (0,64):int64)]`; + `x4 = + ubignum_of_list + [val(word_subword (read Q21 s991) (64,64):int64); + val(word_subword (read Q27 s1007) (64,64):int64); + val(word_subword (read Q28 s1012) (64,64):int64); + val(word_subword (read Q26 s1011) (64,64):int64); + val(word_subword (read Q17 s921) (64,64):int64); + val(word_subword (read Q15 s925) (64,64):int64); + val(word_subword (read Q13 s973) (64,64):int64); + val(word_subword (read Q27 s957) (64,64):int64); + val(word_subword (read Q21 s979) (64,64):int64); + val(word_subword (read Q28 s968) (64,64):int64)]`; + `x5 = + ubignum_of_list + [val(word_subword (read Q0 s593) (64,64):int64); + val(word_subword (read Q1 s600) (64,64):int64); + val(word_subword (read Q2 s615) (64,64):int64); + val(word_subword (read Q3 s609) (64,64):int64); + val(word_subword (read Q4 s599) (64,64):int64); + val(word_subword (read Q5 s626) (64,64):int64); + val(word_subword (read Q6 s624) (64,64):int64); + val(word_subword (read Q7 s628) (64,64):int64); + val(word_subword (read Q8 s651) (64,64):int64); + val(word_subword (read Q9 s663) (64,64):int64)]`; + `z4 = + ubignum_of_list + [val(word_subword (read X5 s982) (0,32):int32); + val(word_subword (read X5 s982) (32,32):int32); + val(word_subword (read X17 s1008) (0,32):int32); + val(word_subword (read X17 s1008) (32,32):int32); + val(word_subword (read X3 s990) (0,32):int32); + val(word_subword (read X3 s990) (32,32):int32); + val(word_subword (read X25 s895) (0,32):int32); + val(word_subword (read X25 s895) (32,32):int32); + val(word_subword (read X23 s992) (0,32):int32); + val(word_subword (read X23 s992) (32,32):int32)]`; + `z5 = + ubignum_of_list + [val(word_subword (read Q21 s991) (0,64):int64); + val(word_subword (read Q27 s1007) (0,64):int64); + val(word_subword (read Q28 s1012) (0,64):int64); + val(word_subword (read Q26 s1011) (0,64):int64); + val(word_subword (read Q17 s921) (0,64):int64); + val(word_subword (read Q15 s925) (0,64):int64); + val(word_subword (read Q13 s973) (0,64):int64); + val(word_subword (read Q27 s957) (0,64):int64); + val(word_subword (read Q21 s979) (0,64):int64); + val(word_subword (read Q28 s968) (0,64):int64)]`];; - (*** The augmented H' = H + L_top ***) +(* ------------------------------------------------------------------------- *) +(* Other local variables (not many of these are really used) *) +(* ------------------------------------------------------------------------- *) - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (69--72) (69--72) THEN - MAP_EVERY ABBREV_TAC - [`q2 = bignum_of_wordlist[sum_s69;sum_s70]`; - `q3 = bignum_of_wordlist[sum_s71;sum_s72]`] THEN - SUBGOAL_THEN - `2 EXP 128 * q3 + q2 = - bignum_of_wordlist [x_2;x_3] * bignum_of_wordlist[y_2;y_3] + q1` - ASSUME_TAC THENL - [MAP_EVERY EXPAND_TAC ["q1"; "q2"; "q3"] THEN - MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN - REPEAT(CONJ_TAC THENL - [CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; ALL_TAC]) THEN - FIRST_X_ASSUM(fun th -> GEN_REWRITE_TAC - (LAND_CONV o LAND_CONV) [SYM th]) THEN - MAP_EVERY EXPAND_TAC ["q23"] THEN - REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ALL_TAC] THEN +let lvs = + ["resx",[`X17`;`0`]; + "xn",[`SP`;`128`]; + "zn",[`SP`;`160`]];; - (*** Third nested block multiplying the absolute differences ***) +(* ------------------------------------------------------------------------- *) +(* Additional definitions, lemmas and tactics to support spec and/or proofs. *) +(* ------------------------------------------------------------------------- *) - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [73;75;80;81;85;87;88;89;92;94;95] (73--95) THEN - RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN - SUBGOAL_THEN - `&xd * &yd:real = - &(bignum_of_wordlist[mullo_s73; sum_s92; sum_s94; sum_s95])` - SUBST_ALL_TAC THENL - [MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - KARATSUBA12_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN - DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN +let SWAR_ADD_LEMMA = prove + (`!(h1:int32) (l1:int32) h2 l2. + val l1 + val l2 < 2 EXP 32 + ==> word_add (word_join h1 l1) (word_join h2 l2):int64 = + word_join (word_add h1 h2) (word_add l1 l2)`, + REPEAT STRIP_TAC THEN + REWRITE_TAC[GSYM VAL_EQ; VAL_WORD_JOIN; VAL_WORD_ADD] THEN + CONV_TAC MOD_DOWN_CONV THEN REWRITE_TAC[DIMINDEX_32; DIMINDEX_64] THEN + ASM_SIMP_TAC[MOD_LT; ARITH_RULE + `(e * x1 + y1) + e * x2 + y2:num = e * (x1 + x2) + (y1 + y2)`] THEN + REWRITE_TAC[GSYM CONG; ARITH_RULE `2 EXP 64 = 2 EXP 32 * 2 EXP 32`] THEN + MATCH_MP_TAC(NUMBER_RULE + `(x':num == x) (mod e) ==> (e * x + l == e * x' + l) (mod (e * e))`) THEN + REWRITE_TAC[CONG_LMOD; CONG_REFL]);; + +let SWAR_SUB_LEMMA = prove + (`!(h1:int32) (l1:int32) h2 l2. + val l2 <= val l1 + ==> word_sub (word_join h1 l1) (word_join h2 l2):int64 = + word_join (word_sub h1 h2) (word_sub l1 l2)`, + REPEAT STRIP_TAC THEN + REWRITE_TAC[WORD_RULE `word_sub x y = z <=> word_add y z = x`] THEN + W(MP_TAC o PART_MATCH (lhand o rand) SWAR_ADD_LEMMA o lhand o snd) THEN + ANTS_TAC THENL + [POP_ASSUM MP_TAC THEN REWRITE_TAC[GSYM DIMINDEX_32] THEN WORD_ARITH_TAC; + DISCH_THEN SUBST1_TAC THEN BINOP_TAC THEN CONV_TAC WORD_RULE]);; + +let WORD_SUBWORD_SWAR_0_32 = prove + (`(!x y. word_subword (word_add x y:int64) (0,32):int32 = + word_add (word_subword x (0,32)) (word_subword y (0,32))) /\ + (!x y. word_subword (word_sub x y:int64) (0,32):int32 = + word_sub (word_subword x (0,32)) (word_subword y (0,32)))`, + REPEAT STRIP_TAC THEN + REWRITE_TAC[GSYM VAL_EQ; VAL_WORD_SUBWORD; INT_VAL_WORD_SUB; VAL_WORD_ADD; + GSYM INT_OF_NUM_CLAUSES; EXP; DIV_1; DIMINDEX_32; DIMINDEX_64; + GSYM INT_OF_NUM_REM; INT_REM_REM_POW_MIN] THEN + CONV_TAC NUM_REDUCE_CONV THEN CONV_TAC INT_REM_DOWN_CONV THEN + REWRITE_TAC[]);; + +let WORD_SUBWORD_SWAR_32_32 = prove + (`(!x y. val(word_subword x (0,32):int32) + val(word_subword y (0,32):int32) + < 2 EXP 32 + ==> word_subword (word_add x y:int64) (32,32):int32 = + word_add (word_subword x (32,32)) (word_subword y (32,32))) /\ + (!x y. val(word_subword y (0,32):int32) <= val(word_subword x (0,32):int32) + ==> word_subword (word_sub x y:int64) (32,32):int32 = + word_sub (word_subword x (32,32)) (word_subword y (32,32)))`, + CONJ_TAC THEN MESON_TAC[SWAR_ADD_LEMMA; SWAR_SUB_LEMMA; WORD_BLAST + `(word_join:int32->int32->int64) + (word_subword x (32,32)) (word_subword x (0,32)) = x /\ + word_subword((word_join:int32->int32->int64) h l) (0,32) = l /\ + word_subword((word_join:int32->int32->int64) h l) (32,32) = h`]);; + +let SIMD_SPLIT_JOIN_CLAUSES = prove + (`(!x. word_subword (word_subword (x:int128) (0,64):int64) (0,32):int32 = + word_subword (x:int128) (0,32)) /\ + (!x. word_subword (word_subword (x:int128) (0,64):int64) (32,32):int32 = + word_subword (x:int128) (32,32)) /\ + (!x. word_subword (word_subword (x:int128) (0,64):int128) (0,32):int32 = + word_subword (x:int128) (0,32)) /\ + (!x. word_subword (word_subword (x:int128) (0,64):int128) (32,32):int32 = + word_subword (x:int128) (32,32)) /\ + (!x. word_subword ((word_zx:int64->int128) x) (0,32):int32 = + word_subword x (0,32)) /\ + (!x. word_subword ((word_zx:int64->int128) x) (32,32):int32 = + word_subword x (32,32)) /\ + (!x y. word_subword ((word_join:int32->int32->int64) x y) (0,32) = y) /\ + (!x y. word_subword ((word_join:int32->int32->int64) x y) (32,32) = x) /\ + (!x y. word_subword ((word_join:int64->int64->int128) x y) (0,64) = y) /\ + (!x y. word_subword ((word_join:int64->int64->int128) x y) (64,64) = x) /\ + (!x. word_zx (word_subword (x:int128) (0,64):int64):int32 = + word_subword x (0,32)) /\ + (!x. word_ushr (word_subword (x:int128) (0,64):int64) 32 = + word_subword x (32,32)) /\ + (!x. word_zx (word_subword (x:int128) (32,32):int64):int32 = + word_subword x (32,32))`, + CONV_TAC WORD_BLAST);; + +let EXTRA_SPLIT_JOIN_CLAUSES = prove + (`(!x y. word_subword (word_join (x:int64) (y:int64):int128) (32,32):int32 = + word_subword y (32,32)) /\ + (!x y. word_subword (word_join (x:int64) (y:int64):int128) (0,32):int32 = + word_subword y (0,32)) /\ + (!x y. word_subword (word_join (x:int32) (y:int32):int64) (0,32) = y) /\ + (!x y. word_subword (word_join (x:int32) (y:int32):int64) (32,32) = x) /\ + (!x. word_subword (x:int128) (0,128) = x) /\ + (!x. word_subword (x:int64) (0,64) = x) /\ + (!x. word_subword (x:int32) (0,32) = x) /\ + (!(x:int128) y. + word_insert x (0,64) + (word_subword (y:int128) (64,64):int128):int128 = + word_join (word_subword x (64,64):int64) + (word_subword y (64,64):int64)) /\ + (!(x:int128) (y:int64). + word_insert x (32,32) (word_zx y:int32):int128 = + word_join (word_subword x (64,64):int64) + (word_join (word_subword y (0,32):int32) + (word_subword x (0,32):int32):int64)) /\ + (!(x:int128) (y:int64). + word_insert x (0,32) (word_zx y:int32):int128 = + word_join (word_subword x (64,64):int64) + (word_join (word_subword x (32,32):int32) + (word_subword y (0,32):int32):int64)) /\ + (!x:int64. word_subword (word_ushr x 32) (0,32):int32 = + word_subword x (32,32))`, + CONV_TAC WORD_BLAST);; + +let UBIGNUM_PACK_UNPACK_CLAUSES = prove + (`(word_subword:int64->num#num->int32) + (word_insert (word_and l (word 0x3ffffff:int64)) (32,26) (h:int64)) + (0,32) = + word(val l MOD 2 EXP 26) /\ + (word_subword:int64->num#num->int32) + (word_insert (word_and l (word 0x3ffffff:int64)) (32,26) (h:int64)) + (32,32) = + word(val h MOD 2 EXP 26) /\ + (word_subword:int64->num#num->int32) + (word_insert (word_and l (word 0x3ffffff:int64)) (32,25) (h:int64)) + (0,32) = + word(val l MOD 2 EXP 26) /\ + (word_subword:int64->num#num->int32) + (word_insert (word_and l (word 0x3ffffff:int64)) (32,25) (h:int64)) + (32,32) = + word(val h MOD 2 EXP 25)`, + CONV_TAC WORD_BLAST);; + +let SIMD_MASK_CLAUSES = + ((fun th -> CONJ th (ONCE_REWRITE_RULE[WORD_AND_SYM] th)) o prove) + (`(!(x:int64) (y:int64). + word_subword (word_and (word 0x1ffffff0000000001ffffff:int128) + (word_join x y)) (0,64) = + word_and (word 0x1ffffff) y) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0x1ffffff0000000001ffffff:int128) + (word_join x y)) (64,64) = + word_and (word 0x1ffffff) x) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0x3ffffff0000000003ffffff:int128) + (word_join x y)) (0,64) = + word_and (word 0x3ffffff) y) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0x3ffffff0000000003ffffff:int128) + (word_join x y)) (64,64) = + word_and (word 0x3ffffff) x) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0xfffffffffe000000fffffffffe000000:int128) + (word_join x y)) (0,64) = + word_and (word 0xfffffffffe000000) y) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0xfffffffffe000000fffffffffe000000:int128) + (word_join x y)) (64,64) = + word_and (word 0xfffffffffe000000) x) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0xfffffffffc000000fffffffffc000000:int128) + (word_join x y)) (0,64) = + word_and (word 0xfffffffffc000000) y) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0xfffffffffc000000fffffffffc000000:int128) + (word_join x y)) (64,64) = + word_and (word 0xfffffffffc000000) x)`, + CONV_TAC WORD_BLAST);; + +let is_readcomponent tm = + match tm with + Comb(Comb(Const("read",_),c),s) -> true + | _ -> false;; + +let get_readcomponents = + sort (<) o find_terms is_readcomponent;; + +let rec process env tms = + match tms with + tm::otms -> + let lv,rt = dest_eq tm in + let nm = fst(dest_var lv) in + let rcs = get_readcomponents(subst env rt) in + let ixs = 0--(length rcs-1) in + let nenv = + map2 (fun rc i -> mk_var(nm^"_"^string_of_int i,type_of rc),rc) + rcs ixs in + process (nenv @ env) otms + | [] -> env;; + +let distinguished_components = process [] named_variables;; + +let abbreviated_variables = + map (subst distinguished_components) named_variables;; + +let ABBREVIATE_STATE_COMPONENTS_TAC = + let armstate_ty = `:armstate` in + fun n -> + let sv = mk_var("s"^string_of_int n,armstate_ty) in + let this = filter (fun (v,t) -> rand t = sv) distinguished_components in + MAP_EVERY (fun (v,sc) -> REABBREV_TAC(mk_eq(v,sc))) this;; + +let ARM_NAMESTEPS_TAC execth = + MAP_EVERY (fun n -> + ARM_STEPS_TAC execth [n] THEN + RULE_ASSUM_TAC(REWRITE_RULE[SIMD_SPLIT_JOIN_CLAUSES; + EXTRA_SPLIT_JOIN_CLAUSES]) THEN + ABBREVIATE_STATE_COMPONENTS_TAC n);; + +let find_abbrev s = + let mfn tm = + match tm with + Comb(Comb(Const("=",_),_),Var(s',_)) -> s' = s + | _ -> false in + fun (asl,w) -> find mfn (map (concl o snd) asl);; + +let USE_ABBREV cont s (asl,w) = cont (find_abbrev s (asl,w)) (asl,w);; + +let STANDARDIZE_INEQ = + let lemma = prove + (`x:num < y ==> &x:real <= &y - &1`, + REWRITE_TAC[REAL_LE_SUB_LADD; REAL_OF_NUM_CLAUSES] THEN ARITH_TAC) in + let rule0 = CONV_RULE (RAND_CONV REAL_INT_SUB_CONV) o MATCH_MP lemma + and rule1 = + CONV_RULE (RAND_CONV(NUM_REDUCE_CONV THENC REAL_INT_SUB_CONV)) o + MATCH_MP lemma + and rule2 = GEN_REWRITE_RULE I [GSYM REAL_OF_NUM_LE] + and rule3 = MATCH_MP REAL_LT_IMP_LE + and rule4 = MATCH_MP(TAUT `x:real <= y ==> x <= y`) in + fun th -> + let th' = tryfind (fun r -> r th) [rule0;rule1;rule2;rule3;rule4] in + if is_ratconst(rand(concl th')) then th' + else failwith "STANDARDIZE_INEQ";; + +let BOUND_ABBREV_THEN cont th (asl,w) = + let th1 = AP_TERM `real_of_int` (AP_TERM `int_of_num` + (GEN_REWRITE_RULE I [GSYM VAL_EQ] th)) in + let th2 = GEN_REWRITE_RULE (LAND_CONV o TOP_DEPTH_CONV) + [GSYM INT_OF_NUM_CLAUSES; INT_VAL_WORD_SUB; + VAL_WORD; VAL_WORD_ADD; VAL_WORD_MUL; VAL_WORD_ZX_GEN; VAL_WORD_SHL; + VAL_WORD_USHR; GSYM INT_OF_NUM_DIV; GSYM INT_OF_NUM_REM] th1 in + let th3 = CONV_RULE(INT_REM_DOWN_CONV THENC + ONCE_DEPTH_CONV(!word_SIZE_CONV)) th2 in + let th4 = BOUNDER_RULE (mapfilter (STANDARDIZE_INEQ o snd) asl) + (lhand(concl th3)) in + let th5 = GEN_REWRITE_RULE LAND_CONV [th3] (CONJUNCT2 th4) in + let th6 = GEN_REWRITE_RULE LAND_CONV [int_of_num_th] th5 in + let th7 = GEN_REWRITE_RULE I [REAL_OF_NUM_LE] th6 in + cont th7 (asl,w);; + +let (DEDUCE_DIGITBOUNDS_TAC:thm list->string->tactic) = + let is_localdef s tm = + match tm with + Comb(Comb(Const("=",_),Comb(Const("ubignum_of_list",_),l)), + Var(s',Tyapp("num",[]))) -> s' = s + | _ -> false + and is_remmy = can (term_match [] `x rem p`) + and ic_tm = `int_of_num` + and ri_tm = `real_of_int` + and yemma = prove + (`&x = i rem p /\ + real_of_int i = r /\ + a <= r /\ r <= &b + ==> &0 <= a ==> x <= b`, + REPEAT STRIP_TAC THEN ASM_REWRITE_TAC[GSYM INT_OF_NUM_LE] THEN + TRANS_TAC INT_LE_TRANS `i:int` THEN CONJ_TAC THENL + [REWRITE_TAC[INT_REM_LE_EQ]; ALL_TAC] THEN + ASM_REWRITE_TAC[GSYM REAL_OF_INT_CLAUSES] THEN ASM_REAL_ARITH_TAC) + and nemma = prove + (`&x = i /\ + real_of_int i = r /\ + a <= r /\ r <= &b + ==> x <= b`, + REPEAT STRIP_TAC THEN ASM_REWRITE_TAC[GSYM INT_OF_NUM_LE] THEN + ASM_REWRITE_TAC[GSYM REAL_OF_INT_CLAUSES]) in + fun ths s (asl,w) -> + let sdef = concl(snd(find (is_localdef s o concl o snd) asl)) + and bths = mapfilter (STANDARDIZE_INEQ o snd) asl + and EXPANSION_RULE v = + SYM(snd(find (fun (_,th) -> let t = concl th in is_eq t && rand t = v) + asl)) in + let FINDBOUND conv tm = + let th = + (conv THENC + REWRITE_CONV[COND_RAND; COND_RATOR] THENC + REWRITE_CONV[SIMD_SPLIT_JOIN_CLAUSES; SIMD_MASK_CLAUSES; + EXTRA_SPLIT_JOIN_CLAUSES; UBIGNUM_PACK_UNPACK_CLAUSES] THENC + SUBS_CONV ths THENC + REWRITE_CONV[GSYM INT_OF_NUM_CLAUSES; INT_VAL_WORD_SUB; + VAL_WORD; VAL_WORD_ADD; VAL_WORD_MUL; VAL_WORD_ZX_GEN; + VAL_WORD_SHL; VAL_WORD_USHR; + GSYM INT_OF_NUM_DIV; GSYM INT_OF_NUM_REM] THENC + INT_REM_DOWN_CONV THENC + ONCE_DEPTH_CONV(!word_SIZE_CONV)) + (mk_comb(ic_tm,tm)) in + let etm = rand(concl th) in + let itm = if is_remmy etm then lhand etm else etm in + let ith = REWRITE_CONV [COND_RAND; COND_RATOR; GSYM REAL_OF_INT_CLAUSES] + (mk_comb(ri_tm,itm)) in + let bth = BOUNDER_RULE bths (rand(concl ith)) in + if is_remmy etm then + let lth = MATCH_MP yemma (CONJ th (CONJ ith bth)) in + MP lth (EQT_ELIM(REAL_RAT_REDUCE_CONV(lhand(concl lth)))) + else + MATCH_MP nemma (CONJ th (CONJ ith bth)) in + let eqs = mapfilter EXPANSION_RULE (frees(rand(lhand sdef))) in + let conv = PURE_REWRITE_CONV eqs in + MAP_EVERY (ASSUME_TAC o FINDBOUND conv) + (dest_list(rand(lhand sdef))) (asl,w);; + +let GEN_DEMODULATE_TAC pats = + let moks = map (can o term_match []) pats in + let patx tm = exists (fun f -> f tm) moks in + fun (asl,w) -> + let tms = sort free_in (find_terms patx w) in + MAP_FIRST (fun t -> + MP_TAC(PART_MATCH (lhand o rand) MOD_LT t) THEN ANTS_TAC THENL + [ASM BOUNDER_TAC[]; DISCH_THEN SUBST1_TAC]) tms (asl,w);; + +let DEMODULATE_TAC = GEN_DEMODULATE_TAC [`x MOD 2 EXP 32`; `x MOD 2 EXP 64`];; + +let FULL_DEMODULATE_TAC = GEN_DEMODULATE_TAC [`x MOD 2 EXP n`];; + +let GEN_DEREMULATE_TAC pats = + let moks = map (can o term_match []) pats in + let patx tm = exists (fun f -> f tm) moks in + fun (asl,w) -> + let tms = sort free_in (find_terms patx w) in + MAP_FIRST (fun t -> + MP_TAC(PART_MATCH (lhand o rand) INT_REM_LT t) THEN ANTS_TAC THENL + [CONJ_TAC THENL [DISCH_THEN(K ALL_TAC); ALL_TAC] THEN ASM BOUNDER_TAC[]; + DISCH_THEN SUBST1_TAC]) tms (asl,w);; + +let DEREMULATE_TAC = GEN_DEREMULATE_TAC [`x rem &2 pow 32`; `x rem &2 pow 64`];; + +let FULL_DEREMULATE_TAC = GEN_DEREMULATE_TAC [`x rem &2 pow n`];; + +let FULLEXPAND_TAC names = + REPEAT(W(fun (asl,w) -> + let names' = intersect names (map name_of (frees(lhand(rator w)))) in + if names' <> [] then MAP_EVERY EXPAND_TAC names' + else failwith "FULLEXPAND_TAC: expansion over"));; + +let ARITHBLOCK_TAC = + let word_simps = + ((fun th -> CONJ th (ONCE_REWRITE_RULE[WORD_AND_SYM] th)) o WORD_BLAST) + `val(word_and x (word 0x1FFFFFF):int64) = val x MOD 2 EXP 25 /\ + val(word_and x (word 0x3FFFFFF):int64) = val x MOD 2 EXP 26 /\ + val(word_and x (word 0xfffffffffc000000):int64) = + 2 EXP 26 * val x DIV 2 EXP 26 /\ + val(word_and x (word 0xfffffffffe000000):int64) = + 2 EXP 25 * val x DIV 2 EXP 25` + and muldiv_simps = prove + (`(&2 pow 25 * x) div &2 pow 25 = x /\ + (&2 pow 26 * x) div &2 pow 26 = x /\ + (&2 pow 26 * x) div &2 pow 25 = &2 * x /\ + (&2 pow 26 * x) div &2 pow 22 = &16 * x /\ + (&2 pow 25 * x) div &2 pow 24 = &2 * x /\ + (&2 pow 25 * x) div &2 pow 21 = &16 * x`, + REPEAT CONJ_TAC THEN INT_ARITH_TAC) in + fun ths -> + W(MAP_EVERY (EXPAND_TAC o name_of) o frees o snd) THEN + W(FULLEXPAND_TAC o map name_of o frees o lhand o rator o snd) THEN + REWRITE_TAC[ubignum_of_list; SIMD_SPLIT_JOIN_CLAUSES; SIMD_MASK_CLAUSES; + EXTRA_SPLIT_JOIN_CLAUSES; UBIGNUM_PACK_UNPACK_CLAUSES] THEN + CONV_TAC(SUBS_CONV ths) THEN + REWRITE_TAC[word_simps; GSYM INT_OF_NUM_CLAUSES; + GSYM INT_OF_NUM_DIV; GSYM INT_OF_NUM_REM; + VAL_WORD; VAL_WORD_ADD; VAL_WORD_MUL; INT_VAL_WORD_SUB; + VAL_WORD_ZX_GEN; VAL_WORD_SHL; VAL_WORD_USHR] THEN + CONV_TAC(ONCE_DEPTH_CONV(!word_SIZE_CONV)) THEN + CONV_TAC INT_REM_DOWN_CONV THEN REPEAT DEREMULATE_TAC THEN + REWRITE_TAC[muldiv_simps] THEN + TRY FULL_DEREMULATE_TAC THEN POP_ASSUM_LIST(K ALL_TAC) THEN + REPEAT(W(fun (asl,w) -> + let dmotms = + find_terms (can (term_match [] `m div n`)) w @ + find_terms (can (term_match [] `m rem n`)) w in + let tm = hd(sort free_in dmotms) in + let th1 = SPECL [lhand tm; rand tm] INT_DIVISION_SIMP in + let qtm = lhand(lhand(lhand(concl th1))) + and rtm = rand(lhand(concl th1)) in + MP_TAC th1 THEN + ABBREV_TAC(mk_eq(genvar(type_of qtm),qtm)) THEN + ABBREV_TAC(mk_eq(genvar(type_of rtm),rtm)) THEN + POP_ASSUM(K ALL_TAC) THEN POP_ASSUM(K ALL_TAC) THEN DISCH_TAC)) THEN + REPEAT(FIRST_X_ASSUM(SUBST_ALL_TAC o MATCH_MP (INT_ARITH + `n * q + r:int = x ==> r = x - n * q`))) THEN + REWRITE_TAC[REAL_INT_CONGRUENCE; INT_OF_NUM_EQ; p_25519; ARITH_EQ] THEN + REWRITE_TAC[GSYM REAL_OF_INT_CLAUSES] THEN REAL_INTEGER_TAC;; + +let extra = prove + (`(word_zx:int64->int32) (word_add x x) = + word_zx (word_mul (word 2:int32) (word_zx x))`, + REWRITE_TAC[GSYM VAL_EQ; VAL_WORD_ZX_GEN; VAL_WORD_ADD; VAL_WORD_MUL] THEN + CONV_TAC MOD_DOWN_CONV THEN REWRITE_TAC[DIMINDEX_32; DIMINDEX_64] THEN + REWRITE_TAC[MOD_MOD_EXP_MIN; ARITH_RULE `MIN 64 32 = 32`] THEN + AP_THM_TAC THEN AP_TERM_TAC THEN CONV_TAC WORD_REDUCE_CONV THEN + ARITH_TAC);; - (*** The rest of the basic 4x4->8 multiply computation and its proof ***) +(* ------------------------------------------------------------------------- *) +(* Lemmas and tactics for the inlined field multiplication proof. *) +(* ------------------------------------------------------------------------- *) - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [96;97;98;99;100;101;104;106;108;110;111;112] (96--112) THEN - MAP_EVERY ABBREV_TAC - [`l = bignum_of_wordlist[mullo_s3; sum_s22; sum_s104; sum_s106]`; - `h = bignum_of_wordlist[sum_s108; sum_s110; sum_s111; sum_s112]`] THEN - SUBGOAL_THEN `2 EXP 256 * h + l = m * n` (SUBST1_TAC o SYM) THENL - [DISCARD_STATE_TAC "s112" THEN MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`512`; `&0:real`] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL - [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN BOUNDER_TAC[]; - REWRITE_TAC[INTEGER_CLOSED]] THEN - SUBGOAL_THEN - `&m * &n:real = - (&1 + &2 pow 128) * (&q0 + &2 pow 128 * &q2 + &2 pow 256 * &q3) + - &2 pow 128 * - (&(bignum_of_wordlist [x_2; x_3]) - - &(bignum_of_wordlist [x_0; x_1])) * - (&(bignum_of_wordlist [y_0; y_1]) - - &(bignum_of_wordlist [y_2; y_3]))` - SUBST1_TAC THENL - [MAP_EVERY UNDISCH_TAC - [`2 EXP 128 * q1 + q0 = - bignum_of_wordlist[x_0; x_1] * bignum_of_wordlist[y_0; y_1]`; - `2 EXP 128 * q3 + q2 = - bignum_of_wordlist[x_2; x_3] * bignum_of_wordlist[y_2; y_3] + - q1`] THEN - MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - CONV_TAC REAL_RING; - ASM_REWRITE_TAC[]] THEN - MAP_EVERY EXPAND_TAC ["h"; "l"; "q0"; "q2"; "q3"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - POP_ASSUM_LIST(K ALL_TAC) THEN - REWRITE_TAC[WORD_XOR_MASK] THEN COND_CASES_TAC THEN - ASM_REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN - CONV_TAC WORD_REDUCE_CONV THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[BITVAL_CLAUSES] THEN DISCH_TAC THEN - FIRST_ASSUM(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN +let lemma0 = prove + (`!x0 x1:int64. + &(val(if val x0 <= val x1 then word_sub x1 x0 + else word_neg(word_sub x1 x0))):real = abs(&(val x1) - &(val x0))`, + REPEAT GEN_TAC THEN REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN + REWRITE_TAC[WORD_NEG_SUB; REAL_ARITH + `abs(x - y):real = if y <= x then x - y else y - x`] THEN + COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN + RULE_ASSUM_TAC(REWRITE_RULE[REAL_OF_NUM_CLAUSES; NOT_LE]) THEN + ASM_SIMP_TAC[VAL_WORD_SUB_CASES; LT_IMP_LE; REAL_OF_NUM_SUB]);; - (*** The initial modular reduction of the high part ***) +let lemma1 = prove + (`!(x0:num) x1 (y0:num) y1. + (if y0 <= y1 + then if x1 <= x0 then word 0 else word 18446744073709551615 + else word_not + (if x1 <= x0 then word 0 else word 18446744073709551615)):int64 = + word_neg(word(bitval(y0 <= y1 <=> x0 < x1)))`, + REPEAT GEN_TAC THEN REWRITE_TAC[GSYM NOT_LE] THEN + REPEAT(COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES]) THEN + CONV_TAC WORD_REDUCE_CONV);; - SUBGOAL_THEN - `(2 EXP 256 * h + l) MOD p_25519 = (38 * h + l) MOD p_25519` - SUBST1_TAC THENL - [ONCE_REWRITE_TAC[GSYM MOD_ADD_MOD] THEN - ONCE_REWRITE_TAC[GSYM MOD_MULT_LMOD] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV; - ALL_TAC] THEN +let lemma2 = prove + (`!p x0 x1 y0 y1:real. + (x0 + p * x1) * (y0 + p * y1) = + x0 * y0 + p pow 2 * x1 * y1 + + p * (x0 * y0 + x1 * y1 + + --(&1) pow bitval(y1 <= y0 <=> x1 < x0) * + abs(x1 - x0) * abs(y0 - y1))`, + REPEAT GEN_TAC THEN + MAP_EVERY ASM_CASES_TAC [`y1:real <= y0`; `x1:real < x0`] THEN + ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN ASM_REAL_ARITH_TAC);; - (*** Instantiate the quotient approximation lemma ***) +let VAL_WORD_MADDL_0 = prove + (`!x y. val(word(0 + val(x:int32) * val(y:int32)):int64) = val x * val y`, + REPEAT GEN_TAC THEN REWRITE_TAC[ADD_CLAUSES; VAL_WORD_EQ_EQ] THEN + REWRITE_TAC[DIMINDEX_64; ARITH_RULE `2 EXP 64 = 2 EXP 32 * 2 EXP 32`] THEN + MATCH_MP_TAC LT_MULT2 THEN REWRITE_TAC[GSYM DIMINDEX_32; VAL_BOUND]);; - MP_TAC(SPECL [`h:num`; `l:num`] p25519redlemma32) THEN ANTS_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - LET_TAC THEN STRIP_TAC] THEN +let DIVMOD_32_32 = prove + (`!n. (2 EXP 32 * n) MOD 2 EXP 64 = 2 EXP 32 * n MOD 2 EXP 32`, + REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - (*** The somewhat fiddly reduction with 32-bit operations etc. ***) +let DIVMOD_33_31 = prove + (`!n. (2 EXP 33 * n) MOD 2 EXP 64 = 2 EXP 33 * n MOD 2 EXP 31`, + REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - ARM_STEPS_TAC CURVE25519_X25519_EXEC (113--137) THEN +let DIVMOD_63_64 = prove + (`!n. (2 EXP 63 * n) MOD 2 EXP 64 = 2 EXP 63 * n MOD 2`, + REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM MP_TAC) - [`u0 = read X7 s137`; - `u1 = read X8 s137`; - `u2 = read X9 s137`; - `u3 = read X10 s137`; - `u4 = read X11 s137`; - `u5 = read X12 s137`; - `u6 = read X13 s137`; - `u7 = read X14 s137`] THEN - REWRITE_TAC[GSYM IMP_CONJ_ALT] THEN - GEN_REWRITE_TAC (LAND_CONV o TOP_DEPTH_CONV) - [word_add; modular; ADD_CLAUSES; VAL_WORD; VAL_WORD_ZX_GEN; - VAL_WORD_USHR; DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN] THEN - REWRITE_TAC[DIV_MOD; GSYM EXP_ADD] THEN - CONV_TAC(DEPTH_CONV NUM_ADD_CONV) THEN - CONV_TAC(DEPTH_CONV NUM_MIN_CONV) THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `n < 2 EXP 64 ==> n MOD 2 EXP 32 * 38 < 2 EXP 64`] THEN - STRIP_TAC THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC [142;144;146;150] (138--150) THEN - SUBGOAL_THEN `word_ushr u7 31:int64 = word q` SUBST_ALL_TAC THENL - [REWRITE_TAC[GSYM VAL_EQ; VAL_WORD; VAL_WORD_USHR] THEN - ASM_SIMP_TAC[DIMINDEX_64; MOD_LT] THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s106:int64) DIV 2 EXP 32 + - val(sum_s112:int64) DIV 2 EXP 32 * 38):int64 = u7`)) THEN - MAP_EVERY EXPAND_TAC ["q"; "l"; "h"] THEN - REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[VAL_WORD; ARITH_RULE `a + b * 38 = 38 * b + a`] THEN - MATCH_MP_TAC MOD_LT THEN REWRITE_TAC[DIMINDEX_64] THEN - REWRITE_TAC[GSYM VAL_WORD_USHR] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - ALL_TAC] THEN - SUBGOAL_THEN - `&(val(word_add (u0:int64) - (word(19 + 19 * val((word_zx:int64->int32)(word q)))))):real = - &(val u0) + &19 * (&q + &1)` - SUBST_ALL_TAC THENL - [REWRITE_TAC[REAL_OF_NUM_CLAUSES; VAL_WORD_ADD; VAL_WORD; VAL_WORD_ZX_GEN; - DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN] THEN - ASM_SIMP_TAC[ARITH_RULE `q <= 77 ==> q < 2 EXP MIN 64 32`; MOD_LT] THEN - CONV_TAC MOD_DOWN_CONV THEN - REWRITE_TAC[ARITH_RULE `19 + 19 * q = 19 * (q + 1)`] THEN - MATCH_MP_TAC MOD_LT THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s108:int64) MOD 2 EXP 32 * 38 + - val(mullo_s3:int64) MOD 2 EXP 32):int64 = u0`)) THEN - MATCH_MP_TAC(ARITH_RULE - `w <= 2 EXP 63 /\ q <= 77 ==> w + 19 * (q + 1) < 2 EXP 64`) THEN - CONJ_TAC THENL [MATCH_MP_TAC VAL_WORD_LE; FIRST_ASSUM ACCEPT_TAC] THEN - ARITH_TAC; - ALL_TAC] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - REWRITE_TAC[REAL_VAL_WORD_XOR; WORD_AND_POW2_BITVAL; - REWRITE_RULE[DIMINDEX_64; NUM_REDUCE_CONV `64 - 1`] - (ISPEC `x:int64` WORD_SHL_LSB)] THEN - REWRITE_TAC[VAL_WORD; DIMINDEX_64; DIVMOD_63_64] THEN - SIMP_TAC[MOD_LT; BITVAL_BOUND_ALT; GSYM REAL_OF_NUM_CLAUSES] THEN - ASM_SIMP_TAC[GSYM VAL_MOD_2; VAL_WORD; DIMINDEX_64; MOD_LT] THEN - STRIP_TAC THEN - ABBREV_TAC - `r = bignum_of_wordlist[sum_s142; sum_s144; sum_s146; sum_s150]` THEN +let VAL_WORD_SPLIT32 = prove + (`!x. 2 EXP 32 * val(word_zx(word_ushr x 32):int32) + val(word_zx x:int32) = + val(x:int64)`, + REWRITE_TAC[VAL_WORD_USHR; VAL_WORD_ZX_GEN; DIMINDEX_32] THEN + GEN_TAC THEN REWRITE_TAC[GSYM MOD_MULT_MOD; GSYM EXP_ADD] THEN + CONV_TAC(ONCE_DEPTH_CONV NUM_ADD_CONV) THEN + MATCH_MP_TAC MOD_LT THEN REWRITE_TAC[VAL_BOUND_64]);; - SUBGOAL_THEN - `(&r:int == &2 pow 255 + &(38 * h + l) - (&q + &1) * &p_25519) - (mod (&2 pow 256))` - ASSUME_TAC THENL - [SUBGOAL_THEN - `38 * h + l = - bignum_of_wordlist[u0;u1;u2;u3] + - 2 EXP 32 * bignum_of_wordlist[u4;u5;u6;u7]` - SUBST1_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o - check (can (term_match [] `word x = n`) o concl))) THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD; DIMINDEX_64] THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `m < 2 EXP 64 /\ n < 2 EXP 64 - ==> m DIV 2 EXP 32 + n DIV 2 EXP 32 * 38 < 2 EXP 64`; - ARITH_RULE `m MOD 2 EXP 32 * 38 + n MOD 2 EXP 32 < 2 EXP 64`] THEN - ARITH_TAC; - ALL_TAC] THEN - SUBGOAL_THEN - `2 EXP 32 * bignum_of_wordlist [u4; u5; u6; u7] = - bignum_of_wordlist - [word_shl u4 32; - word_subword ((word_join:int64->int64->int128) u5 u4) (32,64); - word_subword ((word_join:int64->int64->int128) u6 u5) (32,64); - word_subword ((word_join:int64->int64->int128) u7 u6) (32,64); - word_ushr u7 32]` - SUBST1_TAC THENL - [REWRITE_TAC[val_def; DIMINDEX_64; bignum_of_wordlist] THEN - REWRITE_TAC[ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN - REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN - REWRITE_TAC[BIT_WORD_JOIN; BIT_WORD_USHR; BIT_WORD_SUBWORD; - BIT_WORD_SHL; DIMINDEX_64; DIMINDEX_128] THEN - CONV_TAC NUM_REDUCE_CONV THEN - CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN - CONV_TAC NUM_REDUCE_CONV THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - ONCE_REWRITE_TAC[BIT_GUARD] THEN REWRITE_TAC[DIMINDEX_64] THEN - CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[BITVAL_CLAUSES] THEN - ARITH_TAC; - ALL_TAC] THEN - SIMP_TAC[REAL_INT_CONGRUENCE; INT_POW_EQ_0; INT_OF_NUM_EQ; ARITH_EQ] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; - int_mul_th; int_pow_th] THEN - EXPAND_TAC "r" THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN +let p25519redlemma32 = prove + (`!h l. h < 2 EXP 256 /\ l < 2 EXP 256 + ==> let q = (38 * h DIV 2 EXP 224 + l DIV 2 EXP 224) DIV 2 EXP 31 in + q <= 77 /\ + q < 2 EXP 64 /\ + (q + 1) * p_25519 <= (38 * h + l) + p_25519 /\ + 38 * h + l < (q + 1) * p_25519 + p_25519`, + CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN + REWRITE_TAC[p_25519] THEN ARITH_TAC);; - (*** The final optional correction ***) +let endp25519redlemma = prove + (`(&z == &2 pow 255 + x) (mod (&2 pow 256)) /\ + --(&p_25519) <= x /\ x < &p_25519 /\ z < 2 EXP 256 + ==> x rem &p_25519 = + if z < 2 EXP 255 then &z - &19 else &z - &2 pow 255`, + REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN REPEAT STRIP_TAC THEN + SUBGOAL_THEN `&z:int < &2 pow 255 <=> x:int < &0` SUBST1_TAC THENL + [ALL_TAC; + COND_CASES_TAC THEN MATCH_MP_TAC INT_REM_UNIQ THENL + [EXISTS_TAC `--(&1):int`; EXISTS_TAC `&0:int`]] THEN + FIRST_X_ASSUM(MP_TAC o MATCH_MP + (REWRITE_RULE[IMP_CONJ_ALT] INT_CONG_IMP_EQ)) THEN + REWRITE_TAC[p_25519] THEN + RULE_ASSUM_TAC(REWRITE_RULE[p_25519]) THEN ASM_INT_ARITH_TAC);; - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (154--157) (151--160) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN CONV_TAC SYM_CONV THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_MOD_MOD THEN - MAP_EVERY EXISTS_TAC - [`255`; - `(if r < 2 EXP 255 then &r - &19 else &r - &2 pow 255):real`] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN - ASM_REWRITE_TAC[] THEN DISCARD_STATE_TAC "s160" THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC]) THEN - CONJ_TAC THENL - [REWRITE_TAC[ARITH_RULE `r < 2 EXP 255 <=> r DIV 2 EXP 192 < 2 EXP 63`] THEN - EXPAND_TAC "r" THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - REWRITE_TAC[SYM(NUM_REDUCE_CONV `2 EXP 63 - 1`)] THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD_AND_MASK_WORD] THEN - ABBREV_TAC `bb <=> val(sum_s150:int64) < 2 EXP 63` THEN - SUBGOAL_THEN - `ival(word_and sum_s150 (word 9223372036854775808):int64) < &0 <=> ~bb` - SUBST_ALL_TAC THENL - [REWRITE_TAC[GSYM MSB_IVAL; BIT_WORD_AND] THEN - REWRITE_TAC[MSB_VAL] THEN REWRITE_TAC[DIMINDEX_64] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - EXPAND_TAC "bb" THEN ARITH_TAC; - RULE_ASSUM_TAC(REWRITE_RULE[]) THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC]; - FIRST_ASSUM(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ] - endp25519redlemma)) THEN - ANTS_TAC THENL - [REWRITE_TAC[INT_ARITH `--p:int <= x - y <=> y <= x + p`] THEN - REWRITE_TAC[INT_ARITH `x - y:int < p <=> x < y + p`] THEN - ASM_REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN - EXPAND_TAC "r" THEN BOUNDER_TAC[]; - REWRITE_TAC[INT_ARITH `x - q * p:int = --q * p + x`] THEN - REWRITE_TAC[INT_REM_MUL_ADD] THEN - REWRITE_TAC[int_eq; int_of_num_th; INT_OF_NUM_REM] THEN - DISCH_THEN SUBST1_TAC THEN COND_CASES_TAC THEN - ASM_REWRITE_TAC[int_of_num_th; int_sub_th; int_pow_th]]]);; +let KARATSUBA12_TAC = + REWRITE_TAC[REAL_MUL_RZERO; REAL_ADD_RID] THEN + MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN + MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN + ASM_REWRITE_TAC[INTEGER_CLOSED] THEN + REPLICATE_TAC 2 (CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC]) THEN + REWRITE_TAC[lemma2; REAL_OF_NUM_LE; REAL_OF_NUM_LT] THEN + ACCUMULATOR_POP_ASSUM_LIST(fun thl -> + MP_TAC(end_itlist CONJ(rev thl)) THEN + REWRITE_TAC[WORD_XOR_MASK] THEN + REWRITE_TAC[REAL_OF_NUM_LT; REAL_OF_NUM_LE; GSYM NOT_LE] THEN + COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN + CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN + REWRITE_TAC[REAL_VAL_WORD_NOT; DIMINDEX_64] THEN + DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN + CONV_TAC(RAND_CONV REAL_POLY_CONV) THEN + REWRITE_TAC(filter(is_ratconst o rand o concl) (DECARRY_RULE thl)) THEN + REAL_INTEGER_TAC);; -(* ------------------------------------------------------------------------- *) -(* Instances of mul_4. *) -(* ------------------------------------------------------------------------- *) +let p25519weakredlemma = prove + (`!n. n <= 2 EXP 62 * 2 EXP 256 + ==> let q = n DIV 2 EXP 255 in + q < 2 EXP 64 /\ + q * p_25519 <= n /\ + n < q * p_25519 + 2 * p_25519`, + CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN REWRITE_TAC[p_25519] THEN ARITH_TAC);; -let LOCAL_MUL_4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_mc 172 lvs +let LOCAL_MUL_P25519_TAC = + ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_mc 180 lvs `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m ==> !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n ==> aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x571c) (word_add (read p3 t) (word n3),8 * 4) + nonoverlapping (word pc,0x2554) (word_add (read p3 t) (word n3),8 * 4) ==> ensures arm (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ read PC s = pcin /\ read SP s = read SP t /\ - read X23 s = read X23 t /\ + read X17 s = read X17 t /\ read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s - < 2 * p_25519 /\ - (read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s == - m * n) (mod p_25519)) - (MAYCHANGE [PC; X0; X1; X2; X3; X4; X5; X6; X7; X8; X9; X10; - X11; X12; X13; X14; X15; X16] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` + read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s = + (m * n) MOD p_25519) + (MAYCHANGE [PC; X0; X1; X2; X3; X4; X5; X6; X7; X8; X9; X10; X11; X12; + X13; X14; X15; X16] ,, + MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, + MAYCHANGE SOME_FLAGS)` (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN @@ -6382,463 +3560,112 @@ let LOCAL_MUL_4_TAC = `y:real <= x /\ (&0 <= x /\ x < e) /\ (&0 <= y /\ y < e) ==> &0 <= x - y /\ x - y < e`) THEN ASM_SIMP_TAC[REAL_OF_NUM_CLAUSES; LT_IMP_LE; - ARITH_RULE `~(a:num < b) ==> b <= a`] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - CONJ_TAC THEN BOUNDER_TAC[]; - ALL_TAC] THEN - MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; REWRITE_TAC[INTEGER_CLOSED]]) THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - ASM_REWRITE_TAC[WORD_XOR_MASK] THEN - REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN - DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** Clean up the overall sign ***) - - FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE RAND_CONV [WORD_XOR_MASKS]) THEN - ASM_REWRITE_TAC[] THEN DISCH_TAC THEN - - (*** The augmented H' = H + L_top ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (69--72) (69--72) THEN - MAP_EVERY ABBREV_TAC - [`q2 = bignum_of_wordlist[sum_s69;sum_s70]`; - `q3 = bignum_of_wordlist[sum_s71;sum_s72]`] THEN - SUBGOAL_THEN - `2 EXP 128 * q3 + q2 = - bignum_of_wordlist [x_2;x_3] * bignum_of_wordlist[y_2;y_3] + q1` - ASSUME_TAC THENL - [MAP_EVERY EXPAND_TAC ["q1"; "q2"; "q3"] THEN - MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN - REPEAT(CONJ_TAC THENL - [CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; ALL_TAC]) THEN - FIRST_X_ASSUM(fun th -> GEN_REWRITE_TAC - (LAND_CONV o LAND_CONV) [SYM th]) THEN - MAP_EVERY EXPAND_TAC ["q23"] THEN - REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ALL_TAC] THEN - - (*** Third nested block multiplying the absolute differences ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [73;75;80;81;85;87;88;89;92;94;95] (73--95) THEN - RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN - SUBGOAL_THEN - `&xd * &yd:real = - &(bignum_of_wordlist[mullo_s73; sum_s92; sum_s94; sum_s95])` - SUBST_ALL_TAC THENL - [MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - KARATSUBA12_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN - DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN - - (*** The rest of the basic 4x4->8 multiply computation and its proof ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [96;97;98;99;100;101;104;106;108;110;111;112] (96--112) THEN - MAP_EVERY ABBREV_TAC - [`l = bignum_of_wordlist[mullo_s3; sum_s22; sum_s104; sum_s106]`; - `h = bignum_of_wordlist[sum_s108; sum_s110; sum_s111; sum_s112]`] THEN - SUBGOAL_THEN `2 EXP 256 * h + l = m * n` (SUBST1_TAC o SYM) THENL - [DISCARD_STATE_TAC "s112" THEN MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`512`; `&0:real`] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL - [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN BOUNDER_TAC[]; - REWRITE_TAC[INTEGER_CLOSED]] THEN - SUBGOAL_THEN - `&m * &n:real = - (&1 + &2 pow 128) * (&q0 + &2 pow 128 * &q2 + &2 pow 256 * &q3) + - &2 pow 128 * - (&(bignum_of_wordlist [x_2; x_3]) - - &(bignum_of_wordlist [x_0; x_1])) * - (&(bignum_of_wordlist [y_0; y_1]) - - &(bignum_of_wordlist [y_2; y_3]))` - SUBST1_TAC THENL - [MAP_EVERY UNDISCH_TAC - [`2 EXP 128 * q1 + q0 = - bignum_of_wordlist[x_0; x_1] * bignum_of_wordlist[y_0; y_1]`; - `2 EXP 128 * q3 + q2 = - bignum_of_wordlist[x_2; x_3] * bignum_of_wordlist[y_2; y_3] + - q1`] THEN - MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - CONV_TAC REAL_RING; - ASM_REWRITE_TAC[]] THEN - MAP_EVERY EXPAND_TAC ["h"; "l"; "q0"; "q2"; "q3"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - POP_ASSUM_LIST(K ALL_TAC) THEN - REWRITE_TAC[WORD_XOR_MASK] THEN COND_CASES_TAC THEN - ASM_REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN - CONV_TAC WORD_REDUCE_CONV THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[BITVAL_CLAUSES] THEN DISCH_TAC THEN - FIRST_ASSUM(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** The initial modular reduction of the high part ***) - - REWRITE_TAC[CONG] THEN - SUBGOAL_THEN - `(2 EXP 256 * h + l) MOD p_25519 = (38 * h + l) MOD p_25519` - SUBST1_TAC THENL - [ONCE_REWRITE_TAC[GSYM MOD_ADD_MOD] THEN - ONCE_REWRITE_TAC[GSYM MOD_MULT_LMOD] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV; - ALL_TAC] THEN - - (*** Instantiate the quotient approximation lemma ***) - - MP_TAC(SPECL [`h:num`; `l:num`] p25519redlemma32) THEN ANTS_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - LET_TAC THEN STRIP_TAC] THEN - - (*** The somewhat fiddly reduction with 32-bit operations etc. ***) - - ARM_STEPS_TAC CURVE25519_X25519_EXEC (113--137) THEN - - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM MP_TAC) - [`u0 = read X7 s137`; - `u1 = read X8 s137`; - `u2 = read X9 s137`; - `u3 = read X10 s137`; - `u4 = read X11 s137`; - `u5 = read X12 s137`; - `u6 = read X13 s137`; - `u7 = read X14 s137`] THEN - REWRITE_TAC[GSYM IMP_CONJ_ALT] THEN - GEN_REWRITE_TAC (LAND_CONV o TOP_DEPTH_CONV) - [word_add; modular; ADD_CLAUSES; VAL_WORD; VAL_WORD_ZX_GEN; - VAL_WORD_USHR; DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN] THEN - REWRITE_TAC[DIV_MOD; GSYM EXP_ADD] THEN - CONV_TAC(DEPTH_CONV NUM_ADD_CONV) THEN - CONV_TAC(DEPTH_CONV NUM_MIN_CONV) THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `n < 2 EXP 64 ==> n MOD 2 EXP 32 * 38 < 2 EXP 64`] THEN - STRIP_TAC THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC [142;144;146;150] (138--152) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - - SUBGOAL_THEN `word_ushr u7 31:int64 = word q` SUBST_ALL_TAC THENL - [REWRITE_TAC[GSYM VAL_EQ; VAL_WORD; VAL_WORD_USHR] THEN - ASM_SIMP_TAC[DIMINDEX_64; MOD_LT] THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s106:int64) DIV 2 EXP 32 + - val(sum_s112:int64) DIV 2 EXP 32 * 38):int64 = u7`)) THEN - MAP_EVERY EXPAND_TAC ["q"; "l"; "h"] THEN - REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[VAL_WORD; ARITH_RULE `a + b * 38 = 38 * b + a`] THEN - MATCH_MP_TAC MOD_LT THEN REWRITE_TAC[DIMINDEX_64] THEN - REWRITE_TAC[GSYM VAL_WORD_USHR] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - ALL_TAC] THEN - SUBGOAL_THEN - `&(val(word_add (u0:int64) - (word(0 + 19 * val((word_zx:int64->int32)(word q)))))):real = - &(val u0) + &19 * &q` - SUBST_ALL_TAC THENL - [REWRITE_TAC[REAL_OF_NUM_CLAUSES; VAL_WORD_ADD; VAL_WORD; VAL_WORD_ZX_GEN; - DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN; ADD_CLAUSES] THEN - ASM_SIMP_TAC[ARITH_RULE `q <= 77 ==> q < 2 EXP MIN 64 32`; MOD_LT] THEN - CONV_TAC MOD_DOWN_CONV THEN - MATCH_MP_TAC MOD_LT THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s108:int64) MOD 2 EXP 32 * 38 + - val(mullo_s3:int64) MOD 2 EXP 32):int64 = u0`)) THEN - MATCH_MP_TAC(ARITH_RULE - `w <= 2 EXP 63 /\ q <= 77 ==> w + 19 * q < 2 EXP 64`) THEN - CONJ_TAC THENL [MATCH_MP_TAC VAL_WORD_LE; FIRST_ASSUM ACCEPT_TAC] THEN - ARITH_TAC; - ALL_TAC] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - REWRITE_TAC[REAL_VAL_WORD_XOR; WORD_AND_POW2_BITVAL; - REWRITE_RULE[DIMINDEX_64; NUM_REDUCE_CONV `64 - 1`] - (ISPEC `x:int64` WORD_SHL_LSB)] THEN - REWRITE_TAC[VAL_WORD; DIMINDEX_64; DIVMOD_63_64] THEN - SIMP_TAC[MOD_LT; BITVAL_BOUND_ALT; GSYM REAL_OF_NUM_CLAUSES] THEN - ASM_SIMP_TAC[GSYM VAL_MOD_2; VAL_WORD; DIMINDEX_64; MOD_LT] THEN - STRIP_TAC THEN - - REWRITE_TAC[GSYM CONG; REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[num_congruent; GSYM INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(MESON[] - `!q. (ca - q * p == ca) (mod p) /\ - (&0 <= ca - q * p /\ ca - q * p < p2) /\ - (&0 <= ca - q * p /\ ca - q * p < p2 ==> x = ca - q * p) - ==> x:int < p2 /\ (x == ca) (mod p)`) THEN - EXISTS_TAC `&q:int` THEN - CONJ_TAC THENL [CONV_TAC INTEGER_RULE; ALL_TAC] THEN - CONJ_TAC THENL - [MAP_EVERY UNDISCH_TAC - [`(q + 1) * p_25519 <= (38 * h + l) + p_25519`; - `38 * h + l < (q + 1) * p_25519 + p_25519`] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN INT_ARITH_TAC; - STRIP_TAC] THEN - MATCH_MP_TAC INT_CONG_IMP_EQ THEN EXISTS_TAC `(&2:int) pow 256` THEN - CONJ_TAC THENL - [FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INT_ARITH - `y:int < p ==> &0 <= y /\ &0 <= p /\ p < e /\ &0 <= x /\ x < e - ==> abs(x - y) < e`)) THEN - ASM_REWRITE_TAC[] THEN - REWRITE_TAC[INT_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - ALL_TAC] THEN - - REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN - SUBGOAL_THEN - `38 * h + l = - bignum_of_wordlist[u0;u1;u2;u3] + - 2 EXP 32 * bignum_of_wordlist[u4;u5;u6;u7]` - SUBST1_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o - check (can (term_match [] `word x = n`) o concl))) THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD; DIMINDEX_64] THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `m < 2 EXP 64 /\ n < 2 EXP 64 - ==> m DIV 2 EXP 32 + n DIV 2 EXP 32 * 38 < 2 EXP 64`; - ARITH_RULE `m MOD 2 EXP 32 * 38 + n MOD 2 EXP 32 < 2 EXP 64`] THEN - ARITH_TAC; - ALL_TAC] THEN - SUBGOAL_THEN - `2 EXP 32 * bignum_of_wordlist [u4; u5; u6; u7] = - bignum_of_wordlist - [word_shl u4 32; - word_subword ((word_join:int64->int64->int128) u5 u4) (32,64); - word_subword ((word_join:int64->int64->int128) u6 u5) (32,64); - word_subword ((word_join:int64->int64->int128) u7 u6) (32,64); - word_ushr u7 32]` - SUBST1_TAC THENL - [REWRITE_TAC[val_def; DIMINDEX_64; bignum_of_wordlist] THEN - REWRITE_TAC[ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN - REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN - REWRITE_TAC[BIT_WORD_JOIN; BIT_WORD_USHR; BIT_WORD_SUBWORD; - BIT_WORD_SHL; DIMINDEX_64; DIMINDEX_128] THEN - CONV_TAC NUM_REDUCE_CONV THEN - CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN - CONV_TAC NUM_REDUCE_CONV THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - ONCE_REWRITE_TAC[BIT_GUARD] THEN REWRITE_TAC[DIMINDEX_64] THEN - CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[BITVAL_CLAUSES] THEN - ARITH_TAC; - ALL_TAC] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - SIMP_TAC[REAL_INT_CONGRUENCE; INT_POW_EQ_0; INT_OF_NUM_EQ; ARITH_EQ] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; - int_mul_th; int_pow_th] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of sqr_4. *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_SQR_4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_mc 130 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1. - !n. - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x571c) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = n) - (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s - < 2 * p_25519 /\ - (read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s == - n EXP 2) - (mod p_25519)) - (MAYCHANGE [PC; X2; X3; X4; X5; X6; X7; X8; X9; - X10; X11; X12; X13; X14; X15; X16] ,, - MAYCHANGE - [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - - (*** The initial squaring block, very similar to bignum_sqr_4_8 ***) - (*** First of all, squaring the lower half ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [7;9;14;16;18;19;20;21;22;23;24] (1--24) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; DIVMOD_33_31; VAL_WORD_USHR; - VAL_WORD_SHL; DIMINDEX_64]) THEN - SUBGOAL_THEN - `bignum_of_wordlist[n_0; n_1] EXP 2 = - bignum_of_wordlist[sum_s7; sum_s22; sum_s23; sum_s24]` - ASSUME_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`n_0:int64`; `n_1:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - RULE_ASSUM_TAC(CONV_RULE NUM_REDUCE_CONV) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_ARITH_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** Squaring the upper half ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [29;31;36;38;40;41;42;43;44;45;46] (25--46) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; DIVMOD_33_31; VAL_WORD_USHR; - VAL_WORD_SHL; DIMINDEX_64]) THEN - SUBGOAL_THEN - `bignum_of_wordlist[n_2; n_3] EXP 2 = - bignum_of_wordlist[sum_s29; sum_s44; sum_s45; sum_s46]` - ASSUME_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`n_2:int64`; `n_3:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - RULE_ASSUM_TAC(CONV_RULE NUM_REDUCE_CONV) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_ARITH_TAC; + ARITH_RULE `~(a:num < b) ==> b <= a`] THEN + REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + CONJ_TAC THEN BOUNDER_TAC[]; + ALL_TAC] THEN + MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN + REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + CONJ_TAC THENL [BOUNDER_TAC[]; REWRITE_TAC[INTEGER_CLOSED]]) THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN + ASM_REWRITE_TAC[WORD_XOR_MASK] THEN + REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN + DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - (*** Absolute difference computation ***) + (*** Clean up the overall sign ***) - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC [47;48;51;53] (47--53) THEN - RULE_ASSUM_TAC(REWRITE_RULE[COND_SWAP; WORD_UNMASK_64]) THEN - SUBGOAL_THEN - `abs(&(bignum_of_wordlist[n_0;n_1]) - - &(bignum_of_wordlist[n_2;n_3])):real = - &(bignum_of_wordlist[sum_s51;sum_s53])` - ASSUME_TAC THENL - [MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`128`; `&0:real`] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - BOUNDER_TAC[]; - ALL_TAC]) THEN - CONJ_TAC THENL [REAL_INTEGER_TAC; ALL_TAC] THEN - REWRITE_TAC[real_abs; REAL_SUB_LE; REAL_OF_NUM_LE] THEN - SUBGOAL_THEN - `bignum_of_wordlist [n_2; n_3] <= bignum_of_wordlist [n_0; n_1] <=> - ~carry_s48` - SUBST1_TAC THENL - [REWRITE_TAC[GSYM NOT_LT] THEN AP_TERM_TAC THEN - CONV_TAC SYM_CONV THEN MATCH_MP_TAC FLAG_FROM_CARRY_LT THEN - EXISTS_TAC `128` THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN BOUNDER_TAC[]; - REWRITE_TAC[COND_SWAP] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - REWRITE_TAC[WORD_XOR_MASK] THEN COND_CASES_TAC THEN - ASM_REWRITE_TAC[BITVAL_CLAUSES; REAL_VAL_WORD_NOT] THEN - REWRITE_TAC[BITVAL_CLAUSES; DIMINDEX_64; VAL_WORD_BITVAL] THEN - DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC]; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN + FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE RAND_CONV [WORD_XOR_MASKS]) THEN + ASM_REWRITE_TAC[] THEN DISCH_TAC THEN - (*** The augmented H' = H + L_top computation ***) + (*** The augmented H' = H + L_top ***) - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (54--57) (54--57) THEN + ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (69--72) (69--72) THEN + MAP_EVERY ABBREV_TAC + [`q2 = bignum_of_wordlist[sum_s69;sum_s70]`; + `q3 = bignum_of_wordlist[sum_s71;sum_s72]`] THEN SUBGOAL_THEN - `&(bignum_of_wordlist[sum_s29; sum_s44; sum_s45; sum_s46]):real = - &(bignum_of_wordlist[sum_s54; sum_s55; sum_s56; sum_s57]) - - &(bignum_of_wordlist[sum_s23; sum_s24])` + `2 EXP 128 * q3 + q2 = + bignum_of_wordlist [x_2;x_3] * bignum_of_wordlist[y_2;y_3] + q1` ASSUME_TAC THENL - [REWRITE_TAC[REAL_EQ_SUB_LADD] THEN - FIRST_ASSUM(fun th -> GEN_REWRITE_TAC - (LAND_CONV o LAND_CONV o RAND_CONV) [SYM th]) THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - BOUNDER_TAC[]; - ALL_TAC]) THEN - CONJ_TAC THENL [REAL_INTEGER_TAC; ALL_TAC] THEN - ASM_REWRITE_TAC[] THEN + [MAP_EVERY EXPAND_TAC ["q1"; "q2"; "q3"] THEN + MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN + REPEAT(CONJ_TAC THENL + [CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; ALL_TAC]) THEN + FIRST_X_ASSUM(fun th -> GEN_REWRITE_TAC + (LAND_CONV o LAND_CONV) [SYM th]) THEN + MAP_EVERY EXPAND_TAC ["q23"] THEN + REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN + ALL_TAC] THEN - (*** Squaring the absolute difference ***) + (*** Third nested block multiplying the absolute differences ***) ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [62;64;69;71;73;74;75;76;77;78;79] (58--79) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; DIVMOD_33_31; VAL_WORD_USHR; - VAL_WORD_SHL; DIMINDEX_64]) THEN + [73;75;80;81;85;87;88;89;92;94;95] (73--95) THEN + RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN SUBGOAL_THEN - `bignum_of_wordlist[sum_s51;sum_s53] EXP 2 = - bignum_of_wordlist[sum_s62; sum_s77; sum_s78; sum_s79]` - ASSUME_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`sum_s51:int64`; `sum_s53:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - RULE_ASSUM_TAC(CONV_RULE NUM_REDUCE_CONV) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_ARITH_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** The overall Karatsuba composition to get the full square ***) + `&xd * &yd:real = + &(bignum_of_wordlist[mullo_s73; sum_s92; sum_s94; sum_s95])` + SUBST_ALL_TAC THENL + [MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN + REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + KARATSUBA12_TAC; + ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN + DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (80--90) (80--90) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [COND_SWAP; WORD_UNMASK_64; REAL_BITVAL_NOT; DIMINDEX_64; - GSYM WORD_NOT_MASK; REAL_VAL_WORD_NOT;REAL_VAL_WORD_MASK]) THEN + (*** The rest of the basic 4x4->8 multiply computation and its proof ***) + ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC + [96;97;98;99;100;101;104;106;108;110;111;112] (96--112) THEN MAP_EVERY ABBREV_TAC - [`l = bignum_of_wordlist[sum_s7; sum_s22; sum_s85; sum_s86]`; - `h = bignum_of_wordlist[sum_s87; sum_s88; sum_s89; sum_s90]`] THEN - SUBGOAL_THEN `2 EXP 256 * h + l = n EXP 2` (SUBST1_TAC o SYM) THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"; "n"] THEN + [`l = bignum_of_wordlist[mullo_s3; sum_s22; sum_s104; sum_s106]`; + `h = bignum_of_wordlist[sum_s108; sum_s110; sum_s111; sum_s112]`] THEN + SUBGOAL_THEN `2 EXP 256 * h + l = m * n` (SUBST1_TAC o SYM) THENL + [DISCARD_STATE_TAC "s112" THEN MAP_EVERY EXPAND_TAC ["h"; "l"] THEN REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN MAP_EVERY EXISTS_TAC [`512`; `&0:real`] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - BOUNDER_TAC[]; - ALL_TAC]) THEN - CONJ_TAC THENL [REAL_INTEGER_TAC; ALL_TAC] THEN - REWRITE_TAC[BIGNUM_OF_WORDLIST_SPLIT_RULE(2,2)] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; REAL_ARITH - `(l + &2 pow 128 * h) pow 2 = - &2 pow 256 * h pow 2 + l pow 2 + - &2 pow 128 * (h pow 2 + l pow 2 - (l - h) pow 2)`] THEN - ONCE_REWRITE_TAC[GSYM REAL_POW2_ABS] THEN ASM_REWRITE_TAC[] THEN - ASM_REWRITE_TAC[REAL_ABS_NUM; REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL + [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN BOUNDER_TAC[]; + REWRITE_TAC[INTEGER_CLOSED]] THEN + SUBGOAL_THEN + `&m * &n:real = + (&1 + &2 pow 128) * (&q0 + &2 pow 128 * &q2 + &2 pow 256 * &q3) + + &2 pow 128 * + (&(bignum_of_wordlist [x_2; x_3]) - + &(bignum_of_wordlist [x_0; x_1])) * + (&(bignum_of_wordlist [y_0; y_1]) - + &(bignum_of_wordlist [y_2; y_3]))` + SUBST1_TAC THENL + [MAP_EVERY UNDISCH_TAC + [`2 EXP 128 * q1 + q0 = + bignum_of_wordlist[x_0; x_1] * bignum_of_wordlist[y_0; y_1]`; + `2 EXP 128 * q3 + q2 = + bignum_of_wordlist[x_2; x_3] * bignum_of_wordlist[y_2; y_3] + + q1`] THEN + MAP_EVERY EXPAND_TAC ["m"; "n"] THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN + CONV_TAC REAL_RING; + ASM_REWRITE_TAC[]] THEN + MAP_EVERY EXPAND_TAC ["h"; "l"; "q0"; "q2"; "q3"] THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN + POP_ASSUM_LIST(K ALL_TAC) THEN + REWRITE_TAC[WORD_XOR_MASK] THEN COND_CASES_TAC THEN + ASM_REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN + CONV_TAC WORD_REDUCE_CONV THEN CONV_TAC NUM_REDUCE_CONV THEN + REWRITE_TAC[BITVAL_CLAUSES] THEN DISCH_TAC THEN + FIRST_ASSUM(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN (*** The initial modular reduction of the high part ***) - REWRITE_TAC[CONG] THEN SUBGOAL_THEN `(2 EXP 256 * h + l) MOD p_25519 = (38 * h + l) MOD p_25519` SUBST1_TAC THENL @@ -6856,16 +3683,17 @@ let LOCAL_SQR_4_TAC = (*** The somewhat fiddly reduction with 32-bit operations etc. ***) - ARM_STEPS_TAC CURVE25519_X25519_EXEC (91--115) THEN + ARM_STEPS_TAC CURVE25519_X25519_EXEC (113--137) THEN + MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM MP_TAC) - [`u0 = read X2 s115`; - `u1 = read X3 s115`; - `u2 = read X4 s115`; - `u3 = read X5 s115`; - `u4 = read X6 s115`; - `u5 = read X7 s115`; - `u6 = read X8 s115`; - `u7 = read X9 s115`] THEN + [`u0 = read X7 s137`; + `u1 = read X8 s137`; + `u2 = read X9 s137`; + `u3 = read X10 s137`; + `u4 = read X11 s137`; + `u5 = read X12 s137`; + `u6 = read X13 s137`; + `u7 = read X14 s137`] THEN REWRITE_TAC[GSYM IMP_CONJ_ALT] THEN GEN_REWRITE_TAC (LAND_CONV o TOP_DEPTH_CONV) [word_add; modular; ADD_CLAUSES; VAL_WORD; VAL_WORD_ZX_GEN; @@ -6876,15 +3704,12 @@ let LOCAL_SQR_4_TAC = SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE `n < 2 EXP 64 ==> n MOD 2 EXP 32 * 38 < 2 EXP 64`] THEN STRIP_TAC THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC [120;122;124;128] (116--130) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - + ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC [142;144;146;150] (138--150) THEN SUBGOAL_THEN `word_ushr u7 31:int64 = word q` SUBST_ALL_TAC THENL [REWRITE_TAC[GSYM VAL_EQ; VAL_WORD; VAL_WORD_USHR] THEN ASM_SIMP_TAC[DIMINDEX_64; MOD_LT] THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s86:int64) DIV 2 EXP 32 + - val(sum_s90:int64) DIV 2 EXP 32 * 38):int64 = u7`)) THEN + `word(val(sum_s106:int64) DIV 2 EXP 32 + + val(sum_s112:int64) DIV 2 EXP 32 * 38):int64 = u7`)) THEN MAP_EVERY EXPAND_TAC ["q"; "l"; "h"] THEN REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN @@ -6896,18 +3721,19 @@ let LOCAL_SQR_4_TAC = ALL_TAC] THEN SUBGOAL_THEN `&(val(word_add (u0:int64) - (word(0 + 19 * val((word_zx:int64->int32)(word q)))))):real = - &(val u0) + &19 * &q` + (word(19 + 19 * val((word_zx:int64->int32)(word q)))))):real = + &(val u0) + &19 * (&q + &1)` SUBST_ALL_TAC THENL [REWRITE_TAC[REAL_OF_NUM_CLAUSES; VAL_WORD_ADD; VAL_WORD; VAL_WORD_ZX_GEN; - DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN; ADD_CLAUSES] THEN + DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN] THEN ASM_SIMP_TAC[ARITH_RULE `q <= 77 ==> q < 2 EXP MIN 64 32`; MOD_LT] THEN CONV_TAC MOD_DOWN_CONV THEN + REWRITE_TAC[ARITH_RULE `19 + 19 * q = 19 * (q + 1)`] THEN MATCH_MP_TAC MOD_LT THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s87:int64) MOD 2 EXP 32 * 38 + - val(sum_s7:int64) MOD 2 EXP 32):int64 = u0`)) THEN + `word(val(sum_s108:int64) MOD 2 EXP 32 * 38 + + val(mullo_s3:int64) MOD 2 EXP 32):int64 = u0`)) THEN MATCH_MP_TAC(ARITH_RULE - `w <= 2 EXP 63 /\ q <= 77 ==> w + 19 * q < 2 EXP 64`) THEN + `w <= 2 EXP 63 /\ q <= 77 ==> w + 19 * (q + 1) < 2 EXP 64`) THEN CONJ_TAC THENL [MATCH_MP_TAC VAL_WORD_LE; FIRST_ASSUM ACCEPT_TAC] THEN ARITH_TAC; ALL_TAC] THEN @@ -6919,530 +3745,385 @@ let LOCAL_SQR_4_TAC = SIMP_TAC[MOD_LT; BITVAL_BOUND_ALT; GSYM REAL_OF_NUM_CLAUSES] THEN ASM_SIMP_TAC[GSYM VAL_MOD_2; VAL_WORD; DIMINDEX_64; MOD_LT] THEN STRIP_TAC THEN - - REWRITE_TAC[GSYM CONG; REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[num_congruent; GSYM INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(MESON[] - `!q. (ca - q * p == ca) (mod p) /\ - (&0 <= ca - q * p /\ ca - q * p < p2) /\ - (&0 <= ca - q * p /\ ca - q * p < p2 ==> x = ca - q * p) - ==> x:int < p2 /\ (x == ca) (mod p)`) THEN - EXISTS_TAC `&q:int` THEN - CONJ_TAC THENL [CONV_TAC INTEGER_RULE; ALL_TAC] THEN - CONJ_TAC THENL - [MAP_EVERY UNDISCH_TAC - [`(q + 1) * p_25519 <= (38 * h + l) + p_25519`; - `38 * h + l < (q + 1) * p_25519 + p_25519`] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN INT_ARITH_TAC; - STRIP_TAC] THEN - MATCH_MP_TAC INT_CONG_IMP_EQ THEN EXISTS_TAC `(&2:int) pow 256` THEN - CONJ_TAC THENL - [FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INT_ARITH - `y:int < p ==> &0 <= y /\ &0 <= p /\ p < e /\ &0 <= x /\ x < e - ==> abs(x - y) < e`)) THEN - ASM_REWRITE_TAC[] THEN - REWRITE_TAC[INT_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - ALL_TAC] THEN - - REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN - SUBGOAL_THEN - `38 * h + l = - bignum_of_wordlist[u0;u1;u2;u3] + - 2 EXP 32 * bignum_of_wordlist[u4;u5;u6;u7]` - SUBST1_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o - check (can (term_match [] `word x = n`) o concl))) THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD; DIMINDEX_64] THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `m < 2 EXP 64 /\ n < 2 EXP 64 - ==> m DIV 2 EXP 32 + n DIV 2 EXP 32 * 38 < 2 EXP 64`; - ARITH_RULE `m MOD 2 EXP 32 * 38 + n MOD 2 EXP 32 < 2 EXP 64`] THEN - ARITH_TAC; - ALL_TAC] THEN - SUBGOAL_THEN - `2 EXP 32 * bignum_of_wordlist [u4; u5; u6; u7] = - bignum_of_wordlist - [word_shl u4 32; - word_subword ((word_join:int64->int64->int128) u5 u4) (32,64); - word_subword ((word_join:int64->int64->int128) u6 u5) (32,64); - word_subword ((word_join:int64->int64->int128) u7 u6) (32,64); - word_ushr u7 32]` - SUBST1_TAC THENL - [REWRITE_TAC[val_def; DIMINDEX_64; bignum_of_wordlist] THEN - REWRITE_TAC[ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN - REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN - REWRITE_TAC[BIT_WORD_JOIN; BIT_WORD_USHR; BIT_WORD_SUBWORD; - BIT_WORD_SHL; DIMINDEX_64; DIMINDEX_128] THEN - CONV_TAC NUM_REDUCE_CONV THEN - CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN - CONV_TAC NUM_REDUCE_CONV THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - ONCE_REWRITE_TAC[BIT_GUARD] THEN REWRITE_TAC[DIMINDEX_64] THEN - CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[BITVAL_CLAUSES] THEN - ARITH_TAC; - ALL_TAC] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - SIMP_TAC[REAL_INT_CONGRUENCE; INT_POW_EQ_0; INT_OF_NUM_EQ; ARITH_EQ] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; - int_mul_th; int_pow_th] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of add_twice4 (slightly sharper disjunctive hypothesis). *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_ADD_TWICE4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_mc 16 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x571c) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - (m < 2 * p_25519 \/ n < 2 * p_25519 - ==> (read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s == - m + n) (mod p_25519))) - (MAYCHANGE [PC; X3; X4; X5; X6; X7; X8; X9] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "m_" o lhand o concl) THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (1--8) (1--8) THEN - SUBGOAL_THEN `carry_s8 <=> 2 EXP 256 <= m + n` SUBST_ALL_TAC THENL - [MATCH_MP_TAC FLAG_FROM_CARRY_LE THEN EXISTS_TAC `256` THEN - MAP_EVERY EXPAND_TAC ["m"; "n"] THEN REWRITE_TAC[GSYM REAL_OF_NUM_ADD] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_MUL; GSYM REAL_OF_NUM_POW] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN BOUNDER_TAC[]; - ALL_TAC] THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (11--14) (9--16) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN DISCH_TAC THEN - REWRITE_TAC[num_congruent; GSYM INT_OF_NUM_ADD] THEN - MATCH_MP_TAC(MESON[INT_OF_NUM_LT] - `!x':int. (x' == a) (mod p) /\ x = x' - ==> (x:int == a) (mod p)`) THEN - EXISTS_TAC - `if 2 EXP 256 <= m + n then (&m + &n) - &2 * &p_25519:int else &m + &n` THEN - CONJ_TAC THENL [COND_CASES_TAC THEN CONV_TAC INTEGER_RULE; ALL_TAC] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - ONCE_REWRITE_TAC[int_eq] THEN ONCE_REWRITE_TAC[COND_RAND] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; int_mul_th] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL - [FIRST_X_ASSUM(MP_TAC o SPEC `2 EXP 256` o MATCH_MP (ARITH_RULE - `m < p \/ n < p - ==> !e:num. p < e /\ m < e /\ n < e ==> m + n < e + p`)) THEN - ANTS_TAC THENL - [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN REWRITE_TAC[p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN INT_ARITH_TAC]; - REWRITE_TAC[INTEGER_CLOSED]] THEN - RULE_ASSUM_TAC(REWRITE_RULE[SYM(NUM_EXP_CONV `2 EXP 256`)]) THEN - ABBREV_TAC `bb <=> 2 EXP 256 <= m + n` THEN MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[bignum_of_wordlist; p_25519; GSYM REAL_OF_NUM_CLAUSES] THEN - CONV_TAC NUM_REDUCE_CONV THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of sub_twice4 (slightly sharper hypothesis distinctions). *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_SUB_TWICE4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_mc 16 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x571c) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - (m < 2 * p_25519 /\ n < 2 * p_25519 - ==> read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s - < 2 * p_25519) /\ - (n < 2 * p_25519 - ==> (&(read(memory :> bytes - (word_add (read p3 t) (word n3),8 * 4)) s):int == - &m - &n) (mod (&p_25519)))) - (MAYCHANGE [PC; X3; X4; X5; X6; X7; X8] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "m_" o lhand o concl) THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (1--8) (1--8) THEN - SUBGOAL_THEN `carry_s8 <=> m < n` SUBST_ALL_TAC THENL - [MATCH_MP_TAC FLAG_FROM_CARRY_LT THEN EXISTS_TAC `256` THEN - MAP_EVERY EXPAND_TAC ["m"; "n"] THEN REWRITE_TAC[GSYM REAL_OF_NUM_ADD] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_MUL; GSYM REAL_OF_NUM_POW] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN BOUNDER_TAC[]; - ALL_TAC] THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (11--14) (9--16) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - MATCH_MP_TAC(MESON[INT_OF_NUM_LT] - `!x':int. (x' == &m - &n) (mod p) /\ - (m < p2 /\ n < p2 ==> x' < &p2) /\ - (n < p2 ==> &x = x') - ==> (m < p2 /\ n < p2 ==> x < p2) /\ - (n:num < p2 ==> (&x:int == &m - &n) (mod p))`) THEN - EXISTS_TAC `if m < n then &m - &n + &2 * &p_25519:int else &m - &n` THEN - REPEAT CONJ_TAC THENL - [COND_CASES_TAC THEN CONV_TAC INTEGER_RULE; - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN INT_ARITH_TAC; - DISCH_TAC] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - ONCE_REWRITE_TAC[int_eq] THEN ONCE_REWRITE_TAC[COND_RAND] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; int_mul_th] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL - [CONJ_TAC THENL - [POP_ASSUM MP_TAC THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN INT_ARITH_TAC; - SUBGOAL_THEN `m < 2 EXP 256` MP_TAC THENL - [EXPAND_TAC "m" THEN BOUNDER_TAC[]; - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; p_25519] THEN REAL_ARITH_TAC]]; - REWRITE_TAC[INTEGER_CLOSED]] THEN - ABBREV_TAC `bb <=> m:num < n` THEN MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[bignum_of_wordlist; p_25519; GSYM REAL_OF_NUM_CLAUSES] THEN - CONV_TAC NUM_REDUCE_CONV THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of cmadd_4 (actually there is only one, specific constant). *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_CMADD_4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_mc 32 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x571c) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read X1 s = word 121666 /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s < - 2 * p_25519 /\ - (read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s == - 121666 * m + n) (mod p_25519)) - (MAYCHANGE [PC; X3; X4; X5; X6; X7; X8; X9; X10; X11] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "m_" o lhand o concl) THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC - [3;4;5;6;11;12;13;14;16;17;19;20;21] (1--21) THEN - - RULE_ASSUM_TAC(CONV_RULE WORD_REDUCE_CONV) THEN ABBREV_TAC - `ca = bignum_of_wordlist[sum_s16; sum_s17; sum_s19; sum_s20; sum_s21]` THEN - SUBGOAL_THEN `121666 * m + n < 2 EXP 17 * 2 EXP 256` ASSUME_TAC THENL - [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN CONV_TAC NUM_REDUCE_CONV THEN - BOUNDER_TAC[]; - ALL_TAC] THEN - SUBGOAL_THEN `121666 * m + n = ca` SUBST_ALL_TAC THENL - [MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 320` THEN - REPEAT CONJ_TAC THENL - [UNDISCH_TAC `121666 * m + n < 2 EXP 17 * 2 EXP 256` THEN ARITH_TAC; - EXPAND_TAC "ca" THEN BOUNDER_TAC[]; - REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV] THEN - MAP_EVERY EXPAND_TAC ["m"; "n"; "ca"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN - RULE_ASSUM_TAC(REWRITE_RULE[REAL_BITVAL_NOT]) THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** Instantiate the quotient approximation lemma ***) - - MP_TAC(SPEC `ca:num` p25519weakredlemma) THEN ANTS_TAC THENL - [UNDISCH_TAC `ca < 2 EXP 17 * 2 EXP 256` THEN ARITH_TAC; - CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN STRIP_TAC] THEN - - (*** Quotient estimate computation ***) + `r = bignum_of_wordlist[sum_s142; sum_s144; sum_s146; sum_s150]` THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (22--24) (22--24) THEN - SUBGOAL_THEN `ca DIV 2 EXP 255 = val(sum_s24:int64)` - (fun th -> SUBST_ALL_TAC th THEN ASSUME_TAC th) - THENL - [FIRST_ASSUM(MP_TAC o MATCH_MP (ARITH_RULE - `ca < 2 EXP 17 * 2 EXP 256 - ==> ca DIV 2 EXP 192 DIV 2 EXP 63 < 2 EXP 59`)) THEN - EXPAND_TAC "ca" THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - DISCH_THEN(fun th -> - MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 64` THEN - CONJ_TAC THENL [MP_TAC th THEN ARITH_TAC; REWRITE_TAC[VAL_BOUND_64]]) THEN - REWRITE_TAC[ARITH_RULE `n DIV 2 EXP 63 = (2 * n) DIV 2 EXP 64`] THEN - SUBST1_TAC(SYM(BIGNUM_OF_WORDLIST_DIV_CONV - `bignum_of_wordlist [sum_s22; sum_s24] DIV 2 EXP 64`)) THEN - MATCH_MP_TAC CONG_DIV2 THEN - REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + SUBGOAL_THEN + `(&r:int == &2 pow 255 + &(38 * h + l) - (&q + &1) * &p_25519) + (mod (&2 pow 256))` + ASSUME_TAC THENL + [SUBGOAL_THEN + `38 * h + l = + bignum_of_wordlist[u0;u1;u2;u3] + + 2 EXP 32 * bignum_of_wordlist[u4;u5;u6;u7]` + SUBST1_TAC THENL + [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN + REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o + check (can (term_match [] `word x = n`) o concl))) THEN + REWRITE_TAC[bignum_of_wordlist; VAL_WORD; DIMINDEX_64] THEN + SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE + `m < 2 EXP 64 /\ n < 2 EXP 64 + ==> m DIV 2 EXP 32 + n DIV 2 EXP 32 * 38 < 2 EXP 64`; + ARITH_RULE `m MOD 2 EXP 32 * 38 + n MOD 2 EXP 32 < 2 EXP 64`] THEN + ARITH_TAC; + ALL_TAC] THEN + SUBGOAL_THEN + `2 EXP 32 * bignum_of_wordlist [u4; u5; u6; u7] = + bignum_of_wordlist + [word_shl u4 32; + word_subword ((word_join:int64->int64->int128) u5 u4) (32,64); + word_subword ((word_join:int64->int64->int128) u6 u5) (32,64); + word_subword ((word_join:int64->int64->int128) u7 u6) (32,64); + word_ushr u7 32]` + SUBST1_TAC THENL + [REWRITE_TAC[val_def; DIMINDEX_64; bignum_of_wordlist] THEN + REWRITE_TAC[ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN + REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN + REWRITE_TAC[BIT_WORD_JOIN; BIT_WORD_USHR; BIT_WORD_SUBWORD; + BIT_WORD_SHL; DIMINDEX_64; DIMINDEX_128] THEN + CONV_TAC NUM_REDUCE_CONV THEN + CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN + CONV_TAC NUM_REDUCE_CONV THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN + ONCE_REWRITE_TAC[BIT_GUARD] THEN REWRITE_TAC[DIMINDEX_64] THEN + CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[BITVAL_CLAUSES] THEN + ARITH_TAC; + ALL_TAC] THEN + SIMP_TAC[REAL_INT_CONGRUENCE; INT_POW_EQ_0; INT_OF_NUM_EQ; ARITH_EQ] THEN + REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; + int_mul_th; int_pow_th] THEN + EXPAND_TAC "r" THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - ARM_STEPS_TAC CURVE25519_X25519_EXEC (25--26) THEN - ABBREV_TAC `qm:int64 = word(0 + val(sum_s24:int64) * 19)` THEN - SUBGOAL_THEN `&(val(qm:int64)):real = &19 * &(val(sum_s24:int64))` - ASSUME_TAC THENL - [EXPAND_TAC "qm" THEN REWRITE_TAC[ADD_CLAUSES] THEN - REWRITE_TAC[VAL_WORD; DIMINDEX_64; REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[MULT_SYM] THEN MATCH_MP_TAC MOD_LT THEN MAP_EVERY UNDISCH_TAC - [`val(sum_s24:int64) * p_25519 <= ca`; - `ca < 2 EXP 17 * 2 EXP 256`] THEN - REWRITE_TAC[p_25519] THEN ARITH_TAC; - ALL_TAC] THEN - (*** The rest of the computation ***) + (*** The final optional correction ***) - ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (27--30) (27--32) THEN + ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC (154--157) (151--160) THEN ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[GSYM CONG; num_congruent] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(MESON[] - `!q. (ca - q * p == ca) (mod p) /\ ca - q * p < p2 /\ x = ca - q * p - ==> x:int < p2 /\ (x == ca) (mod p)`) THEN - EXISTS_TAC `&(val(sum_s24:int64)):int` THEN - CONJ_TAC THENL [CONV_TAC INTEGER_RULE; ALL_TAC] THEN - MATCH_MP_TAC(TAUT `p /\ (p ==> q) ==> p /\ q`) THEN CONJ_TAC THENL - [REWRITE_TAC[INT_ARITH `x - y:int < z <=> x < y + z`] THEN - ASM_REWRITE_TAC[INT_OF_NUM_CLAUSES]; - DISCH_TAC] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - MATCH_MP_TAC INT_CONG_IMP_EQ THEN EXISTS_TAC `(&2:int) pow 256` THEN + REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN CONV_TAC SYM_CONV THEN + MATCH_MP_TAC EQUAL_FROM_CONGRUENT_MOD_MOD THEN + MAP_EVERY EXISTS_TAC + [`255`; + `(if r < 2 EXP 255 then &r - &19 else &r - &2 pow 255):real`] THEN + CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN + ASM_REWRITE_TAC[] THEN DISCARD_STATE_TAC "s160" THEN + CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN + REPLICATE_TAC 2 + (CONJ_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC]) THEN CONJ_TAC THENL - [FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INT_ARITH - `y:int < p ==> &0 <= y /\ &0 <= p /\ p < e /\ &0 <= x /\ x < e - ==> abs(x - y) < e`)) THEN - ASM_REWRITE_TAC[INT_SUB_LE; INT_OF_NUM_CLAUSES; LE_0] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV THEN - BOUNDER_TAC[]; - ALL_TAC] THEN - REWRITE_TAC[INTEGER_RULE - `(x:int == y - z) (mod p) <=> (x + z == y) (mod p)`] THEN - REWRITE_TAC[INT_OF_NUM_CLAUSES; GSYM num_congruent] THEN - REWRITE_TAC[REAL_CONGRUENCE; p_25519] THEN CONV_TAC NUM_REDUCE_CONV THEN - EXPAND_TAC "ca" THEN - REWRITE_TAC[p_25519; bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[SYM(NUM_REDUCE_CONV `2 EXP 63 - 1`)] THEN - REWRITE_TAC[VAL_WORD_AND_MASK_WORD] THEN - UNDISCH_THEN `ca DIV 2 EXP 255 = val(sum_s24:int64)` (SUBST1_TAC o SYM) THEN - EXPAND_TAC "ca" THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - REWRITE_TAC[bignum_of_wordlist; ARITH_RULE - `(l + 2 EXP 64 * h) DIV 2 EXP 63 = l DIV 2 EXP 63 + 2 * h`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV] THEN - REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of mux_4. *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_MUX_4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_mc 10 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !b. read ZF t = b - ==> - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x571c) (word_add (read p3 t) (word n3),8 * 4) /\ - nonoverlapping (stackpointer:int64,320) (res,32) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read ZF s = b /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s = - (if b then n else m)) - (MAYCHANGE [PC; X0; X1; X2; X3] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)])` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "m_" o lhand o concl) THEN - ARM_STEPS_TAC CURVE25519_X25519_EXEC (1--10) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC(LAND_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[COND_SWAP] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[]);; + [REWRITE_TAC[ARITH_RULE `r < 2 EXP 255 <=> r DIV 2 EXP 192 < 2 EXP 63`] THEN + EXPAND_TAC "r" THEN + CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN + REWRITE_TAC[SYM(NUM_REDUCE_CONV `2 EXP 63 - 1`)] THEN + REWRITE_TAC[bignum_of_wordlist; VAL_WORD_AND_MASK_WORD] THEN + ABBREV_TAC `bb <=> val(sum_s150:int64) < 2 EXP 63` THEN + SUBGOAL_THEN + `ival(word_and sum_s150 (word 9223372036854775808):int64) < &0 <=> ~bb` + SUBST_ALL_TAC THENL + [REWRITE_TAC[GSYM MSB_IVAL; BIT_WORD_AND] THEN + REWRITE_TAC[MSB_VAL] THEN REWRITE_TAC[DIMINDEX_64] THEN + CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN + EXPAND_TAC "bb" THEN ARITH_TAC; + RULE_ASSUM_TAC(REWRITE_RULE[]) THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN + COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN + CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC]; + FIRST_ASSUM(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ] + endp25519redlemma)) THEN + ANTS_TAC THENL + [REWRITE_TAC[INT_ARITH `--p:int <= x - y <=> y <= x + p`] THEN + REWRITE_TAC[INT_ARITH `x - y:int < p <=> x < y + p`] THEN + ASM_REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN + EXPAND_TAC "r" THEN BOUNDER_TAC[]; + REWRITE_TAC[INT_ARITH `x - q * p:int = --q * p + x`] THEN + REWRITE_TAC[INT_REM_MUL_ADD] THEN + REWRITE_TAC[int_eq; int_of_num_th; INT_OF_NUM_REM] THEN + DISCH_THEN SUBST1_TAC THEN COND_CASES_TAC THEN + ASM_REWRITE_TAC[int_of_num_th; int_sub_th; int_pow_th]]]);; (* ------------------------------------------------------------------------- *) -(* Instances of modular inverse inlining *) +(* Inlined modular inverse proof. *) (* ------------------------------------------------------------------------- *) let LOCAL_MODINV_TAC = ARM_SUBROUTINE_SIM_TAC - (curve25519_x25519_mc,CURVE25519_X25519_EXEC,0x43f8, + (curve25519_x25519_mc,CURVE25519_X25519_EXEC,0x1224, (GEN_REWRITE_CONV RAND_CONV [bignum_inv_p25519_mc] THENC TRIM_LIST_CONV) `TRIM_LIST (12,16) bignum_inv_p25519_mc`, CORE_INV_P25519_CORRECT) [`read X0 s`; `read X1 s`; `read (memory :> bytes(read X1 s,8 * 4)) s`; - `pc + 0x43f8`; `stackpointer:int64`];; + `pc + 0x1224`; `stackpointer:int64`];; (* ------------------------------------------------------------------------- *) -(* Overall point operation proof. *) +(* The swapping-based Montgomery ladder more abstractly. *) (* ------------------------------------------------------------------------- *) -let nintlemma = prove - (`&(num_of_int(x rem &p_25519)) = x rem &p_25519`, - MATCH_MP_TAC INT_OF_NUM_OF_INT THEN MATCH_MP_TAC INT_REM_POS THEN - REWRITE_TAC[INT_OF_NUM_EQ; p_25519] THEN CONV_TAC NUM_REDUCE_CONV);; - -let lemma = prove - (`X = num_of_int(x rem &p_25519) ==> X < p_25519 /\ &X = x rem &p_25519`, - DISCH_THEN SUBST1_TAC THEN - REWRITE_TAC[GSYM INT_OF_NUM_LT; nintlemma; INT_LT_REM_EQ] THEN - REWRITE_TAC[INT_OF_NUM_LT; p_25519] THEN CONV_TAC NUM_REDUCE_CONV);; - -let lemma_double = prove - (`P IN group_carrier (curve25519x_group(f:(int#int) ring)) /\ - montgomery_xz f (group_pow (curve25519x_group f) P n) (x,y) - ==> field f /\ ring_char f = p_25519 - ==> montgomery_xz f - (group_pow (curve25519x_group f) P (2 * n)) - (montgomery_xzdouble (curve25519x f) (x,y))`, - REWRITE_TAC[curve25519x; curve25519x_group] THEN REPEAT STRIP_TAC THEN - MATCH_MP_TAC MONTGOMERY_XZDOUBLE_GROUP THEN ASM_REWRITE_TAC[] THEN - ASM_SIMP_TAC[GSYM curve25519x; MONTGOMERY_NONSINGULAR_CURVE25519X] THEN - REWRITE_TAC[A_25519; p_25519; RING_OF_NUM] THEN - CONV_TAC NUM_REDUCE_CONV);; - -let lemma_double_base = prove - (`P IN group_carrier (curve25519x_group(f:(int#int) ring)) /\ - montgomery_xz f P (x,y) - ==> field f /\ ring_char f = p_25519 - ==> montgomery_xz f - (group_pow (curve25519x_group f) P 2) - (montgomery_xzdouble (curve25519x f) (x,y))`, - SUBST1_TAC(ARITH_RULE `2 = 2 * 1`) THEN - REWRITE_TAC[curve25519x; curve25519x_group] THEN REPEAT STRIP_TAC THEN - MATCH_MP_TAC MONTGOMERY_XZDOUBLE_GROUP THEN ASM_REWRITE_TAC[] THEN - ASM_SIMP_TAC[GROUP_POW_1] THEN +let flipladder = define + `flipladder x n 0 = ((&1,&0),(&x rem &p_25519,&1)) /\ + flipladder x n (i + 1) = + let (x2,z2),(x3,z3) = flipladder x n i in + montgomery_xzdouble curve25519 + (if ODD(n DIV 2 EXP (255 - (i + 1))) <=> ODD(n DIV 2 EXP (255 - i)) + then (x2,z2) else (x3,z3)), + montgomery_xzdiffadd curve25519 (&x,&1) (x2,z2) (x3,z3)`;; + +let ladder_x2 = define + `ladder_x2 x n i = FST(FST(flipladder x n (255 - i)))`;; + +let ladder_z2 = define + `ladder_z2 x n i = SND(FST(flipladder x n (255 - i)))`;; + +let ladder_x3 = define + `ladder_x3 x n i = FST(SND(flipladder x n (255 - i)))`;; + +let ladder_z3 = define + `ladder_z3 x n i = SND(SND(flipladder x n (255 - i)))`;; + +let deproject = define + `deproject (x,z) = + (x * (if p_25519 divides z then 0 else inverse_mod p_25519 z)) + MOD p_25519`;; + +let curve25519x_represents = define + `curve25519x_represents (f:A ring) P n (X,Z) <=> + P IN group_carrier(montgomery_group (curve25519x f)) /\ + montgomery_xz f (group_pow (montgomery_group (curve25519x f)) P n) + (ring_of_int f X,ring_of_int f Z)`;; + +let CURVE25519X_REPRESENTS_DOUBLE = prove + (`!(f:A ring) P n Q. + field f /\ ring_char f = p_25519 /\ + curve25519x_represents f P n Q + ==> curve25519x_represents f P (2 * n) + (montgomery_xzdouble curve25519 Q)`, + REWRITE_TAC[FORALL_PAIR_THM; curve25519x_represents] THEN + MAP_EVERY X_GEN_TAC + [`f:A ring`; `P:(A#A)option`; `n:num`; `X:int`; `Z:int`] THEN + STRIP_TAC THEN GEN_REWRITE_TAC RAND_CONV [GSYM PAIR] THEN + PURE_REWRITE_TAC[curve25519x_represents] THEN ASM_REWRITE_TAC[] THEN + MP_TAC(ISPECL + [`f:A ring`; `ring_of_num (f:A ring) A_25519`; `ring_of_num (f:A ring) 1`; + `P:(A#A)option`; `n:num`; `ring_of_int f X:A,ring_of_int f Z`] + MONTGOMERY_XZDOUBLE_GROUP) THEN ASM_SIMP_TAC[GSYM curve25519x; MONTGOMERY_NONSINGULAR_CURVE25519X] THEN - REWRITE_TAC[A_25519; p_25519; RING_OF_NUM] THEN - CONV_TAC NUM_REDUCE_CONV);; - -let lemma_diffadd1 = prove - (`field f /\ ring_char f = p_25519 /\ - ~(x:(int#int) = ring_0 f) /\ - P IN group_carrier (curve25519x_group f) /\ - montgomery_xz f P (x,ring_of_num f 1) /\ - montgomery_xz f - (group_pow (curve25519x_group f) P (n + 1)) (xn,zn) /\ - montgomery_xz f - (group_pow (curve25519x_group f) P n) (xm,zm) - ==> montgomery_xz f - (group_pow (curve25519x_group f) P (2 * n + 1)) - (montgomery_xzdiffadd (curve25519x f) (x,ring_of_num f 1) - (xn,zn) (xm,zm))`, - REWRITE_TAC[curve25519x; curve25519x_group] THEN REPEAT STRIP_TAC THEN - MATCH_MP_TAC MONTGOMERY_XZDIFFADD_GROUP THEN ASM_REWRITE_TAC[] THEN + REWRITE_TAC[RING_OF_NUM; p_25519; ARITH_EQ] THEN + MATCH_MP_TAC EQ_IMP THEN AP_TERM_TAC THEN + REWRITE_TAC[montgomery_xzdouble; curve25519x; curve25519] THEN + REWRITE_TAC[INTEGER_MOD_RING_CLAUSES; PAIR_EQ] THEN + CONV_TAC INT_REM_DOWN_CONV THEN + FIRST_X_ASSUM(SUBST1_TAC o SYM) THEN + REWRITE_TAC[RING_OF_INT_REM] THEN + REWRITE_TAC[GSYM RING_OF_INT_CLAUSES] THEN + REWRITE_TAC[RING_OF_INT_OF_NUM]);; + +let CURVE25519X_REPRESENTS_DIFFADD_LEFT = prove + (`!(f:A ring) P n X Qm Qn. + field f /\ ring_char f = p_25519 /\ ~(&p_25519 divides X) /\ + curve25519x_represents f P 1 (X,&1) /\ + curve25519x_represents f P (n + 1) Qm /\ + curve25519x_represents f P n Qn + ==> curve25519x_represents f P (2 * n + 1) + (montgomery_xzdiffadd curve25519 (X,&1) Qm Qn)`, + REWRITE_TAC[FORALL_PAIR_THM; curve25519x_represents] THEN + MAP_EVERY X_GEN_TAC + [`f:A ring`; `P:(A#A)option`; `n:num`; `X:int`; + `Xm:int`; `Zm:int`; `Xn:int`; `Zn:int`] THEN + STRIP_TAC THEN GEN_REWRITE_TAC RAND_CONV [GSYM PAIR] THEN + PURE_REWRITE_TAC[curve25519x_represents] THEN ASM_REWRITE_TAC[] THEN + MP_TAC(ISPECL + [`f:A ring`; `ring_of_num (f:A ring) A_25519`; `ring_of_num (f:A ring) 1`; + `P:(A#A)option`; `n:num`; + `ring_of_int f X:A,ring_of_int f (&1)`; + `ring_of_int f Xm:A,ring_of_int f Zm`; + `ring_of_int f Xn:A,ring_of_int f Zn`] + MONTGOMERY_XZDIFFADD_GROUP) THEN ASM_SIMP_TAC[GSYM curve25519x; MONTGOMERY_NONSINGULAR_CURVE25519X] THEN - REWRITE_TAC[A_25519; p_25519; RING_OF_NUM] THEN - ASM_SIMP_TAC[RING_OF_NUM_1; FIELD_NONTRIVIAL] THEN - CONV_TAC NUM_REDUCE_CONV);; - -let lemma_diffadd2 = prove - (`field f /\ ring_char f = p_25519 /\ - ~(x:(int#int) = ring_0 f) /\ - P IN group_carrier (curve25519x_group f) /\ - montgomery_xz f P (x,ring_of_num f 1) /\ - montgomery_xz f - (group_pow (curve25519x_group f) P (n + 1)) (xm,zm) /\ - montgomery_xz f - (group_pow (curve25519x_group f) P n) (xn,zn) - ==> montgomery_xz f - (group_pow (curve25519x_group f) P (2 * n + 1)) - (montgomery_xzdiffadd (curve25519x f) (x,ring_of_num f 1) - (xn,zn) (xm,zm))`, + ASM_REWRITE_TAC[RING_OF_NUM; p_25519; ARITH_EQ] THEN ANTS_TAC THENL + [ASM_REWRITE_TAC[RING_OF_INT_EQ_0] THEN + REWRITE_TAC[GSYM num_divides; DIVIDES_MOD; p_25519] THEN + CONV_TAC NUM_REDUCE_CONV THEN ASM_MESON_TAC[GROUP_POW_1]; + MATCH_MP_TAC EQ_IMP THEN AP_TERM_TAC] THEN + REWRITE_TAC[montgomery_xzdiffadd; curve25519x; curve25519] THEN + REWRITE_TAC[INTEGER_MOD_RING_CLAUSES; PAIR_EQ] THEN + CONV_TAC INT_REM_DOWN_CONV THEN + FIRST_X_ASSUM(SUBST1_TAC o SYM) THEN + REWRITE_TAC[RING_OF_INT_REM] THEN + REWRITE_TAC[GSYM RING_OF_INT_CLAUSES] THEN + REWRITE_TAC[RING_OF_INT_OF_NUM]);; + +let CURVE25519X_REPRESENTS_DIFFADD_RIGHT = prove + (`!(f:A ring) P n X Qm Qn. + field f /\ ring_char f = p_25519 /\ ~(&p_25519 divides X) /\ + curve25519x_represents f P 1 (X,&1) /\ + curve25519x_represents f P n Qm /\ + curve25519x_represents f P (n + 1) Qn + ==> curve25519x_represents f P (2 * n + 1) + (montgomery_xzdiffadd curve25519 (X,&1) Qm Qn)`, + REWRITE_TAC[FORALL_PAIR_THM] THEN REPEAT GEN_TAC THEN + ONCE_REWRITE_TAC[TAUT + `p /\ q /\ r /\ s /\ t /\ u <=> p /\ q /\ r /\ s /\ u /\ t`] THEN DISCH_TAC THEN - FIRST_ASSUM(MP_TAC o MATCH_MP lemma_diffadd1) THEN + FIRST_ASSUM(MP_TAC o MATCH_MP CURVE25519X_REPRESENTS_DIFFADD_LEFT) THEN MATCH_MP_TAC EQ_IMP THEN AP_TERM_TAC THEN - POP_ASSUM STRIP_ASSUME_TAC THEN - REPEAT(FIRST_X_ASSUM(MP_TAC o MATCH_MP MONTGOMERY_XZ_IN_CARRIER)) THEN - ASM_SIMP_TAC[montgomery_xzdiffadd; curve25519x; RING_MUL_SYM; PAIR_EQ] THEN - RING_TAC);; + REWRITE_TAC[montgomery_xzdiffadd; curve25519] THEN + REWRITE_TAC[PAIR_EQ; INTEGER_MOD_RING_CLAUSES] THEN CONJ_TAC THEN + CONV_TAC INT_REM_DOWN_CONV THEN AP_THM_TAC THEN AP_TERM_TAC THEN + INT_ARITH_TAC);; + +let FLIPLADDER_MAIN = prove + (`!(f:A ring) P x n i. + field f /\ ring_char f = p_25519 /\ ~(p_25519 divides x) /\ + curve25519x_represents f P 1 (&x,&1) /\ n < 2 EXP 255 /\ i <= 255 + ==> curve25519x_represents f P (n DIV 2 EXP (255 - i)) + ((if ODD(n DIV 2 EXP (255 - i)) then SND else FST) + (flipladder x n i)) /\ + curve25519x_represents f P (n DIV 2 EXP (255 - i) + 1) + ((if ODD(n DIV 2 EXP (255 - i)) then FST else SND) + (flipladder x n i))`, + REWRITE_TAC[num_divides] THEN REPLICATE_TAC 4 GEN_TAC THEN + REWRITE_TAC[IMP_CONJ; RIGHT_FORALL_IMP_THM] THEN REPEAT DISCH_TAC THEN + INDUCT_TAC THENL + [DISCH_THEN(K ALL_TAC) THEN REWRITE_TAC[flipladder] THEN + ASM_SIMP_TAC[SUB_0; DIV_LT; ARITH_ODD; ADD_CLAUSES] THEN + FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE I [curve25519x_represents]) THEN + SIMP_TAC[curve25519x_represents; group_pow] THEN DISCH_TAC THEN + FIRST_ASSUM(SUBST1_TAC o SYM) THEN REWRITE_TAC[RING_OF_INT_REM] THEN + STRIP_TAC THEN ASM_SIMP_TAC[CURVE25519X_GROUP; GSYM curve25519x_group] THEN + REWRITE_TAC[montgomery_xz; RING_OF_INT_1; RING_OF_INT_0] THEN + REWRITE_TAC[RING_0; RING_1] THEN ASM_MESON_TAC[field]; + DISCH_TAC THEN FIRST_X_ASSUM(MP_TAC o check (is_imp o concl)) THEN + ANTS_TAC THENL [ASM_ARITH_TAC; ALL_TAC]] THEN + REWRITE_TAC[flipladder; ADD1] THEN + ASM_SIMP_TAC[ARITH_RULE + `SUC i <= 255 ==> 255 - i = SUC(255 - (i + 1))`] THEN + REWRITE_TAC[ONCE_REWRITE_RULE[MULT_SYM] (CONJUNCT2 EXP)] THEN + REWRITE_TAC[GSYM DIV_DIV] THEN + ABBREV_TAC `m = n DIV 2 EXP (255 - (i + 1)) DIV 2` THEN + MP_TAC(SPECL [`n DIV 2 EXP (255 - (i + 1))`; `2`] + (CONJUNCT1 DIVISION_SIMP)) THEN + ASM_REWRITE_TAC[MOD_2_CASES; GSYM NOT_ODD; COND_SWAP] THEN + MAP_EVERY ABBREV_TAC + [`b <=> ODD m`; `c <=> ODD(n DIV 2 EXP (255 - (i + 1)))`] THEN + DISCH_THEN(SUBST1_TAC o SYM) THEN + MAP_EVERY ASM_CASES_TAC [`b:bool`; `c:bool`] THEN + ASM_REWRITE_TAC[] THEN LET_TAC THEN ASM_REWRITE_TAC[] THEN + CONV_TAC(ONCE_DEPTH_CONV let_CONV) THEN ASM_REWRITE_TAC[] THEN + REWRITE_TAC[ADD_CLAUSES; ARITH_RULE `m * 2 = 2 * m`; + ARITH_RULE `(2 * m + 1) + 1 = 2 * (m + 1)`] THEN + ASM_MESON_TAC[CURVE25519X_REPRESENTS_DOUBLE; + CURVE25519X_REPRESENTS_DIFFADD_LEFT; + CURVE25519X_REPRESENTS_DIFFADD_RIGHT]);; + +let FLIPLADDER_DEGENERATE = prove + (`!x n i xm zm xn zn. + p_25519 divides x /\ flipladder x n i = (xm,zm),(xn,zn) + ==> zm = &0 /\ xn = &0`, + GEN_TAC THEN GEN_TAC THEN REWRITE_TAC[IMP_CONJ; RIGHT_FORALL_IMP_THM] THEN + REWRITE_TAC[num_divides; GSYM INT_REM_EQ_0] THEN DISCH_TAC THEN + INDUCT_TAC THEN ASM_SIMP_TAC[flipladder; PAIR_EQ] THENL + [MESON_TAC[]; REWRITE_TAC[flipladder; ADD1]] THEN + REPEAT GEN_TAC THEN LET_TAC THEN + SUBGOAL_THEN `z2:int = &0 /\ x3:int = &0` MP_TAC THENL + [ASM_MESON_TAC[]; REPLICATE_TAC 2 (POP_ASSUM(K ALL_TAC))] THEN + STRIP_TAC THEN COND_CASES_TAC THEN + ASM_REWRITE_TAC[montgomery_xzdouble; curve25519; montgomery_xzdouble; + PAIR_EQ; montgomery_xzdiffadd; INTEGER_MOD_RING_CLAUSES] THEN + CONV_TAC INT_REM_DOWN_CONV THEN + DISCH_THEN(fun th -> REWRITE_TAC[GSYM th]) THEN + REWRITE_TAC[INT_MUL_LZERO; INT_MUL_RZERO; INT_SUB_REFL; INT_POW_ZERO; + ARITH_EQ; INT_REM_ZERO]);; + +let DEPROJECT_LADDER_EVEN = prove + (`!x n x2 z2. + n < 2 EXP 255 /\ EVEN n /\ + (&x2 == ladder_x2 x n 0) (mod &p_25519) /\ + (&z2 == ladder_z2 x n 0) (mod &p_25519) + ==> purex25519(n,x) = deproject(x2,z2)`, + REWRITE_TAC[ladder_x2; ladder_z2; SUB_0] THEN REPEAT STRIP_TAC THEN + MATCH_MP_TAC PUREX25519_UNIQUE_IMP THEN CONJ_TAC THENL + [REWRITE_TAC[deproject; p_25519] THEN ARITH_TAC; ALL_TAC] THEN + MAP_EVERY X_GEN_TAC [`f:(int#int)ring`; `Q:((int#int)#(int#int))option`] THEN + STRIP_TAC THEN ASM_CASES_TAC `p_25519 divides x` THENL + [MP_TAC(ISPECL [`x:num`; `n:num`; `255`] FLIPLADDER_DEGENERATE) THEN + DISCH_THEN(MP_TAC o SPECL + [`ladder_x2 x n 0`; `ladder_z2 x n 0`; + `ladder_x3 x n 0`; `ladder_z3 x n 0`]) THEN + ASM_REWRITE_TAC[ladder_x2; ladder_z2; ladder_x3; ladder_z3] THEN + ASM_REWRITE_TAC[SUB_0] THEN DISCH_THEN(CONJUNCTS_THEN SUBST_ALL_TAC) THEN + ASM_REWRITE_TAC[deproject; num_divides; GSYM INT_CONG_0_DIVIDES] THEN + REWRITE_TAC[MULT_CLAUSES; MOD_0; RING_OF_NUM_0] THEN + REWRITE_TAC[curve25519x_group; curve25519x] THEN + MATCH_MP_TAC MONTGOMERY_XMAP_EQ_0_POW THEN + ASM_REWRITE_TAC[GSYM curve25519x_group; GSYM curve25519x; RING_OF_NUM] THEN + ASM_SIMP_TAC[MONTGOMERY_NONSINGULAR_CURVE25519X; RING_OF_NUM_EQ_0] THEN + REWRITE_TAC[p_25519; ARITH_EQ]; + ALL_TAC] THEN + MP_TAC(ISPECL [`f:(int#int)ring`; `Q:((int#int)#(int#int))option`; + `x:num`; `n:num`; `255`] + FLIPLADDER_MAIN) THEN + ASM_REWRITE_TAC[SUB_REFL; EXP; DIV_1; LE_REFL] THEN ANTS_TAC THENL + [ASM_SIMP_TAC[curve25519x_represents; GROUP_POW_1; + GSYM curve25519x_group; RING_OF_INT_OF_NUM; RING_OF_NUM_1] THEN + ASM_SIMP_TAC[MONTGOMERY_XZ_XMAP; RING_OF_NUM_EQ_0; RING_OF_NUM]; + DISCH_THEN(MP_TAC o CONJUNCT1) THEN ASM_REWRITE_TAC[GSYM NOT_EVEN]] THEN + GEN_REWRITE_TAC (LAND_CONV o RAND_CONV) [GSYM PAIR] THEN + REWRITE_TAC[curve25519x_represents] THEN + ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN + ASM_REWRITE_TAC[GSYM curve25519x_group] THEN + REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o + GEN_REWRITE_RULE I [GSYM INT_REM_EQ])) THEN + SUBST1_TAC(SYM(ASSUME `ring_char(f:(int#int)ring) = p_25519`)) THEN + REWRITE_TAC[RING_OF_INT_REM; RING_OF_INT_OF_NUM] THEN + SPEC_TAC(`group_pow (curve25519x_group(f:(int#int)ring)) Q n`, + `P:((int#int)#(int#int))option`) THEN + MATCH_MP_TAC option_INDUCT THEN + GEN_REWRITE_TAC RAND_CONV [FORALL_PAIR_THM] THEN + ASM_SIMP_TAC[montgomery_xmap; montgomery_xz; deproject; + RING_OF_NUM_EQ_0; MULT_CLAUSES; MOD_0; RING_OF_NUM_0] THEN + X_GEN_TAC `y:int#int` THEN STRIP_TAC THEN + FIRST_X_ASSUM(SUBST1_TAC o SYM) THEN + SUBST1_TAC(SYM(ASSUME `ring_char(f:(int#int)ring) = p_25519`)) THEN + REWRITE_TAC[RING_OF_NUM_MOD; RING_OF_NUM_MUL; ring_div] THEN + AP_TERM_TAC THEN MATCH_MP_TAC RING_LINV_UNIQUE THEN + REWRITE_TAC[RING_OF_NUM; GSYM RING_OF_NUM_1] THEN + ASM_REWRITE_TAC[GSYM RING_OF_NUM_MUL; RING_OF_NUM_EQ] THEN + REWRITE_TAC[INVERSE_MOD_LMUL_EQ] THEN + ASM_SIMP_TAC[PRIME_COPRIME_EQ; PRIME_P25519]);; + +(* ------------------------------------------------------------------------- *) +(* Overall point operation proof. *) +(* ------------------------------------------------------------------------- *) let CURVE25519_X25519_CORRECT = time prove (`!res scalar n point X pc stackpointer. aligned 16 stackpointer /\ - ALL (nonoverlapping (stackpointer,320)) - [(word pc,0x571c); (res,32); (scalar,32); (point,32)] /\ - nonoverlapping (res,32) (word pc,0x571c) + ALL (nonoverlapping (stackpointer,224)) + [(word pc,0x2554); (res,32); (scalar,32); (point,32)] /\ + nonoverlapping (res,32) (word pc,0x2554) ==> ensures arm (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ - read PC s = word(pc + 0x10) /\ + read PC s = word(pc + 0x2c) /\ read SP s = stackpointer /\ C_ARGUMENTS [res; scalar; point] s /\ bignum_from_memory (scalar,4) s = n /\ bignum_from_memory (point,4) s = X) - (\s. read PC s = word (pc + 0x5708) /\ + (\s. read PC s = word (pc + 0x2500) /\ bignum_from_memory (res,4) s = rfcx25519(n,X)) (MAYCHANGE [PC; X0; X1; X2; X3; X4; X5; X6; X7; X8; X9; X10; X11; X12; X13; X14; X15; X16; X17; X19; X20; - X21; X22; X23] ,, + X21; X22; X23; X24; X25; X26; X27; X28; X29; X30] ,, + MAYCHANGE [Q0; Q1; Q2; Q3; Q4; Q5; Q6; Q7; Q8; Q9; Q10; + Q11; Q12; Q13; Q14; Q15; Q16; Q17; Q18; Q19; Q20; + Q21; Q22; Q23; Q24; Q25; Q26; Q27; Q28; Q29; Q30; Q31] ,, MAYCHANGE SOME_FLAGS ,, MAYCHANGE [memory :> bytes(res,32); - memory :> bytes(stackpointer,320)])`, + memory :> bytes(stackpointer,224)])`, REWRITE_TAC[FORALL_PAIR_THM] THEN MAP_EVERY X_GEN_TAC [`res:int64`; `scalar:int64`; `n_input:num`; `point:int64`; `X_input:num`; @@ -7459,165 +4140,154 @@ let CURVE25519_X25519_CORRECT = time prove (*** Setup of the main loop ***) - ENSURES_WHILE_ADOWN_TAC `254` `3` `pc + 0xb08` `pc + 0x234c` + ENSURES_WHILE_PDOWN_TAC `255` `pc + 0x138` `pc + 0x112c` `\i s. - read SP s = stackpointer /\ - read X23 s = res /\ - read X20 s = word_sub (word i) (word 1) /\ - bignum_from_memory (stackpointer,4) s = n_input /\ - bignum_from_memory (word_add stackpointer (word 32),4) s = X /\ - read X21 s = word(bitval(ODD(nn DIV 2 EXP i))) /\ - bignum_from_memory(word_add stackpointer (word 64),4) s < 2 * p_25519 /\ - bignum_from_memory(word_add stackpointer (word 160),4) s < 2 * p_25519 /\ - bignum_from_memory(word_add stackpointer (word 224),4) s < 2 * p_25519 /\ - bignum_from_memory(word_add stackpointer (word 288),4) s < 2 * p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - bignum_from_memory(word_add stackpointer (word 64),4) s - MOD p_25519 <= 1 /\ - bignum_from_memory(word_add stackpointer (word 160),4) s - MOD p_25519 = 0 /\ - bignum_from_memory(word_add stackpointer (word 224),4) s - MOD p_25519 = 0 /\ - bignum_from_memory(word_add stackpointer (word 288),4) s - MOD p_25519 <= 1 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P - (if ODD(nn DIV 2 EXP i) - then nn DIV 2 EXP i + 1 else nn DIV 2 EXP i)) - (bignum_from_memory(word_add stackpointer (word 288),4) s, - bignum_from_memory(word_add stackpointer (word 160),4) s) /\ - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P - (if ODD(nn DIV 2 EXP i) - then nn DIV 2 EXP i else nn DIV 2 EXP i + 1)) - (bignum_from_memory(word_add stackpointer (word 224),4) s, - bignum_from_memory(word_add stackpointer (word 64),4) s)` THEN + (read SP s = stackpointer /\ + read (memory :> bytes64(word_add stackpointer (word 192))) s = res /\ + (bignum_from_memory(stackpointer,4) s == nn) (mod (2 EXP 255)) /\ + read Q31 s = word 0x1300000013 /\ + read Q30 s = word 0x3ffffff0000000003ffffff /\ + read Q29 s = word 0x07fffffe07fffffc /\ + read (memory :> bytes64(word_add stackpointer (word 72))) s = + word 0x07fffffe07fffffc /\ + read Q28 s = word 0x07fffffe07ffffb4 /\ + read (memory :> bytes64(word_add stackpointer (word 80))) s = + word 0x07fffffe07ffffb4 /\ + read X0 s = word_sub (word i) (word 1) /\ + read (memory :> bytes64(word_add stackpointer (word 200))) s = + word_sub (word i) (word 1) /\ + read (memory :> bytes64(word_add stackpointer (word 208))) s = + word(bitval(ODD(nn DIV 2 EXP i))) /\ + normalized_ubignum_preglist + [memory :> bytes64 (word_add stackpointer (word 32)); + memory :> bytes64 (word_add stackpointer (word 40)); + memory :> bytes64 (word_add stackpointer (word 48)); + memory :> bytes64 (word_add stackpointer (word 56)); + memory :> bytes64 (word_add stackpointer (word 64))] (&X) s /\ + normalized_ubignum_qreglist[Q0;Q2;Q4;Q6;Q8] (ladder_x2 X nn i) s /\ + normalized_ubignum_qreglist[Q10;Q12;Q14;Q16;Q18] (ladder_x3 X nn i) s /\ + normalized_ubignum_qreglist'[Q1;Q3;Q5;Q7;Q9] (ladder_z2 X nn i) s /\ + normalized_ubignum_qreglist[Q11;Q13;Q15;Q17;Q19] (ladder_z3 X nn i) s) /\ + (read CF s <=> 0 < i)` THEN REPEAT CONJ_TAC THENL [ARITH_TAC; - (*** Initial setup, modification of the inputs and doubling ***) - + MAP_EVERY (fun n -> GHOST_INTRO_TAC + (mk_var("init_q"^string_of_int n,`:int128`)) + (list_mk_icomb "read" [mk_const("Q"^string_of_int n,[])])) (0--31) THEN REWRITE_TAC(!simulation_precanon_thms) THEN ENSURES_INIT_TAC "s0" THEN BIGNUM_LDIGITIZE_TAC "n_" `read (memory :> bytes (scalar,8 * 4)) s0` THEN BIGNUM_LDIGITIZE_TAC "x_" `read (memory :> bytes (point,8 * 4)) s0` THEN - ARM_STEPS_TAC CURVE25519_X25519_EXEC (1--15) THEN - SUBGOAL_THEN - `bignum_from_memory (stackpointer,4) s15 = n_input /\ - bignum_from_memory (word_add stackpointer (word 32),4) s15 = X /\ - bignum_from_memory(word_add stackpointer (word 224),4) s15 = X /\ - bignum_from_memory(word_add stackpointer (word 64),4) s15 = 1` - STRIP_ASSUME_TAC THENL + ARM_STEPS_TAC CURVE25519_X25519_EXEC (1--67) THEN + ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN + CONJ_TAC THENL [CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN - ASM_REWRITE_TAC[] THEN MAP_EVERY EXPAND_TAC ["X"; "X_input"] THEN + ASM_REWRITE_TAC[] THEN EXPAND_TAC "nn" THEN REWRITE_TAC[CONG] THEN + SIMP_TAC[MOD_LT; ARITH_RULE + `2 EXP 254 + n_input MOD 2 EXP 254 - n_input MOD 8 < 2 EXP 255`] THEN + MATCH_MP_TAC(ARITH_RULE + `m <= b /\ x + m:num = a + b ==> x = a + b - m`) THEN + CONJ_TAC THENL + [REWRITE_TAC[ARITH_RULE `8 = 2 EXP (MIN 254 3)`] THEN + REWRITE_TAC[GSYM MOD_MOD_EXP_MIN; MOD_LE]; + ALL_TAC] THEN REWRITE_TAC[ARITH_RULE - `m = n MOD 2 EXP 255 <=> m + 2 EXP 255 * n DIV 2 EXP 255 = n`] THEN + `x MOD 2 EXP 255 + n MOD 8 = 2 EXP 254 + n MOD 2 EXP 254 <=> + x + 2 EXP 254 * n DIV 2 EXP 254 = + 8 * n DIV 2 EXP 3 + 2 EXP 254 + 2 EXP 255 * x DIV 2 EXP 255`] THEN + EXPAND_TAC "n_input" THEN CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - REWRITE_TAC[SYM(NUM_REDUCE_CONV `2 EXP 63 - 1`)] THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD_AND_MASK_WORD] THEN - REWRITE_TAC[VAL_WORD_0; VAL_WORD_1] THEN ARITH_TAC; - RULE_ASSUM_TAC(REWRITE_RULE[BIGNUM_FROM_MEMORY_BYTES])] THEN - LOCAL_SUB_TWICE4_TAC 0 ["d"; "xm"; "zm"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["s"; "xm"; "zm"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["zn"; "p"; "e"] THEN - ARM_STEPS_TAC CURVE25519_X25519_EXEC [26] THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - DISCARD_STATE_TAC "s26" THEN - DISCARD_MATCHING_ASSUMPTIONS [`nonoverlapping_modulo a b c`] THEN - CONV_TAC WORD_REDUCE_CONV THEN - SUBGOAL_THEN `X < 2 * p_25519` ASSUME_TAC THENL - [EXPAND_TAC "X" THEN REWRITE_TAC[p_25519] THEN ARITH_TAC; + REWRITE_TAC[bignum_of_wordlist; WORD_BLAST + `val(word_and x (word 18446744073709551608:int64)) = + 8 * val x DIV 8`] THEN + ONCE_REWRITE_TAC[ARITH_RULE `2 EXP 64 * h = 2 EXP 3 * 2 EXP 61 * h`] THEN + SIMP_TAC[DIV_MULT_ADD; EXP_EQ_0; ARITH_EQ] THEN + REWRITE_TAC[WORD_BLAST + `val(word_or n (word 4611686018427387904:int64)) = + 2 EXP 63 * bitval(bit 63 n) + 2 EXP 62 + val(n) MOD 2 EXP 62`] THEN + SIMP_TAC[DIV_MULT_ADD; EXP_EQ_0; ARITH_EQ; DIV_LT; ARITH_RULE + `2 EXP 62 + n MOD 2 EXP 62 < 2 EXP 63`] THEN + CONV_TAC WORD_BLAST; ALL_TAC] THEN - SUBGOAL_THEN `nn DIV 2 EXP 254 = 1` SUBST1_TAC THENL - [EXPAND_TAC "nn" THEN SIMP_TAC[DIV_ADD; DIVIDES_REFL] THEN - SIMP_TAC[DIV_LT; ARITH_RULE `x:num < n ==> x - k < n`; - MOD_LT_EQ; EXP_EQ_0; ARITH_EQ] THEN - CONV_TAC NUM_REDUCE_CONV; + REPEAT(CONJ_TAC THENL [CONV_TAC WORD_BLAST; ALL_TAC]) THEN + SUBGOAL_THEN `nn DIV 2 EXP 255 = 0` SUBST1_TAC THENL + [REWRITE_TAC[DIV_EQ_0] THEN EXPAND_TAC "nn" THEN ARITH_TAC; CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV)] THEN - ASM_REWRITE_TAC[] THEN - CONJ_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC] THEN - SIMP_TAC[GROUP_POW_1] THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o SYM)) THEN - ASM_REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - REPEAT(FIRST_X_ASSUM(MP_TAC o check (is_imp o concl))) THEN - ASM_REWRITE_TAC[] THEN - REPEAT - (ANTS_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; STRIP_TAC]) THEN - STRIP_TAC THEN - DISCARD_MATCHING_ASSUMPTIONS [`a:num < 2 * b`] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - REPEAT(DISCH_THEN(CONJUNCTS_THEN2 ASSUME_TAC MP_TAC)) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_OF_NUM_CLAUSES] THEN - SIMP_TAC[] THEN CONV_TAC INT_REM_DOWN_CONV THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THENL - [DISCH_THEN(K ALL_TAC) THEN REWRITE_TAC[p_25519] THEN - CONV_TAC INT_REDUCE_CONV; - ALL_TAC] THEN - DISCH_THEN(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ_ALT] - lemma_double_base)) THEN - ASM_REWRITE_TAC[] THEN - MATCH_MP_TAC EQ_IMP THEN AP_TERM_TAC THEN - ASM_REWRITE_TAC[montgomery_xzdouble; curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; + REWRITE_TAC[BITVAL_CLAUSES; normalized_ubignum_preglist'; + normalized_ubignum_preglist] THEN + ASM_REWRITE_TAC[normalized_ubignum_qreglist; normalized_ubignum_qreglist'; + normalized_ubignum_int32list; normalized_ubignum_int32list'; + normalized_ubignum_list; normalized_ubignum_list'; + MAP; ubignum_of_list; INT_CONG_RREM] THEN + REWRITE_TAC[WORD_BLAST + `word_subword (word_insert (h:int128) (0,64) (l:int64):int128) + (0,32):int32 = word_subword l (0,32) /\ + word_subword (word_insert (h:int128) (0,64) (l:int64):int128) + (32,32):int32 = word_subword l (32,32)`] THEN + CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN + REWRITE_TAC[ladder_x2; ladder_z2; ladder_x3; ladder_z3] THEN + REWRITE_TAC[SUB_REFL; flipladder; INT_CONG_REFL; INT_CONG_RREM] THEN + REWRITE_TAC[WORD_BLAST + `word_subword (word_or x (word_shl y 32):int64) (0,32):int32 = + word_zx x /\ + word_subword (word_or (word_and x (word 67108863)) + (word_shl y 32):int64) (32,32):int32 = + word_zx y /\ + word_subword (word_or (word_ushr x 38) + (word_shl y 32):int64) (32,32):int32 = + word_zx y /\ + word_subword (word_or (word_subword (x:int64) (25,26)) + (word_shl y 32):int64) (32,32):int32 = + word_zx y /\ + word_subword (word_or (word_subword (x:int64) (12,26)) + (word_shl y 32):int64) (32,32):int32 = + word_zx y`] THEN + REPEAT CONJ_TAC THEN + TRY(REWRITE_TAC[VAL_WORD_SUBWORD; VAL_WORD_ADD; VAL_WORD_SHL; + VAL_WORD_ZX_GEN; DIMINDEX_64; DIMINDEX_32] THEN + CONV_TAC NUM_REDUCE_CONV THEN ASM BOUNDER_TAC[]) THEN + MATCH_MP_TAC INT_EQ_IMP_CONG THEN + REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN + MAP_EVERY EXPAND_TAC ["X"; "X_input"] THEN + REWRITE_TAC[ARITH_RULE + `x = y MOD 2 EXP 255 <=> x + 2 EXP 255 * y DIV 2 EXP 255 = y`] THEN + CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN + REWRITE_TAC[bignum_of_wordlist] THEN CONV_TAC WORD_BLAST; (*** The main loop invariant for the Montgomery ladder ***) X_GEN_TAC `i:num` THEN STRIP_TAC THEN - GHOST_INTRO_TAC `xn:num` - `bignum_from_memory (word_add stackpointer (word 288),4)` THEN - GHOST_INTRO_TAC `zn:num` - `bignum_from_memory (word_add stackpointer (word 160),4)` THEN - GHOST_INTRO_TAC `xm:num` - `bignum_from_memory (word_add stackpointer (word 224),4)` THEN - GHOST_INTRO_TAC `zm:num` - `bignum_from_memory(word_add stackpointer (word 64),4)` THEN - REWRITE_TAC[WORD_RULE `word_sub (word (i + 1)) (word 1) = word i`] THEN - REWRITE_TAC(!simulation_precanon_thms) THEN ENSURES_INIT_TAC "s0" THEN - LOCAL_SUB_TWICE4_TAC 0 ["dm"; "xm"; "zm"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["sn"; "xn"; "zn"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["dn"; "xn"; "zn"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["sm"; "xm"; "zm"] THEN - LOCAL_MUL_4_TAC 0 ["dmsn"; "sn"; "dm"] THEN + REWRITE_TAC[normalized_ubignum_qreglist; normalized_ubignum_qreglist'; + normalized_ubignum_int32list; normalized_ubignum_int32list'; + normalized_ubignum_list; normalized_ubignum_list'; + normalized_ubignum_preglist; normalized_ubignum_preglist'; + MAP; ALL] THEN + REWRITE_TAC[WORD_RULE `word_sub (word(i + 1)) (word 1) = word i`] THEN + REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN + + (*** Introduce zero-state abbreviations ***) + + ABBREVIATE_STATE_COMPONENTS_TAC 0 THEN + + (*** Manually simulate and analyze the scalar bit selection ***) + + ABBREV_TAC `n = read (memory :> bytes (stackpointer,8 * 4)) s0` THEN SUBGOAL_THEN `read(memory :> bytes64(word_add stackpointer - (word(8 * val(word_ushr (word i:int64) 6))))) s5 = - word(n_input DIV (2 EXP (64 * i DIV 64)) MOD 2 EXP (64 * 1))` + (word(8 * val(word_ushr (word i:int64) 6))))) s0 = + word(n DIV (2 EXP (64 * i DIV 64)) MOD 2 EXP (64 * 1))` ASSUME_TAC THENL - [EXPAND_TAC "n_input" THEN REWRITE_TAC[GSYM BIGNUM_FROM_MEMORY_BYTES] THEN + [EXPAND_TAC "n" THEN REWRITE_TAC[GSYM BIGNUM_FROM_MEMORY_BYTES] THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_DIV; BIGNUM_FROM_MEMORY_MOD] THEN - ASM_SIMP_TAC[ARITH_RULE `i < 254 ==> MIN (4 - i DIV 64) 1 = 1`] THEN + ASM_SIMP_TAC[ARITH_RULE `i < 255 ==> MIN (4 - i DIV 64) 1 = 1`] THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_SING; WORD_VAL] THEN VAL_INT64_TAC `i:num` THEN ASM_REWRITE_TAC[VAL_WORD_USHR] THEN CONV_TAC NUM_REDUCE_CONV THEN REFL_TAC; ALL_TAC] THEN - ARM_STEPS_TAC CURVE25519_X25519_EXEC (6--11) THEN + ARM_STEPS_TAC CURVE25519_X25519_EXEC (1--7) THEN SUBGOAL_THEN `word_and - (word_jushr (word((n_input DIV 2 EXP (64 * i DIV 64)) MOD 2 EXP 64)) + (word_jushr (word((n DIV 2 EXP (64 * i DIV 64)) MOD 2 EXP 64)) (word i)) (word 1:int64) = word(bitval(ODD(nn DIV 2 EXP i)))` @@ -7633,558 +4303,451 @@ let CURVE25519_X25519_CORRECT = time prove REWRITE_TAC[EXP_ADD; GSYM DIV_MOD; ODD_MOD_POW2] THEN MATCH_MP_TAC(TAUT `p /\ (q <=> q') ==> (p /\ q <=> q')`) THEN CONJ_TAC THENL [ARITH_TAC; ALL_TAC] THEN - REWRITE_TAC[GSYM CONG_MOD_2_ALT] THEN - EXPAND_TAC "nn" THEN - SIMP_TAC[DIV_ADD; DIVIDES_EXP_LE_IMP; LT_IMP_LE; ASSUME `i < 254`; - DIV_EXP; EXP_EQ_0; ARITH_EQ] THEN - MATCH_MP_TAC(NUMBER_RULE - `n divides e /\ (y == z) (mod n) ==> (z:num == e + y) (mod n)`) THEN - ASM_REWRITE_TAC[DIVIDES_2; EVEN_EXP; ARITH_EVEN; SUB_EQ_0; NOT_LE] THEN - REWRITE_TAC[ARITH_RULE `2 EXP 254 = 8 * 2 EXP 251`; MOD_MULT_MOD] THEN - REWRITE_TAC[ADD_SUB] THEN - SUBGOAL_THEN `i = 3 + i - 3` SUBST1_TAC THENL - [UNDISCH_TAC `3 <= i` THEN ARITH_TAC; REWRITE_TAC[EXP_ADD]] THEN - REWRITE_TAC[GSYM DIV_DIV; NUM_REDUCE_CONV `2 EXP 3`] THEN - REWRITE_TAC[ARITH_RULE `(8 * n) DIV 8 = n`] THEN - MATCH_MP_TAC CONG_DIV2 THEN - MATCH_MP_TAC CONG_DIVIDES_MODULUS THEN EXISTS_TAC `2 EXP 251` THEN - REWRITE_TAC[CONG_LMOD; CONG_REFL] THEN + REWRITE_TAC[GSYM CONG_MOD_2_ALT] THEN MATCH_MP_TAC CONG_DIV2 THEN + FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (REWRITE_RULE[IMP_CONJ] + CONG_DIVIDES_MODULUS)) THEN REWRITE_TAC[GSYM(ONCE_REWRITE_RULE[MULT_SYM] (CONJUNCT2 EXP))] THEN MATCH_MP_TAC DIVIDES_EXP_LE_IMP THEN - UNDISCH_TAC `i < 254` THEN ARITH_TAC; + UNDISCH_TAC `i < 255` THEN ARITH_TAC; ALL_TAC] THEN - RULE_ASSUM_TAC(REWRITE_RULE[VAL_EQ_0; WORD_SUB_EQ_0; - MESON[VAL_WORD_BITVAL; VAL_EQ; EQ_BITVAL] - `word(bitval b) = word(bitval c) <=> (b <=> c)`]) THEN - LOCAL_MUX_4_TAC 0 ["d"; "dm"; "dn"] THEN - LOCAL_MUX_4_TAC 0 ["s"; "sm"; "sn"] THEN - LOCAL_MUL_4_TAC 0 ["dnsm"; "sm"; "dn"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["dpro"; "dmsn"; "dnsm"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["spro"; "dmsn"; "dnsm"] THEN - LOCAL_SQR_4_TAC 0 ["dpro"; "dpro"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["xm"; "spro"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["zm"; "dpro"; "x"] THEN - LOCAL_MUL_4_TAC 0 ["zn"; "p"; "e"] THEN - ARM_STEPS_TAC CURVE25519_X25519_EXEC [28] THEN - FIRST_X_ASSUM(MP_TAC o - check (can (term_match [] `(MAYCHANGE a ,, b) s s'` o concl))) THEN - POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - DISCH_THEN(fun th -> DISCH_TAC THEN - ENSURES_FINAL_STATE_TAC THEN MP_TAC th) THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - DISCARD_STATE_TAC "s28" THEN - DISCARD_MATCHING_ASSUMPTIONS - [`aligned a b`; `val(word i) = i`; `nonoverlapping_modulo a b c`] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THENL - [REWRITE_TAC[INT_OF_NUM_CLAUSES; INT_OF_NUM_REM] THEN - REWRITE_TAC[ARITH_RULE `b <= 1 <=> b = 0 \/ b = 1`] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - REWRITE_TAC[p_25519] THEN CONV_TAC INT_REDUCE_CONV; + RULE_ASSUM_TAC(REWRITE_RULE + [VAL_WORD_SUB_EQ_0; VAL_WORD_BITVAL; EQ_BITVAL]) THEN + RULE_ASSUM_TAC(PURE_ONCE_REWRITE_RULE + [TAUT `read ZF s = p <=> read ZF s = ~ ~ p`]) THEN + ABBREV_TAC + `flip <=> ~(ODD(nn DIV 2 EXP (i + 1)) <=> ODD(nn DIV 2 EXP i))` THEN + + (*** Now simulate all the rest of the inner loop instructions ***) + + ARM_NAMESTEPS_TAC CURVE25519_X25519_EXEC (8--1021) THEN + + (*** Also introduce the full abbreviations ***) + + MAP_EVERY ABBREV_TAC abbreviated_variables THEN + + (*** Finish the simulation and throw away machine states ***) + + ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN + ASM_REWRITE_TAC[SIMD_SPLIT_JOIN_CLAUSES; SIMD_MASK_CLAUSES; + EXTRA_SPLIT_JOIN_CLAUSES] THEN + REWRITE_TAC[WORD_BLAST + `word_subword (word_insert (x:int128) (0,64) (y:int64):int128) + (0,32):int32 = + word_subword y (0,32) /\ + word_subword (word_insert (x:int128) (0,64) (y:int64):int128) + (32,32):int32 = + word_subword y (32,32)`] THEN + DISCARD_STATE_TAC "s1021" THEN + + (*** Apply a few standard simplifications eagerly ***) + + RULE_ASSUM_TAC(REWRITE_RULE[extra; SIMD_SPLIT_JOIN_CLAUSES; + ADD_CLAUSES; WORD_RULE `word_add x x = word_mul (word 2) x`]) THEN + RULE_ASSUM_TAC(REWRITE_RULE + [WORD_BLAST + `(word_zx:int64->int32) ((word_zx:int128->int64) x) = + word_subword x (0,32)`]) THEN + RULE_ASSUM_TAC(REWRITE_RULE + [WORD_BLAST + `(word_zx:int64->int32) (word_ushr ((word_zx:int128->int64) x) 32) = + word_subword x (32,32)`]) THEN + RULE_ASSUM_TAC(REWRITE_RULE + [WORD_BLAST + `(word_zx:int64->int32) ((word_zx:int32->int64) x) = word_zx x`]) THEN + + (*** The initial linear and selection blocks ***) + + SUBGOAL_THEN + `(&b:int == &x2 - &z2) (mod &p_25519) /\ + (&d:int == &x3 - &z3) (mod &p_25519) /\ + (&a:int == &x2 + &z2) (mod &p_25519) /\ + (&c:int == &x3 + &z3) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [REPEAT CONJ_TAC THEN ARITHBLOCK_TAC[]; ALL_TAC] THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[TAUT - `(ODD n <=> b) <=> (b <=> ODD n)`]) THEN - ABBREV_TAC `n = nn DIV 2 EXP (i + 1)` THEN - ABBREV_TAC `b = ODD(nn DIV 2 EXP i)` THEN - SUBGOAL_THEN `nn DIV 2 EXP i = 2 * n + bitval b` SUBST1_TAC THENL - [MAP_EVERY EXPAND_TAC ["b"; "n"] THEN - REWRITE_TAC[EXP_ADD; GSYM DIV_DIV; BITVAL_ODD] THEN ARITH_TAC; - SIMP_TAC[BITVAL_CLAUSES; ADD_CLAUSES; COND_ID]] THEN - DISCH_TAC THEN + + SUBGOAL_THEN + `(&f:int == if flip then &c else &a) (mod &p_25519) /\ + (&g:int == if flip then &d else &b) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [REPEAT CONJ_TAC THEN + W(MAP_EVERY (EXPAND_TAC o name_of) o + filter (not o (=) `:bool` o type_of) o frees o snd) THEN + W(MAP_EVERY (EXPAND_TAC o name_of) o + filter (not o (=) `:bool` o type_of) o frees o lhand o rator o snd) THEN + REWRITE_TAC[COND_SWAP] THEN COND_CASES_TAC THEN + REWRITE_TAC[SIMD_SPLIT_JOIN_CLAUSES; GSYM INT_REM_EQ]; + ALL_TAC] THEN + + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC []) ["a"; "b"; "c"; "d"; "f"; "g"] THEN + + (*** aa = f^2 ***) + + SUBGOAL_THEN + `(&aa:int == &f pow 2) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [ARITHBLOCK_TAC[]; + DEDUCE_DIGITBOUNDS_TAC [] "aa"] THEN + + (*** bb = g^2 ***) + + SUBGOAL_THEN + `(&bb:int == &g pow 2) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [ARITHBLOCK_TAC[]; + DEDUCE_DIGITBOUNDS_TAC [] "bb"] THEN + + (*** Alternative form bbalt of bb, proof a bit ad-hoc ***) + + MAP_EVERY (USE_ABBREV (MP_TAC o ASSUME)) ["bbalt"; "bb"] THEN + W(fun (asl,w) -> + let l1 = dest_list(rand(lhand(lhand w))) + and l2 = dest_list(rand(lhand(lhand(rand w)))) in + SUBGOAL_THEN (list_mk_conj(map2 (curry mk_eq) l1 l2)) MP_TAC) + THENL + [W(MAP_EVERY (EXPAND_TAC o name_of) o frees o snd) THEN + REPEAT + (CONJ_TAC THENL + [CONV_TAC(ONCE_DEPTH_CONV VAL_EXPAND_CONV) THEN + CONV_TAC(TOP_DEPTH_CONV (BIT_WORD_CONV o + check (not o can (term_match [] `bit i (word_add x y)`)))) THEN + REWRITE_TAC[BITVAL_CLAUSES] THEN ARITH_TAC; + ALL_TAC]) THEN + REWRITE_TAC[UBIGNUM_PACK_UNPACK_CLAUSES] THEN + REWRITE_TAC[VAL_WORD; VAL_WORD_ADD; VAL_WORD_USHR] THEN + CONV_TAC(ONCE_DEPTH_CONV(!word_SIZE_CONV)) THEN + REPEAT DEMODULATE_TAC THEN MATCH_MP_TAC MOD_LT THEN ASM BOUNDER_TAC[]; + DISCH_THEN(fun th -> + GEN_REWRITE_TAC (LAND_CONV o ONCE_DEPTH_CONV) [th] THEN + DISCH_THEN SUBST1_TAC THEN MP_TAC th THEN + GEN_REWRITE_TAC I [IMP_IMP]) THEN + DISCH_THEN(fun th -> + REPLICATE_TAC 11 (POP_ASSUM MP_TAC) THEN + REWRITE_TAC[IMP_IMP; GSYM CONJ_ASSOC] THEN MP_TAC th) THEN + DISCH_THEN(fun eth -> DISCH_THEN(fun th -> + STRIP_ASSUME_TAC th THEN STRIP_ASSUME_TAC(SUBS(CONJUNCTS eth) th)))] THEN + + (*** e = aa - bb. This is a bit messy with explicit SWAR ***) + + MAP_EVERY (USE_ABBREV + (MP_TAC o AP_TERM `\x. val((word_subword:int64->num#num->int32) x (0,32))` o + ASSUME)) (map (fun n -> "e_"^string_of_int n) (0--9)) THEN + REWRITE_TAC[IMP_IMP; GSYM CONJ_ASSOC] THEN + REWRITE_TAC[WORD_BLAST + `word_subword (word_ushr (x:int64) 32) (0,32):int32 = + word_subword x (32,32)`] THEN + REWRITE_TAC[WORD_SUBWORD_SWAR_0_32] THEN + MAP_EVERY (fun th -> + let f = PART_MATCH (lhand o rand) th in + REPEAT(W(fun (asl,w) -> MP_TAC(f (find_term (can f) (lhand w)))) THEN + ANTS_TAC THENL + [REWRITE_TAC[WORD_SUBWORD_SWAR_0_32; VAL_WORD_ADD; VAL_WORD; + GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM; DIMINDEX_32] THEN + CONV_TAC WORD_REDUCE_CONV THEN REPEAT DEREMULATE_TAC THEN + ASM BOUNDER_TAC[]; + DISCH_THEN SUBST1_TAC])) (rev(CONJUNCTS WORD_SUBWORD_SWAR_32_32)) THEN + CONV_TAC(LAND_CONV WORD_REDUCE_CONV) THEN + GEN_REWRITE_TAC (LAND_CONV o ONCE_DEPTH_CONV) [VAL_EQ] THEN + DISCH_THEN(fun th -> + MAP_EVERY (BOUND_ABBREV_THEN MP_TAC) (CONJUNCTS th) THEN + REPEAT DISCH_TAC THEN ASSUME_TAC th) THEN SUBGOAL_THEN - `(ring_of_num f xm':(int#int),ring_of_num f zm') = - montgomery_xzdiffadd (curve25519x f) - (ring_of_num f X,ring_of_num f 1) - (ring_of_num f xn,ring_of_num f zn) - (ring_of_num f xm,ring_of_num f zm) /\ - (ring_of_num f xn',ring_of_num f zn') = - montgomery_xzdouble (curve25519x f) - (if b <=> ODD n then (ring_of_num f xn,ring_of_num f zn) - else (ring_of_num f xm,ring_of_num f zm))` + `(&e:int == &aa - &bb) (mod &p_25519)` MP_TAC THENL - [COND_CASES_TAC THEN - ASM_REWRITE_TAC[montgomery_xzdiffadd; montgomery_xzdouble; - curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - ASM_REWRITE_TAC[] THEN CONV_TAC INT_REM_DOWN_CONV THEN - REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; - ASM_REWRITE_TAC[] THEN - SIMP_TAC[curve25519x_halfcanonically_represents] THEN - DISCH_THEN(K ALL_TAC) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - FIRST_X_ASSUM(CONJUNCTS_THEN(MP_TAC o last o CONJUNCTS o - GEN_REWRITE_RULE I [curve25519x_halfcanonically_represents])) THEN - GEN_REWRITE_TAC I [GSYM IMP_CONJ_ALT] THEN - FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE I - [curve25519x_halfcanonically_represents]) THEN - DISCH_THEN(CONJUNCTS_THEN2 ASSUME_TAC (MP_TAC o CONJUNCT2)) THEN - UNDISCH_TAC - `P IN group_carrier(curve25519x_group(f:(int#int) ring))`] THEN - SUBGOAL_THEN `~(ring_of_num (f:(int#int) ring) X = ring_0 f)` MP_TAC THENL - [ASM_REWRITE_TAC[RING_OF_NUM_EQ_0; DIVIDES_MOD] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM]; - MAP_EVERY UNDISCH_TAC - [`ring_char(f:(int#int) ring) = p_25519`; `field(f:(int#int) ring)`] THEN - POP_ASSUM_LIST(K ALL_TAC)] THEN - REPEAT DISCH_TAC THEN CONJ_TAC THENL - [DISJ_CASES_THEN SUBST_ALL_TAC - (TAUT `(b <=> ODD n) \/ (b <=> ~ODD n)`) THEN - REWRITE_TAC[TAUT `~(~p <=> p)`] THENL - [FIRST_X_ASSUM(MP_TAC o CONJUNCT1); - FIRST_X_ASSUM(MP_TAC o CONJUNCT2)] THEN - UNDISCH_TAC `P IN group_carrier(curve25519x_group(f:(int#int) ring))` THEN - REWRITE_TAC[IMP_IMP] THEN DISCH_THEN(MP_TAC o MATCH_MP lemma_double) THEN - ASM_REWRITE_TAC[COND_SWAP] THEN COND_CASES_TAC THEN - REWRITE_TAC[ARITH_RULE `(2 * n + 1) + 1 = 2 * (n + 1)`]; - REPEAT(POP_ASSUM MP_TAC) THEN - REWRITE_TAC[IMP_IMP; GSYM CONJ_ASSOC] THEN - COND_CASES_TAC THEN REWRITE_TAC[lemma_diffadd1] THEN - GEN_REWRITE_TAC (LAND_CONV o funpow 5 RAND_CONV) [CONJ_SYM] THEN - REWRITE_TAC[lemma_diffadd2]]; + [W(MAP_EVERY (EXPAND_TAC o name_of) o frees o snd) THEN + FIRST_X_ASSUM(CONJUNCTS_THEN(fun th -> REWRITE_TAC[GSYM th])) THEN + CONV_TAC WORD_REDUCE_CONV THEN + REWRITE_TAC[ubignum_of_list; GSYM INT_OF_NUM_CLAUSES; DIMINDEX_32; + INT_VAL_WORD_SUB; VAL_WORD_ADD; VAL_WORD; GSYM INT_OF_NUM_REM] THEN + CONV_TAC INT_REM_DOWN_CONV THEN REPEAT DEREMULATE_TAC THEN + REWRITE_TAC[REAL_INT_CONGRUENCE; INT_OF_NUM_EQ; p_25519; ARITH_EQ] THEN + REWRITE_TAC[GSYM REAL_OF_INT_CLAUSES] THEN + REAL_INTEGER_TAC; + POP_ASSUM(K ALL_TAC) THEN DISCH_TAC] THEN + + (*** bce = bb + 121666 * e ***) - (*** The trivial loop-back subgoal ***) + SUBGOAL_THEN + `(&bce:int == &bbalt + &121666 * &e) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [ARITHBLOCK_TAC + (map (C SPEC (WORD_BLAST + `!x. (word_zx:int64->int32) x = word_subword x (0,32)`) o + (fun n -> mk_var("e_"^string_of_int n,`:int64`))) (0--9)); + DEDUCE_DIGITBOUNDS_TAC + (map (C SPEC (WORD_BLAST + `!x. (word_zx:int64->int32) x = word_subword x (0,32)`) o + (fun n -> mk_var("e_"^string_of_int n,`:int64`))) (0--9)) "bce"] THEN - REPEAT STRIP_TAC THEN ARM_SIM_TAC CURVE25519_X25519_EXEC (1--2) THEN - REWRITE_TAC[COND_RAND; COND_RATOR] THEN - MATCH_MP_TAC(TAUT `p ==> (if p then T else x)`) THEN - MATCH_MP_TAC(WORD_ARITH - `3 < val x /\ val x < 254 ==> 3 <= val(word_sub x (word 1):int64)`) THEN - VAL_INT64_TAC `i:num` THEN ASM_REWRITE_TAC[]; + (*** z4 = bce * e ***) - ALL_TAC] THEN + SUBGOAL_THEN + `(&z4:int == &bce * &e) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [ARITHBLOCK_TAC + (map (C SPEC (WORD_BLAST + `!x. (word_zx:int64->int32) x = word_subword x (0,32)`) o + (fun n -> mk_var("e_"^string_of_int n,`:int64`))) (0--9)); + DEDUCE_DIGITBOUNDS_TAC + (map (C SPEC (WORD_BLAST + `!x. (word_zx:int64->int32) x = word_subword x (0,32)`) o + (fun n -> mk_var("e_"^string_of_int n,`:int64`))) (0--9)) "z4"] THEN - (*** Multiplexing before last doublings ***) - - GHOST_INTRO_TAC `xn:num` - `bignum_from_memory (word_add stackpointer (word 288),4)` THEN - GHOST_INTRO_TAC `zn:num` - `bignum_from_memory (word_add stackpointer (word 160),4)` THEN - GHOST_INTRO_TAC `xm:num` - `bignum_from_memory (word_add stackpointer (word 224),4)` THEN - GHOST_INTRO_TAC `zm:num` - `bignum_from_memory(word_add stackpointer (word 64),4)` THEN - GLOBALIZE_PRECONDITION_TAC THEN - REWRITE_TAC(!simulation_precanon_thms) THEN ENSURES_INIT_TAC "s0" THEN - LOCAL_MUX_4_TAC 3 ["xn"; "xm"; "xn"] THEN - LOCAL_MUX_4_TAC 0 ["zn"; "zm"; "zn"] THEN + (*** bc = b * c and ad = a * d ***) - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM SUBST_ALL_TAC) - [`xn8 = read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s5`; - `zn8 = - read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s5`] THEN - SUBGOAL_THEN - `xn8 < 2 * p_25519 /\ zn8 < 2 * p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - xn8 MOD p_25519 = 0 /\ zn8 MOD p_25519 <= 1 \/ - xn8 MOD p_25519 <= 1 /\ zn8 MOD p_25519 = 0 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P (nn DIV 8)) (xn8,zn8)` - MP_TAC THENL - [ASM_REWRITE_TAC[VAL_WORD_BITVAL; BITVAL_EQ_0; COND_SWAP] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL [COND_CASES_TAC THEN ASM_REWRITE_TAC[]; ALL_TAC]) THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - REWRITE_TAC[VAL_EQ_0; WORD_SUB_EQ_0; WORD_BITVAL_EQ_0] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THENL [ARITH_TAC; ALL_TAC] THEN - REWRITE_TAC[NUM_REDUCE_CONV `2 EXP 3`] THEN - COND_CASES_TAC THEN ASM_SIMP_TAC[]; - - FIRST_X_ASSUM(K ALL_TAC o check (is_forall o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o check - (fun th -> intersect (frees (concl th)) - [`xm:num`; `xn:num`; `zm:num`; `zn:num`] <> []))) THEN - STRIP_TAC] THEN - - (*** The first doubling to get from nn/8 to nn/4 ***) - - LOCAL_SUB_TWICE4_TAC 0 ["d"; "xn"; "zn"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["s"; "xn"; "zn"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["zn"; "p"; "e"] THEN - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM SUBST_ALL_TAC) - [`xn4 = read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s15`; - `zn4 = - read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s15`] THEN - SUBGOAL_THEN - `xn4 < 2 * p_25519 /\ zn4 < 2 * p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - xn4 MOD p_25519 = 0 /\ zn4 MOD p_25519 <= 1 \/ - xn4 MOD p_25519 <= 1 /\ zn4 MOD p_25519 = 0 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P (2 * nn DIV 8)) (xn4,zn4)` - MP_TAC THENL - [ASM_REWRITE_TAC[] THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THENL - [REWRITE_TAC[ARITH_RULE `n <= 1 <=> n = 0 \/ n = 1`] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC INT_REDUCE_CONV; - ALL_TAC] THEN - REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - DISCH_THEN(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ_ALT] - lemma_double)) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_EQ] THEN MATCH_MP_TAC EQ_IMP THEN - AP_TERM_TAC THEN REWRITE_TAC[PAIR_EQ] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN - ASM_REWRITE_TAC[] THEN - ASM_REWRITE_TAC[montgomery_xzdouble; curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; + SUBGOAL_THEN + `(&bc:int == &b * &c) (mod &p_25519) /\ + (&ad:int == &a * &d) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [CONJ_TAC THEN ARITHBLOCK_TAC[]; + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC []) ["bc"; "ad"]] THEN - FIRST_X_ASSUM(K ALL_TAC o check (is_forall o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o check - (fun th -> intersect (frees (concl th)) - [`xn8:num`; `zn8:num`; `d:num`; `d':num`; - `s:num`; `s':num`; `p:num`; `e:num`] <> []))) THEN - STRIP_TAC] THEN - - (*** The next doubling to get from nn/4 to nn/2 ***) - - LOCAL_SUB_TWICE4_TAC 0 ["d"; "xn"; "zn"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["s"; "xn"; "zn"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["zn"; "p"; "e"] THEN - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM SUBST_ALL_TAC) - [`xn2 = read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s25`; - `zn2 = - read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s25`] THEN - SUBGOAL_THEN - `xn2 < 2 * p_25519 /\ zn2 < 2 * p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - xn2 MOD p_25519 = 0 /\ zn2 MOD p_25519 <= 1 \/ - xn2 MOD p_25519 <= 1 /\ zn2 MOD p_25519 = 0 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P (2 * 2 * nn DIV 8)) (xn2,zn2)` - MP_TAC THENL - [ASM_REWRITE_TAC[] THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THENL - [REWRITE_TAC[ARITH_RULE `n <= 1 <=> n = 0 \/ n = 1`] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC INT_REDUCE_CONV; - ALL_TAC] THEN - REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - DISCH_THEN(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ_ALT] - lemma_double)) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_EQ] THEN MATCH_MP_TAC EQ_IMP THEN - AP_TERM_TAC THEN REWRITE_TAC[PAIR_EQ] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN - ASM_REWRITE_TAC[] THEN - ASM_REWRITE_TAC[montgomery_xzdouble; curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; + (*** t1 = ad + bc; t2 = ad - bc ***) - FIRST_X_ASSUM(K ALL_TAC o check (is_forall o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o check - (fun th -> intersect (frees (concl th)) - [`xn4:num`; `zn4:num`; `d:num`; `d':num`; - `s:num`; `s':num`; `p:num`; `e:num`] <> []))) THEN - STRIP_TAC] THEN - - (*** The final doubling to get from nn/2 to nn ***) - - LOCAL_SUB_TWICE4_TAC 0 ["d"; "xn"; "zn"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["s"; "xn"; "zn"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_P25519_TAC 0 ["zn"; "p"; "e"] THEN - SUBGOAL_THEN - `xn < 2 * p_25519 /\ zn < p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - xn MOD p_25519 = 0 /\ zn MOD p_25519 <= 1 \/ - xn MOD p_25519 <= 1 /\ zn MOD p_25519 = 0 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P (2 * 2 * 2 * nn DIV 8)) (xn,zn)` - MP_TAC THENL - [ASM_REWRITE_TAC[] THEN CONJ_TAC THENL - [REWRITE_TAC[MOD_LT_EQ; p_25519; ARITH_EQ]; ALL_TAC] THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_OF_NUM_CLAUSES]) THEN + SUBGOAL_THEN + `(&t1:int == &ad + &bc) (mod &p_25519) /\ + (&t2:int == &ad - &bc) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + (let ths = + map (C SPEC (WORD_BLAST + `!x:int128. word_subword x (0,32):int32 = + word_zx(word_subword x (0,64):int64)`) o + (fun n -> mk_var("ad_"^string_of_int n,`:int128`))) (0--9) @ + map (C SPEC (WORD_BLAST + `!x:int128. word_subword (word_subword x (64,64):int64) (0,32):int32 = + word_zx(word_subword x (64,64):int64)`) o + (fun n -> mk_var("ad_"^string_of_int n,`:int128`))) (0--9) in + [CONJ_TAC THEN ARITHBLOCK_TAC ths; + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC ths) ["t1"; "t2"]]) THEN + + (*** x5 = t1^2; t3 = t2^2 ***) + + SUBGOAL_THEN + `(&x5:int == &t1 pow 2) (mod &p_25519) /\ + (&t3:int == &t2 pow 2) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [CONJ_TAC THEN ARITHBLOCK_TAC[]; + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC []) ["x5"; "t3"]] THEN + + (*** x4 = aa * bb and z5 = x * t3 ***) + + SUBGOAL_THEN + `(&x4:int == &aa * &bb) (mod &p_25519) /\ + (&z5:int == &x * &t3) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + (let ths = map (C SPEC (WORD_BLAST + `!x:int128. word_subword x (0,32):int32 = + word_zx(word_subword x (0,64):int64)`) o + (fun n -> mk_var("t3_"^string_of_int n,`:int128`))) (0--9) in + [CONJ_TAC THEN ARITHBLOCK_TAC ths; + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC ths) ["x4"; "z5"]]) THEN + + (*** The odd goal out, the looping criterion ***) + + REWRITE_TAC[CONJ_ASSOC] THEN CONJ_TAC THENL + [REWRITE_TAC[GSYM CONJ_ASSOC]; + VAL_INT64_TAC `i:num` THEN ASM_REWRITE_TAC[] THEN ARITH_TAC] THEN + + (*** Regularize the form of the digits ***) + + REWRITE_TAC(map (C SPEC (WORD_BLAST + `!x:int128. word_subword x (0,32):int32 = + word_zx(word_subword x (0,64):int64)`) o + (fun n -> mk_var("t3_"^string_of_int n,`:int128`))) (0--9)) THEN + REWRITE_TAC[WORD_BLAST + `!x:int128. word_subword (word_subword x (64,64):int64) (0,32):int32 = + word_zx(word_subword x (64,64):int64)`] THEN + REWRITE_TAC[VAL_WORD_ZX_GEN; DIMINDEX_32; DIMINDEX_64] THEN + REPEAT DEMODULATE_TAC THEN ASM_REWRITE_TAC[] THEN + + (*** Separate the bound properties and prove those first ***) + + W(fun (asl,w) -> + let w1,w2 = partition (can (term_match [] `x:num <= b`)) (conjuncts w) in + GEN_REWRITE_TAC I + [CONJ_ACI_RULE(mk_eq(w,mk_conj(list_mk_conj w1,list_mk_conj w2)))]) THEN + CONJ_TAC THENL [REPEAT CONJ_TAC THEN ASM BOUNDER_TAC[]; ALL_TAC] THEN + + (*** Now the main mathematics ***) + + REWRITE_TAC[ladder_x2; ladder_x3; ladder_z2; ladder_z3] THEN + SUBGOAL_THEN `255 - i = ((255 - (i + 1)) + 1)` SUBST1_TAC THENL + [UNDISCH_TAC `i < 255` THEN ARITH_TAC; ALL_TAC] THEN + REWRITE_TAC[flipladder] THEN + LET_TAC THEN CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN + ASM_SIMP_TAC[ARITH_RULE `i < 255 ==> 255 - (255 - (i + 1) + 1) = i`; + ARITH_RULE `i < 255 ==> 255 - (255 - (i + 1)) = i + 1`] THEN + REPEAT(FIRST_X_ASSUM(MP_TAC o check + (can (term_match [] `(x:int == y) (mod &p)`) o concl))) THEN + FIRST_X_ASSUM(fun th -> + MP_TAC(AP_TERM `(FST o FST):(int#int)#(int#int)->int` th) THEN + MP_TAC(AP_TERM `(SND o FST):(int#int)#(int#int)->int` th) THEN + MP_TAC(AP_TERM `(FST o SND):(int#int)#(int#int)->int` th) THEN + MP_TAC(AP_TERM `(SND o SND):(int#int)#(int#int)->int` th)) THEN + REWRITE_TAC[o_THM; GSYM ladder_x2; GSYM ladder_z2; + GSYM ladder_x3; GSYM ladder_z3] THEN + REPLICATE_TAC 4 (DISCH_THEN SUBST1_TAC) THEN + ONCE_REWRITE_TAC[EQ_SYM_EQ] THEN + ONCE_REWRITE_TAC[GSYM COND_SWAP] THEN ASM_REWRITE_TAC[] THEN + POP_ASSUM_LIST(K ALL_TAC) THEN REWRITE_TAC[COND_SWAP] THEN + COND_CASES_TAC THEN REPEAT DISCH_TAC THEN + REWRITE_TAC[curve25519; montgomery_xzdouble; montgomery_xzdiffadd] THEN + REWRITE_TAC[INTEGER_MOD_RING_CLAUSES; A_25519] THEN + CONV_TAC INT_REM_DOWN_CONV THEN + RULE_ASSUM_TAC(REWRITE_RULE + [num_congruent; GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM]) THEN + RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_REM_EQ]) THEN RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THEN - ONCE_REWRITE_TAC[GSYM MOD_MULT_MOD2] THENL - [REWRITE_TAC[ARITH_RULE `n <= 1 <=> n = 0 \/ n = 1`] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC INT_REDUCE_CONV; - ALL_TAC] THEN - REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(TAUT `q /\ (p ==> r) ==> p ==> q /\ r`) THEN - CONJ_TAC THENL - [REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(ARITH_RULE `x < p ==> x < 2 * p`) THEN - REWRITE_TAC[MOD_LT_EQ; p_25519; ARITH_EQ]; - ALL_TAC] THEN - DISCH_THEN(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ_ALT] - lemma_double)) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_EQ] THEN MATCH_MP_TAC EQ_IMP THEN - AP_TERM_TAC THEN REWRITE_TAC[PAIR_EQ] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN - ASM_REWRITE_TAC[] THEN - ASM_REWRITE_TAC[montgomery_xzdouble; curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN + ASM_REWRITE_TAC[GSYM INT_REM_EQ] THEN CONV_TAC INT_REM_DOWN_CONV THEN ASM_REWRITE_TAC[] THEN CONV_TAC INT_REM_DOWN_CONV THEN REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; - FIRST_X_ASSUM(K ALL_TAC o check (is_forall o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o check - (fun th -> intersect (frees (concl th)) - [`xn2:num`; `zn2:num`; `d:num`; `d':num`; - `s:num`; `s':num`; `p:num`; `e:num`] <> []))) THEN - STRIP_TAC] THEN - - (*** Clean up final goal and observe that we've reached nn ***) - - SUBGOAL_THEN `2 * 2 * 2 * nn DIV 8 = nn` SUBST_ALL_TAC THENL - [REWRITE_TAC[ARITH_RULE `2 * 2 * 2 * nn DIV 8 = nn <=> nn MOD 8 = 0`] THEN - EXPAND_TAC "nn" THEN - REWRITE_TAC[ARITH_RULE `2 EXP 254 = 8 * 2 EXP 251`; MOD_MULT_MOD] THEN - REWRITE_TAC[ADD_SUB; GSYM LEFT_ADD_DISTRIB; MOD_MULT]; - ALL_TAC] THEN - SUBGOAL_THEN `X < 2 * p_25519` ASSUME_TAC THENL - [FIRST_X_ASSUM(MP_TAC o MATCH_MP (ARITH_RULE - `Y MOD 2 EXP 255 = X ==> X < 2 EXP 255`)) THEN - REWRITE_TAC[p_25519] THEN ARITH_TAC; + (*** The trivial loop-back subgoal ***) + + REPEAT STRIP_TAC THEN + REWRITE_TAC[normalized_ubignum_preglist; normalized_ubignum_preglist'; + normalized_ubignum_qreglist; normalized_ubignum_qreglist'; + normalized_ubignum_int32list; normalized_ubignum_int32list'; + normalized_ubignum_list; normalized_ubignum_list'; + MAP; ubignum_of_list] THEN + ARM_SIM_TAC CURVE25519_X25519_EXEC [1]; + ALL_TAC] THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o - check (vfree_in `n_input:num`) o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o - check (vfree_in `X_input:num`) o concl)) THEN + (*** Now the final recoding, inversion and multiplication ***) + + REWRITE_TAC[normalized_ubignum_qreglist; normalized_ubignum_qreglist'; + normalized_ubignum_int32list; normalized_ubignum_int32list'; + normalized_ubignum_list; normalized_ubignum_list'; + LT_REFL; MAP; ubignum_of_list] THEN + GHOST_INTRO_TAC `q0:int128` `read Q0` THEN + GHOST_INTRO_TAC `q1:int128` `read Q1` THEN + GHOST_INTRO_TAC `q2:int128` `read Q2` THEN + GHOST_INTRO_TAC `q3:int128` `read Q3` THEN + GHOST_INTRO_TAC `q4:int128` `read Q4` THEN + GHOST_INTRO_TAC `q5:int128` `read Q5` THEN + GHOST_INTRO_TAC `q6:int128` `read Q6` THEN + GHOST_INTRO_TAC `q7:int128` `read Q7` THEN + GHOST_INTRO_TAC `q8:int128` `read Q8` THEN + GHOST_INTRO_TAC `q9:int128` `read Q9` THEN + REWRITE_TAC(!simulation_precanon_thms) THEN ENSURES_INIT_TAC "s0" THEN - (*** The inlining of modular inverse ***) + (*** Recoding of X2 -> xn ***) - ARM_STEPS_TAC CURVE25519_X25519_EXEC (36--37) THEN - LOCAL_MODINV_TAC 38 THEN - FIRST_X_ASSUM(ASSUME_TAC o MATCH_MP(MESON[PRIME_COPRIME_EQ; PRIME_P25519] - `(bnx = if p_25519 divides n then 0 else inverse_mod p_25519 n) - ==> coprime(p_25519,n) ==> bnx = inverse_mod p_25519 n`)) THEN + ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC + [12;13;14;15;16;17;18;20;21;23;24;26] (1--28) THEN + SUBGOAL_THEN + `(&(bignum_from_memory(word_add stackpointer (word 128),4) s28):int == + ladder_x2 X nn 0) (mod (&p_25519))` + MP_TAC THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THENL + [CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN + FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INTEGER_RULE + `(x:int == n) (mod p) ==> x' = x ==> (x':int == n) (mod p)`)) THEN + REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN + MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN + CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN + CONJ_TAC THENL [ASM BOUNDER_TAC[]; ALL_TAC] THEN + REWRITE_TAC[REAL_CONGRUENCE; EXP_EQ_0; ARITH_EQ] THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN + REWRITE_TAC[VAL_WORD_SHL; VAL_WORD_ZX_GEN; DIMINDEX_64] THEN + REPEAT DEMODULATE_TAC THEN + REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + REWRITE_TAC[REAL_OF_NUM_MOD; GSYM REAL_OF_NUM_CLAUSES] THEN + STRIP_TAC THEN + ACCUMULATOR_ASSUM_LIST(fun ths -> ASSUM_LIST (fun thc -> + MP_TAC(end_itlist CONJ (GEN_DECARRY_RULE thc ths)))) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; + ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN ABBREV_TAC - `zn' = - read(memory :> bytes(word_add stackpointer (word 224),8 * 4)) s38` THEN - - (*** The tweaking to force xn = 0 whenever zn = 0 ***) + `x2 = + read(memory :> bytes(word_add stackpointer (word 128),8 * 4)) s28` THEN + DISCH_TAC THEN - BIGNUM_LDIGITIZE_TAC "xn_" - `read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s38` THEN - BIGNUM_LDIGITIZE_TAC "zn_" - `read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s38` THEN - ARM_STEPS_TAC CURVE25519_X25519_EXEC (39--52) THEN + (*** Recoding of Z2 -> zn, similar but slightly more elaborate ***) + ARM_ACCSTEPS_TAC CURVE25519_X25519_EXEC + [40;42;44;46;47;48;49;50;52;53;55;56;58] (29--60) THEN SUBGOAL_THEN - `read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s52 = - if zn = 0 then 0 else xn` - ASSUME_TAC THENL - [CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN - ASM_REWRITE_TAC[] THEN MAP_EVERY EXPAND_TAC ["zn"; "xn"] THEN - REWRITE_TAC[WORD_SUB_0; VAL_EQ_0; WORD_OR_EQ_0] THEN - REWRITE_TAC[BIGNUM_OF_WORDLIST_EQ_0; ALL] THEN - REWRITE_TAC[COND_SWAP; CONJ_ACI] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[bignum_of_wordlist] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV); - ALL_TAC] THEN + `(&(bignum_from_memory(word_add stackpointer (word 160),4) s60):int == + ladder_z2 X nn 0) (mod (&p_25519))` + MP_TAC THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THENL + [CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN + FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INTEGER_RULE + `(x:int == n) (mod p) + ==> (x' == x) (mod p) ==> (x':int == n) (mod p)`)) THEN + REWRITE_TAC[INT_OF_NUM_CLAUSES; GSYM num_congruent] THEN + MP_TAC(SPEC `word_subword (q9:int128) (32,32):int32` (WORD_BLAST + `!x:int32. val x <= 67108863 + ==> val x = 2 EXP 25 * bitval(bit 25 x) + val x MOD 2 EXP 25`)) THEN + ASM_REWRITE_TAC[] THEN DISCH_THEN SUBST1_TAC THEN + MATCH_MP_TAC(NUMBER_RULE `!d:num. x + d * p = y ==> (x == y) (mod p)`) THEN + EXISTS_TAC `bitval(bit 25 (word_subword (q9:int128) (32,32):int32))` THEN + REWRITE_TAC[ADD_ASSOC] THEN MATCH_MP_TAC(ARITH_RULE + `b * 2 EXP 255 = b * p_25519 + b * 19 /\ + x = y + 2 EXP 230 * c + 19 * b + ==> x + b * p_25519 = y + 2 EXP 230 * (2 EXP 25 * b + c)`) THEN + CONJ_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC] THEN + REWRITE_TAC[GSYM ADD_ASSOC] THEN + MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN + CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN + CONJ_TAC THENL [ASM BOUNDER_TAC[]; ALL_TAC] THEN + REWRITE_TAC[REAL_CONGRUENCE; EXP_EQ_0; ARITH_EQ] THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN + REWRITE_TAC[VAL_WORD_SHL; WORD_BLAST + `val(word_and x (word 33554431):int64) = val x MOD 2 EXP 25`] THEN + REWRITE_TAC[WORD_BLAST + `val(word_and (word_zx (x:int32)) (word 33554432):int64) = + 2 EXP 25 * bitval(bit 25 x)`] THEN + REWRITE_TAC[MULT_EQ_0; EXP_EQ_0; BITVAL_EQ_0; ARITH_EQ] THEN + REWRITE_TAC[VAL_WORD_SHL; VAL_WORD_ZX_GEN; DIMINDEX_64] THEN + REPEAT DEMODULATE_TAC THEN + REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + REWRITE_TAC[REAL_OF_NUM_MOD; GSYM REAL_OF_NUM_CLAUSES] THEN + COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN + CONV_TAC WORD_REDUCE_CONV THEN + STRIP_TAC THEN + ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN + CONV_TAC(RAND_CONV REAL_POLY_CONV) THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN + DISCH_THEN(MP_TAC o end_itlist CONJ o + filter (is_ratconst o rand o concl) o CONJUNCTS) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; + ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN + ABBREV_TAC + `z2 = + read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s60` THEN + DISCH_TAC THEN - (*** Final multiplication ***) + (*** Inlined modular inverse ***) - LOCAL_MUL_P25519_TAC 0 ["resx"; "xn"; "xm"] THEN + ARM_STEPS_TAC CURVE25519_X25519_EXEC (61--62) THEN + LOCAL_MODINV_TAC 63 THEN + ABBREV_TAC + `zn' = + read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s63` THEN - (*** Completing the mathematics ***) + (*** Inlined final field multiplication ***) - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC SYM_CONV THEN MATCH_MP_TAC PUREX25519_UNIQUE_IMP THEN - CONJ_TAC THENL [REWRITE_TAC[MOD_LT_EQ; p_25519] THEN ARITH_TAC; ALL_TAC] THEN - MAP_EVERY X_GEN_TAC [`f:(int#int)ring`; `P:((int#int)#(int#int))option`] THEN - - ASM_CASES_TAC `X MOD p_25519 = 0` THEN - ASM_REWRITE_TAC[RING_OF_NUM_0] THEN STRIP_TAC THENL - [MP_TAC(ISPECL - [`f:(int#int)ring`; `ring_of_num f A_25519:int#int`; - `ring_of_num f 1:int#int`; `P:((int#int)#(int#int))option`; - `nn:num`] MONTGOMERY_XMAP_EQ_0_POW) THEN - ASM_REWRITE_TAC[GSYM curve25519x_group; GSYM curve25519x] THEN - ASM_SIMP_TAC[MONTGOMERY_NONSINGULAR_CURVE25519X; RING_OF_NUM] THEN - ANTS_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC] THEN - DISCH_THEN SUBST1_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int)ring`; `SOME(ring_0 f:int#int,ring_0 f)`]) THEN - ASM_REWRITE_TAC[] THEN ANTS_TAC THENL - [REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - ASM_SIMP_TAC[CURVE25519X_GROUP; montgomery_xz] THEN - GEN_REWRITE_TAC LAND_CONV [IN] THEN - REWRITE_TAC[montgomery_curve; RING_OF_NUM; curve25519x] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_NUM_MOD] THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[p_25519; A_25519] THEN CONV_TAC NUM_REDUCE_CONV THEN - ASM_SIMP_TAC[RING_OF_NUM_1; RING_OF_NUM_0; FIELD_NONTRIVIAL; RING_0] THEN - UNDISCH_TAC `field(f:(int#int)ring)` THEN POP_ASSUM_LIST(K ALL_TAC) THEN - REPEAT STRIP_TAC THEN FIELD_TAC; - ASM_SIMP_TAC[MOD_LT]] THEN - COND_CASES_TAC THEN - ASM_REWRITE_TAC[MOD_0; RING_OF_NUM_0; MULT_CLAUSES] THEN - ONCE_REWRITE_TAC[GSYM MOD_MULT_MOD2] THEN - SIMP_TAC[MOD_0; RING_OF_NUM_0; MULT_CLAUSES]; - ALL_TAC] THEN + LOCAL_MUL_P25519_TAC 1 ["resx"; "xn"; "zn"] THEN - FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int)ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN ANTS_TAC THENL - [ASM_REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[RING_OF_NUM_1] THEN - W(MP_TAC o PART_MATCH (lhand o rand) MONTGOMERY_XZ_XMAP o snd) THEN - ASM_REWRITE_TAC[RING_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_NUM_MOD] THEN - ASM_REWRITE_TAC[MOD_MOD_REFL] THEN - DISCH_THEN MATCH_MP_TAC THEN - ASM_REWRITE_TAC[RING_OF_NUM_EQ_0; DIVIDES_MOD] THEN - ASM_SIMP_TAC[MOD_LT; MOD_MOD_REFL]; - ALL_TAC] THEN + (*** Completing the mathematics ***) - REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - REPEAT(DISCH_THEN(CONJUNCTS_THEN2 ASSUME_TAC MP_TAC)) THEN - FIRST_X_ASSUM(MP_TAC o SPEC `nn:num` o MATCH_MP GROUP_POW) THEN - SPEC_TAC(`group_pow (curve25519x_group(f:(int#int)ring)) P nn`, - `Q:((int#int)#(int#int))option`) THEN - REWRITE_TAC[FORALL_OPTION_THM] THEN - GEN_REWRITE_TAC RAND_CONV [FORALL_PAIR_THM] THEN - REWRITE_TAC[montgomery_xz; montgomery_xmap] THEN - ASM_SIMP_TAC[RING_OF_NUM_EQ_0; DIVIDES_MOD; MOD_LT] THEN - REWRITE_TAC[RING_OF_NUM] THEN ONCE_REWRITE_TAC[IN] THEN - ASM_SIMP_TAC[CURVE25519X_GROUP] THEN - REWRITE_TAC[montgomery_curve; curve25519x] THEN - SIMP_TAC[MULT_CLAUSES; MOD_0; RING_OF_NUM_0] THEN - MAP_EVERY X_GEN_TAC [`u:int#int`; `v:int#int`] THEN - STRIP_TAC THEN - DISCH_THEN(CONJUNCTS_THEN2 ASSUME_TAC (SUBST1_TAC o SYM)) THEN - MP_TAC(ISPEC `f:(int#int)ring` RING_OF_NUM_MOD) THEN - ASM_SIMP_TAC[RING_OF_NUM_MUL] THEN DISCH_THEN(K ALL_TAC) THEN - REWRITE_TAC[ring_div] THEN AP_TERM_TAC THEN - MATCH_MP_TAC RING_RINV_UNIQUE THEN - REWRITE_TAC[RING_OF_NUM; GSYM RING_OF_NUM_MUL] THEN - REWRITE_TAC[GSYM RING_OF_NUM_1; RING_OF_NUM_EQ] THEN - FIRST_X_ASSUM(MP_TAC o check (is_imp o concl)) THEN - ASM_REWRITE_TAC[] THEN - MATCH_MP_TAC(TAUT `(p /\ q ==> r) /\ p ==> (p ==> q) ==> r`) THEN - CONJ_TAC THENL [MESON_TAC[INVERSE_MOD_RMUL]; ALL_TAC] THEN - SIMP_TAC[PRIME_COPRIME_EQ; PRIME_P25519] THEN - ASM_SIMP_TAC[DIVIDES_MOD; MOD_LT] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV);; + ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN + CONV_TAC SYM_CONV THEN REWRITE_TAC[PUREX25519_MOD] THEN + REWRITE_TAC[GSYM deproject] THEN MATCH_MP_TAC DEPROJECT_LADDER_EVEN THEN + ASM_REWRITE_TAC[] THEN EXPAND_TAC "nn" THEN + CONJ_TAC THENL [ARITH_TAC; ALL_TAC] THEN + SIMP_TAC[EVEN_ADD; EVEN_SUB; EVEN_EXP; ARITH; EVEN_MOD_EVEN]);; let CURVE25519_X25519_SUBROUTINE_CORRECT = time prove (`!res scalar n point X pc stackpointer returnaddress. aligned 16 stackpointer /\ - ALL (nonoverlapping (word_sub stackpointer (word 368),368)) - [(word pc,0x571c); (res,32); (scalar,32); (point,32)] /\ - nonoverlapping (res,32) (word pc,0x571c) + ALL (nonoverlapping (word_sub stackpointer (word 384),384)) + [(word pc,0x2554); (res,32); (scalar,32); (point,32)] /\ + nonoverlapping (res,32) (word pc,0x2554) ==> ensures arm (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_mc /\ read PC s = word pc /\ @@ -8197,7 +4760,8 @@ let CURVE25519_X25519_SUBROUTINE_CORRECT = time prove bignum_from_memory (res,4) s = rfcx25519(n,X)) (MAYCHANGE_REGS_AND_FLAGS_PERMITTED_BY_ABI ,, MAYCHANGE [memory :> bytes(res,32); - memory :> bytes(word_sub stackpointer (word 368),368)])`, + memory :> bytes(word_sub stackpointer (word 384),384)])`, ARM_ADD_RETURN_STACK_TAC CURVE25519_X25519_EXEC CURVE25519_X25519_CORRECT - `[X19; X20; X21; X22; X23; X24]` 368);; + `[D8; D9; D10; D11; D12; D13; D14; D15; + X19; X20; X21; X22; X23; X24; X25; X26; X27; X28; X29; X30]` 384);; diff --git a/arm/proofs/curve25519_x25519_byte.ml b/arm/proofs/curve25519_x25519_byte.ml index 656a9839..6daedfcc 100644 --- a/arm/proofs/curve25519_x25519_byte.ml +++ b/arm/proofs/curve25519_x25519_byte.ml @@ -12,6 +12,8 @@ needs "arm/proofs/bignum_inv_p25519.ml";; needs "common/ecencoding.ml";; do_list hide_constant ["X1";"X2";"X3";"X4";"X5"];; +needs "EC/curve25519.ml";; +needs "EC/formulary_xzprojective.ml";; needs "EC/x25519.ml";; do_list unhide_constant ["X1";"X2";"X3";"X4";"X5"];; @@ -19,17 +21,28 @@ prioritize_int();; prioritize_real();; prioritize_num();; +(* ------------------------------------------------------------------------- *) +(* The code. *) +(* ------------------------------------------------------------------------- *) + (**** print_literal_from_elf "arm/curve25519/curve25519_x25519_byte.o";; ****) let curve25519_x25519_byte_mc = define_assert_from_elf "curve25519_x25519_byte_mc" "arm/curve25519/curve25519_x25519_byte.o" [ - 0xa9bf53f3; (* arm_STP X19 X20 SP (Preimmediate_Offset (iword (-- &16))) *) - 0xa9bf5bf5; (* arm_STP X21 X22 SP (Preimmediate_Offset (iword (-- &16))) *) - 0xa9bf63f7; (* arm_STP X23 X24 SP (Preimmediate_Offset (iword (-- &16))) *) - 0xd10503ff; (* arm_SUB SP SP (rvalue (word 320)) *) - 0xaa0003f7; (* arm_MOV X23 X0 *) + 0xd10603ff; (* arm_SUB SP SP (rvalue (word 384)) *) + 0x6d0e27e8; (* arm_STP D8 D9 SP (Immediate_Offset (iword (&224))) *) + 0x6d0f2fea; (* arm_STP D10 D11 SP (Immediate_Offset (iword (&240))) *) + 0x6d1037ec; (* arm_STP D12 D13 SP (Immediate_Offset (iword (&256))) *) + 0x6d113fee; (* arm_STP D14 D15 SP (Immediate_Offset (iword (&272))) *) + 0xa91253f3; (* arm_STP X19 X20 SP (Immediate_Offset (iword (&288))) *) + 0xa9135bf5; (* arm_STP X21 X22 SP (Immediate_Offset (iword (&304))) *) + 0xa91463f7; (* arm_STP X23 X24 SP (Immediate_Offset (iword (&320))) *) + 0xa9156bf9; (* arm_STP X25 X26 SP (Immediate_Offset (iword (&336))) *) + 0xa91673fb; (* arm_STP X27 X28 SP (Immediate_Offset (iword (&352))) *) + 0xa9177bfd; (* arm_STP X29 X30 SP (Immediate_Offset (iword (&368))) *) + 0xf90063e0; (* arm_STR X0 SP (Immediate_Offset (word 192)) *) 0x3940002a; (* arm_LDRB W10 X1 (Immediate_Offset (word 0)) *) 0x39400420; (* arm_LDRB W0 X1 (Immediate_Offset (word 1)) *) 0xaa00214a; (* arm_ORR X10 X10 (Shiftedreg X0 LSL 8) *) @@ -60,6 +73,7 @@ let curve25519_x25519_byte_mc = define_assert_from_elf 0xaa00c16b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 48) *) 0x39403c20; (* arm_LDRB W0 X1 (Immediate_Offset (word 15)) *) 0xaa00e16b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 56) *) + 0x927df14a; (* arm_AND X10 X10 (rvalue (word 18446744073709551608)) *) 0xa9002fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&0))) *) 0x3940402c; (* arm_LDRB W12 X1 (Immediate_Offset (word 16)) *) 0x39404420; (* arm_LDRB W0 X1 (Immediate_Offset (word 17)) *) @@ -91,6332 +105,3496 @@ let curve25519_x25519_byte_mc = define_assert_from_elf 0xaa00c1ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 48) *) 0x39407c20; (* arm_LDRB W0 X1 (Immediate_Offset (word 31)) *) 0xaa00e1ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 56) *) + 0xb24201ad; (* arm_ORR X13 X13 (rvalue (word 4611686018427387904)) *) 0xa90137ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&16))) *) - 0x3940004a; (* arm_LDRB W10 X2 (Immediate_Offset (word 0)) *) + 0x39400044; (* arm_LDRB W4 X2 (Immediate_Offset (word 0)) *) 0x39400440; (* arm_LDRB W0 X2 (Immediate_Offset (word 1)) *) - 0xaa00214a; (* arm_ORR X10 X10 (Shiftedreg X0 LSL 8) *) + 0xaa002084; (* arm_ORR X4 X4 (Shiftedreg X0 LSL 8) *) 0x39400840; (* arm_LDRB W0 X2 (Immediate_Offset (word 2)) *) - 0xaa00414a; (* arm_ORR X10 X10 (Shiftedreg X0 LSL 16) *) + 0xaa004084; (* arm_ORR X4 X4 (Shiftedreg X0 LSL 16) *) 0x39400c40; (* arm_LDRB W0 X2 (Immediate_Offset (word 3)) *) - 0xaa00614a; (* arm_ORR X10 X10 (Shiftedreg X0 LSL 24) *) + 0xaa006084; (* arm_ORR X4 X4 (Shiftedreg X0 LSL 24) *) 0x39401040; (* arm_LDRB W0 X2 (Immediate_Offset (word 4)) *) - 0xaa00814a; (* arm_ORR X10 X10 (Shiftedreg X0 LSL 32) *) + 0xaa008084; (* arm_ORR X4 X4 (Shiftedreg X0 LSL 32) *) 0x39401440; (* arm_LDRB W0 X2 (Immediate_Offset (word 5)) *) - 0xaa00a14a; (* arm_ORR X10 X10 (Shiftedreg X0 LSL 40) *) + 0xaa00a084; (* arm_ORR X4 X4 (Shiftedreg X0 LSL 40) *) 0x39401840; (* arm_LDRB W0 X2 (Immediate_Offset (word 6)) *) - 0xaa00c14a; (* arm_ORR X10 X10 (Shiftedreg X0 LSL 48) *) + 0xaa00c084; (* arm_ORR X4 X4 (Shiftedreg X0 LSL 48) *) 0x39401c40; (* arm_LDRB W0 X2 (Immediate_Offset (word 7)) *) - 0xaa00e14a; (* arm_ORR X10 X10 (Shiftedreg X0 LSL 56) *) - 0x3940204b; (* arm_LDRB W11 X2 (Immediate_Offset (word 8)) *) + 0xaa00e084; (* arm_ORR X4 X4 (Shiftedreg X0 LSL 56) *) + 0x39402045; (* arm_LDRB W5 X2 (Immediate_Offset (word 8)) *) 0x39402440; (* arm_LDRB W0 X2 (Immediate_Offset (word 9)) *) - 0xaa00216b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 8) *) + 0xaa0020a5; (* arm_ORR X5 X5 (Shiftedreg X0 LSL 8) *) 0x39402840; (* arm_LDRB W0 X2 (Immediate_Offset (word 10)) *) - 0xaa00416b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 16) *) + 0xaa0040a5; (* arm_ORR X5 X5 (Shiftedreg X0 LSL 16) *) 0x39402c40; (* arm_LDRB W0 X2 (Immediate_Offset (word 11)) *) - 0xaa00616b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 24) *) + 0xaa0060a5; (* arm_ORR X5 X5 (Shiftedreg X0 LSL 24) *) 0x39403040; (* arm_LDRB W0 X2 (Immediate_Offset (word 12)) *) - 0xaa00816b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 32) *) + 0xaa0080a5; (* arm_ORR X5 X5 (Shiftedreg X0 LSL 32) *) 0x39403440; (* arm_LDRB W0 X2 (Immediate_Offset (word 13)) *) - 0xaa00a16b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 40) *) + 0xaa00a0a5; (* arm_ORR X5 X5 (Shiftedreg X0 LSL 40) *) 0x39403840; (* arm_LDRB W0 X2 (Immediate_Offset (word 14)) *) - 0xaa00c16b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 48) *) + 0xaa00c0a5; (* arm_ORR X5 X5 (Shiftedreg X0 LSL 48) *) 0x39403c40; (* arm_LDRB W0 X2 (Immediate_Offset (word 15)) *) - 0xaa00e16b; (* arm_ORR X11 X11 (Shiftedreg X0 LSL 56) *) - 0xa9022fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&32))) *) - 0x3940404c; (* arm_LDRB W12 X2 (Immediate_Offset (word 16)) *) + 0xaa00e0a5; (* arm_ORR X5 X5 (Shiftedreg X0 LSL 56) *) + 0x39404046; (* arm_LDRB W6 X2 (Immediate_Offset (word 16)) *) 0x39404440; (* arm_LDRB W0 X2 (Immediate_Offset (word 17)) *) - 0xaa00218c; (* arm_ORR X12 X12 (Shiftedreg X0 LSL 8) *) + 0xaa0020c6; (* arm_ORR X6 X6 (Shiftedreg X0 LSL 8) *) 0x39404840; (* arm_LDRB W0 X2 (Immediate_Offset (word 18)) *) - 0xaa00418c; (* arm_ORR X12 X12 (Shiftedreg X0 LSL 16) *) + 0xaa0040c6; (* arm_ORR X6 X6 (Shiftedreg X0 LSL 16) *) 0x39404c40; (* arm_LDRB W0 X2 (Immediate_Offset (word 19)) *) - 0xaa00618c; (* arm_ORR X12 X12 (Shiftedreg X0 LSL 24) *) + 0xaa0060c6; (* arm_ORR X6 X6 (Shiftedreg X0 LSL 24) *) 0x39405040; (* arm_LDRB W0 X2 (Immediate_Offset (word 20)) *) - 0xaa00818c; (* arm_ORR X12 X12 (Shiftedreg X0 LSL 32) *) + 0xaa0080c6; (* arm_ORR X6 X6 (Shiftedreg X0 LSL 32) *) 0x39405440; (* arm_LDRB W0 X2 (Immediate_Offset (word 21)) *) - 0xaa00a18c; (* arm_ORR X12 X12 (Shiftedreg X0 LSL 40) *) + 0xaa00a0c6; (* arm_ORR X6 X6 (Shiftedreg X0 LSL 40) *) 0x39405840; (* arm_LDRB W0 X2 (Immediate_Offset (word 22)) *) - 0xaa00c18c; (* arm_ORR X12 X12 (Shiftedreg X0 LSL 48) *) + 0xaa00c0c6; (* arm_ORR X6 X6 (Shiftedreg X0 LSL 48) *) 0x39405c40; (* arm_LDRB W0 X2 (Immediate_Offset (word 23)) *) - 0xaa00e18c; (* arm_ORR X12 X12 (Shiftedreg X0 LSL 56) *) - 0x3940604d; (* arm_LDRB W13 X2 (Immediate_Offset (word 24)) *) + 0xaa00e0c6; (* arm_ORR X6 X6 (Shiftedreg X0 LSL 56) *) + 0x39406047; (* arm_LDRB W7 X2 (Immediate_Offset (word 24)) *) 0x39406440; (* arm_LDRB W0 X2 (Immediate_Offset (word 25)) *) - 0xaa0021ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 8) *) + 0xaa0020e7; (* arm_ORR X7 X7 (Shiftedreg X0 LSL 8) *) 0x39406840; (* arm_LDRB W0 X2 (Immediate_Offset (word 26)) *) - 0xaa0041ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 16) *) + 0xaa0040e7; (* arm_ORR X7 X7 (Shiftedreg X0 LSL 16) *) 0x39406c40; (* arm_LDRB W0 X2 (Immediate_Offset (word 27)) *) - 0xaa0061ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 24) *) + 0xaa0060e7; (* arm_ORR X7 X7 (Shiftedreg X0 LSL 24) *) 0x39407040; (* arm_LDRB W0 X2 (Immediate_Offset (word 28)) *) - 0xaa0081ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 32) *) + 0xaa0080e7; (* arm_ORR X7 X7 (Shiftedreg X0 LSL 32) *) 0x39407440; (* arm_LDRB W0 X2 (Immediate_Offset (word 29)) *) - 0xaa00a1ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 40) *) + 0xaa00a0e7; (* arm_ORR X7 X7 (Shiftedreg X0 LSL 40) *) 0x39407840; (* arm_LDRB W0 X2 (Immediate_Offset (word 30)) *) - 0xaa00c1ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 48) *) + 0xaa00c0e7; (* arm_ORR X7 X7 (Shiftedreg X0 LSL 48) *) 0x39407c40; (* arm_LDRB W0 X2 (Immediate_Offset (word 31)) *) - 0xaa00e1ad; (* arm_ORR X13 X13 (Shiftedreg X0 LSL 56) *) - 0x9240f9ad; (* arm_AND X13 X13 (rvalue (word 9223372036854775807)) *) + 0xaa00e0e7; (* arm_ORR X7 X7 (Shiftedreg X0 LSL 56) *) + 0xd373fc8c; (* arm_LSR X12 X4 51 *) + 0xd373fcd1; (* arm_LSR X17 X6 51 *) + 0xaa05358c; (* arm_ORR X12 X12 (Shiftedreg X5 LSL 13) *) + 0xaa073631; (* arm_ORR X17 X17 (Shiftedreg X7 LSL 13) *) + 0xd34c94e8; (* arm_UBFM X8 X7 12 37 *) + 0xd366f8e9; (* arm_UBFM X9 X7 38 62 *) + 0xd35ac88b; (* arm_UBFM X11 X4 26 50 *) + 0xd34d94ad; (* arm_UBFM X13 X5 13 37 *) + 0xd366fcae; (* arm_LSR X14 X5 38 *) + 0xd359c8d0; (* arm_UBFM X16 X6 25 50 *) + 0x9240648a; (* arm_AND X10 X4 (rvalue (word 67108863)) *) + 0x9240658c; (* arm_AND X12 X12 (rvalue (word 67108863)) *) + 0x924060cf; (* arm_AND X15 X6 (rvalue (word 33554431)) *) + 0x92406231; (* arm_AND X17 X17 (rvalue (word 33554431)) *) + 0xaa0b814a; (* arm_ORR X10 X10 (Shiftedreg X11 LSL 32) *) + 0xaa0d818b; (* arm_ORR X11 X12 (Shiftedreg X13 LSL 32) *) + 0xaa0f81cc; (* arm_ORR X12 X14 (Shiftedreg X15 LSL 32) *) + 0xaa11820d; (* arm_ORR X13 X16 (Shiftedreg X17 LSL 32) *) + 0xaa09810e; (* arm_ORR X14 X8 (Shiftedreg X9 LSL 32) *) + 0xa9022fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&32))) *) 0xa90337ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&48))) *) - 0xd2800035; (* arm_MOV X21 (rvalue (word 1)) *) - 0xa90e2fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&224))) *) - 0xa90f37ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&240))) *) - 0xa9047ff5; (* arm_STP X21 XZR SP (Immediate_Offset (iword (&64))) *) - 0xa9057fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&80))) *) - 0xa94e1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&224))) *) - 0xa9440fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&64))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa94f23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&240))) *) - 0xa9450fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&80))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9101be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0xa91123e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xa94e13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&224))) *) - 0xa94423e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&64))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa94f1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&240))) *) - 0xa94523e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&80))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa91213e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9131be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) + 0xf90023ee; (* arm_STR X14 SP (Immediate_Offset (word 64)) *) + 0xd2800021; (* arm_MOV X1 (rvalue (word 1)) *) + 0x4e081c20; (* arm_INS_GEN Q0 X1 0 64 *) + 0x4e081fe2; (* arm_INS_GEN Q2 XZR 0 64 *) + 0x4e081fe4; (* arm_INS_GEN Q4 XZR 0 64 *) + 0x4e081fe6; (* arm_INS_GEN Q6 XZR 0 64 *) + 0x4e081fe8; (* arm_INS_GEN Q8 XZR 0 64 *) + 0x4e081fe1; (* arm_INS_GEN Q1 XZR 0 64 *) + 0x4e081fe3; (* arm_INS_GEN Q3 XZR 0 64 *) + 0x4e081fe5; (* arm_INS_GEN Q5 XZR 0 64 *) + 0x4e081fe7; (* arm_INS_GEN Q7 XZR 0 64 *) + 0x4e081fe9; (* arm_INS_GEN Q9 XZR 0 64 *) + 0x4e081d4a; (* arm_INS_GEN Q10 X10 0 64 *) + 0x4e081d6c; (* arm_INS_GEN Q12 X11 0 64 *) + 0x4e081d8e; (* arm_INS_GEN Q14 X12 0 64 *) + 0x4e081db0; (* arm_INS_GEN Q16 X13 0 64 *) + 0x4e081dd2; (* arm_INS_GEN Q18 X14 0 64 *) + 0x4e081c2b; (* arm_INS_GEN Q11 X1 0 64 *) + 0x4e081fed; (* arm_INS_GEN Q13 XZR 0 64 *) + 0x4e081fef; (* arm_INS_GEN Q15 XZR 0 64 *) + 0x4e081ff1; (* arm_INS_GEN Q17 XZR 0 64 *) + 0x4e081ff3; (* arm_INS_GEN Q19 XZR 0 64 *) + 0x52800260; (* arm_MOV W0 (rvalue (word 19)) *) + 0x8b008000; (* arm_ADD X0 X0 (Shiftedreg X0 LSL 32) *) + 0x4e081c1f; (* arm_INS_GEN Q31 X0 0 64 *) + 0x4e181fff; (* arm_INS_GEN Q31 XZR 64 64 *) + 0xb24067e0; (* arm_MOV X0 (rvalue (word 67108863)) *) + 0x4e081c1e; (* arm_INS_GEN Q30 X0 0 64 *) + 0x4e181c1e; (* arm_INS_GEN Q30 X0 64 64 *) + 0xb21f67e0; (* arm_MOV X0 (rvalue (word 576460743847706622)) *) + 0xd1012801; (* arm_SUB X1 X0 (rvalue (word 74)) *) + 0xd1000800; (* arm_SUB X0 X0 (rvalue (word 2)) *) + 0xa90487e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&72))) *) + 0x6d44f3fd; (* arm_LDP D29 D28 SP (Immediate_Offset (iword (&72))) *) + 0xf9006bff; (* arm_STR XZR SP (Immediate_Offset (word 208)) *) + 0xd2801fc0; (* arm_MOV X0 (rvalue (word 254)) *) + 0xf90067e0; (* arm_STR X0 SP (Immediate_Offset (word 200)) *) + 0xd346fc01; (* arm_LSR X1 X0 6 *) + 0xf8617be2; (* arm_LDR X2 SP (Shiftreg_Offset X1 3) *) + 0x9ac02442; (* arm_LSRV X2 X2 X0 *) + 0x92400042; (* arm_AND X2 X2 (rvalue (word 1)) *) + 0xf9406be0; (* arm_LDR X0 SP (Immediate_Offset (word 208)) *) + 0xeb02001f; (* arm_CMP X0 X2 *) + 0xf9006be2; (* arm_STR X2 SP (Immediate_Offset (word 208)) *) + 0x0ea38456; (* arm_ADD_VEC Q22 Q2 Q3 32 64 *) + 0x2ea18795; (* arm_SUB_VEC Q21 Q28 Q1 32 64 *) + 0x0ea18419; (* arm_ADD_VEC Q25 Q0 Q1 32 64 *) + 0x2ea387b8; (* arm_SUB_VEC Q24 Q29 Q3 32 64 *) + 0x0eb38643; (* arm_ADD_VEC Q3 Q18 Q19 32 64 *) + 0x0eb58400; (* arm_ADD_VEC Q0 Q0 Q21 32 64 *) + 0x2eaf87b4; (* arm_SUB_VEC Q20 Q29 Q15 32 64 *) + 0x2ea587a1; (* arm_SUB_VEC Q1 Q29 Q5 32 64 *) + 0x2eab879a; (* arm_SUB_VEC Q26 Q28 Q11 32 64 *) + 0x2eb387b5; (* arm_SUB_VEC Q21 Q29 Q19 32 64 *) + 0x0eab8553; (* arm_ADD_VEC Q19 Q10 Q11 32 64 *) + 0x0eb485cb; (* arm_ADD_VEC Q11 Q14 Q20 32 64 *) + 0x0eb58655; (* arm_ADD_VEC Q21 Q18 Q21 32 64 *) + 0x2eb187b4; (* arm_SUB_VEC Q20 Q29 Q17 32 64 *) + 0x0eb88452; (* arm_ADD_VEC Q18 Q2 Q24 32 64 *) + 0x0eaf85ce; (* arm_ADD_VEC Q14 Q14 Q15 32 64 *) + 0x0eb1860f; (* arm_ADD_VEC Q15 Q16 Q17 32 64 *) + 0x0eb48602; (* arm_ADD_VEC Q2 Q16 Q20 32 64 *) + 0x0ead8598; (* arm_ADD_VEC Q24 Q12 Q13 32 64 *) + 0x0eba855a; (* arm_ADD_VEC Q26 Q10 Q26 32 64 *) + 0x2ead87aa; (* arm_SUB_VEC Q10 Q29 Q13 32 64 *) + 0x2ea787ad; (* arm_SUB_VEC Q13 Q29 Q7 32 64 *) + 0x0ea784d7; (* arm_ADD_VEC Q23 Q6 Q7 32 64 *) + 0x2ea987a7; (* arm_SUB_VEC Q7 Q29 Q9 32 64 *) + 0x0eaa859b; (* arm_ADD_VEC Q27 Q12 Q10 32 64 *) + 0x1e780ed4; (* arm_FCSEL Q20 Q22 Q24 Condition_EQ 64 *) + 0x0ea5849c; (* arm_ADD_VEC Q28 Q4 Q5 32 64 *) + 0x1e6f0eec; (* arm_FCSEL Q12 Q23 Q15 Condition_EQ 64 *) + 0x0ea78507; (* arm_ADD_VEC Q7 Q8 Q7 32 64 *) + 0x1e730f30; (* arm_FCSEL Q16 Q25 Q19 Condition_EQ 64 *) + 0x4e083e80; (* arm_UMOV X0 Q20 0 8 *) + 0x1e6e0f85; (* arm_FCSEL Q5 Q28 Q14 Condition_EQ 64 *) + 0x4e083d95; (* arm_UMOV X21 Q12 0 8 *) + 0x1e750cfd; (* arm_FCSEL Q29 Q7 Q21 Condition_EQ 64 *) + 0x4e083e05; (* arm_UMOV X5 Q16 0 8 *) + 0xd360fc1a; (* arm_LSR X26 X0 32 *) + 0x8b1502bd; (* arm_ADD X29 X21 X21 *) + 0x9bbd7caf; (* arm_UMULL X15 W5 W29 *) + 0x0ead84cd; (* arm_ADD_VEC Q13 Q6 Q13 32 64 *) + 0x8b1a034c; (* arm_ADD X12 X26 X26 *) + 0x4e083cbe; (* arm_UMOV X30 Q5 0 8 *) + 0x1e7b0e4a; (* arm_FCSEL Q10 Q18 Q27 Condition_EQ 64 *) + 0xd360fcab; (* arm_LSR X11 X5 32 *) + 0xd360ffca; (* arm_LSR X10 X30 32 *) + 0x0e836ab4; (* arm_TRN2 Q20 Q21 Q3 32 64 *) + 0x0ea98509; (* arm_ADD_VEC Q9 Q8 Q9 32 64 *) + 0x8b0b016e; (* arm_ADD X14 X11 X11 *) + 0x0e8f6846; (* arm_TRN2 Q6 Q2 Q15 32 64 *) + 0x0e802b2c; (* arm_TRN1 Q12 Q25 Q0 32 64 *) + 0x0ea18481; (* arm_ADD_VEC Q1 Q4 Q1 32 64 *) + 0x0e8d2af0; (* arm_TRN1 Q16 Q23 Q13 32 64 *) + 0x1e620da8; (* arm_FCSEL Q8 Q13 Q2 Condition_EQ 64 *) + 0x0e986b71; (* arm_TRN2 Q17 Q27 Q24 32 64 *) + 0xfd0053fd; (* arm_STR D29 SP (Immediate_Offset (word 160)) *) + 0x8b0a0151; (* arm_ADD X17 X10 X10 *) + 0x0e816b84; (* arm_TRN2 Q4 Q28 Q1 32 64 *) + 0x0e812b85; (* arm_TRN1 Q5 Q28 Q1 32 64 *) + 0x0e8f285c; (* arm_TRN1 Q28 Q2 Q15 32 64 *) + 0x0e922ac2; (* arm_TRN1 Q2 Q22 Q18 32 64 *) + 0x1e7a0c1d; (* arm_FCSEL Q29 Q0 Q26 Condition_EQ 64 *) + 0x0e926acf; (* arm_TRN2 Q15 Q22 Q18 32 64 *) + 0x2eb4c196; (* arm_UMULL_VEC Q22 Q12 Q20 32 *) + 0x9bb17fd6; (* arm_UMULL X22 W30 W17 *) + 0x6d082bfd; (* arm_STP D29 D10 SP (Immediate_Offset (iword (&128))) *) + 0x0e8d6aea; (* arm_TRN2 Q10 Q23 Q13 32 64 *) + 0x0e8e6977; (* arm_TRN2 Q23 Q11 Q14 32 64 *) + 0x0e982b6d; (* arm_TRN1 Q13 Q27 Q24 32 64 *) + 0x1e6b0c3b; (* arm_FCSEL Q27 Q1 Q11 Condition_EQ 64 *) + 0x0e8e296e; (* arm_TRN1 Q14 Q11 Q14 32 64 *) + 0x2ea68056; (* arm_UMLAL_VEC Q22 Q2 Q6 32 *) + 0x9bbe7fd9; (* arm_UMULL X25 W30 W30 *) + 0x2eb780b6; (* arm_UMLAL_VEC Q22 Q5 Q23 32 *) + 0x8b1e03c3; (* arm_ADD X3 X30 X30 *) + 0x2eb18216; (* arm_UMLAL_VEC Q22 Q16 Q17 32 *) + 0x0b1506be; (* arm_ADD W30 W21 (Shiftedreg W21 LSL 1) *) + 0x6d0923fb; (* arm_STP D27 D8 SP (Immediate_Offset (iword (&144))) *) + 0x0b1513de; (* arm_ADD W30 W30 (Shiftedreg W21 LSL 4) *) + 0x0e932b4b; (* arm_TRN1 Q11 Q26 Q19 32 64 *) + 0x0e936b48; (* arm_TRN2 Q8 Q26 Q19 32 64 *) + 0x0e806b33; (* arm_TRN2 Q19 Q25 Q0 32 64 *) + 0x0ebf9e9d; (* arm_MUL_VEC Q29 Q20 Q31 32 64 *) + 0xf9404ff4; (* arm_LDR X20 SP (Immediate_Offset (word 152)) *) + 0x2ea6c279; (* arm_UMULL_VEC Q25 Q19 Q6 32 *) + 0x8b000001; (* arm_ADD X1 X0 X0 *) + 0x2eb7c27b; (* arm_UMULL_VEC Q27 Q19 Q23 32 *) + 0x9ba17ca9; (* arm_UMULL X9 W5 W1 *) + 0x2eb7c180; (* arm_UMULL_VEC Q0 Q12 Q23 32 *) + 0xd360fe98; (* arm_LSR X24 X20 32 *) + 0x0ebf9ef4; (* arm_MUL_VEC Q20 Q23 Q31 32 64 *) + 0xd360feb0; (* arm_LSR X16 X21 32 *) + 0x2eb781f9; (* arm_UMLAL_VEC Q25 Q15 Q23 32 *) + 0x9bae256d; (* arm_UMADDL X13 W11 W14 X9 *) + 0x2eb18099; (* arm_UMLAL_VEC Q25 Q4 Q17 32 *) + 0x9bb13dc9; (* arm_UMADDL X9 W14 W17 X15 *) + 0x2ea6c198; (* arm_UMULL_VEC Q24 Q12 Q6 32 *) + 0x0b100602; (* arm_ADD W2 W16 (Shiftedreg W16 LSL 1) *) + 0x1e630d3a; (* arm_FCSEL Q26 Q9 Q3 Condition_EQ 64 *) + 0x0b101042; (* arm_ADD W2 W2 (Shiftedreg W16 LSL 4) *) + 0x0e832ab2; (* arm_TRN1 Q18 Q21 Q3 32 64 *) + 0x2ebdc263; (* arm_UMULL_VEC Q3 Q19 Q29 32 *) + 0x9ba37cbc; (* arm_UMULL X28 W5 W3 *) + 0x0ebf9cc1; (* arm_MUL_VEC Q1 Q6 Q31 32 64 *) + 0x9ba57ca8; (* arm_UMULL X8 W5 W5 *) + 0x2eb78058; (* arm_UMLAL_VEC Q24 Q2 Q23 32 *) + 0x9bbe36ad; (* arm_UMADDL X13 W21 W30 X13 *) + 0x0ebf9e37; (* arm_MUL_VEC Q23 Q17 Q31 32 64 *) + 0x9bac71db; (* arm_UMADDL X27 W14 W12 X28 *) + 0x0e876926; (* arm_TRN2 Q6 Q9 Q7 32 64 *) + 0x4e083f46; (* arm_UMOV X6 Q26 0 8 *) + 0x2ea181e3; (* arm_UMLAL_VEC Q3 Q15 Q1 32 *) + 0x8b100210; (* arm_ADD X16 X16 X16 *) + 0x2eb48083; (* arm_UMLAL_VEC Q3 Q4 Q20 32 *) + 0xd360fcc4; (* arm_LSR X4 X6 32 *) + 0x2eb78143; (* arm_UMLAL_VEC Q3 Q10 Q23 32 *) + 0x8b0600c7; (* arm_ADD X7 X6 X6 *) + 0x2ea8c27a; (* arm_UMULL_VEC Q26 Q19 Q8 32 *) + 0x8b040097; (* arm_ADD X23 X4 X4 *) + 0x9bb758bc; (* arm_UMADDL X28 W5 W23 X22 *) + 0x0e872927; (* arm_TRN1 Q7 Q9 Q7 32 64 *) + 0x2eb181fb; (* arm_UMLAL_VEC Q27 Q15 Q17 32 *) + 0x0b04048f; (* arm_ADD W15 W4 (Shiftedreg W4 LSL 1) *) + 0x2ea8809b; (* arm_UMLAL_VEC Q27 Q4 Q8 32 *) + 0x0b0411ef; (* arm_ADD W15 W15 (Shiftedreg W4 LSL 4) *) + 0x0b0a0556; (* arm_ADD W22 W10 (Shiftedreg W10 LSL 1) *) + 0x2eb180b8; (* arm_UMLAL_VEC Q24 Q5 Q17 32 *) + 0x0b0a12d6; (* arm_ADD W22 W22 (Shiftedreg W10 LSL 4) *) + 0x9ba7716a; (* arm_UMADDL X10 W11 W7 X28 *) + 0x2ea88159; (* arm_UMLAL_VEC Q25 Q10 Q8 32 *) + 0x9bb07cb5; (* arm_UMULL X21 W5 W16 *) + 0x2ebd80d9; (* arm_UMLAL_VEC Q25 Q6 Q29 32 *) + 0x9bb765f7; (* arm_UMADDL X23 W15 W23 X25 *) + 0x2ebd815b; (* arm_UMLAL_VEC Q27 Q10 Q29 32 *) + 0x9bac7cb3; (* arm_UMULL X19 W5 W12 *) + 0x2ea180db; (* arm_UMLAL_VEC Q27 Q6 Q1 32 *) + 0x9bbd5579; (* arm_UMADDL X25 W11 W29 X21 *) + 0x2eb18040; (* arm_UMLAL_VEC Q0 Q2 Q17 32 *) + 0x9ba3241c; (* arm_UMADDL X28 W0 W3 X9 *) + 0x4f415735; (* arm_SHL_VEC Q21 Q25 1 64 128 *) + 0x9ba14d64; (* arm_UMADDL X4 W11 W1 X19 *) + 0x9bbd1055; (* arm_UMADDL X21 W2 W29 X4 *) + 0x0ebf9d19; (* arm_MUL_VEC Q25 Q8 Q31 32 64 *) + 0x2ea88218; (* arm_UMLAL_VEC Q24 Q16 Q8 32 *) + 0x9bb16413; (* arm_UMADDL X19 W0 W17 X25 *) + 0x2ebd80f8; (* arm_UMLAL_VEC Q24 Q7 Q29 32 *) + 0x9bb17cb9; (* arm_UMULL X25 W5 W17 *) + 0x2ebc8278; (* arm_UMLAL_VEC Q24 Q19 Q28 32 *) + 0x9bb02804; (* arm_UMADDL X4 W0 W16 X10 *) + 0x2ea8c189; (* arm_UMULL_VEC Q9 Q12 Q8 32 *) + 0x9ba75cb7; (* arm_UMADDL X23 W5 W7 X23 *) + 0x2eb28195; (* arm_UMLAL_VEC Q21 Q12 Q18 32 *) + 0x0b0604ca; (* arm_ADD W10 W6 (Shiftedreg W6 LSL 1) *) + 0x4f41577b; (* arm_SHL_VEC Q27 Q27 1 64 128 *) + 0x0b06114a; (* arm_ADD W10 W10 (Shiftedreg W6 LSL 4) *) + 0x9bac735c; (* arm_UMADDL X28 W26 W12 X28 *) + 0x2ebd81fa; (* arm_UMLAL_VEC Q26 Q15 Q29 32 *) + 0x9bb05dc9; (* arm_UMADDL X9 W14 W16 X23 *) + 0x2ebd8049; (* arm_UMLAL_VEC Q9 Q2 Q29 32 *) + 0x9bb122d6; (* arm_UMADDL X22 W22 W17 X8 *) + 0x2ebc8055; (* arm_UMLAL_VEC Q21 Q2 Q28 32 *) + 0x9baa70dc; (* arm_UMADDL X28 W6 W10 X28 *) + 0x9ba06c1b; (* arm_UMADDL X27 W0 W0 X27 *) + 0x8b0e01c8; (* arm_ADD X8 X14 X14 *) + 0x2ea880a0; (* arm_UMLAL_VEC Q0 Q5 Q8 32 *) + 0x9bae7ca5; (* arm_UMULL X5 W5 W14 *) + 0x2ea180a9; (* arm_UMLAL_VEC Q9 Q5 Q1 32 *) + 0x9bbd240e; (* arm_UMADDL X14 W0 W29 X9 *) + 0x2ea1809a; (* arm_UMLAL_VEC Q26 Q4 Q1 32 *) + 0x9bb06c46; (* arm_UMADDL X6 W2 W16 X27 *) + 0x2ea880f6; (* arm_UMLAL_VEC Q22 Q7 Q8 32 *) + 0x9bb117c5; (* arm_UMADDL X5 W30 W17 X5 *) + 0x9ba31445; (* arm_UMADDL X5 W2 W3 X5 *) + 0x8b110237; (* arm_ADD X23 X17 X17 *) + 0x2ebc819b; (* arm_UMLAL_VEC Q27 Q12 Q28 32 *) + 0x9bb7344d; (* arm_UMADDL X13 W2 W23 X13 *) + 0x2eb4815a; (* arm_UMLAL_VEC Q26 Q10 Q20 32 *) + 0x8b0c0189; (* arm_ADD X9 X12 X12 *) + 0x2eb48209; (* arm_UMLAL_VEC Q9 Q16 Q20 32 *) + 0x9bbd195b; (* arm_UMADDL X27 W10 W29 X6 *) + 0x2ebd8200; (* arm_UMLAL_VEC Q0 Q16 Q29 32 *) + 0x9ba36566; (* arm_UMADDL X6 W11 W3 X25 *) + 0x2eb28276; (* arm_UMLAL_VEC Q22 Q19 Q18 32 *) + 0x9ba34f53; (* arm_UMADDL X19 W26 W3 X19 *) + 0x0ebf9e52; (* arm_MUL_VEC Q18 Q18 Q31 32 64 *) + 0x9bb76df7; (* arm_UMADDL X23 W15 W23 X27 *) + 0x2eb980c3; (* arm_UMLAL_VEC Q3 Q6 Q25 32 *) + 0x9bac1800; (* arm_UMADDL X0 W0 W12 X6 *) + 0x2ea180e0; (* arm_UMLAL_VEC Q0 Q7 Q1 32 *) + 0x8b10020b; (* arm_ADD X11 X16 X16 *) + 0x2eb780e9; (* arm_UMLAL_VEC Q9 Q7 Q23 32 *) + 0x9bb13986; (* arm_UMADDL X6 W12 W17 X14 *) + 0x2eab8269; (* arm_UMLAL_VEC Q9 Q19 Q11 32 *) + 0x9bbd1359; (* arm_UMADDL X25 W26 W29 X4 *) + 0x2eb281e9; (* arm_UMLAL_VEC Q9 Q15 Q18 32 *) + 0x9ba3354e; (* arm_UMADDL X14 W10 W3 X13 *) + 0x2eb1c199; (* arm_UMULL_VEC Q25 Q12 Q17 32 *) + 0x9bb0015b; (* arm_UMADDL X27 W10 W16 X0 *) + 0x2eb780da; (* arm_UMLAL_VEC Q26 Q6 Q23 32 *) + 0x8b466b20; (* arm_ADD X0 X25 (Shiftedreg X6 LSR 26) *) + 0x0ebf9f97; (* arm_MUL_VEC Q23 Q28 Q31 32 64 *) + 0x9bac154c; (* arm_UMADDL X12 W10 W12 X5 *) + 0x4f415463; (* arm_SHL_VEC Q3 Q3 1 64 128 *) + 0x8b4066d0; (* arm_ADD X16 X22 (Shiftedreg X0 LSR 25) *) + 0x2eae80b5; (* arm_UMLAL_VEC Q21 Q5 Q14 32 *) + 0x92679816; (* arm_AND X22 X0 (rvalue (word 18446744073675997184)) *) + 0x2eab8183; (* arm_UMLAL_VEC Q3 Q12 Q11 32 *) + 0x8b56621a; (* arm_ADD X26 X16 (Shiftedreg X22 LSR 24) *) + 0x2eb28043; (* arm_UMLAL_VEC Q3 Q2 Q18 32 *) + 0x9bb15550; (* arm_UMADDL X16 W10 W17 X21 *) + 0x2eb780a3; (* arm_UMLAL_VEC Q3 Q5 Q23 32 *) + 0x8b565756; (* arm_ADD X22 X26 (Shiftedreg X22 LSR 21) *) + 0x2eb78089; (* arm_UMLAL_VEC Q9 Q4 Q23 32 *) + 0x9bbd6de5; (* arm_UMADDL X5 W15 W29 X27 *) + 0x2eb1c271; (* arm_UMULL_VEC Q17 Q19 Q17 32 *) + 0x9ba35bd1; (* arm_UMADDL X17 W30 W3 X22 *) + 0x2ea88059; (* arm_UMLAL_VEC Q25 Q2 Q8 32 *) + 0x9ba341f9; (* arm_UMADDL X25 W15 W3 X16 *) + 0x2ebd80b9; (* arm_UMLAL_VEC Q25 Q5 Q29 32 *) + 0x9ba74dfa; (* arm_UMADDL X26 W15 W7 X19 *) + 0x2eae8260; (* arm_UMLAL_VEC Q0 Q19 Q14 32 *) + 0x9ba94451; (* arm_UMADDL X17 W2 W9 X17 *) + 0x2ea881f1; (* arm_UMLAL_VEC Q17 Q15 Q8 32 *) + 0xf94043f3; (* arm_LDR X19 SP (Immediate_Offset (word 128)) *) + 0x2ebd8091; (* arm_UMLAL_VEC Q17 Q4 Q29 32 *) + 0xf94047e7; (* arm_LDR X7 SP (Immediate_Offset (word 136)) *) + 0x4f41575d; (* arm_SHL_VEC Q29 Q26 1 64 128 *) + 0x9ba1454d; (* arm_UMADDL X13 W10 W1 X17 *) + 0x2ead81e0; (* arm_UMLAL_VEC Q0 Q15 Q13 32 *) + 0xd360fe62; (* arm_LSR X2 X19 32 *) + 0x2ead819d; (* arm_UMLAL_VEC Q29 Q12 Q13 32 *) + 0x9ba131fb; (* arm_UMADDL X27 W15 W1 X12 *) + 0x2eab805d; (* arm_UMLAL_VEC Q29 Q2 Q11 32 *) + 0x9ba835fe; (* arm_UMADDL X30 W15 W8 X13 *) + 0x2eb280bd; (* arm_UMLAL_VEC Q29 Q5 Q18 32 *) + 0x8b0700e4; (* arm_ADD X4 X7 X7 *) + 0x2eb7821d; (* arm_UMLAL_VEC Q29 Q16 Q23 32 *) + 0x9ba939fd; (* arm_UMADDL X29 W15 W9 X14 *) + 0x2eab8080; (* arm_UMLAL_VEC Q0 Q4 Q11 32 *) + 0x8b5e6b71; (* arm_ADD X17 X27 (Shiftedreg X30 LSR 26) *) + 0x2eb28140; (* arm_UMLAL_VEC Q0 Q10 Q18 32 *) + 0x9bab71f0; (* arm_UMADDL X16 W15 W11 X28 *) + 0x2eb780c0; (* arm_UMLAL_VEC Q0 Q6 Q23 32 *) + 0x8b5167a1; (* arm_ADD X1 X29 (Shiftedreg X17 LSR 25) *) + 0x2ea18219; (* arm_UMLAL_VEC Q25 Q16 Q1 32 *) + 0x9ba47e6b; (* arm_UMULL X11 W19 W4 *) + 0xf94053e8; (* arm_LDR X8 SP (Immediate_Offset (word 160)) *) + 0x0ebf9dda; (* arm_MUL_VEC Q26 Q14 Q31 32 64 *) + 0x2ea18151; (* arm_UMLAL_VEC Q17 Q10 Q1 32 *) + 0xf9404bef; (* arm_LDR X15 SP (Immediate_Offset (word 144)) *) + 0x2eb480d1; (* arm_UMLAL_VEC Q17 Q6 Q20 32 *) + 0x924067c9; (* arm_AND X9 X30 (rvalue (word 67108863)) *) + 0xb3606229; (* arm_BFM X9 X17 32 24 *) + 0x8b020051; (* arm_ADD X17 X2 X2 *) + 0xd360fdea; (* arm_LSR X10 X15 32 *) + 0x8b416b3b; (* arm_ADD X27 X25 (Shiftedreg X1 LSR 26) *) + 0x2eb480f9; (* arm_UMLAL_VEC Q25 Q7 Q20 32 *) + 0x8b0a014d; (* arm_ADD X13 X10 X10 *) + 0x2ead8279; (* arm_UMLAL_VEC Q25 Q19 Q13 32 *) + 0x8b5b66fd; (* arm_ADD X29 X23 (Shiftedreg X27 LSR 25) *) + 0x2eab81f9; (* arm_UMLAL_VEC Q25 Q15 Q11 32 *) + 0xd360fd1e; (* arm_LSR X30 X8 32 *) + 0x2eb28099; (* arm_UMLAL_VEC Q25 Q4 Q18 32 *) + 0x8b5d68b7; (* arm_ADD X23 X5 (Shiftedreg X29 LSR 26) *) + 0x2eb78159; (* arm_UMLAL_VEC Q25 Q10 Q23 32 *) + 0x924067ae; (* arm_AND X14 X29 (rvalue (word 67108863)) *) + 0x2eba80d9; (* arm_UMLAL_VEC Q25 Q6 Q26 32 *) + 0x8b576605; (* arm_ADD X5 X16 (Shiftedreg X23 LSR 25) *) + 0x4f415628; (* arm_SHL_VEC Q8 Q17 1 64 128 *) + 0x9bb12c4c; (* arm_UMADDL X12 W2 W17 X11 *) + 0x924064bd; (* arm_AND X29 X5 (rvalue (word 67108863)) *) + 0x9bb37e75; (* arm_UMULL X21 W19 W19 *) + 0x2eba80fd; (* arm_UMLAL_VEC Q29 Q7 Q26 32 *) + 0x0b0a0550; (* arm_ADD W16 W10 (Shiftedreg W10 LSL 1) *) + 0x2eba8203; (* arm_UMLAL_VEC Q3 Q16 Q26 32 *) + 0x0b0a1210; (* arm_ADD W16 W16 (Shiftedreg W10 LSL 4) *) + 0xb36062ee; (* arm_BFM X14 X23 32 24 *) + 0x0b18070a; (* arm_ADD W10 W24 (Shiftedreg W24 LSL 1) *) + 0x8b456b56; (* arm_ADD X22 X26 (Shiftedreg X5 LSR 26) *) + 0x0b18114a; (* arm_ADD W10 W10 (Shiftedreg W24 LSL 4) *) + 0x2eae8188; (* arm_UMLAL_VEC Q8 Q12 Q14 32 *) + 0x9bad5619; (* arm_UMADDL X25 W16 W13 X21 *) + 0x2ead8048; (* arm_UMLAL_VEC Q8 Q2 Q13 32 *) + 0xb36062dd; (* arm_BFM X29 X22 32 24 *) + 0x2eab80a8; (* arm_UMLAL_VEC Q8 Q5 Q11 32 *) + 0x8b18031a; (* arm_ADD X26 X24 X24 *) + 0x2eb28208; (* arm_UMLAL_VEC Q8 Q16 Q18 32 *) + 0xa906f7ee; (* arm_STP X14 X29 SP (Immediate_Offset (iword (&104))) *) + 0x2eb780e8; (* arm_UMLAL_VEC Q8 Q7 Q23 32 *) + 0x0b1e07d8; (* arm_ADD W24 W30 (Shiftedreg W30 LSL 1) *) + 0x6f6617b9; (* arm_USRA_VEC Q25 Q29 26 64 128 *) + 0x0b1e1318; (* arm_ADD W24 W24 (Shiftedreg W30 LSL 4) *) + 0x9baf7dfd; (* arm_UMULL X29 W15 W15 *) + 0x2eae805b; (* arm_UMLAL_VEC Q27 Q2 Q14 32 *) + 0x9bad7de3; (* arm_UMULL X3 W15 W13 *) + 0x2ead80bb; (* arm_UMLAL_VEC Q27 Q5 Q13 32 *) + 0x8b140295; (* arm_ADD X21 X20 X20 *) + 0x2eae81f8; (* arm_UMLAL_VEC Q24 Q15 Q14 32 *) + 0x9bb57e65; (* arm_UMULL X5 W19 W21 *) + 0x2ead8098; (* arm_UMLAL_VEC Q24 Q4 Q13 32 *) + 0x9240642b; (* arm_AND X11 X1 (rvalue (word 67108863)) *) + 0x6f671728; (* arm_USRA_VEC Q8 Q25 25 64 128 *) + 0x92406001; (* arm_AND X1 X0 (rvalue (word 33554431)) *) + 0x2eab821b; (* arm_UMLAL_VEC Q27 Q16 Q11 32 *) + 0x9bad1637; (* arm_UMADDL X23 W17 W13 X5 *) + 0x2eb280fb; (* arm_UMLAL_VEC Q27 Q7 Q18 32 *) + 0x8b1e03c5; (* arm_ADD X5 X30 X30 *) + 0x6f661500; (* arm_USRA_VEC Q0 Q8 26 64 128 *) + 0x8b0f01e0; (* arm_ADD X0 X15 X15 *) + 0x2eab8158; (* arm_UMLAL_VEC Q24 Q10 Q11 32 *) + 0x9ba05cf7; (* arm_UMADDL X23 W7 W0 X23 *) + 0x2eb280d8; (* arm_UMLAL_VEC Q24 Q6 Q18 32 *) + 0xd360fcfe; (* arm_LSR X30 X7 32 *) + 0x6f67141b; (* arm_USRA_VEC Q27 Q0 25 64 128 *) + 0x8b1e03d0; (* arm_ADD X16 X30 X30 *) + 0x4e3e1d14; (* arm_AND_VEC Q20 Q8 Q30 128 *) + 0x9bb05fcf; (* arm_UMADDL X15 W30 W16 X23 *) + 0x6f7f07d7; (* arm_USHR_VEC Q23 Q30 1 64 128 *) + 0x0b080517; (* arm_ADD W23 W8 (Shiftedreg W8 LSL 1) *) + 0x6f661778; (* arm_USRA_VEC Q24 Q27 26 64 128 *) + 0x0b0812f7; (* arm_ADD W23 W23 (Shiftedreg W8 LSL 4) *) + 0x9ba50e6e; (* arm_UMADDL X14 W19 W5 X3 *) + 0x4e3e1f68; (* arm_AND_VEC Q8 Q27 Q30 128 *) + 0x8b08011c; (* arm_ADD X28 X8 X8 *) + 0x4e371c1b; (* arm_AND_VEC Q27 Q0 Q23 128 *) + 0x9bb73d08; (* arm_UMADDL X8 W8 W23 X15 *) + 0x4e371f05; (* arm_AND_VEC Q5 Q24 Q23 128 *) + 0x9bbc3843; (* arm_UMADDL X3 W2 W28 X14 *) + 0x2ebc81f6; (* arm_UMLAL_VEC Q22 Q15 Q28 32 *) + 0xb360636b; (* arm_BFM X11 X27 32 24 *) + 0x4e851905; (* arm_UZP1 Q5 Q8 Q5 32 *) + 0x9ba5770e; (* arm_UMADDL X14 W24 W5 X29 *) + 0x9bbc3a65; (* arm_UMADDL X5 W19 W28 X14 *) + 0xfd4027f2; (* arm_LDR D18 SP (Immediate_Offset (word 72)) *) + 0x6e180652; (* arm_INS Q18 Q18 64 0 64 64 *) + 0x9bba0cef; (* arm_UMADDL X15 W7 W26 X3 *) + 0x0ebf9dac; (* arm_MUL_VEC Q12 Q13 Q31 32 64 *) + 0x2ead8215; (* arm_UMLAL_VEC Q21 Q16 Q13 32 *) + 0xa905afe9; (* arm_STP X9 X11 SP (Immediate_Offset (iword (&88))) *) + 0x2eab80f5; (* arm_UMLAL_VEC Q21 Q7 Q11 32 *) + 0x9bba163d; (* arm_UMADDL X29 W17 W26 X5 *) + 0x2eae8096; (* arm_UMLAL_VEC Q22 Q4 Q14 32 *) + 0x0b14068e; (* arm_ADD W14 W20 (Shiftedreg W20 LSL 1) *) + 0x2ead8156; (* arm_UMLAL_VEC Q22 Q10 Q13 32 *) + 0x0b1411ce; (* arm_ADD W14 W14 (Shiftedreg W20 LSL 4) *) + 0x9ba07e63; (* arm_UMULL X3 W19 W0 *) + 0x2eab80d6; (* arm_UMLAL_VEC Q22 Q6 Q11 32 *) + 0x9bb574fd; (* arm_UMADDL X29 W7 W21 X29 *) + 0x6f671715; (* arm_USRA_VEC Q21 Q24 25 64 128 *) + 0x9bae328b; (* arm_UMADDL X11 W20 W14 X12 *) + 0x4e371f20; (* arm_AND_VEC Q0 Q25 Q23 128 *) + 0x9bb53fc5; (* arm_UMADDL X5 W30 W21 X15 *) + 0x4e3e1fae; (* arm_AND_VEC Q14 Q29 Q30 128 *) + 0x9bad760c; (* arm_UMADDL X12 W16 W13 X29 *) + 0x6f6616b6; (* arm_USRA_VEC Q22 Q21 26 64 128 *) + 0x9bb00e3d; (* arm_UMADDL X29 W17 W16 X3 *) + 0x2eac80e3; (* arm_UMLAL_VEC Q3 Q7 Q12 32 *) + 0x8b1a0349; (* arm_ADD X9 X26 X26 *) + 0x4e3e1ea1; (* arm_AND_VEC Q1 Q21 Q30 128 *) + 0x8b4c68bb; (* arm_ADD X27 X5 (Shiftedreg X12 LSR 26) *) + 0x4e771ec8; (* arm_BIC_VEC Q8 Q22 Q23 128 *) + 0x9ba774fd; (* arm_UMADDL X29 W7 W7 X29 *) + 0x4e371ed1; (* arm_AND_VEC Q17 Q22 Q23 128 *) + 0x8b5b6725; (* arm_ADD X5 X25 (Shiftedreg X27 LSR 25) *) + 0x6f671503; (* arm_USRA_VEC Q3 Q8 25 64 128 *) + 0x9ba92319; (* arm_UMADDL X25 W24 W9 X8 *) + 0x2eba8149; (* arm_UMLAL_VEC Q9 Q10 Q26 32 *) + 0x8b0d01a8; (* arm_ADD X8 X13 X13 *) + 0x4e912836; (* arm_TRN1 Q22 Q1 Q17 32 128 *) + 0x9ba82d4b; (* arm_UMADDL X11 W10 W8 X11 *) + 0x6f681503; (* arm_USRA_VEC Q3 Q8 24 64 128 *) + 0x9bb07e74; (* arm_UMULL X20 W19 W16 *) + 0x0eb286da; (* arm_ADD_VEC Q26 Q22 Q18 32 64 *) + 0xfd402bfc; (* arm_LDR D28 SP (Immediate_Offset (word 80)) *) + 0x2eac80c9; (* arm_UMLAL_VEC Q9 Q6 Q12 32 *) + 0x9ba02ee3; (* arm_UMADDL X3 W23 W0 X11 *) + 0x6f6b1503; (* arm_USRA_VEC Q3 Q8 21 64 128 *) + 0x9bba755d; (* arm_UMADDL X29 W10 W26 X29 *) + 0x4e9b1a8b; (* arm_UZP1 Q11 Q20 Q27 32 *) + 0x9ba45054; (* arm_UMADDL X20 W2 W4 X20 *) + 0x9bb55149; (* arm_UMADDL X9 W10 W21 X20 *) + 0x6e0846d1; (* arm_INS Q17 Q22 0 64 64 128 *) + 0x6f661469; (* arm_USRA_VEC Q9 Q3 26 64 128 *) + 0x9bad7e6f; (* arm_UMULL X15 W19 W13 *) + 0x4e3e1c67; (* arm_AND_VEC Q7 Q3 Q30 128 *) + 0x8b10020b; (* arm_ADD X11 X16 X16 *) + 0x4e855961; (* arm_UZP2 Q1 Q11 Q5 32 *) + 0x9bad26f4; (* arm_UMADDL X20 W23 W13 X9 *) + 0x4e371d28; (* arm_AND_VEC Q8 Q9 Q23 128 *) + 0x9ba03c49; (* arm_UMADDL X9 W2 W0 X15 *) + 0x6f67152e; (* arm_USRA_VEC Q14 Q9 25 64 128 *) + 0x924064c6; (* arm_AND X6 X6 (rvalue (word 67108863)) *) + 0x4e8818e7; (* arm_UZP1 Q7 Q7 Q8 32 *) + 0x9bb576fd; (* arm_UMADDL X29 W23 W21 X29 *) + 0x4e85197b; (* arm_UZP1 Q27 Q11 Q5 32 *) + 0x9bba7e6f; (* arm_UMULL X15 W19 W26 *) + 0x6f6615c0; (* arm_USRA_VEC Q0 Q14 26 64 128 *) + 0x8b5664c6; (* arm_ADD X6 X6 (Shiftedreg X22 LSR 25) *) + 0x4e3e1dc3; (* arm_AND_VEC Q3 Q14 Q30 128 *) + 0x92679b76; (* arm_AND X22 X27 (rvalue (word 18446744073675997184)) *) + 0x2eb18742; (* arm_SUB_VEC Q2 Q26 Q17 32 64 *) + 0x0eb186c9; (* arm_ADD_VEC Q9 Q22 Q17 32 64 *) + 0x4e80186e; (* arm_UZP1 Q14 Q3 Q0 32 *) + 0x9bb53c42; (* arm_UMADDL X2 W2 W21 X15 *) + 0x4eb28765; (* arm_ADD_VEC Q5 Q27 Q18 32 128 *) + 0x8b5660a5; (* arm_ADD X5 X5 (Shiftedreg X22 LSR 24) *) + 0x0e893856; (* arm_ZIP1 Q22 Q2 Q9 32 64 *) + 0x6e010792; (* arm_INS Q18 Q28 0 0 8 64 *) + 0x4e8e18e8; (* arm_UZP1 Q8 Q7 Q14 32 *) + 0x8b5654b6; (* arm_ADD X22 X5 (Shiftedreg X22 LSR 21) *) + 0x4e8e58e3; (* arm_UZP2 Q3 Q7 Q14 32 *) + 0x9bb024e5; (* arm_UMADDL X5 W7 W16 X9 *) + 0x4eb28519; (* arm_ADD_VEC Q25 Q8 Q18 32 128 *) + 0x9ba059cf; (* arm_UMADDL X15 W14 W0 X22 *) + 0x4ea1876c; (* arm_ADD_VEC Q12 Q27 Q1 32 128 *) + 0x8b110229; (* arm_ADD X9 X17 X17 *) + 0x6ea184ae; (* arm_SUB_VEC Q14 Q5 Q1 32 128 *) + 0x9bb17e73; (* arm_UMULL X19 W19 W17 *) + 0x6ea38732; (* arm_SUB_VEC Q18 Q25 Q3 32 128 *) + 0xf94033f6; (* arm_LDR X22 SP (Immediate_Offset (word 96)) *) + 0x4ea38514; (* arm_ADD_VEC Q20 Q8 Q3 32 128 *) + 0x9bab3d4f; (* arm_UMADDL X15 W10 W11 X15 *) + 0x4e8c39d0; (* arm_ZIP1 Q16 Q14 Q12 32 128 *) + 0x9bad4dce; (* arm_UMADDL X14 W14 W13 X19 *) + 0x4e8c79ce; (* arm_ZIP2 Q14 Q14 Q12 32 128 *) + 0x92406371; (* arm_AND X17 X27 (rvalue (word 33554431)) *) + 0x4e947a40; (* arm_ZIP2 Q0 Q18 Q20 32 128 *) + 0x9ba43eef; (* arm_UMADDL X15 W23 W4 X15 *) + 0x4e943a41; (* arm_ZIP1 Q1 Q18 Q20 32 128 *) + 0x9ba0394a; (* arm_UMADDL X10 W10 W0 X14 *) + 0x0e897845; (* arm_ZIP2 Q5 Q2 Q9 32 64 *) + 0x0f215418; (* arm_SHL_VEC Q24 Q0 1 32 64 *) + 0x6e084433; (* arm_INS Q19 Q1 0 64 64 128 *) + 0x0f2156da; (* arm_SHL_VEC Q26 Q22 1 32 64 *) + 0x0f215611; (* arm_SHL_VEC Q17 Q16 1 32 64 *) + 0x6e08440f; (* arm_INS Q15 Q0 0 64 64 128 *) + 0x0f2154a7; (* arm_SHL_VEC Q7 Q5 1 32 64 *) + 0x0f215672; (* arm_SHL_VEC Q18 Q19 1 32 64 *) + 0x2eb8c02b; (* arm_UMULL_VEC Q11 Q1 Q24 32 *) + 0x9bb02af3; (* arm_UMADDL X19 W23 W16 X10 *) + 0x2eb1c026; (* arm_UMULL_VEC Q6 Q1 Q17 32 *) + 0x9bad08ea; (* arm_UMADDL X10 W7 W13 X2 *) + 0x6e084604; (* arm_INS Q4 Q16 0 64 64 128 *) + 0x6e0845ca; (* arm_INS Q10 Q14 0 64 64 128 *) + 0x2ebac029; (* arm_UMULL_VEC Q9 Q1 Q26 32 *) + 0xf9402fed; (* arm_LDR X13 SP (Immediate_Offset (word 88)) *) + 0x0f2155fc; (* arm_SHL_VEC Q28 Q15 1 32 64 *) + 0x0f215543; (* arm_SHL_VEC Q3 Q10 1 32 64 *) + 0xf94037ee; (* arm_LDR X14 SP (Immediate_Offset (word 104)) *) + 0x0ebf9d4c; (* arm_MUL_VEC Q12 Q10 Q31 32 64 *) + 0x2ea7c039; (* arm_UMULL_VEC Q25 Q1 Q7 32 *) + 0xf9403be2; (* arm_LDR X2 SP (Immediate_Offset (word 112)) *) + 0x2ebc8246; (* arm_UMLAL_VEC Q6 Q18 Q28 32 *) + 0x9ba02bdb; (* arm_UMADDL X27 W30 W0 X10 *) + 0x9ba05310; (* arm_UMADDL X16 W24 W0 X20 *) + 0x0f2155cd; (* arm_SHL_VEC Q13 Q14 1 32 64 *) + 0x9bba16e5; (* arm_UMADDL X5 W23 W26 X5 *) + 0x0ebf9ec2; (* arm_MUL_VEC Q2 Q22 Q31 32 64 *) + 0x2eadc035; (* arm_UMULL_VEC Q21 Q1 Q13 32 *) + 0x9ba87717; (* arm_UMADDL X23 W24 W8 X29 *) + 0x2eb3824b; (* arm_UMLAL_VEC Q11 Q18 Q19 32 *) + 0xb21f67ea; (* arm_MOV X10 (rvalue (word 576460743847706622)) *) + 0xd100094a; (* arm_SUB X10 X10 (rvalue (word 2)) *) + 0x9bb5171a; (* arm_UMADDL X26 W24 W21 X5 *) + 0x0ebf9ddd; (* arm_MUL_VEC Q29 Q14 Q31 32 64 *) + 0x2eba8279; (* arm_UMLAL_VEC Q25 Q19 Q26 32 *) + 0x8b466827; (* arm_ADD X7 X1 (Shiftedreg X6 LSR 26) *) + 0x0ebf9c94; (* arm_MUL_VEC Q20 Q4 Q31 32 64 *) + 0x924064c6; (* arm_AND X6 X6 (rvalue (word 67108863)) *) + 0x0f215648; (* arm_SHL_VEC Q8 Q18 1 32 64 *) + 0x0f215484; (* arm_SHL_VEC Q4 Q4 1 32 64 *) + 0x2eae83ab; (* arm_UMLAL_VEC Q11 Q29 Q14 32 *) + 0xb36064e6; (* arm_BFM X6 X7 32 25 *) + 0x2ea38019; (* arm_UMLAL_VEC Q25 Q0 Q3 32 *) + 0x9ba44f00; (* arm_UMADDL X0 W24 W4 X19 *) + 0x2ead81f9; (* arm_UMLAL_VEC Q25 Q15 Q13 32 *) + 0xf9003fe6; (* arm_STR X6 SP (Immediate_Offset (word 120)) *) + 0x2ea48255; (* arm_UMLAL_VEC Q21 Q18 Q4 32 *) + 0x9bab0f08; (* arm_UMADDL X8 W24 W11 X3 *) + 0x2eb18015; (* arm_UMLAL_VEC Q21 Q0 Q17 32 *) + 0xf9403ffe; (* arm_LDR X30 SP (Immediate_Offset (word 120)) *) + 0x0ebf9cae; (* arm_MUL_VEC Q14 Q5 Q31 32 64 *) + 0x8b0a0042; (* arm_ADD X2 X2 X10 *) + 0x0f215785; (* arm_SHL_VEC Q5 Q28 1 32 64 *) + 0x0f21549b; (* arm_SHL_VEC Q27 Q4 1 32 64 *) + 0x2ea08006; (* arm_UMLAL_VEC Q6 Q0 Q0 32 *) + 0x9ba93f0b; (* arm_UMADDL X11 W24 W9 X15 *) + 0x2ea38186; (* arm_UMLAL_VEC Q6 Q12 Q3 32 *) + 0x8b0a03c4; (* arm_ADD X4 X30 X10 *) + 0x2ea581cb; (* arm_UMLAL_VEC Q11 Q14 Q5 32 *) + 0x8b0a02c3; (* arm_ADD X3 X22 X10 *) + 0x2eb1804b; (* arm_UMLAL_VEC Q11 Q2 Q17 32 *) + 0x8b4b6806; (* arm_ADD X6 X0 (Shiftedreg X11 LSR 26) *) + 0x2ebb818b; (* arm_UMLAL_VEC Q11 Q12 Q27 32 *) + 0x8b0a01ce; (* arm_ADD X14 X14 X10 *) + 0x2ebb81c6; (* arm_UMLAL_VEC Q6 Q14 Q27 32 *) + 0x8b466508; (* arm_ADD X8 X8 (Shiftedreg X6 LSR 25) *) + 0x2ead8046; (* arm_UMLAL_VEC Q6 Q2 Q13 32 *) + 0xf29ff68a; (* arm_MOVK X10 (word 65460) 0 *) + 0x2ea48219; (* arm_UMLAL_VEC Q25 Q16 Q4 32 *) + 0x8b486a1d; (* arm_ADD X29 X16 (Shiftedreg X8 LSR 26) *) + 0x2ea3c03b; (* arm_UMULL_VEC Q27 Q1 Q3 32 *) + 0x9240656b; (* arm_AND X11 X11 (rvalue (word 67108863)) *) + 0x2ea38249; (* arm_UMLAL_VEC Q9 Q18 Q3 32 *) + 0x8b0a01b3; (* arm_ADD X19 X13 X10 *) + 0x2ead8009; (* arm_UMLAL_VEC Q9 Q0 Q13 32 *) + 0x92406505; (* arm_AND X5 X8 (rvalue (word 67108863)) *) + 0x2ea48389; (* arm_UMLAL_VEC Q9 Q28 Q4 32 *) + 0xb36060cb; (* arm_BFM X11 X6 32 24 *) + 0x2eb08209; (* arm_UMLAL_VEC Q9 Q16 Q16 32 *) + 0x9bbc6f1e; (* arm_UMADDL X30 W24 W28 X27 *) + 0x2ea781c9; (* arm_UMLAL_VEC Q9 Q14 Q7 32 *) + 0xcb0b026d; (* arm_SUB X13 X19 X11 *) + 0x2eb2c02a; (* arm_UMULL_VEC Q10 Q1 Q18 32 *) + 0x8b5d66e7; (* arm_ADD X7 X23 (Shiftedreg X29 LSR 25) *) + 0x2eaf8395; (* arm_UMLAL_VEC Q21 Q28 Q15 32 *) + 0xd360fdb0; (* arm_LSR X16 X13 32 *) + 0x2eb68055; (* arm_UMLAL_VEC Q21 Q2 Q22 32 *) + 0x8b476b40; (* arm_ADD X0 X26 (Shiftedreg X7 LSR 26) *) + 0x6f661539; (* arm_USRA_VEC Q25 Q9 26 64 128 *) + 0x924064f4; (* arm_AND X20 X7 (rvalue (word 67108863)) *) + 0x2ea1c036; (* arm_UMULL_VEC Q22 Q1 Q1 32 *) + 0x8b406728; (* arm_ADD X8 X25 (Shiftedreg X0 LSR 25) *) + 0x2ebcc027; (* arm_UMULL_VEC Q7 Q1 Q28 32 *) + 0x924063a1; (* arm_AND X1 X29 (rvalue (word 33554431)) *) + 0x4e771f32; (* arm_BIC_VEC Q18 Q25 Q23 128 *) + 0x92406513; (* arm_AND X19 X8 (rvalue (word 67108863)) *) + 0x4e3e1d30; (* arm_AND_VEC Q16 Q9 Q30 128 *) + 0x92406587; (* arm_AND X7 X12 (rvalue (word 67108863)) *) + 0x6f671656; (* arm_USRA_VEC Q22 Q18 25 64 128 *) + 0x8b486bca; (* arm_ADD X10 X30 (Shiftedreg X8 LSR 26) *) + 0x2eb88267; (* arm_UMLAL_VEC Q7 Q19 Q24 32 *) + 0xb36063a5; (* arm_BFM X5 X29 32 24 *) + 0x4e371f29; (* arm_AND_VEC Q9 Q25 Q23 128 *) + 0x8b4a64fb; (* arm_ADD X27 X7 (Shiftedreg X10 LSR 25) *) + 0x6f681656; (* arm_USRA_VEC Q22 Q18 24 64 128 *) + 0xd29db435; (* arm_MOV X21 (rvalue (word 60833)) *) + 0xd37ffab5; (* arm_LSL X21 X21 1 *) + 0x8b5b6a2f; (* arm_ADD X15 X17 (Shiftedreg X27 LSR 26) *) + 0x0f215479; (* arm_SHL_VEC Q25 Q3 1 32 64 *) + 0x2eb181c7; (* arm_UMLAL_VEC Q7 Q14 Q17 32 *) + 0x9240677d; (* arm_AND X29 X27 (rvalue (word 67108863)) *) + 0x6f6b1656; (* arm_USRA_VEC Q22 Q18 21 64 128 *) + 0xb36065fd; (* arm_BFM X29 X15 32 25 *) + 0x2eb881ca; (* arm_UMLAL_VEC Q10 Q14 Q24 32 *) + 0x924060d1; (* arm_AND X17 X6 (rvalue (word 33554431)) *) + 0x2ebc804a; (* arm_UMLAL_VEC Q10 Q2 Q28 32 *) + 0xcb050066; (* arm_SUB X6 X3 X5 *) + 0x2eb1818a; (* arm_UMLAL_VEC Q10 Q12 Q17 32 *) + 0x9bb54619; (* arm_UMADDL X25 W16 W21 X17 *) + 0x2ea483aa; (* arm_UMLAL_VEC Q10 Q29 Q4 32 *) + 0x2a0503ec; (* arm_MOV W12 W5 *) + 0x2ea48296; (* arm_UMLAL_VEC Q22 Q20 Q4 32 *) + 0xd360fcda; (* arm_LSR X26 X6 32 *) + 0x2ea881d6; (* arm_UMLAL_VEC Q22 Q14 Q8 32 *) + 0x92406018; (* arm_AND X24 X0 (rvalue (word 33554431)) *) + 0x2eb88056; (* arm_UMLAL_VEC Q22 Q2 Q24 32 *) + 0xa90817eb; (* arm_STP X11 X5 SP (Immediate_Offset (iword (&128))) *) + 0x2ea58196; (* arm_UMLAL_VEC Q22 Q12 Q5 32 *) + 0xb3606014; (* arm_BFM X20 X0 32 24 *) + 0x2eb183b6; (* arm_UMLAL_VEC Q22 Q29 Q17 32 *) + 0x9bb530cc; (* arm_UMADDL X12 W6 W21 X12 *) + 0x2ea4c032; (* arm_UMULL_VEC Q18 Q1 Q4 32 *) + 0xb3606153; (* arm_BFM X19 X10 32 24 *) + 0x2ea48047; (* arm_UMLAL_VEC Q7 Q2 Q4 32 *) + 0xcb1401c7; (* arm_SUB X7 X14 X20 *) + 0x2ead827b; (* arm_UMLAL_VEC Q27 Q19 Q13 32 *) + 0x2a1403e8; (* arm_MOV W8 W20 *) + 0x6f6616ca; (* arm_USRA_VEC Q10 Q22 26 64 128 *) + 0xd360fcee; (* arm_LSR X14 X7 32 *) + 0x2eb18272; (* arm_UMLAL_VEC Q18 Q19 Q17 32 *) + 0x9240615c; (* arm_AND X28 X10 (rvalue (word 33554431)) *) + 0x2ead8187; (* arm_UMLAL_VEC Q7 Q12 Q13 32 *) + 0xcb130045; (* arm_SUB X5 X2 X19 *) + 0x6f67154b; (* arm_USRA_VEC Q11 Q10 25 64 128 *) + 0x2a1303e2; (* arm_MOV W2 W19 *) + 0x2ea4801b; (* arm_UMLAL_VEC Q27 Q0 Q4 32 *) + 0x2eb981d5; (* arm_UMLAL_VEC Q21 Q14 Q25 32 *) + 0xcb1d0097; (* arm_SUB X23 X4 X29 *) + 0x6f661567; (* arm_USRA_VEC Q7 Q11 26 64 128 *) + 0x2a1d03e0; (* arm_MOV W0 W29 *) + 0x2ebc8012; (* arm_UMLAL_VEC Q18 Q0 Q28 32 *) + 0xd360fef6; (* arm_LSR X22 X23 32 *) + 0x2eb181fb; (* arm_UMLAL_VEC Q27 Q15 Q17 32 *) + 0xf90053fd; (* arm_STR X29 SP (Immediate_Offset (word 160)) *) + 0x6f6714e6; (* arm_USRA_VEC Q6 Q7 25 64 128 *) + 0x2a0b03f1; (* arm_MOV W17 W11 *) + 0x4e3e1ec0; (* arm_AND_VEC Q0 Q22 Q30 128 *) + 0x9bb5075b; (* arm_UMADDL X27 W26 W21 X1 *) + 0x2ead81d2; (* arm_UMLAL_VEC Q18 Q14 Q13 32 *) + 0x9bb502fe; (* arm_UMADDL X30 W23 W21 X0 *) + 0x2ea38052; (* arm_UMLAL_VEC Q18 Q2 Q3 32 *) + 0xd360fcaa; (* arm_LSR X10 X5 32 *) + 0x4e3e1cc4; (* arm_AND_VEC Q4 Q6 Q30 128 *) + 0x4e371d41; (* arm_AND_VEC Q1 Q10 Q23 128 *) + 0x9bb561c4; (* arm_UMADDL X4 W14 W21 X24 *) + 0xf9402fe0; (* arm_LDR X0 SP (Immediate_Offset (word 88)) *) + 0x4e0c1c00; (* arm_INS_GEN Q0 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c01; (* arm_INS_GEN Q1 W0 32 32 *) + 0x9bb520e9; (* arm_UMADDL X9 W7 W21 X8 *) + 0x6f6614d2; (* arm_USRA_VEC Q18 Q6 26 64 128 *) + 0x9bb57158; (* arm_UMADDL X24 W10 W21 X28 *) + 0x4e371ce3; (* arm_AND_VEC Q3 Q7 Q23 128 *) + 0x9bb53ec8; (* arm_UMADDL X8 W22 W21 X15 *) + 0x2eba81db; (* arm_UMLAL_VEC Q27 Q14 Q26 32 *) + 0x9bb545af; (* arm_UMADDL X15 W13 W21 X17 *) + 0x6f671655; (* arm_USRA_VEC Q21 Q18 25 64 128 *) + 0xa9094ff4; (* arm_STP X20 X19 SP (Immediate_Offset (iword (&144))) *) + 0x4e3e1d62; (* arm_AND_VEC Q2 Q11 Q30 128 *) + 0xd359fd1d; (* arm_LSR X29 X8 25 *) + 0xf94043e3; (* arm_LDR X3 SP (Immediate_Offset (word 128)) *) + 0x4e0c1c6a; (* arm_INS_GEN Q10 W3 32 32 *) 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) + 0x4e0c1c6b; (* arm_INS_GEN Q11 W3 32 32 *) + 0x8b1d01f1; (* arm_ADD X17 X15 X29 *) + 0x6f6616bb; (* arm_USRA_VEC Q27 Q21 26 64 128 *) + 0x8b1d063c; (* arm_ADD X28 X17 (Shiftedreg X29 LSL 1) *) + 0x4e3e1ea6; (* arm_AND_VEC Q6 Q21 Q30 128 *) + 0x92406114; (* arm_AND X20 X8 (rvalue (word 33554431)) *) + 0x4e371e45; (* arm_AND_VEC Q5 Q18 Q23 128 *) + 0x8b1d1391; (* arm_ADD X17 X28 (Shiftedreg X29 LSL 4) *) + 0x4e371f67; (* arm_AND_VEC Q7 Q27 Q23 128 *) + 0xf94047e3; (* arm_LDR X3 SP (Immediate_Offset (word 136)) *) + 0x4e0c1c76; (* arm_INS_GEN Q22 W3 32 32 *) 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) + 0x4e0c1c77; (* arm_INS_GEN Q23 W3 32 32 *) + 0x8b516b3d; (* arm_ADD X29 X25 (Shiftedreg X17 LSR 26) *) + 0xf94013ef; (* arm_LDR X15 SP (Immediate_Offset (word 32)) *) + 0x4e041dea; (* arm_INS_GEN Q10 W15 0 32 *) 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) + 0x4e041deb; (* arm_INS_GEN Q11 W15 0 32 *) + 0x9240662b; (* arm_AND X11 X17 (rvalue (word 67108863)) *) + 0x6f671770; (* arm_USRA_VEC Q16 Q27 25 64 128 *) + 0x8b5d6588; (* arm_ADD X8 X12 (Shiftedreg X29 LSR 25) *) + 0xf9404be3; (* arm_LDR X3 SP (Immediate_Offset (word 144)) *) + 0x4e0c1c6e; (* arm_INS_GEN Q14 W3 32 32 *) + 0xd360fc63; (* arm_LSR X3 X3 32 *) + 0x4e0c1c6f; (* arm_INS_GEN Q15 W3 32 32 *) + 0x924063ac; (* arm_AND X12 X29 (rvalue (word 33554431)) *) + 0xf94017ef; (* arm_LDR X15 SP (Immediate_Offset (word 40)) *) + 0x4e041df6; (* arm_INS_GEN Q22 W15 0 32 *) 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) + 0x4e041df7; (* arm_INS_GEN Q23 W15 0 32 *) + 0x8b486b7c; (* arm_ADD X28 X27 (Shiftedreg X8 LSR 26) *) + 0x4e3e1e08; (* arm_AND_VEC Q8 Q16 Q30 128 *) + 0x9baa7d81; (* arm_UMULL X1 W12 W10 *) + 0xf9404fe3; (* arm_LDR X3 SP (Immediate_Offset (word 152)) *) + 0x4e0c1c71; (* arm_INS_GEN Q17 W3 32 32 *) + 0xd360fc63; (* arm_LSR X3 X3 32 *) + 0x4e0c1c72; (* arm_INS_GEN Q18 W3 32 32 *) + 0x8b5c6539; (* arm_ADD X25 X9 (Shiftedreg X28 LSR 25) *) + 0xf9401bef; (* arm_LDR X15 SP (Immediate_Offset (word 48)) *) + 0x4e041dee; (* arm_INS_GEN Q14 W15 0 32 *) 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) + 0x4e041def; (* arm_INS_GEN Q15 W15 0 32 *) + 0x9bb508b3; (* arm_UMADDL X19 W5 W21 X2 *) + 0x6f661609; (* arm_USRA_VEC Q9 Q16 26 64 128 *) + 0x8b596882; (* arm_ADD X2 X4 (Shiftedreg X25 LSR 26) *) + 0xf94053e3; (* arm_LDR X3 SP (Immediate_Offset (word 160)) *) + 0x4e0c1c78; (* arm_INS_GEN Q24 W3 32 32 *) + 0xd360fc63; (* arm_LSR X3 X3 32 *) + 0x4e0c1c79; (* arm_INS_GEN Q25 W3 32 32 *) + 0x9bb77d83; (* arm_UMULL X3 W12 W23 *) + 0xf9401fef; (* arm_LDR X15 SP (Immediate_Offset (word 56)) *) + 0x4e041df1; (* arm_INS_GEN Q17 W15 0 32 *) 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xd2801fb4; (* arm_MOV X20 (rvalue (word 253)) *) - 0xa94e1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&224))) *) - 0xa9440fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&64))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa94f23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&240))) *) - 0xa9450fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&80))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9081be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&128))) *) - 0xa90923e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&144))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94a23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa9531be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa94b23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90613e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&96))) *) - 0xa9071be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&112))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa94a0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&160))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa94b0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&176))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90a1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0xa90b23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xa94e13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&224))) *) - 0xa94423e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&64))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa94f1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&240))) *) - 0xa94523e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&80))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) + 0x4e041df2; (* arm_INS_GEN Q18 W15 0 32 *) + 0x8b42667d; (* arm_ADD X29 X19 (Shiftedreg X2 LSR 25) *) + 0x2eb7c01a; (* arm_UMULL_VEC Q26 Q0 Q23 32 *) + 0x92406395; (* arm_AND X21 X28 (rvalue (word 33554431)) *) + 0xf94033e0; (* arm_LDR X0 SP (Immediate_Offset (word 96)) *) + 0x4e0c1c02; (* arm_INS_GEN Q2 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c03; (* arm_INS_GEN Q3 W0 32 32 *) + 0x9ba50ebb; (* arm_UMADDL X27 W21 W5 X3 *) + 0xf94023ef; (* arm_LDR X15 SP (Immediate_Offset (word 64)) *) + 0x4e041df8; (* arm_INS_GEN Q24 W15 0 32 *) + 0xd360fdef; (* arm_LSR X15 X15 32 *) + 0x4e041df9; (* arm_INS_GEN Q25 W15 0 32 *) + 0x8b5d6b11; (* arm_ADD X17 X24 (Shiftedreg X29 LSR 26) *) + 0x2eb2c03d; (* arm_UMULL_VEC Q29 Q1 Q18 32 *) + 0x9240650f; (* arm_AND X15 X8 (rvalue (word 67108863)) *) + 0x2eafc014; (* arm_UMULL_VEC Q20 Q0 Q15 32 *) + 0x8b5167d3; (* arm_ADD X19 X30 (Shiftedreg X17 LSR 25) *) + 0x92406223; (* arm_AND X3 X17 (rvalue (word 33554431)) *) + 0x0ebf9f2c; (* arm_MUL_VEC Q12 Q25 Q31 32 64 *) + 0xf94037e0; (* arm_LDR X0 SP (Immediate_Offset (word 104)) *) + 0x4e0c1c04; (* arm_INS_GEN Q4 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c05; (* arm_INS_GEN Q5 W0 32 32 *) + 0x8b536a84; (* arm_ADD X4 X20 (Shiftedreg X19 LSR 26) *) + 0x2eab805a; (* arm_UMLAL_VEC Q26 Q2 Q11 32 *) + 0x0b03047c; (* arm_ADD W28 W3 (Shiftedreg W3 LSL 1) *) + 0x2eb78054; (* arm_UMLAL_VEC Q20 Q2 Q23 32 *) + 0x0b03139c; (* arm_ADD W28 W28 (Shiftedreg W3 LSL 4) *) + 0x9ba57d88; (* arm_UMULL X8 W12 W5 *) + 0xf9403be0; (* arm_LDR X0 SP (Immediate_Offset (word 112)) *) + 0x4e0c1c06; (* arm_INS_GEN Q6 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c07; (* arm_INS_GEN Q7 W0 32 32 *) + 0x9240673e; (* arm_AND X30 X25 (rvalue (word 67108863)) *) + 0x0ebf9e50; (* arm_MUL_VEC Q16 Q18 Q31 32 64 *) + 0x0b040491; (* arm_ADD W17 W4 (Shiftedreg W4 LSL 1) *) + 0x2eafc035; (* arm_UMULL_VEC Q21 Q1 Q15 32 *) + 0x0b041231; (* arm_ADD W17 W17 (Shiftedreg W4 LSL 4) *) + 0x9ba722b9; (* arm_UMADDL X25 W21 W7 X8 *) + 0x2eab8094; (* arm_UMLAL_VEC Q20 Q4 Q11 32 *) + 0x0b1506a8; (* arm_ADD W8 W21 (Shiftedreg W21 LSL 1) *) + 0xf9403fe0; (* arm_LDR X0 SP (Immediate_Offset (word 120)) *) + 0x0b151108; (* arm_ADD W8 W8 (Shiftedreg W21 LSL 4) *) + 0x4e0c1c08; (* arm_INS_GEN Q8 W0 32 32 *) + 0xd360fc00; (* arm_LSR X0 X0 32 *) + 0x4e0c1c09; (* arm_INS_GEN Q9 W0 32 32 *) + 0x92406042; (* arm_AND X2 X2 (rvalue (word 33554431)) *) + 0x2eaf807d; (* arm_UMLAL_VEC Q29 Q3 Q15 32 *) + 0x9ba66458; (* arm_UMADDL X24 W2 W6 X25 *) + 0x2eb9c00d; (* arm_UMULL_VEC Q13 Q0 Q25 32 *) + 0x9ba76c59; (* arm_UMADDL X25 W2 W7 X27 *) + 0x9ba66460; (* arm_UMADDL X0 W3 W6 X25 *) + 0x0ebf9df3; (* arm_MUL_VEC Q19 Q15 Q31 32 64 *) + 0x2eb2c01b; (* arm_UMULL_VEC Q27 Q0 Q18 32 *) + 0x9bad6074; (* arm_UMADDL X20 W3 W13 X24 *) + 0x2eac80d4; (* arm_UMLAL_VEC Q20 Q6 Q12 32 *) + 0x9bae06b8; (* arm_UMADDL X24 W21 W14 X1 *) + 0x2eb2804d; (* arm_UMLAL_VEC Q13 Q2 Q18 32 *) + 0x9bad0089; (* arm_UMADDL X9 W4 W13 X0 *) + 0x2eabc019; (* arm_UMULL_VEC Q25 Q0 Q11 32 *) + 0x9bb75234; (* arm_UMADDL X20 W17 W23 X20 *) + 0x2eaf805b; (* arm_UMLAL_VEC Q27 Q2 Q15 32 *) + 0x9bba6040; (* arm_UMADDL X0 W2 W26 X24 *) + 0x2eabc03c; (* arm_UMULL_VEC Q28 Q1 Q11 32 *) + 0x9ba57e38; (* arm_UMULL X24 W17 W5 *) + 0x2eb780bd; (* arm_UMLAL_VEC Q29 Q5 Q23 32 *) + 0x9bb62569; (* arm_UMADDL X9 W11 W22 X9 *) + 0x2eaf808d; (* arm_UMLAL_VEC Q13 Q4 Q15 32 *) + 0x9bb0007b; (* arm_UMADDL X27 W3 W16 X0 *) + 0x2eb7809b; (* arm_UMLAL_VEC Q27 Q4 Q23 32 *) + 0x9bae7e20; (* arm_UMULL X0 W17 W14 *) + 0x2eab80db; (* arm_UMLAL_VEC Q27 Q6 Q11 32 *) + 0x9bae7d84; (* arm_UMULL X4 W12 W14 *) + 0x2eac811b; (* arm_UMLAL_VEC Q27 Q8 Q12 32 *) + 0x9baa5179; (* arm_UMADDL X25 W11 W10 X20 *) + 0x2eb1803b; (* arm_UMLAL_VEC Q27 Q1 Q17 32 *) + 0x9baa0380; (* arm_UMADDL X0 W28 W10 X0 *) + 0x2eb780cd; (* arm_UMLAL_VEC Q13 Q6 Q23 32 *) + 0x9ba67e23; (* arm_UMULL X3 W17 W6 *) + 0x2eab810d; (* arm_UMLAL_VEC Q13 Q8 Q11 32 *) + 0x9bba12a1; (* arm_UMADDL X1 W21 W26 X4 *) + 0x2eb08114; (* arm_UMLAL_VEC Q20 Q8 Q16 32 *) + 0x9bad6044; (* arm_UMADDL X4 W2 W13 X24 *) + 0x2eac807c; (* arm_UMLAL_VEC Q28 Q3 Q12 32 *) + 0x9ba70f94; (* arm_UMADDL X20 W28 W7 X3 *) + 0x2eab80fd; (* arm_UMLAL_VEC Q29 Q7 Q11 32 *) + 0x92406663; (* arm_AND X3 X19 (rvalue (word 67108863)) *) + 0x2eac813d; (* arm_UMLAL_VEC Q29 Q9 Q12 32 *) + 0x9bb66e33; (* arm_UMADDL X19 W17 W22 X27 *) + 0x0b02045b; (* arm_ADD W27 W2 (Shiftedreg W2 LSL 1) *) + 0x0ebf9f12; (* arm_MUL_VEC Q18 Q24 Q31 32 64 *) + 0x0b02137b; (* arm_ADD W27 W27 (Shiftedreg W2 LSL 4) *) + 0x2eb78075; (* arm_UMLAL_VEC Q21 Q3 Q23 32 *) + 0x9ba77e38; (* arm_UMULL X24 W17 W7 *) + 0x2eb8802d; (* arm_UMLAL_VEC Q13 Q1 Q24 32 *) + 0x8b130273; (* arm_ADD X19 X19 X19 *) + 0x4f4157bd; (* arm_SHL_VEC Q29 Q29 1 64 128 *) + 0x9bb00441; (* arm_UMADDL X1 W2 W16 X1 *) + 0x2eb7c02f; (* arm_UMULL_VEC Q15 Q1 Q23 32 *) + 0x9bb60360; (* arm_UMADDL X0 W27 W22 X0 *) + 0x2eb8801d; (* arm_UMLAL_VEC Q29 Q0 Q24 32 *) + 0x9ba56382; (* arm_UMADDL X2 W28 W5 X24 *) + 0x0ebf9ef8; (* arm_MUL_VEC Q24 Q23 Q31 32 64 *) + 0x9bb71384; (* arm_UMADDL X4 W28 W23 X4 *) + 0x2eab80b5; (* arm_UMLAL_VEC Q21 Q5 Q11 32 *) + 0x9ba55378; (* arm_UMADDL X24 W27 W5 X20 *) + 0x2eae8034; (* arm_UMLAL_VEC Q20 Q1 Q14 32 *) + 0x9bb74d74; (* arm_UMADDL X20 W11 W23 X19 *) + 0x2eac809a; (* arm_UMLAL_VEC Q26 Q4 Q12 32 *) + 0x9bb70b73; (* arm_UMADDL X19 W27 W23 X2 *) + 0x2eb080da; (* arm_UMLAL_VEC Q26 Q6 Q16 32 *) + 0x9ba612a2; (* arm_UMADDL X2 W21 W6 X4 *) + 0x2eb1805d; (* arm_UMLAL_VEC Q29 Q2 Q17 32 *) + 0x9bb76118; (* arm_UMADDL X24 W8 W23 X24 *) + 0x2eab806f; (* arm_UMLAL_VEC Q15 Q3 Q11 32 *) + 0x9bb002a0; (* arm_UMADDL X0 W21 W16 X0 *) + 0x9bad4ea4; (* arm_UMADDL X4 W21 W13 X19 *) + 0x0ebf9d77; (* arm_MUL_VEC Q23 Q11 Q31 32 64 *) + 0x2eb68074; (* arm_UMLAL_VEC Q20 Q3 Q22 32 *) + 0x9ba70982; (* arm_UMADDL X2 W12 W7 X2 *) + 0x2eaa80b4; (* arm_UMLAL_VEC Q20 Q5 Q10 32 *) + 0x9bba0193; (* arm_UMADDL X19 W12 W26 X0 *) + 0x2eae809d; (* arm_UMLAL_VEC Q29 Q4 Q14 32 *) + 0x9bad6180; (* arm_UMADDL X0 W12 W13 X24 *) + 0x2eb3811a; (* arm_UMLAL_VEC Q26 Q8 Q19 32 *) + 0x9ba551f4; (* arm_UMADDL X20 W15 W5 X20 *) + 0x2eb6803a; (* arm_UMLAL_VEC Q26 Q1 Q22 32 *) + 0x9baa25f5; (* arm_UMADDL X21 W15 W10 X9 *) + 0x2eaa807a; (* arm_UMLAL_VEC Q26 Q3 Q10 32 *) + 0x924067a9; (* arm_AND X9 X29 (rvalue (word 67108863)) *) + 0x2eb680dd; (* arm_UMLAL_VEC Q29 Q6 Q22 32 *) + 0x9ba753d4; (* arm_UMADDL X20 W30 W7 X20 *) + 0x9bb60781; (* arm_UMADDL X1 W28 W22 X1 *) + 0x8b130278; (* arm_ADD X24 X19 X19 *) + 0x2eacc02b; (* arm_UMULL_VEC Q11 Q1 Q12 32 *) + 0x0b030473; (* arm_ADD W19 W3 (Shiftedreg W3 LSL 1) *) + 0x2eb280ba; (* arm_UMLAL_VEC Q26 Q5 Q18 32 *) + 0x0b031273; (* arm_ADD W19 W19 (Shiftedreg W3 LSL 4) *) + 0x9ba65134; (* arm_UMADDL X20 W9 W6 X20 *) + 0x2eaa811d; (* arm_UMLAL_VEC Q29 Q8 Q10 32 *) + 0x0b09053d; (* arm_ADD W29 W9 (Shiftedreg W9 LSL 1) *) + 0x2eb1806d; (* arm_UMLAL_VEC Q13 Q3 Q17 32 *) + 0x0b0913bd; (* arm_ADD W29 W29 (Shiftedreg W9 LSL 4) *) + 0x9baa0a62; (* arm_UMADDL X2 W19 W10 X2 *) + 0x2eb0806b; (* arm_UMLAL_VEC Q11 Q3 Q16 32 *) + 0x9bae57d5; (* arm_UMADDL X21 W30 W14 X21 *) + 0x2eb380ab; (* arm_UMLAL_VEC Q11 Q5 Q19 32 *) + 0x9bad5074; (* arm_UMADDL X20 W3 W13 X20 *) + 0x2eb880eb; (* arm_UMLAL_VEC Q11 Q7 Q24 32 *) + 0x9bb60ba2; (* arm_UMADDL X2 W29 W22 X2 *) + 0x2eb7812b; (* arm_UMLAL_VEC Q11 Q9 Q23 32 *) + 0x9bba5535; (* arm_UMADDL X21 W9 W26 X21 *) + 0x6f7f07d7; (* arm_USHR_VEC Q23 Q30 1 64 128 *) + 0x9baa0621; (* arm_UMADDL X1 W17 W10 X1 *) + 0x2eae80ad; (* arm_UMLAL_VEC Q13 Q5 Q14 32 *) + 0x9ba56278; (* arm_UMADDL X24 W19 W5 X24 *) + 0x2eae807b; (* arm_UMLAL_VEC Q27 Q3 Q14 32 *) + 0x9bb05475; (* arm_UMADDL X21 W3 W16 X21 *) + 0x4f41556b; (* arm_SHL_VEC Q11 Q11 1 64 128 *) + 0x0b1e07c3; (* arm_ADD W3 W30 (Shiftedreg W30 LSL 1) *) + 0x2eb080bc; (* arm_UMLAL_VEC Q28 Q5 Q16 32 *) + 0x0b1e1063; (* arm_ADD W3 W3 (Shiftedreg W30 LSL 4) *) + 0x9bb763b8; (* arm_UMADDL X24 W29 W23 X24 *) + 0x2eb380fc; (* arm_UMLAL_VEC Q28 Q7 Q19 32 *) + 0x8b010021; (* arm_ADD X1 X1 X1 *) + 0x2eb8813c; (* arm_UMLAL_VEC Q28 Q9 Q24 32 *) + 0x9ba50561; (* arm_UMADDL X1 W11 W5 X1 *) + 0x2eac80af; (* arm_UMLAL_VEC Q15 Q5 Q12 32 *) + 0x9bad63d8; (* arm_UMADDL X24 W30 W13 X24 *) + 0x2eb080ef; (* arm_UMLAL_VEC Q15 Q7 Q16 32 *) + 0x9bae65f9; (* arm_UMADDL X25 W15 W14 X25 *) + 0x2eb3812f; (* arm_UMLAL_VEC Q15 Q9 Q19 32 *) + 0x9ba705e1; (* arm_UMADDL X1 W15 W7 X1 *) + 0x4f41579c; (* arm_SHL_VEC Q28 Q28 1 64 128 *) + 0x9ba661f8; (* arm_UMADDL X24 W15 W6 X24 *) + 0x2eac80f5; (* arm_UMLAL_VEC Q21 Q7 Q12 32 *) + 0x9bb00bc2; (* arm_UMADDL X2 W30 W16 X2 *) + 0x2eb08135; (* arm_UMLAL_VEC Q21 Q9 Q16 32 *) + 0x9bba67d9; (* arm_UMADDL X25 W30 W26 X25 *) + 0x4f4155ef; (* arm_SHL_VEC Q15 Q15 1 64 128 *) + 0x9ba607de; (* arm_UMADDL X30 W30 W6 X1 *) + 0x2eb6801c; (* arm_UMLAL_VEC Q28 Q0 Q22 32 *) + 0x9bba09e1; (* arm_UMADDL X1 W15 W26 X2 *) + 0x2eaa805c; (* arm_UMLAL_VEC Q28 Q2 Q10 32 *) + 0x9bb06522; (* arm_UMADDL X2 W9 W16 X25 *) + 0x4f4156b5; (* arm_SHL_VEC Q21 Q21 1 64 128 *) + 0x9ba76178; (* arm_UMADDL X24 W11 W7 X24 *) + 0x2eae800f; (* arm_UMLAL_VEC Q15 Q0 Q14 32 *) + 0x9bae0561; (* arm_UMADDL X1 W11 W14 X1 *) + 0x2eb18015; (* arm_UMLAL_VEC Q21 Q0 Q17 32 *) + 0x9bad7939; (* arm_UMADDL X25 W9 W13 X30 *) + 0x2eb2809c; (* arm_UMLAL_VEC Q28 Q4 Q18 32 *) + 0x9bba0260; (* arm_UMADDL X0 W19 W26 X0 *) + 0x2eac8059; (* arm_UMLAL_VEC Q25 Q2 Q12 32 *) + 0x8b586821; (* arm_ADD X1 X1 (Shiftedreg X24 LSR 26) *) + 0x2eb08099; (* arm_UMLAL_VEC Q25 Q4 Q16 32 *) + 0x9bb60a7e; (* arm_UMADDL X30 W19 W22 X2 *) + 0x2eae8055; (* arm_UMLAL_VEC Q21 Q2 Q14 32 *) + 0x9ba61184; (* arm_UMADDL X4 W12 W6 X4 *) + 0x0ebf9dce; (* arm_MUL_VEC Q14 Q14 Q31 32 64 *) + 0x9bb76679; (* arm_UMADDL X25 W19 W23 X25 *) + 0x92406022; (* arm_AND X2 X1 (rvalue (word 33554431)) *) + 0x0ebf9e30; (* arm_MUL_VEC Q16 Q17 Q31 32 64 *) + 0x2eb380d9; (* arm_UMLAL_VEC Q25 Q6 Q19 32 *) + 0x9bae1269; (* arm_UMADDL X9 W19 W14 X4 *) + 0x2eb680ed; (* arm_UMLAL_VEC Q13 Q7 Q22 32 *) + 0x8b416739; (* arm_ADD X25 X25 (Shiftedreg X1 LSR 25) *) + 0x2eb68095; (* arm_UMLAL_VEC Q21 Q4 Q22 32 *) + 0x9bae03a0; (* arm_UMADDL X0 W29 W14 X0 *) + 0x2eb080fa; (* arm_UMLAL_VEC Q26 Q7 Q16 32 *) + 0x8b596bde; (* arm_ADD X30 X30 (Shiftedreg X25 LSR 26) *) + 0x2eae813a; (* arm_UMLAL_VEC Q26 Q9 Q14 32 *) + 0x0b0f05e1; (* arm_ADD W1 W15 (Shiftedreg W15 LSL 1) *) + 0x2eb080dc; (* arm_UMLAL_VEC Q28 Q6 Q16 32 *) + 0x0b0f1021; (* arm_ADD W1 W1 (Shiftedreg W15 LSL 4) *) + 0x8b5e6684; (* arm_ADD X4 X20 (Shiftedreg X30 LSR 25) *) + 0x2eae811c; (* arm_UMLAL_VEC Q28 Q8 Q14 32 *) + 0x92406739; (* arm_AND X25 X25 (rvalue (word 67108863)) *) + 0x2eb6804f; (* arm_UMLAL_VEC Q15 Q2 Q22 32 *) + 0x8b446ab5; (* arm_ADD X21 X21 (Shiftedreg X4 LSR 26) *) + 0x2eaa800b; (* arm_UMLAL_VEC Q11 Q0 Q10 32 *) + 0xb36063d9; (* arm_BFM X25 X30 32 24 *) + 0x2eb2804b; (* arm_UMLAL_VEC Q11 Q2 Q18 32 *) + 0x926696be; (* arm_AND X30 X21 (rvalue (word 18446744073642442752)) *) + 0x6f66179a; (* arm_USRA_VEC Q26 Q28 26 64 128 *) + 0xd35affd4; (* arm_LSR X20 X30 26 *) + 0x2eaa808f; (* arm_UMLAL_VEC Q15 Q4 Q10 32 *) + 0x8b5e6694; (* arm_ADD X20 X20 (Shiftedreg X30 LSR 25) *) + 0x2eb280cf; (* arm_UMLAL_VEC Q15 Q6 Q18 32 *) + 0x9baa27a9; (* arm_UMADDL X9 W29 W10 X9 *) + 0x2eb0810f; (* arm_UMLAL_VEC Q15 Q8 Q16 32 *) + 0x8b5e5a9e; (* arm_ADD X30 X20 (Shiftedreg X30 LSR 22) *) + 0x2eb680bb; (* arm_UMLAL_VEC Q27 Q5 Q22 32 *) + 0x9bba7e34; (* arm_UMULL X20 W17 W26 *) + 0x2eb280f4; (* arm_UMLAL_VEC Q20 Q7 Q18 32 *) + 0x9bb07a3e; (* arm_UMADDL X30 W17 W16 X30 *) + 0x2eb08134; (* arm_UMLAL_VEC Q20 Q9 Q16 32 *) + 0x9baa0071; (* arm_UMADDL X17 W3 W10 X0 *) + 0x6f67174f; (* arm_USRA_VEC Q15 Q26 25 64 128 *) + 0x9bae5380; (* arm_UMADDL X0 W28 W14 X20 *) + 0x2eaa80fb; (* arm_UMLAL_VEC Q27 Q7 Q10 32 *) + 0x9bba7b94; (* arm_UMADDL X20 W28 W26 X30 *) + 0x2eb2813b; (* arm_UMLAL_VEC Q27 Q9 Q18 32 *) + 0x0b0c059c; (* arm_ADD W28 W12 (Shiftedreg W12 LSL 1) *) + 0x6f6615f4; (* arm_USRA_VEC Q20 Q15 26 64 128 *) + 0x0b0c139c; (* arm_ADD W28 W28 (Shiftedreg W12 LSL 4) *) + 0x9baa037e; (* arm_UMADDL X30 W27 W10 X0 *) + 0x4e3e1df1; (* arm_AND_VEC Q17 Q15 Q30 128 *) + 0x9bae537b; (* arm_UMADDL X27 W27 W14 X20 *) + 0x9baa6d00; (* arm_UMADDL X0 W8 W10 X27 *) + 0x0ebf9ecc; (* arm_MUL_VEC Q12 Q22 Q31 32 64 *) + 0x4e371e8f; (* arm_AND_VEC Q15 Q20 Q23 128 *) + 0x9bb6246e; (* arm_UMADDL X14 W3 W22 X9 *) + 0x2eaa80d5; (* arm_UMLAL_VEC Q21 Q6 Q10 32 *) + 0x9bb6791b; (* arm_UMADDL X27 W8 W22 X30 *) + 0x4e8f2a2f; (* arm_TRN1 Q15 Q17 Q15 32 128 *) + 0x9bb6038a; (* arm_UMADDL X10 W28 W22 X0 *) + 0x2eb0808b; (* arm_UMLAL_VEC Q11 Q4 Q16 32 *) + 0x9bb039fe; (* arm_UMADDL X30 W15 W16 X14 *) + 0x4e371f5a; (* arm_AND_VEC Q26 Q26 Q23 128 *) + 0x9bb06d9c; (* arm_UMADDL X28 W12 W16 X27 *) + 0x2eb28115; (* arm_UMLAL_VEC Q21 Q8 Q18 32 *) + 0x8b0a014a; (* arm_ADD X10 X10 X10 *) + 0x2eb88119; (* arm_UMLAL_VEC Q25 Q8 Q24 32 *) + 0x9ba62a74; (* arm_UMADDL X20 W19 W6 X10 *) + 0x2eaa8039; (* arm_UMLAL_VEC Q25 Q1 Q10 32 *) + 0x8b1c039c; (* arm_ADD X28 X28 X28 *) + 0x2eb28079; (* arm_UMLAL_VEC Q25 Q3 Q18 32 *) + 0x9ba7727c; (* arm_UMADDL X28 W19 W7 X28 *) + 0x6f671695; (* arm_USRA_VEC Q21 Q20 25 64 128 *) + 0x9ba753a0; (* arm_UMADDL X0 W29 W7 X20 *) + 0x2eae80cb; (* arm_UMLAL_VEC Q11 Q6 Q14 32 *) + 0x9bba796a; (* arm_UMADDL X10 W11 W26 X30 *) + 0x2eaa812d; (* arm_UMLAL_VEC Q13 Q9 Q10 32 *) + 0x9ba573b3; (* arm_UMADDL X19 W29 W5 X28 *) + 0x6f6616bb; (* arm_USRA_VEC Q27 Q21 26 64 128 *) + 0x9ba50060; (* arm_UMADDL X0 W3 W5 X0 *) + 0x2eb080b9; (* arm_UMLAL_VEC Q25 Q5 Q16 32 *) + 0x9bb64434; (* arm_UMADDL X20 W1 W22 X17 *) + 0x4e3e1f94; (* arm_AND_VEC Q20 Q28 Q30 128 *) + 0x9bb74c7d; (* arm_UMADDL X29 W3 W23 X19 *) + 0x6f67177d; (* arm_USRA_VEC Q29 Q27 25 64 128 *) + 0x9bb70023; (* arm_UMADDL X3 W1 W23 X0 *) + 0x4e371f7b; (* arm_AND_VEC Q27 Q27 Q23 128 *) + 0x2eac810b; (* arm_UMLAL_VEC Q11 Q8 Q12 32 *) + 0x9bad75ec; (* arm_UMADDL X12 W15 W13 X29 *) + 0x6f6617ad; (* arm_USRA_VEC Q13 Q29 26 64 128 *) + 0x9bad0d67; (* arm_UMADDL X7 W11 W13 X3 *) + 0x4e8728c6; (* arm_TRN1 Q6 Q6 Q7 32 128 *) + 0x9bb05171; (* arm_UMADDL X17 W11 W16 X20 *) + 0x2eae80f9; (* arm_UMLAL_VEC Q25 Q7 Q14 32 *) + 0x92406497; (* arm_AND X23 X4 (rvalue (word 67108863)) *) + 0x4e771db3; (* arm_BIC_VEC Q19 Q13 Q23 128 *) + 0x9ba63173; (* arm_UMADDL X19 W11 W6 X12 *) + 0x4e371dbc; (* arm_AND_VEC Q28 Q13 Q23 128 *) + 0x8b476a23; (* arm_ADD X3 X17 (Shiftedreg X7 LSR 26) *) + 0x6f67166b; (* arm_USRA_VEC Q11 Q19 25 64 128 *) + 0x4e832842; (* arm_TRN1 Q2 Q2 Q3 32 128 *) + 0x8b436671; (* arm_ADD X17 X19 (Shiftedreg X3 LSR 25) *) + 0x4e3e1ead; (* arm_AND_VEC Q13 Q21 Q30 128 *) + 0x924064e5; (* arm_AND X5 X7 (rvalue (word 67108863)) *) + 0x6f68166b; (* arm_USRA_VEC Q11 Q19 24 64 128 *) + 0x8b516947; (* arm_ADD X7 X10 (Shiftedreg X17 LSR 26) *) + 0x4e812800; (* arm_TRN1 Q0 Q0 Q1 32 128 *) + 0x92406713; (* arm_AND X19 X24 (rvalue (word 67108863)) *) + 0x4e3e1fb5; (* arm_AND_VEC Q21 Q29 Q30 128 *) + 0x8b47667d; (* arm_ADD X29 X19 (Shiftedreg X7 LSR 25) *) + 0x6f6b166b; (* arm_USRA_VEC Q11 Q19 21 64 128 *) + 0xb3606065; (* arm_BFM X5 X3 32 24 *) + 0x4e9b29b1; (* arm_TRN1 Q17 Q13 Q27 32 128 *) + 0x8b5d6853; (* arm_ADD X19 X2 (Shiftedreg X29 LSR 26) *) + 0x4e9c2ab3; (* arm_TRN1 Q19 Q21 Q28 32 128 *) + 0x924067a3; (* arm_AND X3 X29 (rvalue (word 67108863)) *) + 0x6e0844d0; (* arm_INS Q16 Q6 0 64 64 128 *) + 0x6e084626; (* arm_INS Q6 Q17 0 64 64 128 *) + 0x4e892908; (* arm_TRN1 Q8 Q8 Q9 32 128 *) + 0xb3606663; (* arm_BFM X3 X19 32 25 *) + 0x4e3e1d75; (* arm_AND_VEC Q21 Q11 Q30 128 *) + 0xb36066b7; (* arm_BFM X23 X21 32 25 *) + 0x6e084512; (* arm_INS Q18 Q8 0 64 64 128 *) + 0x6e084668; (* arm_INS Q8 Q19 0 64 64 128 *) + 0x2eac8139; (* arm_UMLAL_VEC Q25 Q9 Q12 32 *) + 0x4e081ee9; (* arm_INS_GEN Q9 X23 0 64 *) + 0x4e081f27; (* arm_INS_GEN Q7 X25 0 64 *) + 0xfd4027fd; (* arm_LDR D29 SP (Immediate_Offset (word 72)) *) + 0x6e08444c; (* arm_INS Q12 Q2 0 64 64 128 *) + 0x4e852884; (* arm_TRN1 Q4 Q4 Q5 32 128 *) + 0x92406631; (* arm_AND X17 X17 (rvalue (word 67108863)) *) + 0x6f661579; (* arm_USRA_VEC Q25 Q11 26 64 128 *) + 0x6e08440a; (* arm_INS Q10 Q0 0 64 64 128 *) + 0x6e08448e; (* arm_INS Q14 Q4 0 64 64 128 *) + 0x6e0845e4; (* arm_INS Q4 Q15 0 64 64 128 *) + 0x6f671734; (* arm_USRA_VEC Q20 Q25 25 64 128 *) + 0x4e371f3b; (* arm_AND_VEC Q27 Q25 Q23 128 *) + 0xb36060f1; (* arm_BFM X17 X7 32 24 *) + 0x4e081c65; (* arm_INS_GEN Q5 X3 0 64 *) + 0x4e081ca1; (* arm_INS_GEN Q1 X5 0 64 *) + 0x6f66169a; (* arm_USRA_VEC Q26 Q20 26 64 128 *) + 0x4e3e1e9c; (* arm_AND_VEC Q28 Q20 Q30 128 *) + 0x4e9b2aab; (* arm_TRN1 Q11 Q21 Q27 32 128 *) + 0x4e9a2b8d; (* arm_TRN1 Q13 Q28 Q26 32 128 *) + 0x6e084560; (* arm_INS Q0 Q11 0 64 64 128 *) + 0x4e081e23; (* arm_INS_GEN Q3 X17 0 64 *) + 0x6e0845a2; (* arm_INS Q2 Q13 0 64 64 128 *) + 0xfd402bfc; (* arm_LDR D28 SP (Immediate_Offset (word 80)) *) + 0xf94067e0; (* arm_LDR X0 SP (Immediate_Offset (word 200)) *) + 0xf1000400; (* arm_SUBS X0 X0 (rvalue (word 1)) *) + 0xf90067e0; (* arm_STR X0 SP (Immediate_Offset (word 200)) *) + 0x54ff8062; (* arm_BCS (word 2093068) *) + 0x0e043c00; (* arm_UMOV W0 Q0 0 4 *) + 0x0e0c3c01; (* arm_UMOV W1 Q0 1 4 *) + 0x0e043c42; (* arm_UMOV W2 Q2 0 4 *) + 0x0e0c3c43; (* arm_UMOV W3 Q2 1 4 *) + 0x0e043c84; (* arm_UMOV W4 Q4 0 4 *) + 0x0e0c3c85; (* arm_UMOV W5 Q4 1 4 *) + 0x0e043cc6; (* arm_UMOV W6 Q6 0 4 *) + 0x0e0c3cc7; (* arm_UMOV W7 Q6 1 4 *) + 0x0e043d08; (* arm_UMOV W8 Q8 0 4 *) + 0x0e0c3d09; (* arm_UMOV W9 Q8 1 4 *) + 0x8b016800; (* arm_ADD X0 X0 (Shiftedreg X1 LSL 26) *) + 0x8b036841; (* arm_ADD X1 X2 (Shiftedreg X3 LSL 26) *) + 0x8b056882; (* arm_ADD X2 X4 (Shiftedreg X5 LSL 26) *) + 0x8b0768c3; (* arm_ADD X3 X6 (Shiftedreg X7 LSL 26) *) + 0x8b096904; (* arm_ADD X4 X8 (Shiftedreg X9 LSL 26) *) + 0xab01cc00; (* arm_ADDS X0 X0 (Shiftedreg X1 LSL 51) *) + 0xd34dfc26; (* arm_LSR X6 X1 13 *) + 0xd35a6447; (* arm_LSL X7 X2 38 *) + 0xba0700c1; (* arm_ADCS X1 X6 X7 *) + 0xd35afc48; (* arm_LSR X8 X2 26 *) + 0xd3679869; (* arm_LSL X9 X3 25 *) + 0xba090102; (* arm_ADCS X2 X8 X9 *) + 0xd367fc6a; (* arm_LSR X10 X3 39 *) + 0xd374cc8b; (* arm_LSL X11 X4 12 *) + 0x9a0b0143; (* arm_ADC X3 X10 X11 *) + 0xa90807e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&128))) *) + 0xa9090fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&144))) *) + 0x0e043c20; (* arm_UMOV W0 Q1 0 4 *) + 0x0e0c3c21; (* arm_UMOV W1 Q1 1 4 *) + 0x0e043c62; (* arm_UMOV W2 Q3 0 4 *) + 0x0e0c3c63; (* arm_UMOV W3 Q3 1 4 *) + 0x0e043ca4; (* arm_UMOV W4 Q5 0 4 *) + 0x0e0c3ca5; (* arm_UMOV W5 Q5 1 4 *) + 0x0e043ce6; (* arm_UMOV W6 Q7 0 4 *) + 0x0e0c3ce7; (* arm_UMOV W7 Q7 1 4 *) + 0x0e043d28; (* arm_UMOV W8 Q9 0 4 *) + 0x0e0c3d29; (* arm_UMOV W9 Q9 1 4 *) + 0x5280026a; (* arm_MOV W10 (rvalue (word 19)) *) + 0x8b016800; (* arm_ADD X0 X0 (Shiftedreg X1 LSL 26) *) + 0xf267013f; (* arm_TST X9 (rvalue (word 33554432)) *) + 0x8b036841; (* arm_ADD X1 X2 (Shiftedreg X3 LSL 26) *) + 0x9a9f114a; (* arm_CSEL X10 X10 XZR Condition_NE *) + 0x8b056882; (* arm_ADD X2 X4 (Shiftedreg X5 LSL 26) *) + 0x92406129; (* arm_AND X9 X9 (rvalue (word 33554431)) *) + 0x8b0768c3; (* arm_ADD X3 X6 (Shiftedreg X7 LSL 26) *) + 0x8b0a0000; (* arm_ADD X0 X0 X10 *) + 0x8b096904; (* arm_ADD X4 X8 (Shiftedreg X9 LSL 26) *) + 0xab01cc00; (* arm_ADDS X0 X0 (Shiftedreg X1 LSL 51) *) + 0xd34dfc26; (* arm_LSR X6 X1 13 *) + 0xd35a6447; (* arm_LSL X7 X2 38 *) + 0xba0700c1; (* arm_ADCS X1 X6 X7 *) + 0xd35afc48; (* arm_LSR X8 X2 26 *) + 0xd3679869; (* arm_LSL X9 X3 25 *) + 0xba090102; (* arm_ADCS X2 X8 X9 *) + 0xd367fc6a; (* arm_LSR X10 X3 39 *) + 0xd374cc8b; (* arm_LSL X11 X4 12 *) + 0x9a0b0143; (* arm_ADC X3 X10 X11 *) + 0xa90a07e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&160))) *) + 0xa90b0fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&176))) *) + 0x910283e0; (* arm_ADD X0 SP (rvalue (word 160)) *) + 0x910283e1; (* arm_ADD X1 SP (rvalue (word 160)) *) + 0xaa0003f4; (* arm_MOV X20 X0 *) + 0x9280024a; (* arm_MOVN X10 (word 18) 0 *) + 0x9280000b; (* arm_MOVN X11 (word 0) 0 *) + 0xa9002fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&0))) *) + 0x92f0000c; (* arm_MOVN X12 (word 32768) 48 *) + 0xa90133eb; (* arm_STP X11 X12 SP (Immediate_Offset (iword (&16))) *) + 0xa9400c22; (* arm_LDP X2 X3 X1 (Immediate_Offset (iword (&0))) *) + 0xa9411424; (* arm_LDP X4 X5 X1 (Immediate_Offset (iword (&16))) *) + 0xd2800267; (* arm_MOV X7 (rvalue (word 19)) *) + 0xd37ffca6; (* arm_LSR X6 X5 63 *) + 0x9b061ce6; (* arm_MADD X6 X7 X6 X7 *) + 0xab060042; (* arm_ADDS X2 X2 X6 *) + 0xba1f0063; (* arm_ADCS X3 X3 XZR *) 0xba1f0084; (* arm_ADCS X4 X4 XZR *) + 0xb24100a5; (* arm_ORR X5 X5 (rvalue (word 9223372036854775808)) *) 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90413e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&64))) *) - 0xa9051be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&80))) *) - 0xa94613e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&96))) *) - 0xa9481be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&128))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94713e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&112))) *) - 0xa9491be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&144))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94713e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&112))) *) - 0xa94643ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&96))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94803ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&128))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90c23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa90d2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0xd346fe80; (* arm_LSR X0 X20 6 *) - 0xf8607be2; (* arm_LDR X2 SP (Shiftreg_Offset X0 3) *) - 0x9ad42442; (* arm_LSRV X2 X2 X20 *) - 0x92400042; (* arm_AND X2 X2 (rvalue (word 1)) *) - 0xeb0202bf; (* arm_CMP X21 X2 *) - 0xaa0203f5; (* arm_MOV X21 X2 *) - 0xa94807e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&128))) *) - 0xa94a0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&160))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91007e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&256))) *) - 0xa94907e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&144))) *) - 0xa94b0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&176))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91107e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&272))) *) - 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0xa9460fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&96))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91207e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&288))) *) - 0xa94507e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&80))) *) - 0xa9470fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&112))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91307e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&304))) *) - 0xa94413e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&64))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94513e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&80))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94513e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&80))) *) - 0xa94443ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&64))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90e23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&224))) *) - 0xa90f2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&240))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa94c1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa94e0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&224))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa94d23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xa94f0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&240))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9041be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&64))) *) - 0xa90523e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&80))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94e23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&224))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa94d1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&208))) *) - 0xa94f23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&240))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90e13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&224))) *) - 0xa90f1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&240))) *) - 0xa9442fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&64))) *) - 0xa94537ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&80))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9040fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&64))) *) - 0xa90517e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&80))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xa94e2fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&224))) *) - 0xa94f37ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&240))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa90e0fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&224))) *) - 0xa90f17e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&240))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94413e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&64))) *) - 0xa9421be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&32))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94513e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&80))) *) - 0xa9431be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&48))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94513e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&80))) *) - 0xa94443ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&64))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94203ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&32))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90423e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&64))) *) - 0xa9052be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&80))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xd1000694; (* arm_SUB X20 X20 (rvalue (word 1)) *) - 0xf1000e9f; (* arm_CMP X20 (rvalue (word 3)) *) - 0x54ff3dc2; (* arm_BCS (word 2090936) *) - 0xeb1f02bf; (* arm_CMP X21 XZR *) - 0xa94e07e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&224))) *) - 0xa9520fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91207e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&288))) *) - 0xa94f07e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&240))) *) - 0xa9530fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&304))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa91307e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&304))) *) - 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0xa94a0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&160))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa90a07e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&160))) *) - 0xa94507e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&80))) *) - 0xa94b0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&176))) *) - 0x9a821000; (* arm_CSEL X0 X0 X2 Condition_NE *) - 0x9a831021; (* arm_CSEL X1 X1 X3 Condition_NE *) - 0xa90b07e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&176))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa94a0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&160))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa94b0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&176))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9101be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0xa91123e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94a23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa9531be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa94b23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa91213e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9131be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa94a0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&160))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa94b0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&176))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9101be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0xa91123e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94a23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa9531be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa94b23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa91213e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9131be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa94a0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&160))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa94b0fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&176))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa9101be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0xa91123e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94a23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa9531be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa94b23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&176))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xd28004c9; (* arm_MOV X9 (rvalue (word 38)) *) - 0x9a9f2129; (* arm_CSEL X9 X9 XZR Condition_CS *) - 0xab090063; (* arm_ADDS X3 X3 X9 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa91213e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9131be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&304))) *) - 0xa9502fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&256))) *) - 0xa95137ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&272))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9100fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&256))) *) - 0xa91117e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&272))) *) - 0xa9522fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&288))) *) - 0xa95337ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&304))) *) - 0x9baa7d42; (* arm_UMULL X2 W10 W10 *) - 0xd360fd4e; (* arm_LSR X14 X10 32 *) - 0x9bae7dc3; (* arm_UMULL X3 W14 W14 *) - 0x9bae7d4e; (* arm_UMULL X14 W10 W14 *) - 0xab0e8442; (* arm_ADDS X2 X2 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0063; (* arm_ADC X3 X3 X14 *) - 0x9bab7d64; (* arm_UMULL X4 W11 W11 *) - 0xd360fd6e; (* arm_LSR X14 X11 32 *) - 0x9bae7dc5; (* arm_UMULL X5 W14 W14 *) - 0x9bae7d6e; (* arm_UMULL X14 W11 W14 *) - 0x9b0b7d4f; (* arm_MUL X15 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0e8484; (* arm_ADDS X4 X4 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00a5; (* arm_ADC X5 X5 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0xab0f0063; (* arm_ADDS X3 X3 X15 *) - 0xba100084; (* arm_ADCS X4 X4 X16 *) - 0x9a1f00a5; (* arm_ADC X5 X5 XZR *) - 0x9bac7d86; (* arm_UMULL X6 W12 W12 *) - 0xd360fd8e; (* arm_LSR X14 X12 32 *) - 0x9bae7dc7; (* arm_UMULL X7 W14 W14 *) - 0x9bae7d8e; (* arm_UMULL X14 W12 W14 *) - 0xab0e84c6; (* arm_ADDS X6 X6 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e00e7; (* arm_ADC X7 X7 X14 *) - 0x9bad7da8; (* arm_UMULL X8 W13 W13 *) - 0xd360fdae; (* arm_LSR X14 X13 32 *) - 0x9bae7dc9; (* arm_UMULL X9 W14 W14 *) - 0x9bae7dae; (* arm_UMULL X14 W13 W14 *) - 0x9b0d7d8f; (* arm_MUL X15 X12 X13 *) - 0x9bcd7d90; (* arm_UMULH X16 X12 X13 *) - 0xab0e8508; (* arm_ADDS X8 X8 (Shiftedreg X14 LSL 33) *) - 0xd35ffdce; (* arm_LSR X14 X14 31 *) - 0x9a0e0129; (* arm_ADC X9 X9 X14 *) - 0xab0f01ef; (* arm_ADDS X15 X15 X15 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xab0f00e7; (* arm_ADDS X7 X7 X15 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0xeb0c014a; (* arm_SUBS X10 X10 X12 *) - 0xfa0d016b; (* arm_SBCS X11 X11 X13 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xca10014a; (* arm_EOR X10 X10 X16 *) - 0xeb10014a; (* arm_SUBS X10 X10 X16 *) - 0xca10016b; (* arm_EOR X11 X11 X16 *) - 0xda10016b; (* arm_SBC X11 X11 X16 *) - 0xab0400c6; (* arm_ADDS X6 X6 X4 *) - 0xba0500e7; (* arm_ADCS X7 X7 X5 *) - 0xba1f0108; (* arm_ADCS X8 X8 XZR *) - 0x9a1f0129; (* arm_ADC X9 X9 XZR *) - 0x9baa7d4c; (* arm_UMULL X12 W10 W10 *) - 0xd360fd45; (* arm_LSR X5 X10 32 *) - 0x9ba57cad; (* arm_UMULL X13 W5 W5 *) - 0x9ba57d45; (* arm_UMULL X5 W10 W5 *) - 0xab05858c; (* arm_ADDS X12 X12 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ad; (* arm_ADC X13 X13 X5 *) - 0x9bab7d6f; (* arm_UMULL X15 W11 W11 *) - 0xd360fd65; (* arm_LSR X5 X11 32 *) - 0x9ba57cae; (* arm_UMULL X14 W5 W5 *) - 0x9ba57d65; (* arm_UMULL X5 W11 W5 *) - 0x9b0b7d44; (* arm_MUL X4 X10 X11 *) - 0x9bcb7d50; (* arm_UMULH X16 X10 X11 *) - 0xab0585ef; (* arm_ADDS X15 X15 (Shiftedreg X5 LSL 33) *) - 0xd35ffca5; (* arm_LSR X5 X5 31 *) - 0x9a0501ce; (* arm_ADC X14 X14 X5 *) - 0xab040084; (* arm_ADDS X4 X4 X4 *) - 0xba100210; (* arm_ADCS X16 X16 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab0401ad; (* arm_ADDS X13 X13 X4 *) - 0xba1001ef; (* arm_ADCS X15 X15 X16 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xab060044; (* arm_ADDS X4 X2 X6 *) - 0xba070065; (* arm_ADCS X5 X3 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0xba0900e7; (* arm_ADCS X7 X7 X9 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xeb0c0084; (* arm_SUBS X4 X4 X12 *) - 0xfa0d00a5; (* arm_SBCS X5 X5 X13 *) - 0xfa0f00c6; (* arm_SBCS X6 X6 X15 *) - 0xfa0e00e7; (* arm_SBCS X7 X7 X14 *) - 0xba100108; (* arm_ADCS X8 X8 X16 *) - 0x9a100129; (* arm_ADC X9 X9 X16 *) - 0xd28004ca; (* arm_MOV X10 (rvalue (word 38)) *) - 0x9baa7ccc; (* arm_UMULL X12 W6 W10 *) - 0x8b22418c; (* arm_ADD X12 X12 (Extendedreg W2 UXTW) *) - 0xd360fc42; (* arm_LSR X2 X2 32 *) - 0xd360fcc6; (* arm_LSR X6 X6 32 *) - 0x9baa08c6; (* arm_UMADDL X6 W6 W10 X2 *) - 0xaa0c03e2; (* arm_MOV X2 X12 *) - 0x9baa7cec; (* arm_UMULL X12 W7 W10 *) - 0x8b23418c; (* arm_ADD X12 X12 (Extendedreg W3 UXTW) *) - 0xd360fc63; (* arm_LSR X3 X3 32 *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0x9baa0ce7; (* arm_UMADDL X7 W7 W10 X3 *) - 0xaa0c03e3; (* arm_MOV X3 X12 *) - 0x9baa7d0c; (* arm_UMULL X12 W8 W10 *) - 0x8b24418c; (* arm_ADD X12 X12 (Extendedreg W4 UXTW) *) - 0xd360fc84; (* arm_LSR X4 X4 32 *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0x9baa1108; (* arm_UMADDL X8 W8 W10 X4 *) - 0xaa0c03e4; (* arm_MOV X4 X12 *) - 0x9baa7d2c; (* arm_UMULL X12 W9 W10 *) - 0x8b25418c; (* arm_ADD X12 X12 (Extendedreg W5 UXTW) *) - 0xd360fca5; (* arm_LSR X5 X5 32 *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0x9baa1529; (* arm_UMADDL X9 W9 W10 X5 *) - 0xaa0c03e5; (* arm_MOV X5 X12 *) - 0xd35ffd2d; (* arm_LSR X13 X9 31 *) - 0xd280026b; (* arm_MOV X11 (rvalue (word 19)) *) - 0x9bad7d6b; (* arm_UMULL X11 W11 W13 *) - 0x8b0b0042; (* arm_ADD X2 X2 X11 *) - 0xab068042; (* arm_ADDS X2 X2 (Shiftedreg X6 LSL 32) *) - 0x93c680ea; (* arm_EXTR X10 X7 X6 32 *) - 0xba0a0063; (* arm_ADCS X3 X3 X10 *) - 0x93c7810a; (* arm_EXTR X10 X8 X7 32 *) - 0xba0a0084; (* arm_ADCS X4 X4 X10 *) - 0x93c8812a; (* arm_EXTR X10 X9 X8 32 *) - 0xd34101ab; (* arm_LSL X11 X13 63 *) - 0xca0b00a5; (* arm_EOR X5 X5 X11 *) - 0x9a0a00a5; (* arm_ADC X5 X5 X10 *) - 0xa9120fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&288))) *) - 0xa91317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&304))) *) - 0xa9521be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&288))) *) - 0xa9500fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&256))) *) - 0xeb0400a5; (* arm_SUBS X5 X5 X4 *) - 0xfa0300c6; (* arm_SBCS X6 X6 X3 *) - 0xa95323e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&304))) *) - 0xa9510fe4; (* arm_LDP X4 X3 SP (Immediate_Offset (iword (&272))) *) - 0xfa0400e7; (* arm_SBCS X7 X7 X4 *) - 0xfa030108; (* arm_SBCS X8 X8 X3 *) - 0xd28004c4; (* arm_MOV X4 (rvalue (word 38)) *) - 0x9a9f3083; (* arm_CSEL X3 X4 XZR Condition_CC *) - 0xeb0300a5; (* arm_SUBS X5 X5 X3 *) - 0xfa1f00c6; (* arm_SBCS X6 X6 XZR *) - 0xfa1f00e7; (* arm_SBCS X7 X7 XZR *) - 0xda1f0108; (* arm_SBC X8 X8 XZR *) - 0xa90c1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&192))) *) - 0xa90d23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&208))) *) - 0xd29b6841; (* arm_MOV X1 (rvalue (word 56130)) *) - 0xb2700021; (* arm_ORR X1 X1 (rvalue (word 65536)) *) - 0xa94c23e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&192))) *) - 0xa94d2be9; (* arm_LDP X9 X10 SP (Immediate_Offset (iword (&208))) *) - 0x9b077c23; (* arm_MUL X3 X1 X7 *) - 0x9b087c24; (* arm_MUL X4 X1 X8 *) - 0x9b097c25; (* arm_MUL X5 X1 X9 *) - 0x9b0a7c26; (* arm_MUL X6 X1 X10 *) - 0x9bc77c27; (* arm_UMULH X7 X1 X7 *) - 0x9bc87c28; (* arm_UMULH X8 X1 X8 *) - 0x9bc97c29; (* arm_UMULH X9 X1 X9 *) - 0x9bca7c2a; (* arm_UMULH X10 X1 X10 *) - 0xab070084; (* arm_ADDS X4 X4 X7 *) - 0xba0800a5; (* arm_ADCS X5 X5 X8 *) - 0xba0900c6; (* arm_ADCS X6 X6 X9 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xa95023e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&256))) *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba080084; (* arm_ADCS X4 X4 X8 *) - 0xa95123e7; (* arm_LDP X7 X8 SP (Immediate_Offset (iword (&272))) *) - 0xba0700a5; (* arm_ADCS X5 X5 X7 *) - 0xba0800c6; (* arm_ADCS X6 X6 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xab0600df; (* arm_CMN X6 X6 *) - 0x9240f8c6; (* arm_AND X6 X6 (rvalue (word 9223372036854775807)) *) - 0x9a0a0148; (* arm_ADC X8 X10 X10 *) - 0xd2800269; (* arm_MOV X9 (rvalue (word 19)) *) - 0x9b097d07; (* arm_MUL X7 X8 X9 *) - 0xab070063; (* arm_ADDS X3 X3 X7 *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a1f00c6; (* arm_ADC X6 X6 XZR *) - 0xa90a13e3; (* arm_STP X3 X4 SP (Immediate_Offset (iword (&160))) *) - 0xa90b1be5; (* arm_STP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa9501be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&256))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa9511be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&272))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa95003ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&256))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba07ca5; (* arm_UMULL X5 W5 W0 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xa91223e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&288))) *) - 0xa9132be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&304))) *) - 0xa94c13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&192))) *) - 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa94d13e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&208))) *) - 0xa94c43ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&192))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba014a5; (* arm_UMADDL X5 W5 W0 X5 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) - 0xf241015f; (* arm_TST X10 (rvalue (word 9223372036854775808)) *) - 0x9a9f5063; (* arm_CSEL X3 X3 XZR Condition_PL *) - 0xeb0300e7; (* arm_SUBS X7 X7 X3 *) - 0xfa1f0108; (* arm_SBCS X8 X8 XZR *) - 0xfa1f0129; (* arm_SBCS X9 X9 XZR *) - 0xda1f014a; (* arm_SBC X10 X10 XZR *) - 0x9240f94a; (* arm_AND X10 X10 (rvalue (word 9223372036854775807)) *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0x910383e0; (* arm_ADD X0 SP (rvalue (word 224)) *) - 0x910283e1; (* arm_ADD X1 SP (rvalue (word 160)) *) - 0xaa0003f4; (* arm_MOV X20 X0 *) - 0x9280024a; (* arm_MOVN X10 (word 18) 0 *) - 0x9280000b; (* arm_MOVN X11 (word 0) 0 *) - 0xa9002fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&0))) *) - 0x92f0000c; (* arm_MOVN X12 (word 32768) 48 *) - 0xa90133eb; (* arm_STP X11 X12 SP (Immediate_Offset (iword (&16))) *) - 0xa9400c22; (* arm_LDP X2 X3 X1 (Immediate_Offset (iword (&0))) *) - 0xa9411424; (* arm_LDP X4 X5 X1 (Immediate_Offset (iword (&16))) *) - 0xd2800267; (* arm_MOV X7 (rvalue (word 19)) *) - 0xd37ffca6; (* arm_LSR X6 X5 63 *) - 0x9b061ce6; (* arm_MADD X6 X7 X6 X7 *) - 0xab060042; (* arm_ADDS X2 X2 X6 *) - 0xba1f0063; (* arm_ADCS X3 X3 XZR *) - 0xba1f0084; (* arm_ADCS X4 X4 XZR *) - 0xb24100a5; (* arm_ORR X5 X5 (rvalue (word 9223372036854775808)) *) - 0xba1f00a5; (* arm_ADCS X5 X5 XZR *) - 0x9a9f30e6; (* arm_CSEL X6 X7 XZR Condition_CC *) - 0xeb060042; (* arm_SUBS X2 X2 X6 *) - 0xfa1f0063; (* arm_SBCS X3 X3 XZR *) - 0xfa1f0084; (* arm_SBCS X4 X4 XZR *) - 0xda1f00a5; (* arm_SBC X5 X5 XZR *) - 0x9240f8a5; (* arm_AND X5 X5 (rvalue (word 9223372036854775807)) *) - 0xa9020fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&32))) *) - 0xa90317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&48))) *) - 0xa9047fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&64))) *) - 0xa9057fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&80))) *) - 0xd284132a; (* arm_MOV X10 (rvalue (word 8345)) *) - 0xf2aea04a; (* arm_MOVK X10 (word 29954) 16 *) - 0xf2d3c46a; (* arm_MOVK X10 (word 40483) 32 *) - 0xf2f41f2a; (* arm_MOVK X10 (word 41209) 48 *) - 0xd284b2ab; (* arm_MOV X11 (rvalue (word 9621)) *) - 0xf2a3a26b; (* arm_MOVK X11 (word 7443) 16 *) - 0xf2d1e7eb; (* arm_MOVK X11 (word 36671) 32 *) - 0xf2f518cb; (* arm_MOVK X11 (word 43206) 48 *) - 0xd28a484c; (* arm_MOV X12 (rvalue (word 21058)) *) - 0xf2a0b58c; (* arm_MOVK X12 (word 1452) 16 *) - 0xf2d1270c; (* arm_MOVK X12 (word 35128) 32 *) - 0xf2ed8d8c; (* arm_MOVK X12 (word 27756) 48 *) - 0xd280c2ad; (* arm_MOV X13 (rvalue (word 1557)) *) - 0xf2a82eed; (* arm_MOVK X13 (word 16759) 16 *) - 0xf2c1164d; (* arm_MOVK X13 (word 2226) 32 *) - 0xf2e4ecad; (* arm_MOVK X13 (word 10085) 48 *) - 0xa9062fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&96))) *) - 0xa90737ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&112))) *) - 0xd2800155; (* arm_MOV X21 (rvalue (word 10)) *) - 0xd2800036; (* arm_MOV X22 (rvalue (word 1)) *) - 0x1400010b; (* arm_B (word 1068) *) - 0xeb1f015f; (* arm_CMP X10 XZR *) - 0xda9f53ee; (* arm_CSETM X14 Condition_MI *) - 0xda8a554a; (* arm_CNEG X10 X10 Condition_MI *) - 0xeb1f017f; (* arm_CMP X11 XZR *) - 0xda9f53ef; (* arm_CSETM X15 Condition_MI *) - 0xda8b556b; (* arm_CNEG X11 X11 Condition_MI *) - 0xeb1f019f; (* arm_CMP X12 XZR *) - 0xda9f53f0; (* arm_CSETM X16 Condition_MI *) - 0xda8c558c; (* arm_CNEG X12 X12 Condition_MI *) - 0xeb1f01bf; (* arm_CMP X13 XZR *) - 0xda9f53f1; (* arm_CSETM X17 Condition_MI *) - 0xda8d55ad; (* arm_CNEG X13 X13 Condition_MI *) - 0x8a0e0140; (* arm_AND X0 X10 X14 *) - 0x8a0f0161; (* arm_AND X1 X11 X15 *) - 0x8b010009; (* arm_ADD X9 X0 X1 *) - 0x8a100180; (* arm_AND X0 X12 X16 *) - 0x8a1101a1; (* arm_AND X1 X13 X17 *) - 0x8b010013; (* arm_ADD X19 X0 X1 *) - 0xf94003e7; (* arm_LDR X7 SP (Immediate_Offset (word 0)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000124; (* arm_ADDS X4 X9 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xf94013e8; (* arm_LDR X8 SP (Immediate_Offset (word 32)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000265; (* arm_ADDS X5 X19 X0 *) - 0x9a0103e3; (* arm_ADC X3 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf94007e7; (* arm_LDR X7 SP (Immediate_Offset (word 8)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0103e6; (* arm_ADC X6 XZR X1 *) - 0xf94017e8; (* arm_LDR X8 SP (Immediate_Offset (word 40)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100c6; (* arm_ADC X6 X6 X1 *) - 0x93c4ec44; (* arm_EXTR X4 X2 X4 59 *) - 0xf90003e4; (* arm_STR X4 SP (Immediate_Offset (word 0)) *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000063; (* arm_ADDS X3 X3 X0 *) - 0x9a0103e4; (* arm_ADC X4 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000063; (* arm_ADDS X3 X3 X0 *) - 0x9a010084; (* arm_ADC X4 X4 X1 *) - 0x93c5ec65; (* arm_EXTR X5 X3 X5 59 *) - 0xf90013e5; (* arm_STR X5 SP (Immediate_Offset (word 32)) *) - 0xf9400be7; (* arm_LDR X7 SP (Immediate_Offset (word 16)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0x9a0103e5; (* arm_ADC X5 XZR X1 *) - 0xf9401be8; (* arm_LDR X8 SP (Immediate_Offset (word 48)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0x93c2ecc2; (* arm_EXTR X2 X6 X2 59 *) - 0xf90007e2; (* arm_STR X2 SP (Immediate_Offset (word 8)) *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0x93c3ec83; (* arm_EXTR X3 X4 X3 59 *) - 0xf90017e3; (* arm_STR X3 SP (Immediate_Offset (word 40)) *) - 0xf9400fe7; (* arm_LDR X7 SP (Immediate_Offset (word 24)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x937ffc23; (* arm_ASR X3 X1 63 *) - 0x8a0a0063; (* arm_AND X3 X3 X10 *) - 0xcb0303e3; (* arm_NEG X3 X3 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf9401fe8; (* arm_LDR X8 SP (Immediate_Offset (word 56)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x937ffc20; (* arm_ASR X0 X1 63 *) - 0x8a0b0000; (* arm_AND X0 X0 X11 *) - 0xcb000063; (* arm_SUB X3 X3 X0 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0x93c6eca6; (* arm_EXTR X6 X5 X6 59 *) - 0xf9000be6; (* arm_STR X6 SP (Immediate_Offset (word 16)) *) - 0x93c5ec65; (* arm_EXTR X5 X3 X5 59 *) - 0xf9000fe5; (* arm_STR X5 SP (Immediate_Offset (word 24)) *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x937ffc25; (* arm_ASR X5 X1 63 *) - 0x8a0c00a5; (* arm_AND X5 X5 X12 *) - 0xcb0503e5; (* arm_NEG X5 X5 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x937ffc20; (* arm_ASR X0 X1 63 *) - 0x8a0d0000; (* arm_AND X0 X0 X13 *) - 0xcb0000a5; (* arm_SUB X5 X5 X0 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0x93c4ec44; (* arm_EXTR X4 X2 X4 59 *) - 0xf9001be4; (* arm_STR X4 SP (Immediate_Offset (word 48)) *) - 0x93c2eca2; (* arm_EXTR X2 X5 X2 59 *) - 0xf9001fe2; (* arm_STR X2 SP (Immediate_Offset (word 56)) *) - 0xf94023e7; (* arm_LDR X7 SP (Immediate_Offset (word 64)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000124; (* arm_ADDS X4 X9 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xf94033e8; (* arm_LDR X8 SP (Immediate_Offset (word 96)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0xf90023e4; (* arm_STR X4 SP (Immediate_Offset (word 64)) *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000265; (* arm_ADDS X5 X19 X0 *) - 0x9a0103e3; (* arm_ADC X3 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0xf90033e5; (* arm_STR X5 SP (Immediate_Offset (word 96)) *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf94027e7; (* arm_LDR X7 SP (Immediate_Offset (word 72)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0103e6; (* arm_ADC X6 XZR X1 *) - 0xf94037e8; (* arm_LDR X8 SP (Immediate_Offset (word 104)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0xf90027e2; (* arm_STR X2 SP (Immediate_Offset (word 72)) *) - 0x9a0100c6; (* arm_ADC X6 X6 X1 *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000063; (* arm_ADDS X3 X3 X0 *) - 0x9a0103e4; (* arm_ADC X4 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000063; (* arm_ADDS X3 X3 X0 *) - 0xf90037e3; (* arm_STR X3 SP (Immediate_Offset (word 104)) *) - 0x9a010084; (* arm_ADC X4 X4 X1 *) - 0xf9402be7; (* arm_LDR X7 SP (Immediate_Offset (word 80)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0x9a0103e5; (* arm_ADC X5 XZR X1 *) - 0xf9403be8; (* arm_LDR X8 SP (Immediate_Offset (word 112)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0xf9002be6; (* arm_STR X6 SP (Immediate_Offset (word 80)) *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0xf9003be4; (* arm_STR X4 SP (Immediate_Offset (word 112)) *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0xf9402fe7; (* arm_LDR X7 SP (Immediate_Offset (word 88)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x8a0a01c3; (* arm_AND X3 X14 X10 *) - 0xcb0303e3; (* arm_NEG X3 X3 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf9403fe8; (* arm_LDR X8 SP (Immediate_Offset (word 120)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x8a0b01e0; (* arm_AND X0 X15 X11 *) - 0xcb000063; (* arm_SUB X3 X3 X0 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0x93c5fc66; (* arm_EXTR X6 X3 X5 63 *) - 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0x8b83fcc6; (* arm_ADD X6 X6 (Shiftedreg X3 ASR 63) *) - 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) - 0x9b037cc4; (* arm_MUL X4 X6 X3 *) - 0x8b06fca5; (* arm_ADD X5 X5 (Shiftedreg X6 LSL 63) *) - 0x9b437cc3; (* arm_SMULH X3 X6 X3 *) - 0xf9402be6; (* arm_LDR X6 SP (Immediate_Offset (word 80)) *) - 0xab040000; (* arm_ADDS X0 X0 X4 *) - 0xba030021; (* arm_ADCS X1 X1 X3 *) - 0x937ffc63; (* arm_ASR X3 X3 63 *) - 0xba0300c6; (* arm_ADCS X6 X6 X3 *) - 0x9a0300a5; (* arm_ADC X5 X5 X3 *) - 0xa90407e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0xa90517e6; (* arm_STP X6 X5 SP (Immediate_Offset (iword (&80))) *) - 0xca1000e1; (* arm_EOR X1 X7 X16 *) - 0x8a0c0205; (* arm_AND X5 X16 X12 *) - 0xcb0503e5; (* arm_NEG X5 X5 *) - 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) - 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0xca110101; (* arm_EOR X1 X8 X17 *) - 0x8a0d0220; (* arm_AND X0 X17 X13 *) - 0xcb0000a5; (* arm_SUB X5 X5 X0 *) - 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) - 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0x93c2fca6; (* arm_EXTR X6 X5 X2 63 *) - 0xa94607e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&96))) *) - 0x8b85fcc6; (* arm_ADD X6 X6 (Shiftedreg X5 ASR 63) *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9b057cc4; (* arm_MUL X4 X6 X5 *) - 0x8b06fc42; (* arm_ADD X2 X2 (Shiftedreg X6 LSL 63) *) - 0x9b457cc5; (* arm_SMULH X5 X6 X5 *) - 0xf9403be3; (* arm_LDR X3 SP (Immediate_Offset (word 112)) *) - 0xab040000; (* arm_ADDS X0 X0 X4 *) - 0xba050021; (* arm_ADCS X1 X1 X5 *) - 0x937ffca5; (* arm_ASR X5 X5 63 *) - 0xba050063; (* arm_ADCS X3 X3 X5 *) - 0x9a050042; (* arm_ADC X2 X2 X5 *) - 0xa90607e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&96))) *) - 0xa9070be3; (* arm_STP X3 X2 SP (Immediate_Offset (iword (&112))) *) - 0xaa1603e1; (* arm_MOV X1 X22 *) - 0xf94003e2; (* arm_LDR X2 SP (Immediate_Offset (word 0)) *) - 0xf94013e3; (* arm_LDR X3 SP (Immediate_Offset (word 32)) *) - 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) - 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) - 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) - 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) - 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x91440088; (* arm_ADD X8 X4 (rvalue (word 1048576)) *) - 0x9355a508; (* arm_SBFM X8 X8 21 41 *) - 0xd2a0020b; (* arm_MOVZ X11 (word 16) 16 *) - 0x8b0b556b; (* arm_ADD X11 X11 (Shiftedreg X11 LSL 21) *) - 0x8b0b0089; (* arm_ADD X9 X4 X11 *) - 0x936afd29; (* arm_ASR X9 X9 42 *) - 0x914400aa; (* arm_ADD X10 X5 (rvalue (word 1048576)) *) - 0x9355a54a; (* arm_SBFM X10 X10 21 41 *) - 0x8b0b00ab; (* arm_ADD X11 X5 X11 *) - 0x936afd6b; (* arm_ASR X11 X11 42 *) - 0x9b027d06; (* arm_MUL X6 X8 X2 *) - 0x9b037d27; (* arm_MUL X7 X9 X3 *) - 0x9b027d42; (* arm_MUL X2 X10 X2 *) - 0x9b037d63; (* arm_MUL X3 X11 X3 *) - 0x8b0700c4; (* arm_ADD X4 X6 X7 *) - 0x8b030045; (* arm_ADD X5 X2 X3 *) - 0x9354fc82; (* arm_ASR X2 X4 20 *) - 0x9354fca3; (* arm_ASR X3 X5 20 *) - 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) - 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) - 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) - 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) - 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9144008c; (* arm_ADD X12 X4 (rvalue (word 1048576)) *) - 0x9355a58c; (* arm_SBFM X12 X12 21 41 *) - 0xd2a0020f; (* arm_MOVZ X15 (word 16) 16 *) - 0x8b0f55ef; (* arm_ADD X15 X15 (Shiftedreg X15 LSL 21) *) - 0x8b0f008d; (* arm_ADD X13 X4 X15 *) - 0x936afdad; (* arm_ASR X13 X13 42 *) - 0x914400ae; (* arm_ADD X14 X5 (rvalue (word 1048576)) *) - 0x9355a5ce; (* arm_SBFM X14 X14 21 41 *) - 0x8b0f00af; (* arm_ADD X15 X5 X15 *) - 0x936afdef; (* arm_ASR X15 X15 42 *) - 0x9b027d86; (* arm_MUL X6 X12 X2 *) - 0x9b037da7; (* arm_MUL X7 X13 X3 *) - 0x9b027dc2; (* arm_MUL X2 X14 X2 *) - 0x9b037de3; (* arm_MUL X3 X15 X3 *) - 0x8b0700c4; (* arm_ADD X4 X6 X7 *) - 0x8b030045; (* arm_ADD X5 X2 X3 *) - 0x9354fc82; (* arm_ASR X2 X4 20 *) - 0x9354fca3; (* arm_ASR X3 X5 20 *) - 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) - 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) - 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) - 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) - 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9b087d82; (* arm_MUL X2 X12 X8 *) - 0x9b097d83; (* arm_MUL X3 X12 X9 *) - 0x9b087dc6; (* arm_MUL X6 X14 X8 *) - 0x9b097dc7; (* arm_MUL X7 X14 X9 *) - 0x9b0a09a8; (* arm_MADD X8 X13 X10 X2 *) - 0x9b0b0da9; (* arm_MADD X9 X13 X11 X3 *) - 0x9b0a19f0; (* arm_MADD X16 X15 X10 X6 *) - 0x9b0b1df1; (* arm_MADD X17 X15 X11 X7 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) - 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) - 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) - 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) - 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) - 0x8b0600a5; (* arm_ADD X5 X5 X6 *) - 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) - 0x9341fca5; (* arm_ASR X5 X5 1 *) - 0x9144008c; (* arm_ADD X12 X4 (rvalue (word 1048576)) *) - 0x9356a98c; (* arm_SBFM X12 X12 22 42 *) - 0xd2a0020f; (* arm_MOVZ X15 (word 16) 16 *) - 0x8b0f55ef; (* arm_ADD X15 X15 (Shiftedreg X15 LSL 21) *) - 0x8b0f008d; (* arm_ADD X13 X4 X15 *) - 0x936bfdad; (* arm_ASR X13 X13 43 *) - 0x914400ae; (* arm_ADD X14 X5 (rvalue (word 1048576)) *) - 0x9356a9ce; (* arm_SBFM X14 X14 22 42 *) - 0x8b0f00af; (* arm_ADD X15 X5 X15 *) - 0x936bfdef; (* arm_ASR X15 X15 43 *) - 0x9b08fd82; (* arm_MNEG X2 X12 X8 *) - 0x9b09fd83; (* arm_MNEG X3 X12 X9 *) - 0x9b08fdc4; (* arm_MNEG X4 X14 X8 *) - 0x9b09fdc5; (* arm_MNEG X5 X14 X9 *) - 0x9b1089aa; (* arm_MSUB X10 X13 X16 X2 *) - 0x9b118dab; (* arm_MSUB X11 X13 X17 X3 *) - 0x9b1091ec; (* arm_MSUB X12 X15 X16 X4 *) - 0x9b1195ed; (* arm_MSUB X13 X15 X17 X5 *) - 0xaa0103f6; (* arm_MOV X22 X1 *) - 0xf10006b5; (* arm_SUBS X21 X21 (rvalue (word 1)) *) - 0x54ff9281; (* arm_BNE (word 2093648) *) - 0xf94003e0; (* arm_LDR X0 SP (Immediate_Offset (word 0)) *) - 0xf94013e1; (* arm_LDR X1 SP (Immediate_Offset (word 32)) *) - 0x9b0a7c00; (* arm_MUL X0 X0 X10 *) - 0x9b0b0021; (* arm_MADD X1 X1 X11 X0 *) - 0x937ffc20; (* arm_ASR X0 X1 63 *) - 0xeb1f015f; (* arm_CMP X10 XZR *) - 0xda9f53ee; (* arm_CSETM X14 Condition_MI *) - 0xda8a554a; (* arm_CNEG X10 X10 Condition_MI *) - 0xca0001ce; (* arm_EOR X14 X14 X0 *) - 0xeb1f017f; (* arm_CMP X11 XZR *) - 0xda9f53ef; (* arm_CSETM X15 Condition_MI *) - 0xda8b556b; (* arm_CNEG X11 X11 Condition_MI *) - 0xca0001ef; (* arm_EOR X15 X15 X0 *) - 0xeb1f019f; (* arm_CMP X12 XZR *) - 0xda9f53f0; (* arm_CSETM X16 Condition_MI *) - 0xda8c558c; (* arm_CNEG X12 X12 Condition_MI *) - 0xca000210; (* arm_EOR X16 X16 X0 *) - 0xeb1f01bf; (* arm_CMP X13 XZR *) - 0xda9f53f1; (* arm_CSETM X17 Condition_MI *) - 0xda8d55ad; (* arm_CNEG X13 X13 Condition_MI *) - 0xca000231; (* arm_EOR X17 X17 X0 *) - 0x8a0e0140; (* arm_AND X0 X10 X14 *) - 0x8a0f0161; (* arm_AND X1 X11 X15 *) - 0x8b010009; (* arm_ADD X9 X0 X1 *) - 0xf94023e7; (* arm_LDR X7 SP (Immediate_Offset (word 64)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000124; (* arm_ADDS X4 X9 X0 *) - 0x9a0103e2; (* arm_ADC X2 XZR X1 *) - 0xf94033e8; (* arm_LDR X8 SP (Immediate_Offset (word 96)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000084; (* arm_ADDS X4 X4 X0 *) - 0xf90023e4; (* arm_STR X4 SP (Immediate_Offset (word 64)) *) - 0x9a010042; (* arm_ADC X2 X2 X1 *) - 0xf94027e7; (* arm_LDR X7 SP (Immediate_Offset (word 72)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0x9a0103e6; (* arm_ADC X6 XZR X1 *) - 0xf94037e8; (* arm_LDR X8 SP (Immediate_Offset (word 104)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab000042; (* arm_ADDS X2 X2 X0 *) - 0xf90027e2; (* arm_STR X2 SP (Immediate_Offset (word 72)) *) - 0x9a0100c6; (* arm_ADC X6 X6 X1 *) - 0xf9402be7; (* arm_LDR X7 SP (Immediate_Offset (word 80)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0x9a0103e5; (* arm_ADC X5 XZR X1 *) - 0xf9403be8; (* arm_LDR X8 SP (Immediate_Offset (word 112)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000c6; (* arm_ADDS X6 X6 X0 *) - 0xf9002be6; (* arm_STR X6 SP (Immediate_Offset (word 80)) *) - 0x9a0100a5; (* arm_ADC X5 X5 X1 *) - 0xf9402fe7; (* arm_LDR X7 SP (Immediate_Offset (word 88)) *) - 0xca0e00e1; (* arm_EOR X1 X7 X14 *) - 0x8a0a01c3; (* arm_AND X3 X14 X10 *) - 0xcb0303e3; (* arm_NEG X3 X3 *) - 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) - 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0xf9403fe8; (* arm_LDR X8 SP (Immediate_Offset (word 120)) *) - 0xca0f0101; (* arm_EOR X1 X8 X15 *) - 0x8a0b01e0; (* arm_AND X0 X15 X11 *) - 0xcb000063; (* arm_SUB X3 X3 X0 *) - 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) - 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) - 0xab0000a5; (* arm_ADDS X5 X5 X0 *) - 0x9a010063; (* arm_ADC X3 X3 X1 *) - 0x93c5fc66; (* arm_EXTR X6 X3 X5 63 *) - 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) - 0xea03007f; (* arm_TST X3 X3 *) - 0x9a8644c6; (* arm_CINC X6 X6 Condition_PL *) - 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) - 0x9b037cc4; (* arm_MUL X4 X6 X3 *) - 0x8b06fca5; (* arm_ADD X5 X5 (Shiftedreg X6 LSL 63) *) - 0x9b437cc6; (* arm_SMULH X6 X6 X3 *) - 0xf9402be2; (* arm_LDR X2 SP (Immediate_Offset (word 80)) *) - 0xab040000; (* arm_ADDS X0 X0 X4 *) - 0xba060021; (* arm_ADCS X1 X1 X6 *) - 0x937ffcc6; (* arm_ASR X6 X6 63 *) - 0xba060042; (* arm_ADCS X2 X2 X6 *) - 0xba0600a5; (* arm_ADCS X5 X5 X6 *) - 0x9a9f4063; (* arm_CSEL X3 X3 XZR Condition_MI *) - 0xeb030000; (* arm_SUBS X0 X0 X3 *) - 0xfa1f0021; (* arm_SBCS X1 X1 XZR *) - 0xfa1f0042; (* arm_SBCS X2 X2 XZR *) - 0xda1f00a5; (* arm_SBC X5 X5 XZR *) - 0x9240f8a5; (* arm_AND X5 X5 (rvalue (word 9223372036854775807)) *) - 0xaa1403e4; (* arm_MOV X4 X20 *) - 0xa9000480; (* arm_STP X0 X1 X4 (Immediate_Offset (iword (&0))) *) - 0xa9011482; (* arm_STP X2 X5 X4 (Immediate_Offset (iword (&16))) *) - 0xa94a07e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&160))) *) - 0xa94b0fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&176))) *) - 0xaa010000; (* arm_ORR X0 X0 X1 *) - 0xaa030042; (* arm_ORR X2 X2 X3 *) - 0xaa020004; (* arm_ORR X4 X0 X2 *) - 0xeb1f009f; (* arm_CMP X4 XZR *) - 0xa95207e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&288))) *) - 0x9a9f1000; (* arm_CSEL X0 X0 XZR Condition_NE *) - 0x9a9f1021; (* arm_CSEL X1 X1 XZR Condition_NE *) - 0xa9530fe2; (* arm_LDP X2 X3 SP (Immediate_Offset (iword (&304))) *) - 0xa91207e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&288))) *) - 0x9a9f1042; (* arm_CSEL X2 X2 XZR Condition_NE *) - 0x9a9f1063; (* arm_CSEL X3 X3 XZR Condition_NE *) - 0xa9130fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&304))) *) - 0xa95213e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&288))) *) - 0xa94e1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&224))) *) - 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f0108; (* arm_ADC X8 X8 X15 *) - 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a100108; (* arm_ADC X8 X8 X16 *) - 0x9b067c89; (* arm_MUL X9 X4 X6 *) - 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab080129; (* arm_ADDS X9 X9 X8 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0900e8; (* arm_ADDS X8 X7 X9 *) - 0xba0a0129; (* arm_ADCS X9 X9 X10 *) - 0x9a1f014a; (* arm_ADC X10 X10 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0801e8; (* arm_ADCS X8 X15 X8 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba090069; (* arm_ADCS X9 X3 X9 *) - 0x9a10014a; (* arm_ADC X10 X10 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa94f1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&240))) *) - 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) - 0xd360fc60; (* arm_LSR X0 X3 32 *) - 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) - 0xd360fcb0; (* arm_LSR X16 X5 32 *) - 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) - 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) - 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) - 0xd360fdef; (* arm_LSR X15 X15 32 *) - 0x9a0f018c; (* arm_ADC X12 X12 X15 *) - 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) - 0xd360fe10; (* arm_LSR X16 X16 32 *) - 0x9a10018c; (* arm_ADC X12 X12 X16 *) - 0x9b067c8d; (* arm_MUL X13 X4 X6 *) - 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) - 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) - 0xda902210; (* arm_CINV X16 X16 Condition_CC *) - 0x9b037c8f; (* arm_MUL X15 X4 X3 *) - 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) - 0xab0d016c; (* arm_ADDS X12 X11 X13 *) - 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xba0d006d; (* arm_ADCS X13 X3 X13 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xa95313e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&304))) *) - 0xa95243ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&288))) *) - 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) - 0xfa100084; (* arm_SBCS X4 X4 X16 *) - 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) - 0xa94e03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&224))) *) - 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) - 0xfa060006; (* arm_SBCS X6 X0 X6 *) - 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) - 0xca100063; (* arm_EOR X3 X3 X16 *) - 0xeb100063; (* arm_SUBS X3 X3 X16 *) - 0xca100084; (* arm_EOR X4 X4 X16 *) - 0xda100084; (* arm_SBC X4 X4 X16 *) - 0xca0000a5; (* arm_EOR X5 X5 X0 *) - 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) - 0xca0000c6; (* arm_EOR X6 X6 X0 *) - 0xda0000c6; (* arm_SBC X6 X6 X0 *) - 0xca100010; (* arm_EOR X16 X0 X16 *) - 0xab09016b; (* arm_ADDS X11 X11 X9 *) - 0xba0a018c; (* arm_ADCS X12 X12 X10 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0x9b057c62; (* arm_MUL X2 X3 X5 *) - 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) - 0x9b067c8f; (* arm_MUL X15 X4 X6 *) - 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) - 0xeb030084; (* arm_SUBS X4 X4 X3 *) - 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) - 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) - 0xab0001ef; (* arm_ADDS X15 X15 X0 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) - 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) - 0xda892129; (* arm_CINV X9 X9 Condition_CC *) - 0x9b067c85; (* arm_MUL X5 X4 X6 *) - 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) - 0xab0f0040; (* arm_ADDS X0 X2 X15 *) - 0xba0101ef; (* arm_ADCS X15 X15 X1 *) - 0x9a1f0021; (* arm_ADC X1 X1 XZR *) - 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) - 0xca0900a5; (* arm_EOR X5 X5 X9 *) - 0xba0000a0; (* arm_ADCS X0 X5 X0 *) - 0xca0900c6; (* arm_EOR X6 X6 X9 *) - 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) - 0x9a090021; (* arm_ADC X1 X1 X9 *) - 0xab070169; (* arm_ADDS X9 X11 X7 *) - 0xba08018a; (* arm_ADCS X10 X12 X8 *) - 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) - 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) - 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) - 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) - 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) - 0xca100042; (* arm_EOR X2 X2 X16 *) - 0xba090049; (* arm_ADCS X9 X2 X9 *) - 0xca100000; (* arm_EOR X0 X0 X16 *) - 0xba0a000a; (* arm_ADCS X10 X0 X10 *) - 0xca1001ef; (* arm_EOR X15 X15 X16 *) - 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) - 0xca100021; (* arm_EOR X1 X1 X16 *) - 0xba0c002c; (* arm_ADCS X12 X1 X12 *) - 0xba1001ad; (* arm_ADCS X13 X13 X16 *) - 0x9a1001ce; (* arm_ADC X14 X14 X16 *) - 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) - 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) - 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) - 0xd360fce7; (* arm_LSR X7 X7 32 *) - 0xd360fd6b; (* arm_LSR X11 X11 32 *) - 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) - 0xaa0403e7; (* arm_MOV X7 X4 *) - 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) - 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) - 0xd360fd08; (* arm_LSR X8 X8 32 *) - 0xd360fd8c; (* arm_LSR X12 X12 32 *) - 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) - 0xaa0403e8; (* arm_MOV X8 X4 *) - 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) - 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) - 0xd360fd29; (* arm_LSR X9 X9 32 *) - 0xd360fdad; (* arm_LSR X13 X13 32 *) - 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) - 0xaa0403e9; (* arm_MOV X9 X4 *) - 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) - 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) - 0xd360fd4a; (* arm_LSR X10 X10 32 *) - 0xd360fdce; (* arm_LSR X14 X14 32 *) - 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) - 0xaa0403ea; (* arm_MOV X10 X4 *) - 0xd35ffdc0; (* arm_LSR X0 X14 31 *) - 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) - 0x9ba014a5; (* arm_UMADDL X5 W5 W0 X5 *) - 0x8b0500e7; (* arm_ADD X7 X7 X5 *) - 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) - 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) - 0xba030108; (* arm_ADCS X8 X8 X3 *) - 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) - 0xba030129; (* arm_ADCS X9 X9 X3 *) - 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) - 0xd3410005; (* arm_LSL X5 X0 63 *) - 0xca05014a; (* arm_EOR X10 X10 X5 *) - 0x9a03014a; (* arm_ADC X10 X10 X3 *) - 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) - 0xf241015f; (* arm_TST X10 (rvalue (word 9223372036854775808)) *) - 0x9a9f5063; (* arm_CSEL X3 X3 XZR Condition_PL *) - 0xeb0300e7; (* arm_SUBS X7 X7 X3 *) - 0xfa1f0108; (* arm_SBCS X8 X8 XZR *) - 0xfa1f0129; (* arm_SBCS X9 X9 XZR *) - 0xda1f014a; (* arm_SBC X10 X10 XZR *) - 0x9240f94a; (* arm_AND X10 X10 (rvalue (word 9223372036854775807)) *) - 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) - 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) - 0xa94a2fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&160))) *) - 0x390002ea; (* arm_STRB W10 X23 (Immediate_Offset (word 0)) *) - 0xd348fd4a; (* arm_LSR X10 X10 8 *) - 0x390006ea; (* arm_STRB W10 X23 (Immediate_Offset (word 1)) *) - 0xd348fd4a; (* arm_LSR X10 X10 8 *) - 0x39000aea; (* arm_STRB W10 X23 (Immediate_Offset (word 2)) *) - 0xd348fd4a; (* arm_LSR X10 X10 8 *) - 0x39000eea; (* arm_STRB W10 X23 (Immediate_Offset (word 3)) *) - 0xd348fd4a; (* arm_LSR X10 X10 8 *) - 0x390012ea; (* arm_STRB W10 X23 (Immediate_Offset (word 4)) *) - 0xd348fd4a; (* arm_LSR X10 X10 8 *) - 0x390016ea; (* arm_STRB W10 X23 (Immediate_Offset (word 5)) *) - 0xd348fd4a; (* arm_LSR X10 X10 8 *) - 0x39001aea; (* arm_STRB W10 X23 (Immediate_Offset (word 6)) *) - 0xd348fd4a; (* arm_LSR X10 X10 8 *) - 0x39001eea; (* arm_STRB W10 X23 (Immediate_Offset (word 7)) *) - 0x390022eb; (* arm_STRB W11 X23 (Immediate_Offset (word 8)) *) - 0xd348fd6b; (* arm_LSR X11 X11 8 *) - 0x390026eb; (* arm_STRB W11 X23 (Immediate_Offset (word 9)) *) - 0xd348fd6b; (* arm_LSR X11 X11 8 *) - 0x39002aeb; (* arm_STRB W11 X23 (Immediate_Offset (word 10)) *) - 0xd348fd6b; (* arm_LSR X11 X11 8 *) - 0x39002eeb; (* arm_STRB W11 X23 (Immediate_Offset (word 11)) *) - 0xd348fd6b; (* arm_LSR X11 X11 8 *) - 0x390032eb; (* arm_STRB W11 X23 (Immediate_Offset (word 12)) *) - 0xd348fd6b; (* arm_LSR X11 X11 8 *) - 0x390036eb; (* arm_STRB W11 X23 (Immediate_Offset (word 13)) *) - 0xd348fd6b; (* arm_LSR X11 X11 8 *) - 0x39003aeb; (* arm_STRB W11 X23 (Immediate_Offset (word 14)) *) - 0xd348fd6b; (* arm_LSR X11 X11 8 *) - 0x39003eeb; (* arm_STRB W11 X23 (Immediate_Offset (word 15)) *) - 0xa94b37ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&176))) *) - 0x390042ec; (* arm_STRB W12 X23 (Immediate_Offset (word 16)) *) - 0xd348fd8c; (* arm_LSR X12 X12 8 *) - 0x390046ec; (* arm_STRB W12 X23 (Immediate_Offset (word 17)) *) - 0xd348fd8c; (* arm_LSR X12 X12 8 *) - 0x39004aec; (* arm_STRB W12 X23 (Immediate_Offset (word 18)) *) - 0xd348fd8c; (* arm_LSR X12 X12 8 *) - 0x39004eec; (* arm_STRB W12 X23 (Immediate_Offset (word 19)) *) - 0xd348fd8c; (* arm_LSR X12 X12 8 *) - 0x390052ec; (* arm_STRB W12 X23 (Immediate_Offset (word 20)) *) - 0xd348fd8c; (* arm_LSR X12 X12 8 *) - 0x390056ec; (* arm_STRB W12 X23 (Immediate_Offset (word 21)) *) - 0xd348fd8c; (* arm_LSR X12 X12 8 *) - 0x39005aec; (* arm_STRB W12 X23 (Immediate_Offset (word 22)) *) - 0xd348fd8c; (* arm_LSR X12 X12 8 *) - 0x39005eec; (* arm_STRB W12 X23 (Immediate_Offset (word 23)) *) - 0x390062ed; (* arm_STRB W13 X23 (Immediate_Offset (word 24)) *) - 0xd348fdad; (* arm_LSR X13 X13 8 *) - 0x390066ed; (* arm_STRB W13 X23 (Immediate_Offset (word 25)) *) - 0xd348fdad; (* arm_LSR X13 X13 8 *) - 0x39006aed; (* arm_STRB W13 X23 (Immediate_Offset (word 26)) *) - 0xd348fdad; (* arm_LSR X13 X13 8 *) - 0x39006eed; (* arm_STRB W13 X23 (Immediate_Offset (word 27)) *) - 0xd348fdad; (* arm_LSR X13 X13 8 *) - 0x390072ed; (* arm_STRB W13 X23 (Immediate_Offset (word 28)) *) - 0xd348fdad; (* arm_LSR X13 X13 8 *) - 0x390076ed; (* arm_STRB W13 X23 (Immediate_Offset (word 29)) *) - 0xd348fdad; (* arm_LSR X13 X13 8 *) - 0x39007aed; (* arm_STRB W13 X23 (Immediate_Offset (word 30)) *) - 0xd348fdad; (* arm_LSR X13 X13 8 *) - 0x39007eed; (* arm_STRB W13 X23 (Immediate_Offset (word 31)) *) - 0x910503ff; (* arm_ADD SP SP (rvalue (word 320)) *) - 0xa8c163f7; (* arm_LDP X23 X24 SP (Postimmediate_Offset (iword (&16))) *) - 0xa8c15bf5; (* arm_LDP X21 X22 SP (Postimmediate_Offset (iword (&16))) *) - 0xa8c153f3; (* arm_LDP X19 X20 SP (Postimmediate_Offset (iword (&16))) *) - 0xd65f03c0 (* arm_RET X30 *) -];; - -let CURVE25519_X25519_BYTE_EXEC = ARM_MK_EXEC_RULE curve25519_x25519_byte_mc;; - -(* ------------------------------------------------------------------------- *) -(* Abbreviations used to state the specification. *) -(* ------------------------------------------------------------------------- *) - -let p_25519 = define `p_25519 = 57896044618658097711785492504343953926634992332820282019728792003956564819949`;; - -let curve25519x = define - `curve25519x (f:A ring) = (f,ring_of_num f A_25519,ring_of_num f 1)`;; - -let curve25519x_halfcanonically_represents = new_definition - `curve25519x_halfcanonically_represents (f:A ring) P (X,Z) <=> - X < 2 * p_25519 /\ Z < 2 * p_25519 /\ - montgomery_xz f P (ring_of_num f X,ring_of_num f Z)`;; - -(* ------------------------------------------------------------------------- *) -(* Common lemmas and tactics for the component proofs. *) -(* ------------------------------------------------------------------------- *) - -let lemma0 = prove - (`!x0 x1:int64. - &(val(if val x0 <= val x1 then word_sub x1 x0 - else word_neg(word_sub x1 x0))):real = abs(&(val x1) - &(val x0))`, - REPEAT GEN_TAC THEN REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[WORD_NEG_SUB; REAL_ARITH - `abs(x - y):real = if y <= x then x - y else y - x`] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - RULE_ASSUM_TAC(REWRITE_RULE[REAL_OF_NUM_CLAUSES; NOT_LE]) THEN - ASM_SIMP_TAC[VAL_WORD_SUB_CASES; LT_IMP_LE; REAL_OF_NUM_SUB]);; - -let lemma1 = prove - (`!(x0:num) x1 (y0:num) y1. - (if y0 <= y1 - then if x1 <= x0 then word 0 else word 18446744073709551615 - else word_not - (if x1 <= x0 then word 0 else word 18446744073709551615)):int64 = - word_neg(word(bitval(y0 <= y1 <=> x0 < x1)))`, - REPEAT GEN_TAC THEN REWRITE_TAC[GSYM NOT_LE] THEN - REPEAT(COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES]) THEN - CONV_TAC WORD_REDUCE_CONV);; - -let lemma2 = prove - (`!p x0 x1 y0 y1:real. - (x0 + p * x1) * (y0 + p * y1) = - x0 * y0 + p pow 2 * x1 * y1 + - p * (x0 * y0 + x1 * y1 + - --(&1) pow bitval(y1 <= y0 <=> x1 < x0) * - abs(x1 - x0) * abs(y0 - y1))`, - REPEAT GEN_TAC THEN - MAP_EVERY ASM_CASES_TAC [`y1:real <= y0`; `x1:real < x0`] THEN - ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN ASM_REAL_ARITH_TAC);; - -let VAL_WORD_MADDL_0 = prove - (`!x y. val(word(0 + val(x:int32) * val(y:int32)):int64) = val x * val y`, - REPEAT GEN_TAC THEN REWRITE_TAC[ADD_CLAUSES; VAL_WORD_EQ_EQ] THEN - REWRITE_TAC[DIMINDEX_64; ARITH_RULE `2 EXP 64 = 2 EXP 32 * 2 EXP 32`] THEN - MATCH_MP_TAC LT_MULT2 THEN REWRITE_TAC[GSYM DIMINDEX_32; VAL_BOUND]);; - -let DIVMOD_32_32 = prove - (`!n. (2 EXP 32 * n) MOD 2 EXP 64 = 2 EXP 32 * n MOD 2 EXP 32`, - REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - -let DIVMOD_33_31 = prove - (`!n. (2 EXP 33 * n) MOD 2 EXP 64 = 2 EXP 33 * n MOD 2 EXP 31`, - REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - -let DIVMOD_63_64 = prove - (`!n. (2 EXP 63 * n) MOD 2 EXP 64 = 2 EXP 63 * n MOD 2`, - REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - -let VAL_WORD_SPLIT32 = prove - (`!x. 2 EXP 32 * val(word_zx(word_ushr x 32):int32) + val(word_zx x:int32) = - val(x:int64)`, - REWRITE_TAC[VAL_WORD_USHR; VAL_WORD_ZX_GEN; DIMINDEX_32] THEN - GEN_TAC THEN REWRITE_TAC[GSYM MOD_MULT_MOD; GSYM EXP_ADD] THEN - CONV_TAC(ONCE_DEPTH_CONV NUM_ADD_CONV) THEN - MATCH_MP_TAC MOD_LT THEN REWRITE_TAC[VAL_BOUND_64]);; - -let p25519redlemma32 = prove - (`!h l. h < 2 EXP 256 /\ l < 2 EXP 256 - ==> let q = (38 * h DIV 2 EXP 224 + l DIV 2 EXP 224) DIV 2 EXP 31 in - q <= 77 /\ - q < 2 EXP 64 /\ - (q + 1) * p_25519 <= (38 * h + l) + p_25519 /\ - 38 * h + l < (q + 1) * p_25519 + p_25519`, - CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN - REWRITE_TAC[p_25519] THEN ARITH_TAC);; - -let endp25519redlemma = prove - (`(&z == &2 pow 255 + x) (mod (&2 pow 256)) /\ - --(&p_25519) <= x /\ x < &p_25519 /\ z < 2 EXP 256 - ==> x rem &p_25519 = - if z < 2 EXP 255 then &z - &19 else &z - &2 pow 255`, - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN REPEAT STRIP_TAC THEN - SUBGOAL_THEN `&z:int < &2 pow 255 <=> x:int < &0` SUBST1_TAC THENL - [ALL_TAC; - COND_CASES_TAC THEN MATCH_MP_TAC INT_REM_UNIQ THENL - [EXISTS_TAC `--(&1):int`; EXISTS_TAC `&0:int`]] THEN - FIRST_X_ASSUM(MP_TAC o MATCH_MP - (REWRITE_RULE[IMP_CONJ_ALT] INT_CONG_IMP_EQ)) THEN - REWRITE_TAC[p_25519] THEN - RULE_ASSUM_TAC(REWRITE_RULE[p_25519]) THEN ASM_INT_ARITH_TAC);; - -let KARATSUBA12_TAC = - REWRITE_TAC[REAL_MUL_RZERO; REAL_ADD_RID] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN - ASM_REWRITE_TAC[INTEGER_CLOSED] THEN - REPLICATE_TAC 2 (CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC]) THEN - REWRITE_TAC[lemma2; REAL_OF_NUM_LE; REAL_OF_NUM_LT] THEN - ACCUMULATOR_POP_ASSUM_LIST(fun thl -> - MP_TAC(end_itlist CONJ(rev thl)) THEN - REWRITE_TAC[WORD_XOR_MASK] THEN - REWRITE_TAC[REAL_OF_NUM_LT; REAL_OF_NUM_LE; GSYM NOT_LE] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - REWRITE_TAC[REAL_VAL_WORD_NOT; DIMINDEX_64] THEN - DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN - CONV_TAC(RAND_CONV REAL_POLY_CONV) THEN - REWRITE_TAC(filter(is_ratconst o rand o concl) (DECARRY_RULE thl)) THEN - REAL_INTEGER_TAC);; - -let p25519weakredlemma = prove - (`!n. n <= 2 EXP 62 * 2 EXP 256 - ==> let q = n DIV 2 EXP 255 in - q < 2 EXP 64 /\ - q * p_25519 <= n /\ - n < q * p_25519 + 2 * p_25519`, - CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN REWRITE_TAC[p_25519] THEN ARITH_TAC);; - -let lvs = - ["resx",[`X23`;`0`]; - "x",[`SP`;`32`]; - "zm",[`SP`;`64`]; - "sm",[`SP`;`64`]; - "dpro",[`SP`;`64`]; - "sn",[`SP`;`96`]; - "dm",[`SP`;`128`]; - "zn",[`SP`;`160`]; - "dn",[`SP`;`160`]; - "e",[`SP`;`160`]; - "dmsn",[`SP`;`192`]; - "p",[`SP`;`192`]; - "xm",[`SP`;`224`]; - "dnsm",[`SP`;`224`]; - "spro",[`SP`;`224`]; - "d",[`SP`;`256`]; - "xn",[`SP`;`288`]; - "s",[`SP`;`288`]];; - -(* ------------------------------------------------------------------------- *) -(* Instances of mul_p25519. *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_MUL_P25519_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_byte_mc 180 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x59e4) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s = - (m * n) MOD p_25519) - (MAYCHANGE [PC; X0; X1; X2; X3; X4; X5; X6; X7; X8; X9; X10; X11; X12; - X13; X14; X15; X16] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "y_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "x_" o lhand o concl) THEN - - (*** Retrofitted insertion for the 32-bit fiddling (1 of 2) ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC [9;11;12;14] (1--14) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; VAL_WORD_USHR; VAL_WORD_SHL; - DIVMOD_32_32; DIMINDEX_64]) THEN - SUBGOAL_THEN - `&2 pow 64 * &(val(sum_s14:int64)) + &(val(sum_s12:int64)):real = - &(val(x_0:int64)) * &(val(y_0:int64))` - MP_TAC THENL - [MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`128`; `&0:real`] THEN - REPLICATE_TAC 2 (CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC]) THEN - REWRITE_TAC[INTEGER_CLOSED] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`x_0:int64`; `y_0:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN DISCH_TAC THEN - POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - SPEC_TAC(`sum_s12:int64`,`mullo_s3:int64`) THEN - SPEC_TAC(`sum_s14:int64`,`mulhi_s3:int64`) THEN - SPEC_TAC(`s14:armstate`,`s4:armstate`) THEN REPEAT STRIP_TAC] THEN - - (*** First nested block multiplying the lower halves ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [5;10;11;15;17;18;19;22;24;25] (5--25) THEN - RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN - - MAP_EVERY ABBREV_TAC - [`q0 = bignum_of_wordlist[mullo_s3;sum_s22]`; - `q1 = bignum_of_wordlist[sum_s24;sum_s25]`] THEN - SUBGOAL_THEN - `2 EXP 128 * q1 + q0 = - bignum_of_wordlist [x_0;x_1] * bignum_of_wordlist[y_0;y_1]` - ASSUME_TAC THENL - [MAP_EVERY EXPAND_TAC ["q0"; "q1"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - KARATSUBA12_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN - DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN - - (*** Retrofitted insertion for the 32-bit fiddling (2 of 2) ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC [34;36;37;39] (26--39) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; VAL_WORD_USHR; VAL_WORD_SHL; - DIVMOD_32_32; DIMINDEX_64]) THEN - SUBGOAL_THEN - `&2 pow 64 * &(val(sum_s39:int64)) + &(val(sum_s37:int64)):real = - &(val(x_2:int64)) * &(val(y_2:int64))` - MP_TAC THENL - [MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`128`; `&0:real`] THEN - REPLICATE_TAC 2 (CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC]) THEN - REWRITE_TAC[INTEGER_CLOSED] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`x_2:int64`; `y_2:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN DISCH_TAC THEN - POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - SPEC_TAC(`sum_s37:int64`,`mullo_s28:int64`) THEN - SPEC_TAC(`sum_s39:int64`,`mulhi_s28:int64`) THEN - SPEC_TAC(`s39:armstate`,`s29:armstate`) THEN REPEAT STRIP_TAC] THEN - - (*** Second nested block multiplying the upper halves ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [30;35;36;40;42;43;44;47;49;50] (30--50) THEN - RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN - - ABBREV_TAC - `q23 = bignum_of_wordlist[mullo_s28;sum_s47; sum_s49;sum_s50]` THEN - SUBGOAL_THEN - `q23 = bignum_of_wordlist [x_2;x_3] * bignum_of_wordlist[y_2;y_3]` - ASSUME_TAC THENL - [EXPAND_TAC "q23" THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - KARATSUBA12_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN - DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN - - (*** The sign-magnitude difference computation ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [53;54; 57;58; 61;63; 65;67] (51--68) THEN - RULE_ASSUM_TAC(REWRITE_RULE[WORD_UNMASK_64]) THEN - - MAP_EVERY ABBREV_TAC - [`sgn <=> ~(carry_s58 <=> carry_s54)`; - `xd = bignum_of_wordlist[sum_s61;sum_s63]`; - `yd = bignum_of_wordlist[sum_s65;sum_s67]`] THEN - SUBGOAL_THEN - `(&(bignum_of_wordlist[x_2;x_3]) - - &(bignum_of_wordlist[x_0;x_1])) * - (&(bignum_of_wordlist[y_0;y_1]) - - &(bignum_of_wordlist[y_2;y_3])):real = - --(&1) pow bitval sgn * &xd * &yd` - ASSUME_TAC THENL - [TRANS_TAC EQ_TRANS - `(--(&1) pow bitval carry_s54 * &xd) * - (--(&1) pow bitval carry_s58 * &yd):real` THEN - CONJ_TAC THENL - [ALL_TAC; - EXPAND_TAC "sgn" THEN REWRITE_TAC[BITVAL_NOT; BITVAL_IFF] THEN - POP_ASSUM_LIST(K ALL_TAC) THEN REWRITE_TAC[bitval] THEN - REPEAT(COND_CASES_TAC THEN ASM_REWRITE_TAC[]) THEN - CONV_TAC NUM_REDUCE_CONV THEN REAL_ARITH_TAC] THEN - SUBGOAL_THEN - `(carry_s54 <=> - bignum_of_wordlist[x_2;x_3] < bignum_of_wordlist[x_0;x_1]) /\ - (carry_s58 <=> - bignum_of_wordlist[y_0;y_1] < bignum_of_wordlist[y_2;y_3])` - (CONJUNCTS_THEN SUBST_ALL_TAC) - THENL - [CONJ_TAC THEN MATCH_MP_TAC FLAG_FROM_CARRY_LT THEN EXISTS_TAC `128` THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - REWRITE_TAC[REAL_BITVAL_NOT; REAL_VAL_WORD_MASK; DIMINDEX_64] THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN BOUNDER_TAC[]; - ALL_TAC] THEN - BINOP_TAC THEN REWRITE_TAC[bitval] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[real_pow; REAL_MUL_LID] THEN - REWRITE_TAC[REAL_ARITH `x - y:real = --(&1) pow 1 * z <=> y - x = z`] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`128`; `&0:real`] THEN - (CONJ_TAC THENL - [MATCH_MP_TAC(REAL_ARITH - `y:real <= x /\ (&0 <= x /\ x < e) /\ (&0 <= y /\ y < e) - ==> &0 <= x - y /\ x - y < e`) THEN - ASM_SIMP_TAC[REAL_OF_NUM_CLAUSES; LT_IMP_LE; - ARITH_RULE `~(a:num < b) ==> b <= a`] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - CONJ_TAC THEN BOUNDER_TAC[]; - ALL_TAC] THEN - MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; REWRITE_TAC[INTEGER_CLOSED]]) THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - ASM_REWRITE_TAC[WORD_XOR_MASK] THEN - REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN - DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** Clean up the overall sign ***) + 0x9a9f30e6; (* arm_CSEL X6 X7 XZR Condition_CC *) + 0xeb060042; (* arm_SUBS X2 X2 X6 *) + 0xfa1f0063; (* arm_SBCS X3 X3 XZR *) + 0xfa1f0084; (* arm_SBCS X4 X4 XZR *) + 0xda1f00a5; (* arm_SBC X5 X5 XZR *) + 0x9240f8a5; (* arm_AND X5 X5 (rvalue (word 9223372036854775807)) *) + 0xa9020fe2; (* arm_STP X2 X3 SP (Immediate_Offset (iword (&32))) *) + 0xa90317e4; (* arm_STP X4 X5 SP (Immediate_Offset (iword (&48))) *) + 0xa9047fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&64))) *) + 0xa9057fff; (* arm_STP XZR XZR SP (Immediate_Offset (iword (&80))) *) + 0xd284132a; (* arm_MOV X10 (rvalue (word 8345)) *) + 0xf2aea04a; (* arm_MOVK X10 (word 29954) 16 *) + 0xf2d3c46a; (* arm_MOVK X10 (word 40483) 32 *) + 0xf2f41f2a; (* arm_MOVK X10 (word 41209) 48 *) + 0xd284b2ab; (* arm_MOV X11 (rvalue (word 9621)) *) + 0xf2a3a26b; (* arm_MOVK X11 (word 7443) 16 *) + 0xf2d1e7eb; (* arm_MOVK X11 (word 36671) 32 *) + 0xf2f518cb; (* arm_MOVK X11 (word 43206) 48 *) + 0xd28a484c; (* arm_MOV X12 (rvalue (word 21058)) *) + 0xf2a0b58c; (* arm_MOVK X12 (word 1452) 16 *) + 0xf2d1270c; (* arm_MOVK X12 (word 35128) 32 *) + 0xf2ed8d8c; (* arm_MOVK X12 (word 27756) 48 *) + 0xd280c2ad; (* arm_MOV X13 (rvalue (word 1557)) *) + 0xf2a82eed; (* arm_MOVK X13 (word 16759) 16 *) + 0xf2c1164d; (* arm_MOVK X13 (word 2226) 32 *) + 0xf2e4ecad; (* arm_MOVK X13 (word 10085) 48 *) + 0xa9062fea; (* arm_STP X10 X11 SP (Immediate_Offset (iword (&96))) *) + 0xa90737ec; (* arm_STP X12 X13 SP (Immediate_Offset (iword (&112))) *) + 0xd2800155; (* arm_MOV X21 (rvalue (word 10)) *) + 0xd2800036; (* arm_MOV X22 (rvalue (word 1)) *) + 0x1400010b; (* arm_B (word 1068) *) + 0xeb1f015f; (* arm_CMP X10 XZR *) + 0xda9f53ee; (* arm_CSETM X14 Condition_MI *) + 0xda8a554a; (* arm_CNEG X10 X10 Condition_MI *) + 0xeb1f017f; (* arm_CMP X11 XZR *) + 0xda9f53ef; (* arm_CSETM X15 Condition_MI *) + 0xda8b556b; (* arm_CNEG X11 X11 Condition_MI *) + 0xeb1f019f; (* arm_CMP X12 XZR *) + 0xda9f53f0; (* arm_CSETM X16 Condition_MI *) + 0xda8c558c; (* arm_CNEG X12 X12 Condition_MI *) + 0xeb1f01bf; (* arm_CMP X13 XZR *) + 0xda9f53f1; (* arm_CSETM X17 Condition_MI *) + 0xda8d55ad; (* arm_CNEG X13 X13 Condition_MI *) + 0x8a0e0140; (* arm_AND X0 X10 X14 *) + 0x8a0f0161; (* arm_AND X1 X11 X15 *) + 0x8b010009; (* arm_ADD X9 X0 X1 *) + 0x8a100180; (* arm_AND X0 X12 X16 *) + 0x8a1101a1; (* arm_AND X1 X13 X17 *) + 0x8b010013; (* arm_ADD X19 X0 X1 *) + 0xf94003e7; (* arm_LDR X7 SP (Immediate_Offset (word 0)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000124; (* arm_ADDS X4 X9 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xf94013e8; (* arm_LDR X8 SP (Immediate_Offset (word 32)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000265; (* arm_ADDS X5 X19 X0 *) + 0x9a0103e3; (* arm_ADC X3 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf94007e7; (* arm_LDR X7 SP (Immediate_Offset (word 8)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0103e6; (* arm_ADC X6 XZR X1 *) + 0xf94017e8; (* arm_LDR X8 SP (Immediate_Offset (word 40)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100c6; (* arm_ADC X6 X6 X1 *) + 0x93c4ec44; (* arm_EXTR X4 X2 X4 59 *) + 0xf90003e4; (* arm_STR X4 SP (Immediate_Offset (word 0)) *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000063; (* arm_ADDS X3 X3 X0 *) + 0x9a0103e4; (* arm_ADC X4 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000063; (* arm_ADDS X3 X3 X0 *) + 0x9a010084; (* arm_ADC X4 X4 X1 *) + 0x93c5ec65; (* arm_EXTR X5 X3 X5 59 *) + 0xf90013e5; (* arm_STR X5 SP (Immediate_Offset (word 32)) *) + 0xf9400be7; (* arm_LDR X7 SP (Immediate_Offset (word 16)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0x9a0103e5; (* arm_ADC X5 XZR X1 *) + 0xf9401be8; (* arm_LDR X8 SP (Immediate_Offset (word 48)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0x93c2ecc2; (* arm_EXTR X2 X6 X2 59 *) + 0xf90007e2; (* arm_STR X2 SP (Immediate_Offset (word 8)) *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0x93c3ec83; (* arm_EXTR X3 X4 X3 59 *) + 0xf90017e3; (* arm_STR X3 SP (Immediate_Offset (word 40)) *) + 0xf9400fe7; (* arm_LDR X7 SP (Immediate_Offset (word 24)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x937ffc23; (* arm_ASR X3 X1 63 *) + 0x8a0a0063; (* arm_AND X3 X3 X10 *) + 0xcb0303e3; (* arm_NEG X3 X3 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf9401fe8; (* arm_LDR X8 SP (Immediate_Offset (word 56)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x937ffc20; (* arm_ASR X0 X1 63 *) + 0x8a0b0000; (* arm_AND X0 X0 X11 *) + 0xcb000063; (* arm_SUB X3 X3 X0 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0x93c6eca6; (* arm_EXTR X6 X5 X6 59 *) + 0xf9000be6; (* arm_STR X6 SP (Immediate_Offset (word 16)) *) + 0x93c5ec65; (* arm_EXTR X5 X3 X5 59 *) + 0xf9000fe5; (* arm_STR X5 SP (Immediate_Offset (word 24)) *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x937ffc25; (* arm_ASR X5 X1 63 *) + 0x8a0c00a5; (* arm_AND X5 X5 X12 *) + 0xcb0503e5; (* arm_NEG X5 X5 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x937ffc20; (* arm_ASR X0 X1 63 *) + 0x8a0d0000; (* arm_AND X0 X0 X13 *) + 0xcb0000a5; (* arm_SUB X5 X5 X0 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0x93c4ec44; (* arm_EXTR X4 X2 X4 59 *) + 0xf9001be4; (* arm_STR X4 SP (Immediate_Offset (word 48)) *) + 0x93c2eca2; (* arm_EXTR X2 X5 X2 59 *) + 0xf9001fe2; (* arm_STR X2 SP (Immediate_Offset (word 56)) *) + 0xf94023e7; (* arm_LDR X7 SP (Immediate_Offset (word 64)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000124; (* arm_ADDS X4 X9 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xf94033e8; (* arm_LDR X8 SP (Immediate_Offset (word 96)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0xf90023e4; (* arm_STR X4 SP (Immediate_Offset (word 64)) *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000265; (* arm_ADDS X5 X19 X0 *) + 0x9a0103e3; (* arm_ADC X3 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0xf90033e5; (* arm_STR X5 SP (Immediate_Offset (word 96)) *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf94027e7; (* arm_LDR X7 SP (Immediate_Offset (word 72)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0103e6; (* arm_ADC X6 XZR X1 *) + 0xf94037e8; (* arm_LDR X8 SP (Immediate_Offset (word 104)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0xf90027e2; (* arm_STR X2 SP (Immediate_Offset (word 72)) *) + 0x9a0100c6; (* arm_ADC X6 X6 X1 *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000063; (* arm_ADDS X3 X3 X0 *) + 0x9a0103e4; (* arm_ADC X4 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000063; (* arm_ADDS X3 X3 X0 *) + 0xf90037e3; (* arm_STR X3 SP (Immediate_Offset (word 104)) *) + 0x9a010084; (* arm_ADC X4 X4 X1 *) + 0xf9402be7; (* arm_LDR X7 SP (Immediate_Offset (word 80)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0x9a0103e5; (* arm_ADC X5 XZR X1 *) + 0xf9403be8; (* arm_LDR X8 SP (Immediate_Offset (word 112)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0xf9002be6; (* arm_STR X6 SP (Immediate_Offset (word 80)) *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0xf9003be4; (* arm_STR X4 SP (Immediate_Offset (word 112)) *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0xf9402fe7; (* arm_LDR X7 SP (Immediate_Offset (word 88)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x8a0a01c3; (* arm_AND X3 X14 X10 *) + 0xcb0303e3; (* arm_NEG X3 X3 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf9403fe8; (* arm_LDR X8 SP (Immediate_Offset (word 120)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x8a0b01e0; (* arm_AND X0 X15 X11 *) + 0xcb000063; (* arm_SUB X3 X3 X0 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0x93c5fc66; (* arm_EXTR X6 X3 X5 63 *) + 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) + 0x8b83fcc6; (* arm_ADD X6 X6 (Shiftedreg X3 ASR 63) *) + 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) + 0x9b037cc4; (* arm_MUL X4 X6 X3 *) + 0x8b06fca5; (* arm_ADD X5 X5 (Shiftedreg X6 LSL 63) *) + 0x9b437cc3; (* arm_SMULH X3 X6 X3 *) + 0xf9402be6; (* arm_LDR X6 SP (Immediate_Offset (word 80)) *) + 0xab040000; (* arm_ADDS X0 X0 X4 *) + 0xba030021; (* arm_ADCS X1 X1 X3 *) + 0x937ffc63; (* arm_ASR X3 X3 63 *) + 0xba0300c6; (* arm_ADCS X6 X6 X3 *) + 0x9a0300a5; (* arm_ADC X5 X5 X3 *) + 0xa90407e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&64))) *) + 0xa90517e6; (* arm_STP X6 X5 SP (Immediate_Offset (iword (&80))) *) + 0xca1000e1; (* arm_EOR X1 X7 X16 *) + 0x8a0c0205; (* arm_AND X5 X16 X12 *) + 0xcb0503e5; (* arm_NEG X5 X5 *) + 0x9b0c7c20; (* arm_MUL X0 X1 X12 *) + 0x9bcc7c21; (* arm_UMULH X1 X1 X12 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0xca110101; (* arm_EOR X1 X8 X17 *) + 0x8a0d0220; (* arm_AND X0 X17 X13 *) + 0xcb0000a5; (* arm_SUB X5 X5 X0 *) + 0x9b0d7c20; (* arm_MUL X0 X1 X13 *) + 0x9bcd7c21; (* arm_UMULH X1 X1 X13 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0x93c2fca6; (* arm_EXTR X6 X5 X2 63 *) + 0xa94607e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&96))) *) + 0x8b85fcc6; (* arm_ADD X6 X6 (Shiftedreg X5 ASR 63) *) + 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) + 0x9b057cc4; (* arm_MUL X4 X6 X5 *) + 0x8b06fc42; (* arm_ADD X2 X2 (Shiftedreg X6 LSL 63) *) + 0x9b457cc5; (* arm_SMULH X5 X6 X5 *) + 0xf9403be3; (* arm_LDR X3 SP (Immediate_Offset (word 112)) *) + 0xab040000; (* arm_ADDS X0 X0 X4 *) + 0xba050021; (* arm_ADCS X1 X1 X5 *) + 0x937ffca5; (* arm_ASR X5 X5 63 *) + 0xba050063; (* arm_ADCS X3 X3 X5 *) + 0x9a050042; (* arm_ADC X2 X2 X5 *) + 0xa90607e0; (* arm_STP X0 X1 SP (Immediate_Offset (iword (&96))) *) + 0xa9070be3; (* arm_STP X3 X2 SP (Immediate_Offset (iword (&112))) *) + 0xaa1603e1; (* arm_MOV X1 X22 *) + 0xf94003e2; (* arm_LDR X2 SP (Immediate_Offset (word 0)) *) + 0xf94013e3; (* arm_LDR X3 SP (Immediate_Offset (word 32)) *) + 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) + 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) + 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) + 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) + 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x91440088; (* arm_ADD X8 X4 (rvalue (word 1048576)) *) + 0x9355a508; (* arm_SBFM X8 X8 21 41 *) + 0xd2a0020b; (* arm_MOVZ X11 (word 16) 16 *) + 0x8b0b556b; (* arm_ADD X11 X11 (Shiftedreg X11 LSL 21) *) + 0x8b0b0089; (* arm_ADD X9 X4 X11 *) + 0x936afd29; (* arm_ASR X9 X9 42 *) + 0x914400aa; (* arm_ADD X10 X5 (rvalue (word 1048576)) *) + 0x9355a54a; (* arm_SBFM X10 X10 21 41 *) + 0x8b0b00ab; (* arm_ADD X11 X5 X11 *) + 0x936afd6b; (* arm_ASR X11 X11 42 *) + 0x9b027d06; (* arm_MUL X6 X8 X2 *) + 0x9b037d27; (* arm_MUL X7 X9 X3 *) + 0x9b027d42; (* arm_MUL X2 X10 X2 *) + 0x9b037d63; (* arm_MUL X3 X11 X3 *) + 0x8b0700c4; (* arm_ADD X4 X6 X7 *) + 0x8b030045; (* arm_ADD X5 X2 X3 *) + 0x9354fc82; (* arm_ASR X2 X4 20 *) + 0x9354fca3; (* arm_ASR X3 X5 20 *) + 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) + 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) + 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) + 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) + 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9144008c; (* arm_ADD X12 X4 (rvalue (word 1048576)) *) + 0x9355a58c; (* arm_SBFM X12 X12 21 41 *) + 0xd2a0020f; (* arm_MOVZ X15 (word 16) 16 *) + 0x8b0f55ef; (* arm_ADD X15 X15 (Shiftedreg X15 LSL 21) *) + 0x8b0f008d; (* arm_ADD X13 X4 X15 *) + 0x936afdad; (* arm_ASR X13 X13 42 *) + 0x914400ae; (* arm_ADD X14 X5 (rvalue (word 1048576)) *) + 0x9355a5ce; (* arm_SBFM X14 X14 21 41 *) + 0x8b0f00af; (* arm_ADD X15 X5 X15 *) + 0x936afdef; (* arm_ASR X15 X15 42 *) + 0x9b027d86; (* arm_MUL X6 X12 X2 *) + 0x9b037da7; (* arm_MUL X7 X13 X3 *) + 0x9b027dc2; (* arm_MUL X2 X14 X2 *) + 0x9b037de3; (* arm_MUL X3 X15 X3 *) + 0x8b0700c4; (* arm_ADD X4 X6 X7 *) + 0x8b030045; (* arm_ADD X5 X2 X3 *) + 0x9354fc82; (* arm_ASR X2 X4 20 *) + 0x9354fca3; (* arm_ASR X3 X5 20 *) + 0x92404c44; (* arm_AND X4 X2 (rvalue (word 1048575)) *) + 0xb2575884; (* arm_ORR X4 X4 (rvalue (word 18446741874686296064)) *) + 0x92404c65; (* arm_AND X5 X3 (rvalue (word 1048575)) *) + 0xb24204a5; (* arm_ORR X5 X5 (rvalue (word 13835058055282163712)) *) + 0xf24000bf; (* arm_TST X5 (rvalue (word 1)) *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9b087d82; (* arm_MUL X2 X12 X8 *) + 0x9b097d83; (* arm_MUL X3 X12 X9 *) + 0x9b087dc6; (* arm_MUL X6 X14 X8 *) + 0x9b097dc7; (* arm_MUL X7 X14 X9 *) + 0x9b0a09a8; (* arm_MADD X8 X13 X10 X2 *) + 0x9b0b0da9; (* arm_MADD X9 X13 X11 X3 *) + 0x9b0a19f0; (* arm_MADD X16 X15 X10 X6 *) + 0x9b0b1df1; (* arm_MADD X17 X15 X11 X7 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0xf27f00bf; (* arm_TST X5 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9a9f1086; (* arm_CSEL X6 X4 XZR Condition_NE *) + 0xfa5f1028; (* arm_CCMP X1 XZR (word 8) Condition_NE *) + 0xda81b421; (* arm_CNEG X1 X1 Condition_GE *) + 0xda86b4c6; (* arm_CNEG X6 X6 Condition_GE *) + 0x9a84a0a4; (* arm_CSEL X4 X5 X4 Condition_GE *) + 0x8b0600a5; (* arm_ADD X5 X5 X6 *) + 0x91000821; (* arm_ADD X1 X1 (rvalue (word 2)) *) + 0x9341fca5; (* arm_ASR X5 X5 1 *) + 0x9144008c; (* arm_ADD X12 X4 (rvalue (word 1048576)) *) + 0x9356a98c; (* arm_SBFM X12 X12 22 42 *) + 0xd2a0020f; (* arm_MOVZ X15 (word 16) 16 *) + 0x8b0f55ef; (* arm_ADD X15 X15 (Shiftedreg X15 LSL 21) *) + 0x8b0f008d; (* arm_ADD X13 X4 X15 *) + 0x936bfdad; (* arm_ASR X13 X13 43 *) + 0x914400ae; (* arm_ADD X14 X5 (rvalue (word 1048576)) *) + 0x9356a9ce; (* arm_SBFM X14 X14 22 42 *) + 0x8b0f00af; (* arm_ADD X15 X5 X15 *) + 0x936bfdef; (* arm_ASR X15 X15 43 *) + 0x9b08fd82; (* arm_MNEG X2 X12 X8 *) + 0x9b09fd83; (* arm_MNEG X3 X12 X9 *) + 0x9b08fdc4; (* arm_MNEG X4 X14 X8 *) + 0x9b09fdc5; (* arm_MNEG X5 X14 X9 *) + 0x9b1089aa; (* arm_MSUB X10 X13 X16 X2 *) + 0x9b118dab; (* arm_MSUB X11 X13 X17 X3 *) + 0x9b1091ec; (* arm_MSUB X12 X15 X16 X4 *) + 0x9b1195ed; (* arm_MSUB X13 X15 X17 X5 *) + 0xaa0103f6; (* arm_MOV X22 X1 *) + 0xf10006b5; (* arm_SUBS X21 X21 (rvalue (word 1)) *) + 0x54ff9281; (* arm_BNE (word 2093648) *) + 0xf94003e0; (* arm_LDR X0 SP (Immediate_Offset (word 0)) *) + 0xf94013e1; (* arm_LDR X1 SP (Immediate_Offset (word 32)) *) + 0x9b0a7c00; (* arm_MUL X0 X0 X10 *) + 0x9b0b0021; (* arm_MADD X1 X1 X11 X0 *) + 0x937ffc20; (* arm_ASR X0 X1 63 *) + 0xeb1f015f; (* arm_CMP X10 XZR *) + 0xda9f53ee; (* arm_CSETM X14 Condition_MI *) + 0xda8a554a; (* arm_CNEG X10 X10 Condition_MI *) + 0xca0001ce; (* arm_EOR X14 X14 X0 *) + 0xeb1f017f; (* arm_CMP X11 XZR *) + 0xda9f53ef; (* arm_CSETM X15 Condition_MI *) + 0xda8b556b; (* arm_CNEG X11 X11 Condition_MI *) + 0xca0001ef; (* arm_EOR X15 X15 X0 *) + 0xeb1f019f; (* arm_CMP X12 XZR *) + 0xda9f53f0; (* arm_CSETM X16 Condition_MI *) + 0xda8c558c; (* arm_CNEG X12 X12 Condition_MI *) + 0xca000210; (* arm_EOR X16 X16 X0 *) + 0xeb1f01bf; (* arm_CMP X13 XZR *) + 0xda9f53f1; (* arm_CSETM X17 Condition_MI *) + 0xda8d55ad; (* arm_CNEG X13 X13 Condition_MI *) + 0xca000231; (* arm_EOR X17 X17 X0 *) + 0x8a0e0140; (* arm_AND X0 X10 X14 *) + 0x8a0f0161; (* arm_AND X1 X11 X15 *) + 0x8b010009; (* arm_ADD X9 X0 X1 *) + 0xf94023e7; (* arm_LDR X7 SP (Immediate_Offset (word 64)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000124; (* arm_ADDS X4 X9 X0 *) + 0x9a0103e2; (* arm_ADC X2 XZR X1 *) + 0xf94033e8; (* arm_LDR X8 SP (Immediate_Offset (word 96)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000084; (* arm_ADDS X4 X4 X0 *) + 0xf90023e4; (* arm_STR X4 SP (Immediate_Offset (word 64)) *) + 0x9a010042; (* arm_ADC X2 X2 X1 *) + 0xf94027e7; (* arm_LDR X7 SP (Immediate_Offset (word 72)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0x9a0103e6; (* arm_ADC X6 XZR X1 *) + 0xf94037e8; (* arm_LDR X8 SP (Immediate_Offset (word 104)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab000042; (* arm_ADDS X2 X2 X0 *) + 0xf90027e2; (* arm_STR X2 SP (Immediate_Offset (word 72)) *) + 0x9a0100c6; (* arm_ADC X6 X6 X1 *) + 0xf9402be7; (* arm_LDR X7 SP (Immediate_Offset (word 80)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0x9a0103e5; (* arm_ADC X5 XZR X1 *) + 0xf9403be8; (* arm_LDR X8 SP (Immediate_Offset (word 112)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000c6; (* arm_ADDS X6 X6 X0 *) + 0xf9002be6; (* arm_STR X6 SP (Immediate_Offset (word 80)) *) + 0x9a0100a5; (* arm_ADC X5 X5 X1 *) + 0xf9402fe7; (* arm_LDR X7 SP (Immediate_Offset (word 88)) *) + 0xca0e00e1; (* arm_EOR X1 X7 X14 *) + 0x8a0a01c3; (* arm_AND X3 X14 X10 *) + 0xcb0303e3; (* arm_NEG X3 X3 *) + 0x9b0a7c20; (* arm_MUL X0 X1 X10 *) + 0x9bca7c21; (* arm_UMULH X1 X1 X10 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0xf9403fe8; (* arm_LDR X8 SP (Immediate_Offset (word 120)) *) + 0xca0f0101; (* arm_EOR X1 X8 X15 *) + 0x8a0b01e0; (* arm_AND X0 X15 X11 *) + 0xcb000063; (* arm_SUB X3 X3 X0 *) + 0x9b0b7c20; (* arm_MUL X0 X1 X11 *) + 0x9bcb7c21; (* arm_UMULH X1 X1 X11 *) + 0xab0000a5; (* arm_ADDS X5 X5 X0 *) + 0x9a010063; (* arm_ADC X3 X3 X1 *) + 0x93c5fc66; (* arm_EXTR X6 X3 X5 63 *) + 0xa94407e0; (* arm_LDP X0 X1 SP (Immediate_Offset (iword (&64))) *) + 0xea03007f; (* arm_TST X3 X3 *) + 0x9a8644c6; (* arm_CINC X6 X6 Condition_PL *) + 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) + 0x9b037cc4; (* arm_MUL X4 X6 X3 *) + 0x8b06fca5; (* arm_ADD X5 X5 (Shiftedreg X6 LSL 63) *) + 0x9b437cc6; (* arm_SMULH X6 X6 X3 *) + 0xf9402be2; (* arm_LDR X2 SP (Immediate_Offset (word 80)) *) + 0xab040000; (* arm_ADDS X0 X0 X4 *) + 0xba060021; (* arm_ADCS X1 X1 X6 *) + 0x937ffcc6; (* arm_ASR X6 X6 63 *) + 0xba060042; (* arm_ADCS X2 X2 X6 *) + 0xba0600a5; (* arm_ADCS X5 X5 X6 *) + 0x9a9f4063; (* arm_CSEL X3 X3 XZR Condition_MI *) + 0xeb030000; (* arm_SUBS X0 X0 X3 *) + 0xfa1f0021; (* arm_SBCS X1 X1 XZR *) + 0xfa1f0042; (* arm_SBCS X2 X2 XZR *) + 0xda1f00a5; (* arm_SBC X5 X5 XZR *) + 0x9240f8a5; (* arm_AND X5 X5 (rvalue (word 9223372036854775807)) *) + 0xaa1403e4; (* arm_MOV X4 X20 *) + 0xa9000480; (* arm_STP X0 X1 X4 (Immediate_Offset (iword (&0))) *) + 0xa9011482; (* arm_STP X2 X5 X4 (Immediate_Offset (iword (&16))) *) + 0xa94813e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&128))) *) + 0xa94a1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&160))) *) + 0x9ba57c67; (* arm_UMULL X7 W3 W5 *) + 0xd360fc60; (* arm_LSR X0 X3 32 *) + 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) + 0xd360fcb0; (* arm_LSR X16 X5 32 *) + 0x9ba07e08; (* arm_UMULL X8 W16 W0 *) + 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) + 0xab0f80e7; (* arm_ADDS X7 X7 (Shiftedreg X15 LSL 32) *) + 0xd360fdef; (* arm_LSR X15 X15 32 *) + 0x9a0f0108; (* arm_ADC X8 X8 X15 *) + 0xab1080e7; (* arm_ADDS X7 X7 (Shiftedreg X16 LSL 32) *) + 0xd360fe10; (* arm_LSR X16 X16 32 *) + 0x9a100108; (* arm_ADC X8 X8 X16 *) + 0x9b067c89; (* arm_MUL X9 X4 X6 *) + 0x9bc67c8a; (* arm_UMULH X10 X4 X6 *) + 0xeb030084; (* arm_SUBS X4 X4 X3 *) + 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) + 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) + 0xab080129; (* arm_ADDS X9 X9 X8 *) + 0x9a1f014a; (* arm_ADC X10 X10 XZR *) + 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) + 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) + 0xda902210; (* arm_CINV X16 X16 Condition_CC *) + 0x9b037c8f; (* arm_MUL X15 X4 X3 *) + 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) + 0xab0900e8; (* arm_ADDS X8 X7 X9 *) + 0xba0a0129; (* arm_ADCS X9 X9 X10 *) + 0x9a1f014a; (* arm_ADC X10 X10 XZR *) + 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) + 0xca1001ef; (* arm_EOR X15 X15 X16 *) + 0xba0801e8; (* arm_ADCS X8 X15 X8 *) + 0xca100063; (* arm_EOR X3 X3 X16 *) + 0xba090069; (* arm_ADCS X9 X3 X9 *) + 0x9a10014a; (* arm_ADC X10 X10 X16 *) + 0xa94913e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&144))) *) + 0xa94b1be5; (* arm_LDP X5 X6 SP (Immediate_Offset (iword (&176))) *) + 0x9ba57c6b; (* arm_UMULL X11 W3 W5 *) + 0xd360fc60; (* arm_LSR X0 X3 32 *) + 0x9ba57c0f; (* arm_UMULL X15 W0 W5 *) + 0xd360fcb0; (* arm_LSR X16 X5 32 *) + 0x9ba07e0c; (* arm_UMULL X12 W16 W0 *) + 0x9bb07c70; (* arm_UMULL X16 W3 W16 *) + 0xab0f816b; (* arm_ADDS X11 X11 (Shiftedreg X15 LSL 32) *) + 0xd360fdef; (* arm_LSR X15 X15 32 *) + 0x9a0f018c; (* arm_ADC X12 X12 X15 *) + 0xab10816b; (* arm_ADDS X11 X11 (Shiftedreg X16 LSL 32) *) + 0xd360fe10; (* arm_LSR X16 X16 32 *) + 0x9a10018c; (* arm_ADC X12 X12 X16 *) + 0x9b067c8d; (* arm_MUL X13 X4 X6 *) + 0x9bc67c8e; (* arm_UMULH X14 X4 X6 *) + 0xeb030084; (* arm_SUBS X4 X4 X3 *) + 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) + 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) + 0xab0c01ad; (* arm_ADDS X13 X13 X12 *) + 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) + 0xeb0600a3; (* arm_SUBS X3 X5 X6 *) + 0xda832463; (* arm_CNEG X3 X3 Condition_CC *) + 0xda902210; (* arm_CINV X16 X16 Condition_CC *) + 0x9b037c8f; (* arm_MUL X15 X4 X3 *) + 0x9bc37c83; (* arm_UMULH X3 X4 X3 *) + 0xab0d016c; (* arm_ADDS X12 X11 X13 *) + 0xba0e01ad; (* arm_ADCS X13 X13 X14 *) + 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) + 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) + 0xca1001ef; (* arm_EOR X15 X15 X16 *) + 0xba0c01ec; (* arm_ADCS X12 X15 X12 *) + 0xca100063; (* arm_EOR X3 X3 X16 *) + 0xba0d006d; (* arm_ADCS X13 X3 X13 *) + 0x9a1001ce; (* arm_ADC X14 X14 X16 *) + 0xa94913e3; (* arm_LDP X3 X4 SP (Immediate_Offset (iword (&144))) *) + 0xa94843ef; (* arm_LDP X15 X16 SP (Immediate_Offset (iword (&128))) *) + 0xeb0f0063; (* arm_SUBS X3 X3 X15 *) + 0xfa100084; (* arm_SBCS X4 X4 X16 *) + 0xda9f23f0; (* arm_CSETM X16 Condition_CC *) + 0xa94a03ef; (* arm_LDP X15 X0 SP (Immediate_Offset (iword (&160))) *) + 0xeb0501e5; (* arm_SUBS X5 X15 X5 *) + 0xfa060006; (* arm_SBCS X6 X0 X6 *) + 0xda9f23e0; (* arm_CSETM X0 Condition_CC *) + 0xca100063; (* arm_EOR X3 X3 X16 *) + 0xeb100063; (* arm_SUBS X3 X3 X16 *) + 0xca100084; (* arm_EOR X4 X4 X16 *) + 0xda100084; (* arm_SBC X4 X4 X16 *) + 0xca0000a5; (* arm_EOR X5 X5 X0 *) + 0xeb0000a5; (* arm_SUBS X5 X5 X0 *) + 0xca0000c6; (* arm_EOR X6 X6 X0 *) + 0xda0000c6; (* arm_SBC X6 X6 X0 *) + 0xca100010; (* arm_EOR X16 X0 X16 *) + 0xab09016b; (* arm_ADDS X11 X11 X9 *) + 0xba0a018c; (* arm_ADCS X12 X12 X10 *) + 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) + 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) + 0x9b057c62; (* arm_MUL X2 X3 X5 *) + 0x9bc57c60; (* arm_UMULH X0 X3 X5 *) + 0x9b067c8f; (* arm_MUL X15 X4 X6 *) + 0x9bc67c81; (* arm_UMULH X1 X4 X6 *) + 0xeb030084; (* arm_SUBS X4 X4 X3 *) + 0xda842484; (* arm_CNEG X4 X4 Condition_CC *) + 0xda9f23e9; (* arm_CSETM X9 Condition_CC *) + 0xab0001ef; (* arm_ADDS X15 X15 X0 *) + 0x9a1f0021; (* arm_ADC X1 X1 XZR *) + 0xeb0600a6; (* arm_SUBS X6 X5 X6 *) + 0xda8624c6; (* arm_CNEG X6 X6 Condition_CC *) + 0xda892129; (* arm_CINV X9 X9 Condition_CC *) + 0x9b067c85; (* arm_MUL X5 X4 X6 *) + 0x9bc67c86; (* arm_UMULH X6 X4 X6 *) + 0xab0f0040; (* arm_ADDS X0 X2 X15 *) + 0xba0101ef; (* arm_ADCS X15 X15 X1 *) + 0x9a1f0021; (* arm_ADC X1 X1 XZR *) + 0xb100053f; (* arm_CMN X9 (rvalue (word 1)) *) + 0xca0900a5; (* arm_EOR X5 X5 X9 *) + 0xba0000a0; (* arm_ADCS X0 X5 X0 *) + 0xca0900c6; (* arm_EOR X6 X6 X9 *) + 0xba0f00cf; (* arm_ADCS X15 X6 X15 *) + 0x9a090021; (* arm_ADC X1 X1 X9 *) + 0xab070169; (* arm_ADDS X9 X11 X7 *) + 0xba08018a; (* arm_ADCS X10 X12 X8 *) + 0xba0b01ab; (* arm_ADCS X11 X13 X11 *) + 0xba0c01cc; (* arm_ADCS X12 X14 X12 *) + 0xba1f01ad; (* arm_ADCS X13 X13 XZR *) + 0x9a1f01ce; (* arm_ADC X14 X14 XZR *) + 0xb100061f; (* arm_CMN X16 (rvalue (word 1)) *) + 0xca100042; (* arm_EOR X2 X2 X16 *) + 0xba090049; (* arm_ADCS X9 X2 X9 *) + 0xca100000; (* arm_EOR X0 X0 X16 *) + 0xba0a000a; (* arm_ADCS X10 X0 X10 *) + 0xca1001ef; (* arm_EOR X15 X15 X16 *) + 0xba0b01eb; (* arm_ADCS X11 X15 X11 *) + 0xca100021; (* arm_EOR X1 X1 X16 *) + 0xba0c002c; (* arm_ADCS X12 X1 X12 *) + 0xba1001ad; (* arm_ADCS X13 X13 X16 *) + 0x9a1001ce; (* arm_ADC X14 X14 X16 *) + 0xd28004c3; (* arm_MOV X3 (rvalue (word 38)) *) + 0x9ba37d64; (* arm_UMULL X4 W11 W3 *) + 0x8b274084; (* arm_ADD X4 X4 (Extendedreg W7 UXTW) *) + 0xd360fce7; (* arm_LSR X7 X7 32 *) + 0xd360fd6b; (* arm_LSR X11 X11 32 *) + 0x9ba31d6b; (* arm_UMADDL X11 W11 W3 X7 *) + 0xaa0403e7; (* arm_MOV X7 X4 *) + 0x9ba37d84; (* arm_UMULL X4 W12 W3 *) + 0x8b284084; (* arm_ADD X4 X4 (Extendedreg W8 UXTW) *) + 0xd360fd08; (* arm_LSR X8 X8 32 *) + 0xd360fd8c; (* arm_LSR X12 X12 32 *) + 0x9ba3218c; (* arm_UMADDL X12 W12 W3 X8 *) + 0xaa0403e8; (* arm_MOV X8 X4 *) + 0x9ba37da4; (* arm_UMULL X4 W13 W3 *) + 0x8b294084; (* arm_ADD X4 X4 (Extendedreg W9 UXTW) *) + 0xd360fd29; (* arm_LSR X9 X9 32 *) + 0xd360fdad; (* arm_LSR X13 X13 32 *) + 0x9ba325ad; (* arm_UMADDL X13 W13 W3 X9 *) + 0xaa0403e9; (* arm_MOV X9 X4 *) + 0x9ba37dc4; (* arm_UMULL X4 W14 W3 *) + 0x8b2a4084; (* arm_ADD X4 X4 (Extendedreg W10 UXTW) *) + 0xd360fd4a; (* arm_LSR X10 X10 32 *) + 0xd360fdce; (* arm_LSR X14 X14 32 *) + 0x9ba329ce; (* arm_UMADDL X14 W14 W3 X10 *) + 0xaa0403ea; (* arm_MOV X10 X4 *) + 0xd35ffdc0; (* arm_LSR X0 X14 31 *) + 0xd2800265; (* arm_MOV X5 (rvalue (word 19)) *) + 0x9ba014a5; (* arm_UMADDL X5 W5 W0 X5 *) + 0x8b0500e7; (* arm_ADD X7 X7 X5 *) + 0xab0b80e7; (* arm_ADDS X7 X7 (Shiftedreg X11 LSL 32) *) + 0x93cb8183; (* arm_EXTR X3 X12 X11 32 *) + 0xba030108; (* arm_ADCS X8 X8 X3 *) + 0x93cc81a3; (* arm_EXTR X3 X13 X12 32 *) + 0xba030129; (* arm_ADCS X9 X9 X3 *) + 0x93cd81c3; (* arm_EXTR X3 X14 X13 32 *) + 0xd3410005; (* arm_LSL X5 X0 63 *) + 0xca05014a; (* arm_EOR X10 X10 X5 *) + 0x9a03014a; (* arm_ADC X10 X10 X3 *) + 0xd2800263; (* arm_MOV X3 (rvalue (word 19)) *) + 0xf241015f; (* arm_TST X10 (rvalue (word 9223372036854775808)) *) + 0x9a9f5063; (* arm_CSEL X3 X3 XZR Condition_PL *) + 0xeb0300e7; (* arm_SUBS X7 X7 X3 *) + 0xfa1f0108; (* arm_SBCS X8 X8 XZR *) + 0xfa1f0129; (* arm_SBCS X9 X9 XZR *) + 0xda1f014a; (* arm_SBC X10 X10 XZR *) + 0x9240f94a; (* arm_AND X10 X10 (rvalue (word 9223372036854775807)) *) + 0xa90a23e7; (* arm_STP X7 X8 SP (Immediate_Offset (iword (&160))) *) + 0xa90b2be9; (* arm_STP X9 X10 SP (Immediate_Offset (iword (&176))) *) + 0xf94063f1; (* arm_LDR X17 SP (Immediate_Offset (word 192)) *) + 0xa94a2fea; (* arm_LDP X10 X11 SP (Immediate_Offset (iword (&160))) *) + 0x3900022a; (* arm_STRB W10 X17 (Immediate_Offset (word 0)) *) + 0xd348fd4a; (* arm_LSR X10 X10 8 *) + 0x3900062a; (* arm_STRB W10 X17 (Immediate_Offset (word 1)) *) + 0xd348fd4a; (* arm_LSR X10 X10 8 *) + 0x39000a2a; (* arm_STRB W10 X17 (Immediate_Offset (word 2)) *) + 0xd348fd4a; (* arm_LSR X10 X10 8 *) + 0x39000e2a; (* arm_STRB W10 X17 (Immediate_Offset (word 3)) *) + 0xd348fd4a; (* arm_LSR X10 X10 8 *) + 0x3900122a; (* arm_STRB W10 X17 (Immediate_Offset (word 4)) *) + 0xd348fd4a; (* arm_LSR X10 X10 8 *) + 0x3900162a; (* arm_STRB W10 X17 (Immediate_Offset (word 5)) *) + 0xd348fd4a; (* arm_LSR X10 X10 8 *) + 0x39001a2a; (* arm_STRB W10 X17 (Immediate_Offset (word 6)) *) + 0xd348fd4a; (* arm_LSR X10 X10 8 *) + 0x39001e2a; (* arm_STRB W10 X17 (Immediate_Offset (word 7)) *) + 0x3900222b; (* arm_STRB W11 X17 (Immediate_Offset (word 8)) *) + 0xd348fd6b; (* arm_LSR X11 X11 8 *) + 0x3900262b; (* arm_STRB W11 X17 (Immediate_Offset (word 9)) *) + 0xd348fd6b; (* arm_LSR X11 X11 8 *) + 0x39002a2b; (* arm_STRB W11 X17 (Immediate_Offset (word 10)) *) + 0xd348fd6b; (* arm_LSR X11 X11 8 *) + 0x39002e2b; (* arm_STRB W11 X17 (Immediate_Offset (word 11)) *) + 0xd348fd6b; (* arm_LSR X11 X11 8 *) + 0x3900322b; (* arm_STRB W11 X17 (Immediate_Offset (word 12)) *) + 0xd348fd6b; (* arm_LSR X11 X11 8 *) + 0x3900362b; (* arm_STRB W11 X17 (Immediate_Offset (word 13)) *) + 0xd348fd6b; (* arm_LSR X11 X11 8 *) + 0x39003a2b; (* arm_STRB W11 X17 (Immediate_Offset (word 14)) *) + 0xd348fd6b; (* arm_LSR X11 X11 8 *) + 0x39003e2b; (* arm_STRB W11 X17 (Immediate_Offset (word 15)) *) + 0xa94b37ec; (* arm_LDP X12 X13 SP (Immediate_Offset (iword (&176))) *) + 0x3900422c; (* arm_STRB W12 X17 (Immediate_Offset (word 16)) *) + 0xd348fd8c; (* arm_LSR X12 X12 8 *) + 0x3900462c; (* arm_STRB W12 X17 (Immediate_Offset (word 17)) *) + 0xd348fd8c; (* arm_LSR X12 X12 8 *) + 0x39004a2c; (* arm_STRB W12 X17 (Immediate_Offset (word 18)) *) + 0xd348fd8c; (* arm_LSR X12 X12 8 *) + 0x39004e2c; (* arm_STRB W12 X17 (Immediate_Offset (word 19)) *) + 0xd348fd8c; (* arm_LSR X12 X12 8 *) + 0x3900522c; (* arm_STRB W12 X17 (Immediate_Offset (word 20)) *) + 0xd348fd8c; (* arm_LSR X12 X12 8 *) + 0x3900562c; (* arm_STRB W12 X17 (Immediate_Offset (word 21)) *) + 0xd348fd8c; (* arm_LSR X12 X12 8 *) + 0x39005a2c; (* arm_STRB W12 X17 (Immediate_Offset (word 22)) *) + 0xd348fd8c; (* arm_LSR X12 X12 8 *) + 0x39005e2c; (* arm_STRB W12 X17 (Immediate_Offset (word 23)) *) + 0x3900622d; (* arm_STRB W13 X17 (Immediate_Offset (word 24)) *) + 0xd348fdad; (* arm_LSR X13 X13 8 *) + 0x3900662d; (* arm_STRB W13 X17 (Immediate_Offset (word 25)) *) + 0xd348fdad; (* arm_LSR X13 X13 8 *) + 0x39006a2d; (* arm_STRB W13 X17 (Immediate_Offset (word 26)) *) + 0xd348fdad; (* arm_LSR X13 X13 8 *) + 0x39006e2d; (* arm_STRB W13 X17 (Immediate_Offset (word 27)) *) + 0xd348fdad; (* arm_LSR X13 X13 8 *) + 0x3900722d; (* arm_STRB W13 X17 (Immediate_Offset (word 28)) *) + 0xd348fdad; (* arm_LSR X13 X13 8 *) + 0x3900762d; (* arm_STRB W13 X17 (Immediate_Offset (word 29)) *) + 0xd348fdad; (* arm_LSR X13 X13 8 *) + 0x39007a2d; (* arm_STRB W13 X17 (Immediate_Offset (word 30)) *) + 0xd348fdad; (* arm_LSR X13 X13 8 *) + 0x39007e2d; (* arm_STRB W13 X17 (Immediate_Offset (word 31)) *) + 0x6d4e27e8; (* arm_LDP D8 D9 SP (Immediate_Offset (iword (&224))) *) + 0x6d4f2fea; (* arm_LDP D10 D11 SP (Immediate_Offset (iword (&240))) *) + 0x6d5037ec; (* arm_LDP D12 D13 SP (Immediate_Offset (iword (&256))) *) + 0x6d513fee; (* arm_LDP D14 D15 SP (Immediate_Offset (iword (&272))) *) + 0xa95253f3; (* arm_LDP X19 X20 SP (Immediate_Offset (iword (&288))) *) + 0xa9535bf5; (* arm_LDP X21 X22 SP (Immediate_Offset (iword (&304))) *) + 0xa95463f7; (* arm_LDP X23 X24 SP (Immediate_Offset (iword (&320))) *) + 0xa9556bf9; (* arm_LDP X25 X26 SP (Immediate_Offset (iword (&336))) *) + 0xa95673fb; (* arm_LDP X27 X28 SP (Immediate_Offset (iword (&352))) *) + 0xa9577bfd; (* arm_LDP X29 X30 SP (Immediate_Offset (iword (&368))) *) + 0x910603ff; (* arm_ADD SP SP (rvalue (word 384)) *) + 0xd65f03c0 (* arm_RET X30 *) +];; - FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE RAND_CONV [WORD_XOR_MASKS]) THEN - ASM_REWRITE_TAC[] THEN DISCH_TAC THEN +let CURVE25519_X25519_BYTE_EXEC = ARM_MK_EXEC_RULE curve25519_x25519_byte_mc;; - (*** The augmented H' = H + L_top ***) +(* ------------------------------------------------------------------------- *) +(* Some abbreviations around the base-25.5 representation *) +(* ------------------------------------------------------------------------- *) - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (69--72) (69--72) THEN - MAP_EVERY ABBREV_TAC - [`q2 = bignum_of_wordlist[sum_s69;sum_s70]`; - `q3 = bignum_of_wordlist[sum_s71;sum_s72]`] THEN - SUBGOAL_THEN - `2 EXP 128 * q3 + q2 = - bignum_of_wordlist [x_2;x_3] * bignum_of_wordlist[y_2;y_3] + q1` - ASSUME_TAC THENL - [MAP_EVERY EXPAND_TAC ["q1"; "q2"; "q3"] THEN - MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN - REPEAT(CONJ_TAC THENL - [CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; ALL_TAC]) THEN - FIRST_X_ASSUM(fun th -> GEN_REWRITE_TAC - (LAND_CONV o LAND_CONV) [SYM th]) THEN - MAP_EVERY EXPAND_TAC ["q23"] THEN - REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ALL_TAC] THEN +let ubignum_of_list = define + `ubignum_of_list [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9] = + d0 + + 2 EXP 26 * d1 + + 2 EXP 51 * d2 + + 2 EXP 77 * d3 + + 2 EXP 102 * d4 + + 2 EXP 128 * d5 + + 2 EXP 153 * d6 + + 2 EXP 179 * d7 + + 2 EXP 204 * d8 + + 2 EXP 230 * d9`;; + +let ubignum_of_int32list = define + `ubignum_of_int32list (l:int32 list) = ubignum_of_list (MAP val l)`;; + +(*** This is a paired representation using parts of the vector registers ***) + +let ubignum_of_qreglist = define + `ubignum_of_qreglist [q0:(armstate,int128)component;q2;q4;q6;q8] s = + ubignum_of_int32list + [word_subword (read q0 s) (0,32); word_subword (read q0 s) (32,32); + word_subword (read q2 s) (0,32); word_subword (read q2 s) (32,32); + word_subword (read q4 s) (0,32); word_subword (read q4 s) (32,32); + word_subword (read q6 s) (0,32); word_subword (read q6 s) (32,32); + word_subword (read q8 s) (0,32); word_subword (read q8 s) (32,32)]`;; + +(**** This is a pure representation with one GPR per digit ***) + +let ubignum_of_xreglist = define + `ubignum_of_xreglist (l:((armstate,int64)component) list) s = + ubignum_of_list (MAP (\c. val(read c s)) l)`;; + +(**** Similar, but only looking at the W register form, the lowest 32 bits ***) + +let ubignum_of_wreglist = define + `ubignum_of_wreglist (l:((armstate,int64)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (0,32):int32)) l)`;; + +(*** Simular, in the high and low 64-bits of 128-bit registers ***) + +let ubignum_of_hreglist = define + `ubignum_of_hreglist (l:((armstate,int128)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (64,64):int64)) l)`;; + +let ubignum_of_lreglist = define + `ubignum_of_lreglist (l:((armstate,int128)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (0,64):int64)) l)`;; + +(*** Similar again, this time 32-bit chunks, which might be better ***) + +let ubignum_of_h32reglist = define + `ubignum_of_h32reglist (l:((armstate,int128)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (32,32):int32)) l)`;; + +let ubignum_of_l32reglist = define + `ubignum_of_l32reglist (l:((armstate,int128)component) list) s = + ubignum_of_list (MAP (\c. val(word_subword (read c s) (0,32):int32)) l)`;; + +(*** This is how they are sometimes packed in pairs into GPRs ***) + +let ubignum_of_preglist = define + `ubignum_of_preglist [p0:(armstate,int64)component;p2;p4;p6;p8] s = + ubignum_of_int32list + [word_subword (read p0 s) (0,32); word_subword (read p0 s) (32,32); + word_subword (read p2 s) (0,32); word_subword (read p2 s) (32,32); + word_subword (read p4 s) (0,32); word_subword (read p4 s) (32,32); + word_subword (read p6 s) (0,32); word_subword (read p6 s) (32,32); + word_subword (read p8 s) (0,32); word_subword (read p8 s) (32,32)]`;; + +(*** There are two slightly different notions of normalization. + *** The primed one comes up when using the scalar version of + *** multiplication, which does nor repack right-to-left and so + *** can have a larger top digit. Otherwise, the digit bounds + *** are roughly alternating 25 and 26 bits plus a bit extra. + ***) + +let normalized_ubignum_list = define + `normalized_ubignum_list [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9] x <=> + (&(ubignum_of_list [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9]):int == x) + (mod &p_25519) /\ + d0 <= 67108863 /\ d1 <= 34000000 /\ + d2 <= 67108863 /\ d3 <= 34000000 /\ + d4 <= 67108863 /\ d5 <= 34000000 /\ + d6 <= 67108863 /\ d7 <= 34000000 /\ + d8 <= 67108863 /\ d9 <= 34000000`;; + +let normalized_ubignum_int32list = define + `normalized_ubignum_int32list (l:int32 list) x = + normalized_ubignum_list (MAP val l) x`;; + +let normalized_ubignum_preglist = define + `normalized_ubignum_preglist + [p0:(armstate,int64)component;p2;p4;p6;p8] x s = + normalized_ubignum_int32list + [word_subword (read p0 s) (0,32); word_subword (read p0 s) (32,32); + word_subword (read p2 s) (0,32); word_subword (read p2 s) (32,32); + word_subword (read p4 s) (0,32); word_subword (read p4 s) (32,32); + word_subword (read p6 s) (0,32); word_subword (read p6 s) (32,32); + word_subword (read p8 s) (0,32); word_subword (read p8 s) (32,32)] + x`;; + +let normalized_ubignum_qreglist = define + `normalized_ubignum_qreglist + [q0:(armstate,int128)component;q2;q4;q6;q8] x s = + normalized_ubignum_int32list + [word_subword (read q0 s) (0,32); word_subword (read q0 s) (32,32); + word_subword (read q2 s) (0,32); word_subword (read q2 s) (32,32); + word_subword (read q4 s) (0,32); word_subword (read q4 s) (32,32); + word_subword (read q6 s) (0,32); word_subword (read q6 s) (32,32); + word_subword (read q8 s) (0,32); word_subword (read q8 s) (32,32)] + x`;; + +let normalized_ubignum_list' = define + `normalized_ubignum_list' [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9] x <=> + (&(ubignum_of_list [d0;d1;d2;d3;d4;d5;d6;d7;d8;d9]):int == x) + (mod &p_25519) /\ + d0 <= 67108863 /\ d1 <= 34000000 /\ + d2 <= 67108863 /\ d3 <= 34000000 /\ + d4 <= 67108863 /\ d5 <= 34000000 /\ + d6 <= 67108863 /\ d7 <= 34000000 /\ + d8 <= 67108863 /\ d9 <= 67108863`;; + +let normalized_ubignum_int32list' = define + `normalized_ubignum_int32list' (l:int32 list) x = + normalized_ubignum_list' (MAP val l) x`;; + +let normalized_ubignum_preglist' = define + `normalized_ubignum_preglist' + [p0:(armstate,int64)component;p2;p4;p6;p8] x s = + normalized_ubignum_int32list' + [word_subword (read p0 s) (0,32); word_subword (read p0 s) (32,32); + word_subword (read p2 s) (0,32); word_subword (read p2 s) (32,32); + word_subword (read p4 s) (0,32); word_subword (read p4 s) (32,32); + word_subword (read p6 s) (0,32); word_subword (read p6 s) (32,32); + word_subword (read p8 s) (0,32); word_subword (read p8 s) (32,32)] + x`;; + +let normalized_ubignum_qreglist' = define + `normalized_ubignum_qreglist' + [q0:(armstate,int128)component;q2;q4;q6;q8] x s = + normalized_ubignum_int32list' + [word_subword (read q0 s) (0,32); word_subword (read q0 s) (32,32); + word_subword (read q2 s) (0,32); word_subword (read q2 s) (32,32); + word_subword (read q4 s) (0,32); word_subword (read q4 s) (32,32); + word_subword (read q6 s) (0,32); word_subword (read q6 s) (32,32); + word_subword (read q8 s) (0,32); word_subword (read q8 s) (32,32)] + x`;; - (*** Third nested block multiplying the absolute differences ***) +(* ------------------------------------------------------------------------- *) +(* Key state components in inner loop, extracted from code annotations. *) +(* ------------------------------------------------------------------------- *) - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [73;75;80;81;85;87;88;89;92;94;95] (73--95) THEN - RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN - SUBGOAL_THEN - `&xd * &yd:real = - &(bignum_of_wordlist[mullo_s73; sum_s92; sum_s94; sum_s95])` - SUBST_ALL_TAC THENL - [MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - KARATSUBA12_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN - DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN +let named_variables = + [`x = + ubignum_of_list + [val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 32))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 32))) s0) (32,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 40))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 40))) s0) (32,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 48))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 48))) s0) (32,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 56))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 56))) s0) (32,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 64))) s0) (0,32):int32); + val(word_subword + (read (memory :> bytes64(word_add stackpointer (word 64))) s0) (32,32):int32)]`; + `x2 = + ubignum_of_list + [val(word_subword (read Q0 s0) (0,32):int32); + val(word_subword (read Q0 s0) (32,32):int32); + val(word_subword (read Q2 s0) (0,32):int32); + val(word_subword (read Q2 s0) (32,32):int32); + val(word_subword (read Q4 s0) (0,32):int32); + val(word_subword (read Q4 s0) (32,32):int32); + val(word_subword (read Q6 s0) (0,32):int32); + val(word_subword (read Q6 s0) (32,32):int32); + val(word_subword (read Q8 s0) (0,32):int32); + val(word_subword (read Q8 s0) (32,32):int32)]`; + `x3 = + ubignum_of_list + [val(word_subword (read Q10 s0) (0,32):int32); + val(word_subword (read Q10 s0) (32,32):int32); + val(word_subword (read Q12 s0) (0,32):int32); + val(word_subword (read Q12 s0) (32,32):int32); + val(word_subword (read Q14 s0) (0,32):int32); + val(word_subword (read Q14 s0) (32,32):int32); + val(word_subword (read Q16 s0) (0,32):int32); + val(word_subword (read Q16 s0) (32,32):int32); + val(word_subword (read Q18 s0) (0,32):int32); + val(word_subword (read Q18 s0) (32,32):int32)]`; + `z2 = + ubignum_of_list + [val(word_subword (read Q1 s0) (0,32):int32); + val(word_subword (read Q1 s0) (32,32):int32); + val(word_subword (read Q3 s0) (0,32):int32); + val(word_subword (read Q3 s0) (32,32):int32); + val(word_subword (read Q5 s0) (0,32):int32); + val(word_subword (read Q5 s0) (32,32):int32); + val(word_subword (read Q7 s0) (0,32):int32); + val(word_subword (read Q7 s0) (32,32):int32); + val(word_subword (read Q9 s0) (0,32):int32); + val(word_subword (read Q9 s0) (32,32):int32)]`; + `z3 = + ubignum_of_list + [val(word_subword (read Q11 s0) (0,32):int32); + val(word_subword (read Q11 s0) (32,32):int32); + val(word_subword (read Q13 s0) (0,32):int32); + val(word_subword (read Q13 s0) (32,32):int32); + val(word_subword (read Q15 s0) (0,32):int32); + val(word_subword (read Q15 s0) (32,32):int32); + val(word_subword (read Q17 s0) (0,32):int32); + val(word_subword (read Q17 s0) (32,32):int32); + val(word_subword (read Q19 s0) (0,32):int32); + val(word_subword (read Q19 s0) (32,32):int32)]`; + `a = + ubignum_of_list + [val(word_subword (read Q25 s10) (0,32):int32); + val(word_subword (read Q25 s10) (32,32):int32); + val(word_subword (read Q22 s8) (0,32):int32); + val(word_subword (read Q22 s8) (32,32):int32); + val(word_subword (read Q28 s34) (0,32):int32); + val(word_subword (read Q28 s34) (32,32):int32); + val(word_subword (read Q23 s30) (0,32):int32); + val(word_subword (read Q23 s30) (32,32):int32); + val(word_subword (read Q9 s53) (0,32):int32); + val(word_subword (read Q9 s53) (32,32):int32)]`; + `aa = + ubignum_of_list + [val(word_subword (read X9 s258) (0,32):int32); + val(word_subword (read X9 s258) (32,32):int32); + val(word_subword (read X11 s335) (0,32):int32); + val(word_subword (read X11 s335) (32,32):int32); + val(word_subword (read X14 s282) (0,32):int32); + val(word_subword (read X14 s282) (32,32):int32); + val(word_subword (read X29 s289) (0,32):int32); + val(word_subword (read X29 s289) (32,32):int32); + val(word_subword (read X6 s478) (0,32):int32); + val(word_subword (read X6 s478) (32,32):int32)]`; + `ad = + ubignum_of_list + [val(word_subword (read Q7 s390) (0,64):int64); + val(word_subword (read Q8 s394) (0,64):int64); + val(word_subword (read Q3 s404) (0,64):int64); + val(word_subword (read Q0 s402) (0,64):int64); + val(word_subword (read Q20 s321) (0,64):int64); + val(word_subword (read Q27 s330) (0,64):int64); + val(word_subword (read Q8 s328) (0,64):int64); + val(word_subword (read Q5 s332) (0,64):int64); + val(word_subword (read Q1 s364) (0,64):int64); + val(word_subword (read Q17 s368) (0,64):int64)]`; + `b = + ubignum_of_list + [val(word_subword (read Q0 s13) (0,32):int32); + val(word_subword (read Q0 s13) (32,32):int32); + val(word_subword (read Q18 s22) (0,32):int32); + val(word_subword (read Q18 s22) (32,32):int32); + val(word_subword (read Q1 s57) (0,32):int32); + val(word_subword (read Q1 s57) (32,32):int32); + val(word_subword (read Q13 s46) (0,32):int32); + val(word_subword (read Q13 s46) (32,32):int32); + val(word_subword (read Q7 s36) (0,32):int32); + val(word_subword (read Q7 s36) (32,32):int32)]`; + `bb = + ubignum_of_list + [val(word_subword (read X11 s514) (0,32):int32); + val(word_subword (read X11 s514) (32,32):int32); + val(word_subword (read X5 s538) (0,32):int32); + val(word_subword (read X5 s538) (32,32):int32); + val(word_subword (read X20 s565) (0,32):int32); + val(word_subword (read X20 s565) (32,32):int32); + val(word_subword (read X19 s569) (0,32):int32); + val(word_subword (read X19 s569) (32,32):int32); + val(word_subword (read X29 s549) (0,32):int32); + val(word_subword (read X29 s549) (32,32):int32)]`; + `bbalt = + ubignum_of_list + [val(read X17 s592); val(read X17 s551); val(read X12 s557); + val(read X1 s530); val(read X8 s573); val(read X24 s561); + val(read X2 s581); val(read X28 s577); val(read X0 s586); + val(read X15 s549)]`; + `bc = + ubignum_of_list + [val(word_subword (read Q7 s390) (64,64):int64); + val(word_subword (read Q8 s394) (64,64):int64); + val(word_subword (read Q3 s404) (64,64):int64); + val(word_subword (read Q0 s402) (64,64):int64); + val(word_subword (read Q20 s321) (64,64):int64); + val(word_subword (read Q27 s330) (64,64):int64); + val(word_subword (read Q8 s328) (64,64):int64); + val(word_subword (read Q5 s332) (64,64):int64); + val(word_subword (read Q1 s364) (64,64):int64); + val(word_subword (read Q17 s368) (64,64):int64)]`; + `bce = + ubignum_of_list + [val(read X11 s638); val(read X12 s645); val(read X15 s688); + val(read X21 s676); val(read X30 s707); val(read X2 s720); + val(read X9 s803); val(read X3 s691); val(read X3 s760); + val(read X4 s697)]`; + `c = + ubignum_of_list + [val(word_subword (read Q19 s18) (0,32):int32); + val(word_subword (read Q19 s18) (32,32):int32); + val(word_subword (read Q24 s26) (0,32):int32); + val(word_subword (read Q24 s26) (32,32):int32); + val(word_subword (read Q14 s23) (0,32):int32); + val(word_subword (read Q14 s23) (32,32):int32); + val(word_subword (read Q15 s24) (0,32):int32); + val(word_subword (read Q15 s24) (32,32):int32); + val(word_subword (read Q3 s12) (0,32):int32); + val(word_subword (read Q3 s12) (32,32):int32)]`; + `d = + ubignum_of_list + [val(word_subword (read Q26 s27) (0,32):int32); + val(word_subword (read Q26 s27) (32,32):int32); + val(word_subword (read Q27 s32) (0,32):int32); + val(word_subword (read Q27 s32) (32,32):int32); + val(word_subword (read Q11 s19) (0,32):int32); + val(word_subword (read Q11 s19) (32,32):int32); + val(word_subword (read Q2 s25) (0,32):int32); + val(word_subword (read Q2 s25) (32,32):int32); + val(word_subword (read Q21 s20) (0,32):int32); + val(word_subword (read Q21 s20) (32,32):int32)]`; + `e = + ubignum_of_list + [val(word_subword (read X13 s522) (0,32):int32); + val(word_subword (read X16 s522) (0,32):int32); + val(word_subword (read X6 s559) (0,32):int32); + val(word_subword (read X26 s559) (0,32):int32); + val(word_subword (read X7 s575) (0,32):int32); + val(word_subword (read X14 s575) (0,32):int32); + val(word_subword (read X5 s598) (0,32):int32); + val(word_subword (read X10 s598) (0,32):int32); + val(word_subword (read X23 s588) (0,32):int32); + val(word_subword (read X22 s588) (0,32):int32)]`; + `f = + ubignum_of_list + [val(word_subword (read Q16 s37) (0,32):int32); + val(word_subword (read Q16 s37) (32,32):int32); + val(word_subword (read Q20 s33) (0,32):int32); + val(word_subword (read Q20 s33) (32,32):int32); + val(word_subword (read Q5 s39) (0,32):int32); + val(word_subword (read Q5 s39) (32,32):int32); + val(word_subword (read Q12 s35) (0,32):int32); + val(word_subword (read Q12 s35) (32,32):int32); + val(word_subword (read Q26 s104) (0,32):int32); + val(word_subword (read Q26 s104) (32,32):int32)]`; + `g = + ubignum_of_list + [val(word_subword (read Q29 s67) (0,32):int32); + val(word_subword (read Q29 s67) (32,32):int32); + val(word_subword (read Q10 s49) (0,32):int32); + val(word_subword (read Q10 s49) (32,32):int32); + val(word_subword (read Q27 s75) (0,32):int32); + val(word_subword (read Q27 s75) (32,32):int32); + val(word_subword (read Q8 s59) (0,32):int32); + val(word_subword (read Q8 s59) (32,32):int32); + val(word_subword (read Q29 s41) (0,32):int32); + val(word_subword (read Q29 s41) (32,32):int32)]`; + `t1 = + ubignum_of_list + [val(word_subword (read Q1 s434) (32,32):int32); + val(word_subword (read Q19 s438) (32,32):int32); + val(word_subword (read Q0 s432) (32,32):int32); + val(word_subword (read Q15 s441) (32,32):int32); + val(word_subword (read Q16 s428) (32,32):int32); + val(word_subword (read Q4 s448) (32,32):int32); + val(word_subword (read Q14 s430) (32,32):int32); + val(word_subword (read Q10 s449) (32,32):int32); + val(word_subword (read Q22 s412) (32,32):int32); + val(word_subword (read Q5 s436) (32,32):int32)]`; + `t2 = + ubignum_of_list + [val(word_subword (read Q1 s434) (0,32):int32); + val(word_subword (read Q19 s438) (0,32):int32); + val(word_subword (read Q0 s432) (0,32):int32); + val(word_subword (read Q15 s441) (0,32):int32); + val(word_subword (read Q16 s428) (0,32):int32); + val(word_subword (read Q4 s448) (0,32):int32); + val(word_subword (read Q14 s430) (0,32):int32); + val(word_subword (read Q10 s449) (0,32):int32); + val(word_subword (read Q22 s412) (0,32):int32); + val(word_subword (read Q5 s436) (0,32):int32)]`; + `t3 = + ubignum_of_list + [val(word_subword (read Q0 s593) (0,64):int64); + val(word_subword (read Q1 s600) (0,64):int64); + val(word_subword (read Q2 s615) (0,64):int64); + val(word_subword (read Q3 s609) (0,64):int64); + val(word_subword (read Q4 s599) (0,64):int64); + val(word_subword (read Q5 s626) (0,64):int64); + val(word_subword (read Q6 s624) (0,64):int64); + val(word_subword (read Q7 s628) (0,64):int64); + val(word_subword (read Q8 s651) (0,64):int64); + val(word_subword (read Q9 s663) (0,64):int64)]`; + `x4 = + ubignum_of_list + [val(word_subword (read Q21 s991) (64,64):int64); + val(word_subword (read Q27 s1007) (64,64):int64); + val(word_subword (read Q28 s1012) (64,64):int64); + val(word_subword (read Q26 s1011) (64,64):int64); + val(word_subword (read Q17 s921) (64,64):int64); + val(word_subword (read Q15 s925) (64,64):int64); + val(word_subword (read Q13 s973) (64,64):int64); + val(word_subword (read Q27 s957) (64,64):int64); + val(word_subword (read Q21 s979) (64,64):int64); + val(word_subword (read Q28 s968) (64,64):int64)]`; + `x5 = + ubignum_of_list + [val(word_subword (read Q0 s593) (64,64):int64); + val(word_subword (read Q1 s600) (64,64):int64); + val(word_subword (read Q2 s615) (64,64):int64); + val(word_subword (read Q3 s609) (64,64):int64); + val(word_subword (read Q4 s599) (64,64):int64); + val(word_subword (read Q5 s626) (64,64):int64); + val(word_subword (read Q6 s624) (64,64):int64); + val(word_subword (read Q7 s628) (64,64):int64); + val(word_subword (read Q8 s651) (64,64):int64); + val(word_subword (read Q9 s663) (64,64):int64)]`; + `z4 = + ubignum_of_list + [val(word_subword (read X5 s982) (0,32):int32); + val(word_subword (read X5 s982) (32,32):int32); + val(word_subword (read X17 s1008) (0,32):int32); + val(word_subword (read X17 s1008) (32,32):int32); + val(word_subword (read X3 s990) (0,32):int32); + val(word_subword (read X3 s990) (32,32):int32); + val(word_subword (read X25 s895) (0,32):int32); + val(word_subword (read X25 s895) (32,32):int32); + val(word_subword (read X23 s992) (0,32):int32); + val(word_subword (read X23 s992) (32,32):int32)]`; + `z5 = + ubignum_of_list + [val(word_subword (read Q21 s991) (0,64):int64); + val(word_subword (read Q27 s1007) (0,64):int64); + val(word_subword (read Q28 s1012) (0,64):int64); + val(word_subword (read Q26 s1011) (0,64):int64); + val(word_subword (read Q17 s921) (0,64):int64); + val(word_subword (read Q15 s925) (0,64):int64); + val(word_subword (read Q13 s973) (0,64):int64); + val(word_subword (read Q27 s957) (0,64):int64); + val(word_subword (read Q21 s979) (0,64):int64); + val(word_subword (read Q28 s968) (0,64):int64)]`];; - (*** The rest of the basic 4x4->8 multiply computation and its proof ***) +(* ------------------------------------------------------------------------- *) +(* Other local variables (not many of these are really used) *) +(* ------------------------------------------------------------------------- *) - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [96;97;98;99;100;101;104;106;108;110;111;112] (96--112) THEN - MAP_EVERY ABBREV_TAC - [`l = bignum_of_wordlist[mullo_s3; sum_s22; sum_s104; sum_s106]`; - `h = bignum_of_wordlist[sum_s108; sum_s110; sum_s111; sum_s112]`] THEN - SUBGOAL_THEN `2 EXP 256 * h + l = m * n` (SUBST1_TAC o SYM) THENL - [DISCARD_STATE_TAC "s112" THEN MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`512`; `&0:real`] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL - [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN BOUNDER_TAC[]; - REWRITE_TAC[INTEGER_CLOSED]] THEN - SUBGOAL_THEN - `&m * &n:real = - (&1 + &2 pow 128) * (&q0 + &2 pow 128 * &q2 + &2 pow 256 * &q3) + - &2 pow 128 * - (&(bignum_of_wordlist [x_2; x_3]) - - &(bignum_of_wordlist [x_0; x_1])) * - (&(bignum_of_wordlist [y_0; y_1]) - - &(bignum_of_wordlist [y_2; y_3]))` - SUBST1_TAC THENL - [MAP_EVERY UNDISCH_TAC - [`2 EXP 128 * q1 + q0 = - bignum_of_wordlist[x_0; x_1] * bignum_of_wordlist[y_0; y_1]`; - `2 EXP 128 * q3 + q2 = - bignum_of_wordlist[x_2; x_3] * bignum_of_wordlist[y_2; y_3] + - q1`] THEN - MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - CONV_TAC REAL_RING; - ASM_REWRITE_TAC[]] THEN - MAP_EVERY EXPAND_TAC ["h"; "l"; "q0"; "q2"; "q3"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - POP_ASSUM_LIST(K ALL_TAC) THEN - REWRITE_TAC[WORD_XOR_MASK] THEN COND_CASES_TAC THEN - ASM_REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN - CONV_TAC WORD_REDUCE_CONV THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[BITVAL_CLAUSES] THEN DISCH_TAC THEN - FIRST_ASSUM(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN +let lvs = + ["resx",[`X17`;`0`]; + "xn",[`SP`;`128`]; + "zn",[`SP`;`160`]];; - (*** The initial modular reduction of the high part ***) +(* ------------------------------------------------------------------------- *) +(* Additional definitions, lemmas and tactics to support spec and/or proofs. *) +(* ------------------------------------------------------------------------- *) - SUBGOAL_THEN - `(2 EXP 256 * h + l) MOD p_25519 = (38 * h + l) MOD p_25519` - SUBST1_TAC THENL - [ONCE_REWRITE_TAC[GSYM MOD_ADD_MOD] THEN - ONCE_REWRITE_TAC[GSYM MOD_MULT_LMOD] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV; - ALL_TAC] THEN +let SWAR_ADD_LEMMA = prove + (`!(h1:int32) (l1:int32) h2 l2. + val l1 + val l2 < 2 EXP 32 + ==> word_add (word_join h1 l1) (word_join h2 l2):int64 = + word_join (word_add h1 h2) (word_add l1 l2)`, + REPEAT STRIP_TAC THEN + REWRITE_TAC[GSYM VAL_EQ; VAL_WORD_JOIN; VAL_WORD_ADD] THEN + CONV_TAC MOD_DOWN_CONV THEN REWRITE_TAC[DIMINDEX_32; DIMINDEX_64] THEN + ASM_SIMP_TAC[MOD_LT; ARITH_RULE + `(e * x1 + y1) + e * x2 + y2:num = e * (x1 + x2) + (y1 + y2)`] THEN + REWRITE_TAC[GSYM CONG; ARITH_RULE `2 EXP 64 = 2 EXP 32 * 2 EXP 32`] THEN + MATCH_MP_TAC(NUMBER_RULE + `(x':num == x) (mod e) ==> (e * x + l == e * x' + l) (mod (e * e))`) THEN + REWRITE_TAC[CONG_LMOD; CONG_REFL]);; + +let SWAR_SUB_LEMMA = prove + (`!(h1:int32) (l1:int32) h2 l2. + val l2 <= val l1 + ==> word_sub (word_join h1 l1) (word_join h2 l2):int64 = + word_join (word_sub h1 h2) (word_sub l1 l2)`, + REPEAT STRIP_TAC THEN + REWRITE_TAC[WORD_RULE `word_sub x y = z <=> word_add y z = x`] THEN + W(MP_TAC o PART_MATCH (lhand o rand) SWAR_ADD_LEMMA o lhand o snd) THEN + ANTS_TAC THENL + [POP_ASSUM MP_TAC THEN REWRITE_TAC[GSYM DIMINDEX_32] THEN WORD_ARITH_TAC; + DISCH_THEN SUBST1_TAC THEN BINOP_TAC THEN CONV_TAC WORD_RULE]);; + +let WORD_SUBWORD_SWAR_0_32 = prove + (`(!x y. word_subword (word_add x y:int64) (0,32):int32 = + word_add (word_subword x (0,32)) (word_subword y (0,32))) /\ + (!x y. word_subword (word_sub x y:int64) (0,32):int32 = + word_sub (word_subword x (0,32)) (word_subword y (0,32)))`, + REPEAT STRIP_TAC THEN + REWRITE_TAC[GSYM VAL_EQ; VAL_WORD_SUBWORD; INT_VAL_WORD_SUB; VAL_WORD_ADD; + GSYM INT_OF_NUM_CLAUSES; EXP; DIV_1; DIMINDEX_32; DIMINDEX_64; + GSYM INT_OF_NUM_REM; INT_REM_REM_POW_MIN] THEN + CONV_TAC NUM_REDUCE_CONV THEN CONV_TAC INT_REM_DOWN_CONV THEN + REWRITE_TAC[]);; + +let WORD_SUBWORD_SWAR_32_32 = prove + (`(!x y. val(word_subword x (0,32):int32) + val(word_subword y (0,32):int32) + < 2 EXP 32 + ==> word_subword (word_add x y:int64) (32,32):int32 = + word_add (word_subword x (32,32)) (word_subword y (32,32))) /\ + (!x y. val(word_subword y (0,32):int32) <= val(word_subword x (0,32):int32) + ==> word_subword (word_sub x y:int64) (32,32):int32 = + word_sub (word_subword x (32,32)) (word_subword y (32,32)))`, + CONJ_TAC THEN MESON_TAC[SWAR_ADD_LEMMA; SWAR_SUB_LEMMA; WORD_BLAST + `(word_join:int32->int32->int64) + (word_subword x (32,32)) (word_subword x (0,32)) = x /\ + word_subword((word_join:int32->int32->int64) h l) (0,32) = l /\ + word_subword((word_join:int32->int32->int64) h l) (32,32) = h`]);; + +let SIMD_SPLIT_JOIN_CLAUSES = prove + (`(!x. word_subword (word_subword (x:int128) (0,64):int64) (0,32):int32 = + word_subword (x:int128) (0,32)) /\ + (!x. word_subword (word_subword (x:int128) (0,64):int64) (32,32):int32 = + word_subword (x:int128) (32,32)) /\ + (!x. word_subword (word_subword (x:int128) (0,64):int128) (0,32):int32 = + word_subword (x:int128) (0,32)) /\ + (!x. word_subword (word_subword (x:int128) (0,64):int128) (32,32):int32 = + word_subword (x:int128) (32,32)) /\ + (!x. word_subword ((word_zx:int64->int128) x) (0,32):int32 = + word_subword x (0,32)) /\ + (!x. word_subword ((word_zx:int64->int128) x) (32,32):int32 = + word_subword x (32,32)) /\ + (!x y. word_subword ((word_join:int32->int32->int64) x y) (0,32) = y) /\ + (!x y. word_subword ((word_join:int32->int32->int64) x y) (32,32) = x) /\ + (!x y. word_subword ((word_join:int64->int64->int128) x y) (0,64) = y) /\ + (!x y. word_subword ((word_join:int64->int64->int128) x y) (64,64) = x) /\ + (!x. word_zx (word_subword (x:int128) (0,64):int64):int32 = + word_subword x (0,32)) /\ + (!x. word_ushr (word_subword (x:int128) (0,64):int64) 32 = + word_subword x (32,32)) /\ + (!x. word_zx (word_subword (x:int128) (32,32):int64):int32 = + word_subword x (32,32))`, + CONV_TAC WORD_BLAST);; + +let EXTRA_SPLIT_JOIN_CLAUSES = prove + (`(!x y. word_subword (word_join (x:int64) (y:int64):int128) (32,32):int32 = + word_subword y (32,32)) /\ + (!x y. word_subword (word_join (x:int64) (y:int64):int128) (0,32):int32 = + word_subword y (0,32)) /\ + (!x y. word_subword (word_join (x:int32) (y:int32):int64) (0,32) = y) /\ + (!x y. word_subword (word_join (x:int32) (y:int32):int64) (32,32) = x) /\ + (!x. word_subword (x:int128) (0,128) = x) /\ + (!x. word_subword (x:int64) (0,64) = x) /\ + (!x. word_subword (x:int32) (0,32) = x) /\ + (!(x:int128) y. + word_insert x (0,64) + (word_subword (y:int128) (64,64):int128):int128 = + word_join (word_subword x (64,64):int64) + (word_subword y (64,64):int64)) /\ + (!(x:int128) (y:int64). + word_insert x (32,32) (word_zx y:int32):int128 = + word_join (word_subword x (64,64):int64) + (word_join (word_subword y (0,32):int32) + (word_subword x (0,32):int32):int64)) /\ + (!(x:int128) (y:int64). + word_insert x (0,32) (word_zx y:int32):int128 = + word_join (word_subword x (64,64):int64) + (word_join (word_subword x (32,32):int32) + (word_subword y (0,32):int32):int64)) /\ + (!x:int64. word_subword (word_ushr x 32) (0,32):int32 = + word_subword x (32,32))`, + CONV_TAC WORD_BLAST);; + +let UBIGNUM_PACK_UNPACK_CLAUSES = prove + (`(word_subword:int64->num#num->int32) + (word_insert (word_and l (word 0x3ffffff:int64)) (32,26) (h:int64)) + (0,32) = + word(val l MOD 2 EXP 26) /\ + (word_subword:int64->num#num->int32) + (word_insert (word_and l (word 0x3ffffff:int64)) (32,26) (h:int64)) + (32,32) = + word(val h MOD 2 EXP 26) /\ + (word_subword:int64->num#num->int32) + (word_insert (word_and l (word 0x3ffffff:int64)) (32,25) (h:int64)) + (0,32) = + word(val l MOD 2 EXP 26) /\ + (word_subword:int64->num#num->int32) + (word_insert (word_and l (word 0x3ffffff:int64)) (32,25) (h:int64)) + (32,32) = + word(val h MOD 2 EXP 25)`, + CONV_TAC WORD_BLAST);; + +let SIMD_MASK_CLAUSES = + ((fun th -> CONJ th (ONCE_REWRITE_RULE[WORD_AND_SYM] th)) o prove) + (`(!(x:int64) (y:int64). + word_subword (word_and (word 0x1ffffff0000000001ffffff:int128) + (word_join x y)) (0,64) = + word_and (word 0x1ffffff) y) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0x1ffffff0000000001ffffff:int128) + (word_join x y)) (64,64) = + word_and (word 0x1ffffff) x) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0x3ffffff0000000003ffffff:int128) + (word_join x y)) (0,64) = + word_and (word 0x3ffffff) y) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0x3ffffff0000000003ffffff:int128) + (word_join x y)) (64,64) = + word_and (word 0x3ffffff) x) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0xfffffffffe000000fffffffffe000000:int128) + (word_join x y)) (0,64) = + word_and (word 0xfffffffffe000000) y) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0xfffffffffe000000fffffffffe000000:int128) + (word_join x y)) (64,64) = + word_and (word 0xfffffffffe000000) x) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0xfffffffffc000000fffffffffc000000:int128) + (word_join x y)) (0,64) = + word_and (word 0xfffffffffc000000) y) /\ + (!(x:int64) (y:int64). + word_subword (word_and (word 0xfffffffffc000000fffffffffc000000:int128) + (word_join x y)) (64,64) = + word_and (word 0xfffffffffc000000) x)`, + CONV_TAC WORD_BLAST);; + +let is_readcomponent tm = + match tm with + Comb(Comb(Const("read",_),c),s) -> true + | _ -> false;; + +let get_readcomponents = + sort (<) o find_terms is_readcomponent;; + +let rec process env tms = + match tms with + tm::otms -> + let lv,rt = dest_eq tm in + let nm = fst(dest_var lv) in + let rcs = get_readcomponents(subst env rt) in + let ixs = 0--(length rcs-1) in + let nenv = + map2 (fun rc i -> mk_var(nm^"_"^string_of_int i,type_of rc),rc) + rcs ixs in + process (nenv @ env) otms + | [] -> env;; + +let distinguished_components = process [] named_variables;; + +let abbreviated_variables = + map (subst distinguished_components) named_variables;; + +let ABBREVIATE_STATE_COMPONENTS_TAC = + let armstate_ty = `:armstate` in + fun n -> + let sv = mk_var("s"^string_of_int n,armstate_ty) in + let this = filter (fun (v,t) -> rand t = sv) distinguished_components in + MAP_EVERY (fun (v,sc) -> REABBREV_TAC(mk_eq(v,sc))) this;; + +let ARM_NAMESTEPS_TAC execth = + MAP_EVERY (fun n -> + ARM_STEPS_TAC execth [n] THEN + RULE_ASSUM_TAC(REWRITE_RULE[SIMD_SPLIT_JOIN_CLAUSES; + EXTRA_SPLIT_JOIN_CLAUSES]) THEN + ABBREVIATE_STATE_COMPONENTS_TAC n);; + +let find_abbrev s = + let mfn tm = + match tm with + Comb(Comb(Const("=",_),_),Var(s',_)) -> s' = s + | _ -> false in + fun (asl,w) -> find mfn (map (concl o snd) asl);; + +let USE_ABBREV cont s (asl,w) = cont (find_abbrev s (asl,w)) (asl,w);; + +let STANDARDIZE_INEQ = + let lemma = prove + (`x:num < y ==> &x:real <= &y - &1`, + REWRITE_TAC[REAL_LE_SUB_LADD; REAL_OF_NUM_CLAUSES] THEN ARITH_TAC) in + let rule0 = CONV_RULE (RAND_CONV REAL_INT_SUB_CONV) o MATCH_MP lemma + and rule1 = + CONV_RULE (RAND_CONV(NUM_REDUCE_CONV THENC REAL_INT_SUB_CONV)) o + MATCH_MP lemma + and rule2 = GEN_REWRITE_RULE I [GSYM REAL_OF_NUM_LE] + and rule3 = MATCH_MP REAL_LT_IMP_LE + and rule4 = MATCH_MP(TAUT `x:real <= y ==> x <= y`) in + fun th -> + let th' = tryfind (fun r -> r th) [rule0;rule1;rule2;rule3;rule4] in + if is_ratconst(rand(concl th')) then th' + else failwith "STANDARDIZE_INEQ";; + +let BOUND_ABBREV_THEN cont th (asl,w) = + let th1 = AP_TERM `real_of_int` (AP_TERM `int_of_num` + (GEN_REWRITE_RULE I [GSYM VAL_EQ] th)) in + let th2 = GEN_REWRITE_RULE (LAND_CONV o TOP_DEPTH_CONV) + [GSYM INT_OF_NUM_CLAUSES; INT_VAL_WORD_SUB; + VAL_WORD; VAL_WORD_ADD; VAL_WORD_MUL; VAL_WORD_ZX_GEN; VAL_WORD_SHL; + VAL_WORD_USHR; GSYM INT_OF_NUM_DIV; GSYM INT_OF_NUM_REM] th1 in + let th3 = CONV_RULE(INT_REM_DOWN_CONV THENC + ONCE_DEPTH_CONV(!word_SIZE_CONV)) th2 in + let th4 = BOUNDER_RULE (mapfilter (STANDARDIZE_INEQ o snd) asl) + (lhand(concl th3)) in + let th5 = GEN_REWRITE_RULE LAND_CONV [th3] (CONJUNCT2 th4) in + let th6 = GEN_REWRITE_RULE LAND_CONV [int_of_num_th] th5 in + let th7 = GEN_REWRITE_RULE I [REAL_OF_NUM_LE] th6 in + cont th7 (asl,w);; + +let (DEDUCE_DIGITBOUNDS_TAC:thm list->string->tactic) = + let is_localdef s tm = + match tm with + Comb(Comb(Const("=",_),Comb(Const("ubignum_of_list",_),l)), + Var(s',Tyapp("num",[]))) -> s' = s + | _ -> false + and is_remmy = can (term_match [] `x rem p`) + and ic_tm = `int_of_num` + and ri_tm = `real_of_int` + and yemma = prove + (`&x = i rem p /\ + real_of_int i = r /\ + a <= r /\ r <= &b + ==> &0 <= a ==> x <= b`, + REPEAT STRIP_TAC THEN ASM_REWRITE_TAC[GSYM INT_OF_NUM_LE] THEN + TRANS_TAC INT_LE_TRANS `i:int` THEN CONJ_TAC THENL + [REWRITE_TAC[INT_REM_LE_EQ]; ALL_TAC] THEN + ASM_REWRITE_TAC[GSYM REAL_OF_INT_CLAUSES] THEN ASM_REAL_ARITH_TAC) + and nemma = prove + (`&x = i /\ + real_of_int i = r /\ + a <= r /\ r <= &b + ==> x <= b`, + REPEAT STRIP_TAC THEN ASM_REWRITE_TAC[GSYM INT_OF_NUM_LE] THEN + ASM_REWRITE_TAC[GSYM REAL_OF_INT_CLAUSES]) in + fun ths s (asl,w) -> + let sdef = concl(snd(find (is_localdef s o concl o snd) asl)) + and bths = mapfilter (STANDARDIZE_INEQ o snd) asl + and EXPANSION_RULE v = + SYM(snd(find (fun (_,th) -> let t = concl th in is_eq t && rand t = v) + asl)) in + let FINDBOUND conv tm = + let th = + (conv THENC + REWRITE_CONV[COND_RAND; COND_RATOR] THENC + REWRITE_CONV[SIMD_SPLIT_JOIN_CLAUSES; SIMD_MASK_CLAUSES; + EXTRA_SPLIT_JOIN_CLAUSES; UBIGNUM_PACK_UNPACK_CLAUSES] THENC + SUBS_CONV ths THENC + REWRITE_CONV[GSYM INT_OF_NUM_CLAUSES; INT_VAL_WORD_SUB; + VAL_WORD; VAL_WORD_ADD; VAL_WORD_MUL; VAL_WORD_ZX_GEN; + VAL_WORD_SHL; VAL_WORD_USHR; + GSYM INT_OF_NUM_DIV; GSYM INT_OF_NUM_REM] THENC + INT_REM_DOWN_CONV THENC + ONCE_DEPTH_CONV(!word_SIZE_CONV)) + (mk_comb(ic_tm,tm)) in + let etm = rand(concl th) in + let itm = if is_remmy etm then lhand etm else etm in + let ith = REWRITE_CONV [COND_RAND; COND_RATOR; GSYM REAL_OF_INT_CLAUSES] + (mk_comb(ri_tm,itm)) in + let bth = BOUNDER_RULE bths (rand(concl ith)) in + if is_remmy etm then + let lth = MATCH_MP yemma (CONJ th (CONJ ith bth)) in + MP lth (EQT_ELIM(REAL_RAT_REDUCE_CONV(lhand(concl lth)))) + else + MATCH_MP nemma (CONJ th (CONJ ith bth)) in + let eqs = mapfilter EXPANSION_RULE (frees(rand(lhand sdef))) in + let conv = PURE_REWRITE_CONV eqs in + MAP_EVERY (ASSUME_TAC o FINDBOUND conv) + (dest_list(rand(lhand sdef))) (asl,w);; + +let GEN_DEMODULATE_TAC pats = + let moks = map (can o term_match []) pats in + let patx tm = exists (fun f -> f tm) moks in + fun (asl,w) -> + let tms = sort free_in (find_terms patx w) in + MAP_FIRST (fun t -> + MP_TAC(PART_MATCH (lhand o rand) MOD_LT t) THEN ANTS_TAC THENL + [ASM BOUNDER_TAC[]; DISCH_THEN SUBST1_TAC]) tms (asl,w);; + +let DEMODULATE_TAC = GEN_DEMODULATE_TAC [`x MOD 2 EXP 32`; `x MOD 2 EXP 64`];; + +let FULL_DEMODULATE_TAC = GEN_DEMODULATE_TAC [`x MOD 2 EXP n`];; + +let GEN_DEREMULATE_TAC pats = + let moks = map (can o term_match []) pats in + let patx tm = exists (fun f -> f tm) moks in + fun (asl,w) -> + let tms = sort free_in (find_terms patx w) in + MAP_FIRST (fun t -> + MP_TAC(PART_MATCH (lhand o rand) INT_REM_LT t) THEN ANTS_TAC THENL + [CONJ_TAC THENL [DISCH_THEN(K ALL_TAC); ALL_TAC] THEN ASM BOUNDER_TAC[]; + DISCH_THEN SUBST1_TAC]) tms (asl,w);; + +let DEREMULATE_TAC = GEN_DEREMULATE_TAC [`x rem &2 pow 32`; `x rem &2 pow 64`];; + +let FULL_DEREMULATE_TAC = GEN_DEREMULATE_TAC [`x rem &2 pow n`];; + +let FULLEXPAND_TAC names = + REPEAT(W(fun (asl,w) -> + let names' = intersect names (map name_of (frees(lhand(rator w)))) in + if names' <> [] then MAP_EVERY EXPAND_TAC names' + else failwith "FULLEXPAND_TAC: expansion over"));; + +let ARITHBLOCK_TAC = + let word_simps = + ((fun th -> CONJ th (ONCE_REWRITE_RULE[WORD_AND_SYM] th)) o WORD_BLAST) + `val(word_and x (word 0x1FFFFFF):int64) = val x MOD 2 EXP 25 /\ + val(word_and x (word 0x3FFFFFF):int64) = val x MOD 2 EXP 26 /\ + val(word_and x (word 0xfffffffffc000000):int64) = + 2 EXP 26 * val x DIV 2 EXP 26 /\ + val(word_and x (word 0xfffffffffe000000):int64) = + 2 EXP 25 * val x DIV 2 EXP 25` + and muldiv_simps = prove + (`(&2 pow 25 * x) div &2 pow 25 = x /\ + (&2 pow 26 * x) div &2 pow 26 = x /\ + (&2 pow 26 * x) div &2 pow 25 = &2 * x /\ + (&2 pow 26 * x) div &2 pow 22 = &16 * x /\ + (&2 pow 25 * x) div &2 pow 24 = &2 * x /\ + (&2 pow 25 * x) div &2 pow 21 = &16 * x`, + REPEAT CONJ_TAC THEN INT_ARITH_TAC) in + fun ths -> + W(MAP_EVERY (EXPAND_TAC o name_of) o frees o snd) THEN + W(FULLEXPAND_TAC o map name_of o frees o lhand o rator o snd) THEN + REWRITE_TAC[ubignum_of_list; SIMD_SPLIT_JOIN_CLAUSES; SIMD_MASK_CLAUSES; + EXTRA_SPLIT_JOIN_CLAUSES; UBIGNUM_PACK_UNPACK_CLAUSES] THEN + CONV_TAC(SUBS_CONV ths) THEN + REWRITE_TAC[word_simps; GSYM INT_OF_NUM_CLAUSES; + GSYM INT_OF_NUM_DIV; GSYM INT_OF_NUM_REM; + VAL_WORD; VAL_WORD_ADD; VAL_WORD_MUL; INT_VAL_WORD_SUB; + VAL_WORD_ZX_GEN; VAL_WORD_SHL; VAL_WORD_USHR] THEN + CONV_TAC(ONCE_DEPTH_CONV(!word_SIZE_CONV)) THEN + CONV_TAC INT_REM_DOWN_CONV THEN REPEAT DEREMULATE_TAC THEN + REWRITE_TAC[muldiv_simps] THEN + TRY FULL_DEREMULATE_TAC THEN POP_ASSUM_LIST(K ALL_TAC) THEN + REPEAT(W(fun (asl,w) -> + let dmotms = + find_terms (can (term_match [] `m div n`)) w @ + find_terms (can (term_match [] `m rem n`)) w in + let tm = hd(sort free_in dmotms) in + let th1 = SPECL [lhand tm; rand tm] INT_DIVISION_SIMP in + let qtm = lhand(lhand(lhand(concl th1))) + and rtm = rand(lhand(concl th1)) in + MP_TAC th1 THEN + ABBREV_TAC(mk_eq(genvar(type_of qtm),qtm)) THEN + ABBREV_TAC(mk_eq(genvar(type_of rtm),rtm)) THEN + POP_ASSUM(K ALL_TAC) THEN POP_ASSUM(K ALL_TAC) THEN DISCH_TAC)) THEN + REPEAT(FIRST_X_ASSUM(SUBST_ALL_TAC o MATCH_MP (INT_ARITH + `n * q + r:int = x ==> r = x - n * q`))) THEN + REWRITE_TAC[REAL_INT_CONGRUENCE; INT_OF_NUM_EQ; p_25519; ARITH_EQ] THEN + REWRITE_TAC[GSYM REAL_OF_INT_CLAUSES] THEN REAL_INTEGER_TAC;; + +let extra = prove + (`(word_zx:int64->int32) (word_add x x) = + word_zx (word_mul (word 2:int32) (word_zx x))`, + REWRITE_TAC[GSYM VAL_EQ; VAL_WORD_ZX_GEN; VAL_WORD_ADD; VAL_WORD_MUL] THEN + CONV_TAC MOD_DOWN_CONV THEN REWRITE_TAC[DIMINDEX_32; DIMINDEX_64] THEN + REWRITE_TAC[MOD_MOD_EXP_MIN; ARITH_RULE `MIN 64 32 = 32`] THEN + AP_THM_TAC THEN AP_TERM_TAC THEN CONV_TAC WORD_REDUCE_CONV THEN + ARITH_TAC);; - (*** Instantiate the quotient approximation lemma ***) +(* ------------------------------------------------------------------------- *) +(* Lemmas and tactics for the inlined field multiplication proof. *) +(* ------------------------------------------------------------------------- *) - MP_TAC(SPECL [`h:num`; `l:num`] p25519redlemma32) THEN ANTS_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - LET_TAC THEN STRIP_TAC] THEN +let lemma0 = prove + (`!x0 x1:int64. + &(val(if val x0 <= val x1 then word_sub x1 x0 + else word_neg(word_sub x1 x0))):real = abs(&(val x1) - &(val x0))`, + REPEAT GEN_TAC THEN REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN + REWRITE_TAC[WORD_NEG_SUB; REAL_ARITH + `abs(x - y):real = if y <= x then x - y else y - x`] THEN + COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN + RULE_ASSUM_TAC(REWRITE_RULE[REAL_OF_NUM_CLAUSES; NOT_LE]) THEN + ASM_SIMP_TAC[VAL_WORD_SUB_CASES; LT_IMP_LE; REAL_OF_NUM_SUB]);; - (*** The somewhat fiddly reduction with 32-bit operations etc. ***) +let lemma1 = prove + (`!(x0:num) x1 (y0:num) y1. + (if y0 <= y1 + then if x1 <= x0 then word 0 else word 18446744073709551615 + else word_not + (if x1 <= x0 then word 0 else word 18446744073709551615)):int64 = + word_neg(word(bitval(y0 <= y1 <=> x0 < x1)))`, + REPEAT GEN_TAC THEN REWRITE_TAC[GSYM NOT_LE] THEN + REPEAT(COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES]) THEN + CONV_TAC WORD_REDUCE_CONV);; - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (113--137) THEN +let lemma2 = prove + (`!p x0 x1 y0 y1:real. + (x0 + p * x1) * (y0 + p * y1) = + x0 * y0 + p pow 2 * x1 * y1 + + p * (x0 * y0 + x1 * y1 + + --(&1) pow bitval(y1 <= y0 <=> x1 < x0) * + abs(x1 - x0) * abs(y0 - y1))`, + REPEAT GEN_TAC THEN + MAP_EVERY ASM_CASES_TAC [`y1:real <= y0`; `x1:real < x0`] THEN + ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN ASM_REAL_ARITH_TAC);; - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM MP_TAC) - [`u0 = read X7 s137`; - `u1 = read X8 s137`; - `u2 = read X9 s137`; - `u3 = read X10 s137`; - `u4 = read X11 s137`; - `u5 = read X12 s137`; - `u6 = read X13 s137`; - `u7 = read X14 s137`] THEN - REWRITE_TAC[GSYM IMP_CONJ_ALT] THEN - GEN_REWRITE_TAC (LAND_CONV o TOP_DEPTH_CONV) - [word_add; modular; ADD_CLAUSES; VAL_WORD; VAL_WORD_ZX_GEN; - VAL_WORD_USHR; DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN] THEN - REWRITE_TAC[DIV_MOD; GSYM EXP_ADD] THEN - CONV_TAC(DEPTH_CONV NUM_ADD_CONV) THEN - CONV_TAC(DEPTH_CONV NUM_MIN_CONV) THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `n < 2 EXP 64 ==> n MOD 2 EXP 32 * 38 < 2 EXP 64`] THEN - STRIP_TAC THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC [142;144;146;150] (138--150) THEN - SUBGOAL_THEN `word_ushr u7 31:int64 = word q` SUBST_ALL_TAC THENL - [REWRITE_TAC[GSYM VAL_EQ; VAL_WORD; VAL_WORD_USHR] THEN - ASM_SIMP_TAC[DIMINDEX_64; MOD_LT] THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s106:int64) DIV 2 EXP 32 + - val(sum_s112:int64) DIV 2 EXP 32 * 38):int64 = u7`)) THEN - MAP_EVERY EXPAND_TAC ["q"; "l"; "h"] THEN - REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[VAL_WORD; ARITH_RULE `a + b * 38 = 38 * b + a`] THEN - MATCH_MP_TAC MOD_LT THEN REWRITE_TAC[DIMINDEX_64] THEN - REWRITE_TAC[GSYM VAL_WORD_USHR] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - ALL_TAC] THEN - SUBGOAL_THEN - `&(val(word_add (u0:int64) - (word(19 + 19 * val((word_zx:int64->int32)(word q)))))):real = - &(val u0) + &19 * (&q + &1)` - SUBST_ALL_TAC THENL - [REWRITE_TAC[REAL_OF_NUM_CLAUSES; VAL_WORD_ADD; VAL_WORD; VAL_WORD_ZX_GEN; - DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN] THEN - ASM_SIMP_TAC[ARITH_RULE `q <= 77 ==> q < 2 EXP MIN 64 32`; MOD_LT] THEN - CONV_TAC MOD_DOWN_CONV THEN - REWRITE_TAC[ARITH_RULE `19 + 19 * q = 19 * (q + 1)`] THEN - MATCH_MP_TAC MOD_LT THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s108:int64) MOD 2 EXP 32 * 38 + - val(mullo_s3:int64) MOD 2 EXP 32):int64 = u0`)) THEN - MATCH_MP_TAC(ARITH_RULE - `w <= 2 EXP 63 /\ q <= 77 ==> w + 19 * (q + 1) < 2 EXP 64`) THEN - CONJ_TAC THENL [MATCH_MP_TAC VAL_WORD_LE; FIRST_ASSUM ACCEPT_TAC] THEN - ARITH_TAC; - ALL_TAC] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - REWRITE_TAC[REAL_VAL_WORD_XOR; WORD_AND_POW2_BITVAL; - REWRITE_RULE[DIMINDEX_64; NUM_REDUCE_CONV `64 - 1`] - (ISPEC `x:int64` WORD_SHL_LSB)] THEN - REWRITE_TAC[VAL_WORD; DIMINDEX_64; DIVMOD_63_64] THEN - SIMP_TAC[MOD_LT; BITVAL_BOUND_ALT; GSYM REAL_OF_NUM_CLAUSES] THEN - ASM_SIMP_TAC[GSYM VAL_MOD_2; VAL_WORD; DIMINDEX_64; MOD_LT] THEN - STRIP_TAC THEN - ABBREV_TAC - `r = bignum_of_wordlist[sum_s142; sum_s144; sum_s146; sum_s150]` THEN +let VAL_WORD_MADDL_0 = prove + (`!x y. val(word(0 + val(x:int32) * val(y:int32)):int64) = val x * val y`, + REPEAT GEN_TAC THEN REWRITE_TAC[ADD_CLAUSES; VAL_WORD_EQ_EQ] THEN + REWRITE_TAC[DIMINDEX_64; ARITH_RULE `2 EXP 64 = 2 EXP 32 * 2 EXP 32`] THEN + MATCH_MP_TAC LT_MULT2 THEN REWRITE_TAC[GSYM DIMINDEX_32; VAL_BOUND]);; - SUBGOAL_THEN - `(&r:int == &2 pow 255 + &(38 * h + l) - (&q + &1) * &p_25519) - (mod (&2 pow 256))` - ASSUME_TAC THENL - [SUBGOAL_THEN - `38 * h + l = - bignum_of_wordlist[u0;u1;u2;u3] + - 2 EXP 32 * bignum_of_wordlist[u4;u5;u6;u7]` - SUBST1_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o - check (can (term_match [] `word x = n`) o concl))) THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD; DIMINDEX_64] THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `m < 2 EXP 64 /\ n < 2 EXP 64 - ==> m DIV 2 EXP 32 + n DIV 2 EXP 32 * 38 < 2 EXP 64`; - ARITH_RULE `m MOD 2 EXP 32 * 38 + n MOD 2 EXP 32 < 2 EXP 64`] THEN - ARITH_TAC; - ALL_TAC] THEN - SUBGOAL_THEN - `2 EXP 32 * bignum_of_wordlist [u4; u5; u6; u7] = - bignum_of_wordlist - [word_shl u4 32; - word_subword ((word_join:int64->int64->int128) u5 u4) (32,64); - word_subword ((word_join:int64->int64->int128) u6 u5) (32,64); - word_subword ((word_join:int64->int64->int128) u7 u6) (32,64); - word_ushr u7 32]` - SUBST1_TAC THENL - [REWRITE_TAC[val_def; DIMINDEX_64; bignum_of_wordlist] THEN - REWRITE_TAC[ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN - REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN - REWRITE_TAC[BIT_WORD_JOIN; BIT_WORD_USHR; BIT_WORD_SUBWORD; - BIT_WORD_SHL; DIMINDEX_64; DIMINDEX_128] THEN - CONV_TAC NUM_REDUCE_CONV THEN - CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN - CONV_TAC NUM_REDUCE_CONV THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - ONCE_REWRITE_TAC[BIT_GUARD] THEN REWRITE_TAC[DIMINDEX_64] THEN - CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[BITVAL_CLAUSES] THEN - ARITH_TAC; - ALL_TAC] THEN - SIMP_TAC[REAL_INT_CONGRUENCE; INT_POW_EQ_0; INT_OF_NUM_EQ; ARITH_EQ] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; - int_mul_th; int_pow_th] THEN - EXPAND_TAC "r" THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN +let DIVMOD_32_32 = prove + (`!n. (2 EXP 32 * n) MOD 2 EXP 64 = 2 EXP 32 * n MOD 2 EXP 32`, + REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - (*** The final optional correction ***) +let DIVMOD_33_31 = prove + (`!n. (2 EXP 33 * n) MOD 2 EXP 64 = 2 EXP 33 * n MOD 2 EXP 31`, + REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (154--157) (151--160) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN CONV_TAC SYM_CONV THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_MOD_MOD THEN - MAP_EVERY EXISTS_TAC - [`255`; - `(if r < 2 EXP 255 then &r - &19 else &r - &2 pow 255):real`] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN - ASM_REWRITE_TAC[] THEN DISCARD_STATE_TAC "s160" THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC]) THEN - CONJ_TAC THENL - [REWRITE_TAC[ARITH_RULE `r < 2 EXP 255 <=> r DIV 2 EXP 192 < 2 EXP 63`] THEN - EXPAND_TAC "r" THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - REWRITE_TAC[SYM(NUM_REDUCE_CONV `2 EXP 63 - 1`)] THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD_AND_MASK_WORD] THEN - ABBREV_TAC `bb <=> val(sum_s150:int64) < 2 EXP 63` THEN - SUBGOAL_THEN - `ival(word_and sum_s150 (word 9223372036854775808):int64) < &0 <=> ~bb` - SUBST_ALL_TAC THENL - [REWRITE_TAC[GSYM MSB_IVAL; BIT_WORD_AND] THEN - REWRITE_TAC[MSB_VAL] THEN REWRITE_TAC[DIMINDEX_64] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - EXPAND_TAC "bb" THEN ARITH_TAC; - RULE_ASSUM_TAC(REWRITE_RULE[]) THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC]; - FIRST_ASSUM(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ] - endp25519redlemma)) THEN - ANTS_TAC THENL - [REWRITE_TAC[INT_ARITH `--p:int <= x - y <=> y <= x + p`] THEN - REWRITE_TAC[INT_ARITH `x - y:int < p <=> x < y + p`] THEN - ASM_REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN - EXPAND_TAC "r" THEN BOUNDER_TAC[]; - REWRITE_TAC[INT_ARITH `x - q * p:int = --q * p + x`] THEN - REWRITE_TAC[INT_REM_MUL_ADD] THEN - REWRITE_TAC[int_eq; int_of_num_th; INT_OF_NUM_REM] THEN - DISCH_THEN SUBST1_TAC THEN COND_CASES_TAC THEN - ASM_REWRITE_TAC[int_of_num_th; int_sub_th; int_pow_th]]]);; +let DIVMOD_63_64 = prove + (`!n. (2 EXP 63 * n) MOD 2 EXP 64 = 2 EXP 63 * n MOD 2`, + REWRITE_TAC[GSYM MOD_MULT2] THEN ARITH_TAC);; + +let VAL_WORD_SPLIT32 = prove + (`!x. 2 EXP 32 * val(word_zx(word_ushr x 32):int32) + val(word_zx x:int32) = + val(x:int64)`, + REWRITE_TAC[VAL_WORD_USHR; VAL_WORD_ZX_GEN; DIMINDEX_32] THEN + GEN_TAC THEN REWRITE_TAC[GSYM MOD_MULT_MOD; GSYM EXP_ADD] THEN + CONV_TAC(ONCE_DEPTH_CONV NUM_ADD_CONV) THEN + MATCH_MP_TAC MOD_LT THEN REWRITE_TAC[VAL_BOUND_64]);; + +let p25519redlemma32 = prove + (`!h l. h < 2 EXP 256 /\ l < 2 EXP 256 + ==> let q = (38 * h DIV 2 EXP 224 + l DIV 2 EXP 224) DIV 2 EXP 31 in + q <= 77 /\ + q < 2 EXP 64 /\ + (q + 1) * p_25519 <= (38 * h + l) + p_25519 /\ + 38 * h + l < (q + 1) * p_25519 + p_25519`, + CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN + REWRITE_TAC[p_25519] THEN ARITH_TAC);; + +let endp25519redlemma = prove + (`(&z == &2 pow 255 + x) (mod (&2 pow 256)) /\ + --(&p_25519) <= x /\ x < &p_25519 /\ z < 2 EXP 256 + ==> x rem &p_25519 = + if z < 2 EXP 255 then &z - &19 else &z - &2 pow 255`, + REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN REPEAT STRIP_TAC THEN + SUBGOAL_THEN `&z:int < &2 pow 255 <=> x:int < &0` SUBST1_TAC THENL + [ALL_TAC; + COND_CASES_TAC THEN MATCH_MP_TAC INT_REM_UNIQ THENL + [EXISTS_TAC `--(&1):int`; EXISTS_TAC `&0:int`]] THEN + FIRST_X_ASSUM(MP_TAC o MATCH_MP + (REWRITE_RULE[IMP_CONJ_ALT] INT_CONG_IMP_EQ)) THEN + REWRITE_TAC[p_25519] THEN + RULE_ASSUM_TAC(REWRITE_RULE[p_25519]) THEN ASM_INT_ARITH_TAC);; + +let KARATSUBA12_TAC = + REWRITE_TAC[REAL_MUL_RZERO; REAL_ADD_RID] THEN + MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN + MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN + ASM_REWRITE_TAC[INTEGER_CLOSED] THEN + REPLICATE_TAC 2 (CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC]) THEN + REWRITE_TAC[lemma2; REAL_OF_NUM_LE; REAL_OF_NUM_LT] THEN + ACCUMULATOR_POP_ASSUM_LIST(fun thl -> + MP_TAC(end_itlist CONJ(rev thl)) THEN + REWRITE_TAC[WORD_XOR_MASK] THEN + REWRITE_TAC[REAL_OF_NUM_LT; REAL_OF_NUM_LE; GSYM NOT_LE] THEN + COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN + CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN + REWRITE_TAC[REAL_VAL_WORD_NOT; DIMINDEX_64] THEN + DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN + CONV_TAC(RAND_CONV REAL_POLY_CONV) THEN + REWRITE_TAC(filter(is_ratconst o rand o concl) (DECARRY_RULE thl)) THEN + REAL_INTEGER_TAC);; -(* ------------------------------------------------------------------------- *) -(* Instances of mul_4. *) -(* ------------------------------------------------------------------------- *) +let p25519weakredlemma = prove + (`!n. n <= 2 EXP 62 * 2 EXP 256 + ==> let q = n DIV 2 EXP 255 in + q < 2 EXP 64 /\ + q * p_25519 <= n /\ + n < q * p_25519 + 2 * p_25519`, + CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN REWRITE_TAC[p_25519] THEN ARITH_TAC);; -let LOCAL_MUL_4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_byte_mc 172 lvs +let LOCAL_MUL_P25519_TAC = + ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_byte_mc 180 lvs `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m ==> !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n ==> aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x59e4) (word_add (read p3 t) (word n3),8 * 4) + nonoverlapping (word pc,0x27f8) (word_add (read p3 t) (word n3),8 * 4) ==> ensures arm (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ read PC s = pcin /\ read SP s = read SP t /\ - read X23 s = read X23 t /\ + read X17 s = read X17 t /\ read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s - < 2 * p_25519 /\ - (read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s == - m * n) (mod p_25519)) - (MAYCHANGE [PC; X0; X1; X2; X3; X4; X5; X6; X7; X8; X9; X10; - X11; X12; X13; X14; X15; X16] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` + read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s = + (m * n) MOD p_25519) + (MAYCHANGE [PC; X0; X1; X2; X3; X4; X5; X6; X7; X8; X9; X10; X11; X12; + X13; X14; X15; X16] ,, + MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, + MAYCHANGE SOME_FLAGS)` (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN @@ -6570,453 +3748,102 @@ let LOCAL_MUL_4_TAC = ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN ASM_REWRITE_TAC[WORD_XOR_MASK] THEN REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN - DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** Clean up the overall sign ***) - - FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE RAND_CONV [WORD_XOR_MASKS]) THEN - ASM_REWRITE_TAC[] THEN DISCH_TAC THEN - - (*** The augmented H' = H + L_top ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (69--72) (69--72) THEN - MAP_EVERY ABBREV_TAC - [`q2 = bignum_of_wordlist[sum_s69;sum_s70]`; - `q3 = bignum_of_wordlist[sum_s71;sum_s72]`] THEN - SUBGOAL_THEN - `2 EXP 128 * q3 + q2 = - bignum_of_wordlist [x_2;x_3] * bignum_of_wordlist[y_2;y_3] + q1` - ASSUME_TAC THENL - [MAP_EVERY EXPAND_TAC ["q1"; "q2"; "q3"] THEN - MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN - REPEAT(CONJ_TAC THENL - [CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; ALL_TAC]) THEN - FIRST_X_ASSUM(fun th -> GEN_REWRITE_TAC - (LAND_CONV o LAND_CONV) [SYM th]) THEN - MAP_EVERY EXPAND_TAC ["q23"] THEN - REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ALL_TAC] THEN - - (*** Third nested block multiplying the absolute differences ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [73;75;80;81;85;87;88;89;92;94;95] (73--95) THEN - RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN - SUBGOAL_THEN - `&xd * &yd:real = - &(bignum_of_wordlist[mullo_s73; sum_s92; sum_s94; sum_s95])` - SUBST_ALL_TAC THENL - [MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - KARATSUBA12_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN - DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN - - (*** The rest of the basic 4x4->8 multiply computation and its proof ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [96;97;98;99;100;101;104;106;108;110;111;112] (96--112) THEN - MAP_EVERY ABBREV_TAC - [`l = bignum_of_wordlist[mullo_s3; sum_s22; sum_s104; sum_s106]`; - `h = bignum_of_wordlist[sum_s108; sum_s110; sum_s111; sum_s112]`] THEN - SUBGOAL_THEN `2 EXP 256 * h + l = m * n` (SUBST1_TAC o SYM) THENL - [DISCARD_STATE_TAC "s112" THEN MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`512`; `&0:real`] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL - [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN BOUNDER_TAC[]; - REWRITE_TAC[INTEGER_CLOSED]] THEN - SUBGOAL_THEN - `&m * &n:real = - (&1 + &2 pow 128) * (&q0 + &2 pow 128 * &q2 + &2 pow 256 * &q3) + - &2 pow 128 * - (&(bignum_of_wordlist [x_2; x_3]) - - &(bignum_of_wordlist [x_0; x_1])) * - (&(bignum_of_wordlist [y_0; y_1]) - - &(bignum_of_wordlist [y_2; y_3]))` - SUBST1_TAC THENL - [MAP_EVERY UNDISCH_TAC - [`2 EXP 128 * q1 + q0 = - bignum_of_wordlist[x_0; x_1] * bignum_of_wordlist[y_0; y_1]`; - `2 EXP 128 * q3 + q2 = - bignum_of_wordlist[x_2; x_3] * bignum_of_wordlist[y_2; y_3] + - q1`] THEN - MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - CONV_TAC REAL_RING; - ASM_REWRITE_TAC[]] THEN - MAP_EVERY EXPAND_TAC ["h"; "l"; "q0"; "q2"; "q3"] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - POP_ASSUM_LIST(K ALL_TAC) THEN - REWRITE_TAC[WORD_XOR_MASK] THEN COND_CASES_TAC THEN - ASM_REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN - CONV_TAC WORD_REDUCE_CONV THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[BITVAL_CLAUSES] THEN DISCH_TAC THEN - FIRST_ASSUM(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** The initial modular reduction of the high part ***) - - REWRITE_TAC[CONG] THEN - SUBGOAL_THEN - `(2 EXP 256 * h + l) MOD p_25519 = (38 * h + l) MOD p_25519` - SUBST1_TAC THENL - [ONCE_REWRITE_TAC[GSYM MOD_ADD_MOD] THEN - ONCE_REWRITE_TAC[GSYM MOD_MULT_LMOD] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV; - ALL_TAC] THEN - - (*** Instantiate the quotient approximation lemma ***) - - MP_TAC(SPECL [`h:num`; `l:num`] p25519redlemma32) THEN ANTS_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - LET_TAC THEN STRIP_TAC] THEN - - (*** The somewhat fiddly reduction with 32-bit operations etc. ***) - - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (113--137) THEN - - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM MP_TAC) - [`u0 = read X7 s137`; - `u1 = read X8 s137`; - `u2 = read X9 s137`; - `u3 = read X10 s137`; - `u4 = read X11 s137`; - `u5 = read X12 s137`; - `u6 = read X13 s137`; - `u7 = read X14 s137`] THEN - REWRITE_TAC[GSYM IMP_CONJ_ALT] THEN - GEN_REWRITE_TAC (LAND_CONV o TOP_DEPTH_CONV) - [word_add; modular; ADD_CLAUSES; VAL_WORD; VAL_WORD_ZX_GEN; - VAL_WORD_USHR; DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN] THEN - REWRITE_TAC[DIV_MOD; GSYM EXP_ADD] THEN - CONV_TAC(DEPTH_CONV NUM_ADD_CONV) THEN - CONV_TAC(DEPTH_CONV NUM_MIN_CONV) THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `n < 2 EXP 64 ==> n MOD 2 EXP 32 * 38 < 2 EXP 64`] THEN - STRIP_TAC THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC [142;144;146;150] (138--152) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - - SUBGOAL_THEN `word_ushr u7 31:int64 = word q` SUBST_ALL_TAC THENL - [REWRITE_TAC[GSYM VAL_EQ; VAL_WORD; VAL_WORD_USHR] THEN - ASM_SIMP_TAC[DIMINDEX_64; MOD_LT] THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s106:int64) DIV 2 EXP 32 + - val(sum_s112:int64) DIV 2 EXP 32 * 38):int64 = u7`)) THEN - MAP_EVERY EXPAND_TAC ["q"; "l"; "h"] THEN - REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[VAL_WORD; ARITH_RULE `a + b * 38 = 38 * b + a`] THEN - MATCH_MP_TAC MOD_LT THEN REWRITE_TAC[DIMINDEX_64] THEN - REWRITE_TAC[GSYM VAL_WORD_USHR] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - ALL_TAC] THEN - SUBGOAL_THEN - `&(val(word_add (u0:int64) - (word(0 + 19 * val((word_zx:int64->int32)(word q)))))):real = - &(val u0) + &19 * &q` - SUBST_ALL_TAC THENL - [REWRITE_TAC[REAL_OF_NUM_CLAUSES; VAL_WORD_ADD; VAL_WORD; VAL_WORD_ZX_GEN; - DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN; ADD_CLAUSES] THEN - ASM_SIMP_TAC[ARITH_RULE `q <= 77 ==> q < 2 EXP MIN 64 32`; MOD_LT] THEN - CONV_TAC MOD_DOWN_CONV THEN - MATCH_MP_TAC MOD_LT THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s108:int64) MOD 2 EXP 32 * 38 + - val(mullo_s3:int64) MOD 2 EXP 32):int64 = u0`)) THEN - MATCH_MP_TAC(ARITH_RULE - `w <= 2 EXP 63 /\ q <= 77 ==> w + 19 * q < 2 EXP 64`) THEN - CONJ_TAC THENL [MATCH_MP_TAC VAL_WORD_LE; FIRST_ASSUM ACCEPT_TAC] THEN - ARITH_TAC; - ALL_TAC] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - REWRITE_TAC[REAL_VAL_WORD_XOR; WORD_AND_POW2_BITVAL; - REWRITE_RULE[DIMINDEX_64; NUM_REDUCE_CONV `64 - 1`] - (ISPEC `x:int64` WORD_SHL_LSB)] THEN - REWRITE_TAC[VAL_WORD; DIMINDEX_64; DIVMOD_63_64] THEN - SIMP_TAC[MOD_LT; BITVAL_BOUND_ALT; GSYM REAL_OF_NUM_CLAUSES] THEN - ASM_SIMP_TAC[GSYM VAL_MOD_2; VAL_WORD; DIMINDEX_64; MOD_LT] THEN - STRIP_TAC THEN - - REWRITE_TAC[GSYM CONG; REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[num_congruent; GSYM INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(MESON[] - `!q. (ca - q * p == ca) (mod p) /\ - (&0 <= ca - q * p /\ ca - q * p < p2) /\ - (&0 <= ca - q * p /\ ca - q * p < p2 ==> x = ca - q * p) - ==> x:int < p2 /\ (x == ca) (mod p)`) THEN - EXISTS_TAC `&q:int` THEN - CONJ_TAC THENL [CONV_TAC INTEGER_RULE; ALL_TAC] THEN - CONJ_TAC THENL - [MAP_EVERY UNDISCH_TAC - [`(q + 1) * p_25519 <= (38 * h + l) + p_25519`; - `38 * h + l < (q + 1) * p_25519 + p_25519`] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN INT_ARITH_TAC; - STRIP_TAC] THEN - MATCH_MP_TAC INT_CONG_IMP_EQ THEN EXISTS_TAC `(&2:int) pow 256` THEN - CONJ_TAC THENL - [FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INT_ARITH - `y:int < p ==> &0 <= y /\ &0 <= p /\ p < e /\ &0 <= x /\ x < e - ==> abs(x - y) < e`)) THEN - ASM_REWRITE_TAC[] THEN - REWRITE_TAC[INT_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - ALL_TAC] THEN - - REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN - SUBGOAL_THEN - `38 * h + l = - bignum_of_wordlist[u0;u1;u2;u3] + - 2 EXP 32 * bignum_of_wordlist[u4;u5;u6;u7]` - SUBST1_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o - check (can (term_match [] `word x = n`) o concl))) THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD; DIMINDEX_64] THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `m < 2 EXP 64 /\ n < 2 EXP 64 - ==> m DIV 2 EXP 32 + n DIV 2 EXP 32 * 38 < 2 EXP 64`; - ARITH_RULE `m MOD 2 EXP 32 * 38 + n MOD 2 EXP 32 < 2 EXP 64`] THEN - ARITH_TAC; - ALL_TAC] THEN - SUBGOAL_THEN - `2 EXP 32 * bignum_of_wordlist [u4; u5; u6; u7] = - bignum_of_wordlist - [word_shl u4 32; - word_subword ((word_join:int64->int64->int128) u5 u4) (32,64); - word_subword ((word_join:int64->int64->int128) u6 u5) (32,64); - word_subword ((word_join:int64->int64->int128) u7 u6) (32,64); - word_ushr u7 32]` - SUBST1_TAC THENL - [REWRITE_TAC[val_def; DIMINDEX_64; bignum_of_wordlist] THEN - REWRITE_TAC[ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN - REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN - REWRITE_TAC[BIT_WORD_JOIN; BIT_WORD_USHR; BIT_WORD_SUBWORD; - BIT_WORD_SHL; DIMINDEX_64; DIMINDEX_128] THEN - CONV_TAC NUM_REDUCE_CONV THEN - CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN - CONV_TAC NUM_REDUCE_CONV THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - ONCE_REWRITE_TAC[BIT_GUARD] THEN REWRITE_TAC[DIMINDEX_64] THEN - CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[BITVAL_CLAUSES] THEN - ARITH_TAC; - ALL_TAC] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - SIMP_TAC[REAL_INT_CONGRUENCE; INT_POW_EQ_0; INT_OF_NUM_EQ; ARITH_EQ] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; - int_mul_th; int_pow_th] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of sqr_4. *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_SQR_4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_byte_mc 130 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1. - !n. - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x59e4) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = n) - (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s - < 2 * p_25519 /\ - (read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s == - n EXP 2) - (mod p_25519)) - (MAYCHANGE [PC; X2; X3; X4; X5; X6; X7; X8; X9; - X10; X11; X12; X13; X14; X15; X16] ,, - MAYCHANGE - [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - - (*** The initial squaring block, very similar to bignum_sqr_4_8 ***) - (*** First of all, squaring the lower half ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [7;9;14;16;18;19;20;21;22;23;24] (1--24) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; DIVMOD_33_31; VAL_WORD_USHR; - VAL_WORD_SHL; DIMINDEX_64]) THEN - SUBGOAL_THEN - `bignum_of_wordlist[n_0; n_1] EXP 2 = - bignum_of_wordlist[sum_s7; sum_s22; sum_s23; sum_s24]` - ASSUME_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`n_0:int64`; `n_1:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - RULE_ASSUM_TAC(CONV_RULE NUM_REDUCE_CONV) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_ARITH_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** Squaring the upper half ***) - - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [29;31;36;38;40;41;42;43;44;45;46] (25--46) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; DIVMOD_33_31; VAL_WORD_USHR; - VAL_WORD_SHL; DIMINDEX_64]) THEN - SUBGOAL_THEN - `bignum_of_wordlist[n_2; n_3] EXP 2 = - bignum_of_wordlist[sum_s29; sum_s44; sum_s45; sum_s46]` - ASSUME_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`n_2:int64`; `n_3:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - RULE_ASSUM_TAC(CONV_RULE NUM_REDUCE_CONV) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_ARITH_TAC; + DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - (*** Absolute difference computation ***) + (*** Clean up the overall sign ***) - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC [47;48;51;53] (47--53) THEN - RULE_ASSUM_TAC(REWRITE_RULE[COND_SWAP; WORD_UNMASK_64]) THEN - SUBGOAL_THEN - `abs(&(bignum_of_wordlist[n_0;n_1]) - - &(bignum_of_wordlist[n_2;n_3])):real = - &(bignum_of_wordlist[sum_s51;sum_s53])` - ASSUME_TAC THENL - [MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`128`; `&0:real`] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - BOUNDER_TAC[]; - ALL_TAC]) THEN - CONJ_TAC THENL [REAL_INTEGER_TAC; ALL_TAC] THEN - REWRITE_TAC[real_abs; REAL_SUB_LE; REAL_OF_NUM_LE] THEN - SUBGOAL_THEN - `bignum_of_wordlist [n_2; n_3] <= bignum_of_wordlist [n_0; n_1] <=> - ~carry_s48` - SUBST1_TAC THENL - [REWRITE_TAC[GSYM NOT_LT] THEN AP_TERM_TAC THEN - CONV_TAC SYM_CONV THEN MATCH_MP_TAC FLAG_FROM_CARRY_LT THEN - EXISTS_TAC `128` THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN BOUNDER_TAC[]; - REWRITE_TAC[COND_SWAP] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN - REWRITE_TAC[WORD_XOR_MASK] THEN COND_CASES_TAC THEN - ASM_REWRITE_TAC[BITVAL_CLAUSES; REAL_VAL_WORD_NOT] THEN - REWRITE_TAC[BITVAL_CLAUSES; DIMINDEX_64; VAL_WORD_BITVAL] THEN - DISCH_THEN(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC]; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN + FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE RAND_CONV [WORD_XOR_MASKS]) THEN + ASM_REWRITE_TAC[] THEN DISCH_TAC THEN - (*** The augmented H' = H + L_top computation ***) + (*** The augmented H' = H + L_top ***) - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (54--57) (54--57) THEN + ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (69--72) (69--72) THEN + MAP_EVERY ABBREV_TAC + [`q2 = bignum_of_wordlist[sum_s69;sum_s70]`; + `q3 = bignum_of_wordlist[sum_s71;sum_s72]`] THEN SUBGOAL_THEN - `&(bignum_of_wordlist[sum_s29; sum_s44; sum_s45; sum_s46]):real = - &(bignum_of_wordlist[sum_s54; sum_s55; sum_s56; sum_s57]) - - &(bignum_of_wordlist[sum_s23; sum_s24])` + `2 EXP 128 * q3 + q2 = + bignum_of_wordlist [x_2;x_3] * bignum_of_wordlist[y_2;y_3] + q1` ASSUME_TAC THENL - [REWRITE_TAC[REAL_EQ_SUB_LADD] THEN - FIRST_ASSUM(fun th -> GEN_REWRITE_TAC - (LAND_CONV o LAND_CONV o RAND_CONV) [SYM th]) THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - BOUNDER_TAC[]; - ALL_TAC]) THEN - CONJ_TAC THENL [REAL_INTEGER_TAC; ALL_TAC] THEN - ASM_REWRITE_TAC[] THEN + [MAP_EVERY EXPAND_TAC ["q1"; "q2"; "q3"] THEN + MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN + REPEAT(CONJ_TAC THENL + [CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; ALL_TAC]) THEN + FIRST_X_ASSUM(fun th -> GEN_REWRITE_TAC + (LAND_CONV o LAND_CONV) [SYM th]) THEN + MAP_EVERY EXPAND_TAC ["q23"] THEN + REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN + ALL_TAC] THEN - (*** Squaring the absolute difference ***) + (*** Third nested block multiplying the absolute differences ***) ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [62;64;69;71;73;74;75;76;77;78;79] (58--79) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [VAL_WORD_MADDL_0; DIVMOD_33_31; VAL_WORD_USHR; - VAL_WORD_SHL; DIMINDEX_64]) THEN + [73;75;80;81;85;87;88;89;92;94;95] (73--95) THEN + RULE_ASSUM_TAC(REWRITE_RULE[lemma0; lemma1]) THEN SUBGOAL_THEN - `bignum_of_wordlist[sum_s51;sum_s53] EXP 2 = - bignum_of_wordlist[sum_s62; sum_s77; sum_s78; sum_s79]` - ASSUME_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - MAP_EVERY (SUBST_ALL_TAC o SYM o C SPEC VAL_WORD_SPLIT32) - [`sum_s51:int64`; `sum_s53:int64`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV]) THEN - RULE_ASSUM_TAC(CONV_RULE NUM_REDUCE_CONV) THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_ARITH_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** The overall Karatsuba composition to get the full square ***) + `&xd * &yd:real = + &(bignum_of_wordlist[mullo_s73; sum_s92; sum_s94; sum_s95])` + SUBST_ALL_TAC THENL + [MAP_EVERY EXPAND_TAC ["xd"; "yd"] THEN + REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + KARATSUBA12_TAC; + ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC) THEN + DISCARD_MATCHING_ASSUMPTIONS [`word a = b`]] THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (80--90) (80--90) THEN - RULE_ASSUM_TAC(REWRITE_RULE - [COND_SWAP; WORD_UNMASK_64; REAL_BITVAL_NOT; DIMINDEX_64; - GSYM WORD_NOT_MASK; REAL_VAL_WORD_NOT;REAL_VAL_WORD_MASK]) THEN + (*** The rest of the basic 4x4->8 multiply computation and its proof ***) + ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC + [96;97;98;99;100;101;104;106;108;110;111;112] (96--112) THEN MAP_EVERY ABBREV_TAC - [`l = bignum_of_wordlist[sum_s7; sum_s22; sum_s85; sum_s86]`; - `h = bignum_of_wordlist[sum_s87; sum_s88; sum_s89; sum_s90]`] THEN - SUBGOAL_THEN `2 EXP 256 * h + l = n EXP 2` (SUBST1_TAC o SYM) THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"; "n"] THEN + [`l = bignum_of_wordlist[mullo_s3; sum_s22; sum_s104; sum_s106]`; + `h = bignum_of_wordlist[sum_s108; sum_s110; sum_s111; sum_s112]`] THEN + SUBGOAL_THEN `2 EXP 256 * h + l = m * n` (SUBST1_TAC o SYM) THENL + [DISCARD_STATE_TAC "s112" THEN MAP_EVERY EXPAND_TAC ["h"; "l"] THEN REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN MAP_EVERY EXISTS_TAC [`512`; `&0:real`] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL - [REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - BOUNDER_TAC[]; - ALL_TAC]) THEN - CONJ_TAC THENL [REAL_INTEGER_TAC; ALL_TAC] THEN - REWRITE_TAC[BIGNUM_OF_WORDLIST_SPLIT_RULE(2,2)] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; REAL_ARITH - `(l + &2 pow 128 * h) pow 2 = - &2 pow 256 * h pow 2 + l pow 2 + - &2 pow 128 * (h pow 2 + l pow 2 - (l - h) pow 2)`] THEN - ONCE_REWRITE_TAC[GSYM REAL_POW2_ABS] THEN ASM_REWRITE_TAC[] THEN - ASM_REWRITE_TAC[REAL_ABS_NUM; REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL + [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES] THEN BOUNDER_TAC[]; + REWRITE_TAC[INTEGER_CLOSED]] THEN + SUBGOAL_THEN + `&m * &n:real = + (&1 + &2 pow 128) * (&q0 + &2 pow 128 * &q2 + &2 pow 256 * &q3) + + &2 pow 128 * + (&(bignum_of_wordlist [x_2; x_3]) - + &(bignum_of_wordlist [x_0; x_1])) * + (&(bignum_of_wordlist [y_0; y_1]) - + &(bignum_of_wordlist [y_2; y_3]))` + SUBST1_TAC THENL + [MAP_EVERY UNDISCH_TAC + [`2 EXP 128 * q1 + q0 = + bignum_of_wordlist[x_0; x_1] * bignum_of_wordlist[y_0; y_1]`; + `2 EXP 128 * q3 + q2 = + bignum_of_wordlist[x_2; x_3] * bignum_of_wordlist[y_2; y_3] + + q1`] THEN + MAP_EVERY EXPAND_TAC ["m"; "n"] THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN + CONV_TAC REAL_RING; + ASM_REWRITE_TAC[]] THEN + MAP_EVERY EXPAND_TAC ["h"; "l"; "q0"; "q2"; "q3"] THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ) THEN + POP_ASSUM_LIST(K ALL_TAC) THEN + REWRITE_TAC[WORD_XOR_MASK] THEN COND_CASES_TAC THEN + ASM_REWRITE_TAC[REAL_VAL_WORD_NOT; BITVAL_CLAUSES; DIMINDEX_64] THEN + CONV_TAC WORD_REDUCE_CONV THEN CONV_TAC NUM_REDUCE_CONV THEN + REWRITE_TAC[BITVAL_CLAUSES] THEN DISCH_TAC THEN + FIRST_ASSUM(MP_TAC o end_itlist CONJ o DESUM_RULE o CONJUNCTS) THEN DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN (*** The initial modular reduction of the high part ***) - REWRITE_TAC[CONG] THEN SUBGOAL_THEN `(2 EXP 256 * h + l) MOD p_25519 = (38 * h + l) MOD p_25519` SUBST1_TAC THENL @@ -7034,16 +3861,17 @@ let LOCAL_SQR_4_TAC = (*** The somewhat fiddly reduction with 32-bit operations etc. ***) - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (91--115) THEN + ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (113--137) THEN + MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM MP_TAC) - [`u0 = read X2 s115`; - `u1 = read X3 s115`; - `u2 = read X4 s115`; - `u3 = read X5 s115`; - `u4 = read X6 s115`; - `u5 = read X7 s115`; - `u6 = read X8 s115`; - `u7 = read X9 s115`] THEN + [`u0 = read X7 s137`; + `u1 = read X8 s137`; + `u2 = read X9 s137`; + `u3 = read X10 s137`; + `u4 = read X11 s137`; + `u5 = read X12 s137`; + `u6 = read X13 s137`; + `u7 = read X14 s137`] THEN REWRITE_TAC[GSYM IMP_CONJ_ALT] THEN GEN_REWRITE_TAC (LAND_CONV o TOP_DEPTH_CONV) [word_add; modular; ADD_CLAUSES; VAL_WORD; VAL_WORD_ZX_GEN; @@ -7054,15 +3882,12 @@ let LOCAL_SQR_4_TAC = SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE `n < 2 EXP 64 ==> n MOD 2 EXP 32 * 38 < 2 EXP 64`] THEN STRIP_TAC THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC [120;122;124;128] (116--130) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - + ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC [142;144;146;150] (138--150) THEN SUBGOAL_THEN `word_ushr u7 31:int64 = word q` SUBST_ALL_TAC THENL [REWRITE_TAC[GSYM VAL_EQ; VAL_WORD; VAL_WORD_USHR] THEN ASM_SIMP_TAC[DIMINDEX_64; MOD_LT] THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s86:int64) DIV 2 EXP 32 + - val(sum_s90:int64) DIV 2 EXP 32 * 38):int64 = u7`)) THEN + `word(val(sum_s106:int64) DIV 2 EXP 32 + + val(sum_s112:int64) DIV 2 EXP 32 * 38):int64 = u7`)) THEN MAP_EVERY EXPAND_TAC ["q"; "l"; "h"] THEN REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN @@ -7074,18 +3899,19 @@ let LOCAL_SQR_4_TAC = ALL_TAC] THEN SUBGOAL_THEN `&(val(word_add (u0:int64) - (word(0 + 19 * val((word_zx:int64->int32)(word q)))))):real = - &(val u0) + &19 * &q` + (word(19 + 19 * val((word_zx:int64->int32)(word q)))))):real = + &(val u0) + &19 * (&q + &1)` SUBST_ALL_TAC THENL [REWRITE_TAC[REAL_OF_NUM_CLAUSES; VAL_WORD_ADD; VAL_WORD; VAL_WORD_ZX_GEN; - DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN; ADD_CLAUSES] THEN + DIMINDEX_32; DIMINDEX_64; MOD_MOD_EXP_MIN] THEN ASM_SIMP_TAC[ARITH_RULE `q <= 77 ==> q < 2 EXP MIN 64 32`; MOD_LT] THEN CONV_TAC MOD_DOWN_CONV THEN + REWRITE_TAC[ARITH_RULE `19 + 19 * q = 19 * (q + 1)`] THEN MATCH_MP_TAC MOD_LT THEN SUBST1_TAC(SYM(ASSUME - `word(val(sum_s87:int64) MOD 2 EXP 32 * 38 + - val(sum_s7:int64) MOD 2 EXP 32):int64 = u0`)) THEN + `word(val(sum_s108:int64) MOD 2 EXP 32 * 38 + + val(mullo_s3:int64) MOD 2 EXP 32):int64 = u0`)) THEN MATCH_MP_TAC(ARITH_RULE - `w <= 2 EXP 63 /\ q <= 77 ==> w + 19 * q < 2 EXP 64`) THEN + `w <= 2 EXP 63 /\ q <= 77 ==> w + 19 * (q + 1) < 2 EXP 64`) THEN CONJ_TAC THENL [MATCH_MP_TAC VAL_WORD_LE; FIRST_ASSUM ACCEPT_TAC] THEN ARITH_TAC; ALL_TAC] THEN @@ -7097,531 +3923,385 @@ let LOCAL_SQR_4_TAC = SIMP_TAC[MOD_LT; BITVAL_BOUND_ALT; GSYM REAL_OF_NUM_CLAUSES] THEN ASM_SIMP_TAC[GSYM VAL_MOD_2; VAL_WORD; DIMINDEX_64; MOD_LT] THEN STRIP_TAC THEN - - REWRITE_TAC[GSYM CONG; REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[num_congruent; GSYM INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(MESON[] - `!q. (ca - q * p == ca) (mod p) /\ - (&0 <= ca - q * p /\ ca - q * p < p2) /\ - (&0 <= ca - q * p /\ ca - q * p < p2 ==> x = ca - q * p) - ==> x:int < p2 /\ (x == ca) (mod p)`) THEN - EXISTS_TAC `&q:int` THEN - CONJ_TAC THENL [CONV_TAC INTEGER_RULE; ALL_TAC] THEN - CONJ_TAC THENL - [MAP_EVERY UNDISCH_TAC - [`(q + 1) * p_25519 <= (38 * h + l) + p_25519`; - `38 * h + l < (q + 1) * p_25519 + p_25519`] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN INT_ARITH_TAC; - STRIP_TAC] THEN - MATCH_MP_TAC INT_CONG_IMP_EQ THEN EXISTS_TAC `(&2:int) pow 256` THEN - CONJ_TAC THENL - [FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INT_ARITH - `y:int < p ==> &0 <= y /\ &0 <= p /\ p < e /\ &0 <= x /\ x < e - ==> abs(x - y) < e`)) THEN - ASM_REWRITE_TAC[] THEN - REWRITE_TAC[INT_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - ALL_TAC] THEN - - REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN - SUBGOAL_THEN - `38 * h + l = - bignum_of_wordlist[u0;u1;u2;u3] + - 2 EXP 32 * bignum_of_wordlist[u4;u5;u6;u7]` - SUBST1_TAC THENL - [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN - REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o - check (can (term_match [] `word x = n`) o concl))) THEN - REWRITE_TAC[bignum_of_wordlist; VAL_WORD; DIMINDEX_64] THEN - SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE - `m < 2 EXP 64 /\ n < 2 EXP 64 - ==> m DIV 2 EXP 32 + n DIV 2 EXP 32 * 38 < 2 EXP 64`; - ARITH_RULE `m MOD 2 EXP 32 * 38 + n MOD 2 EXP 32 < 2 EXP 64`] THEN - ARITH_TAC; - ALL_TAC] THEN - SUBGOAL_THEN - `2 EXP 32 * bignum_of_wordlist [u4; u5; u6; u7] = - bignum_of_wordlist - [word_shl u4 32; - word_subword ((word_join:int64->int64->int128) u5 u4) (32,64); - word_subword ((word_join:int64->int64->int128) u6 u5) (32,64); - word_subword ((word_join:int64->int64->int128) u7 u6) (32,64); - word_ushr u7 32]` - SUBST1_TAC THENL - [REWRITE_TAC[val_def; DIMINDEX_64; bignum_of_wordlist] THEN - REWRITE_TAC[ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN - REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN - REWRITE_TAC[BIT_WORD_JOIN; BIT_WORD_USHR; BIT_WORD_SUBWORD; - BIT_WORD_SHL; DIMINDEX_64; DIMINDEX_128] THEN - CONV_TAC NUM_REDUCE_CONV THEN - CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN - CONV_TAC NUM_REDUCE_CONV THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - ONCE_REWRITE_TAC[BIT_GUARD] THEN REWRITE_TAC[DIMINDEX_64] THEN - CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[BITVAL_CLAUSES] THEN - ARITH_TAC; - ALL_TAC] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - SIMP_TAC[REAL_INT_CONGRUENCE; INT_POW_EQ_0; INT_OF_NUM_EQ; ARITH_EQ] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; - int_mul_th; int_pow_th] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of add_twice4 (slightly sharper disjunctive hypothesis). *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_ADD_TWICE4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_byte_mc 16 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x59e4) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - (m < 2 * p_25519 \/ n < 2 * p_25519 - ==> (read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s == - m + n) (mod p_25519))) - (MAYCHANGE [PC; X3; X4; X5; X6; X7; X8; X9] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "m_" o lhand o concl) THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (1--8) (1--8) THEN - SUBGOAL_THEN `carry_s8 <=> 2 EXP 256 <= m + n` SUBST_ALL_TAC THENL - [MATCH_MP_TAC FLAG_FROM_CARRY_LE THEN EXISTS_TAC `256` THEN - MAP_EVERY EXPAND_TAC ["m"; "n"] THEN REWRITE_TAC[GSYM REAL_OF_NUM_ADD] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_MUL; GSYM REAL_OF_NUM_POW] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN BOUNDER_TAC[]; - ALL_TAC] THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (11--14) (9--16) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN DISCH_TAC THEN - REWRITE_TAC[num_congruent; GSYM INT_OF_NUM_ADD] THEN - MATCH_MP_TAC(MESON[INT_OF_NUM_LT] - `!x':int. (x' == a) (mod p) /\ x = x' - ==> (x:int == a) (mod p)`) THEN - EXISTS_TAC - `if 2 EXP 256 <= m + n then (&m + &n) - &2 * &p_25519:int else &m + &n` THEN - CONJ_TAC THENL [COND_CASES_TAC THEN CONV_TAC INTEGER_RULE; ALL_TAC] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - ONCE_REWRITE_TAC[int_eq] THEN ONCE_REWRITE_TAC[COND_RAND] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; int_mul_th] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL - [FIRST_X_ASSUM(MP_TAC o SPEC `2 EXP 256` o MATCH_MP (ARITH_RULE - `m < p \/ n < p - ==> !e:num. p < e /\ m < e /\ n < e ==> m + n < e + p`)) THEN - ANTS_TAC THENL - [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN REWRITE_TAC[p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN INT_ARITH_TAC]; - REWRITE_TAC[INTEGER_CLOSED]] THEN - RULE_ASSUM_TAC(REWRITE_RULE[SYM(NUM_EXP_CONV `2 EXP 256`)]) THEN - ABBREV_TAC `bb <=> 2 EXP 256 <= m + n` THEN MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[bignum_of_wordlist; p_25519; GSYM REAL_OF_NUM_CLAUSES] THEN - CONV_TAC NUM_REDUCE_CONV THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of sub_twice4 (slightly sharper hypothesis distinctions). *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_SUB_TWICE4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_byte_mc 16 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x59e4) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - (m < 2 * p_25519 /\ n < 2 * p_25519 - ==> read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s - < 2 * p_25519) /\ - (n < 2 * p_25519 - ==> (&(read(memory :> bytes - (word_add (read p3 t) (word n3),8 * 4)) s):int == - &m - &n) (mod (&p_25519)))) - (MAYCHANGE [PC; X3; X4; X5; X6; X7; X8] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "m_" o lhand o concl) THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (1--8) (1--8) THEN - SUBGOAL_THEN `carry_s8 <=> m < n` SUBST_ALL_TAC THENL - [MATCH_MP_TAC FLAG_FROM_CARRY_LT THEN EXISTS_TAC `256` THEN - MAP_EVERY EXPAND_TAC ["m"; "n"] THEN REWRITE_TAC[GSYM REAL_OF_NUM_ADD] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_MUL; GSYM REAL_OF_NUM_POW] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN BOUNDER_TAC[]; - ALL_TAC] THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (11--14) (9--16) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - MATCH_MP_TAC(MESON[INT_OF_NUM_LT] - `!x':int. (x' == &m - &n) (mod p) /\ - (m < p2 /\ n < p2 ==> x' < &p2) /\ - (n < p2 ==> &x = x') - ==> (m < p2 /\ n < p2 ==> x < p2) /\ - (n:num < p2 ==> (&x:int == &m - &n) (mod p))`) THEN - EXISTS_TAC `if m < n then &m - &n + &2 * &p_25519:int else &m - &n` THEN - REPEAT CONJ_TAC THENL - [COND_CASES_TAC THEN CONV_TAC INTEGER_RULE; - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN INT_ARITH_TAC; - DISCH_TAC] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - ONCE_REWRITE_TAC[int_eq] THEN ONCE_REWRITE_TAC[COND_RAND] THEN - REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; int_mul_th] THEN - MATCH_MP_TAC EQUAL_FROM_CONGRUENT_REAL THEN - MAP_EVERY EXISTS_TAC [`256`; `&0:real`] THEN - CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN CONJ_TAC THENL - [CONJ_TAC THENL - [POP_ASSUM MP_TAC THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN INT_ARITH_TAC; - SUBGOAL_THEN `m < 2 EXP 256` MP_TAC THENL - [EXPAND_TAC "m" THEN BOUNDER_TAC[]; - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; p_25519] THEN REAL_ARITH_TAC]]; - REWRITE_TAC[INTEGER_CLOSED]] THEN - ABBREV_TAC `bb <=> m:num < n` THEN MAP_EVERY EXPAND_TAC ["m"; "n"] THEN - REWRITE_TAC[bignum_of_wordlist; p_25519; GSYM REAL_OF_NUM_CLAUSES] THEN - CONV_TAC NUM_REDUCE_CONV THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of cmadd_4 (actually there is only one, specific constant). *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_CMADD_4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_byte_mc 32 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x59e4) (word_add (read p3 t) (word n3),8 * 4) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read X1 s = word 121666 /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s < - 2 * p_25519 /\ - (read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s == - 121666 * m + n) (mod p_25519)) - (MAYCHANGE [PC; X3; X4; X5; X6; X7; X8; X9; X10; X11] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)] ,, - MAYCHANGE SOME_FLAGS)` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "m_" o lhand o concl) THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC - [3;4;5;6;11;12;13;14;16;17;19;20;21] (1--21) THEN - - RULE_ASSUM_TAC(CONV_RULE WORD_REDUCE_CONV) THEN ABBREV_TAC - `ca = bignum_of_wordlist[sum_s16; sum_s17; sum_s19; sum_s20; sum_s21]` THEN - SUBGOAL_THEN `121666 * m + n < 2 EXP 17 * 2 EXP 256` ASSUME_TAC THENL - [MAP_EVERY EXPAND_TAC ["m"; "n"] THEN CONV_TAC NUM_REDUCE_CONV THEN - BOUNDER_TAC[]; - ALL_TAC] THEN - SUBGOAL_THEN `121666 * m + n = ca` SUBST_ALL_TAC THENL - [MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 320` THEN - REPEAT CONJ_TAC THENL - [UNDISCH_TAC `121666 * m + n < 2 EXP 17 * 2 EXP 256` THEN ARITH_TAC; - EXPAND_TAC "ca" THEN BOUNDER_TAC[]; - REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV] THEN - MAP_EVERY EXPAND_TAC ["m"; "n"; "ca"] THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES; p_25519] THEN - CONV_TAC NUM_REDUCE_CONV THEN - RULE_ASSUM_TAC(REWRITE_RULE[REAL_BITVAL_NOT]) THEN - ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; - ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - - (*** Instantiate the quotient approximation lemma ***) - - MP_TAC(SPEC `ca:num` p25519weakredlemma) THEN ANTS_TAC THENL - [UNDISCH_TAC `ca < 2 EXP 17 * 2 EXP 256` THEN ARITH_TAC; - CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN STRIP_TAC] THEN - - (*** Quotient estimate computation ***) + `r = bignum_of_wordlist[sum_s142; sum_s144; sum_s146; sum_s150]` THEN - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (22--24) (22--24) THEN - SUBGOAL_THEN `ca DIV 2 EXP 255 = val(sum_s24:int64)` - (fun th -> SUBST_ALL_TAC th THEN ASSUME_TAC th) - THENL - [FIRST_ASSUM(MP_TAC o MATCH_MP (ARITH_RULE - `ca < 2 EXP 17 * 2 EXP 256 - ==> ca DIV 2 EXP 192 DIV 2 EXP 63 < 2 EXP 59`)) THEN - EXPAND_TAC "ca" THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - DISCH_THEN(fun th -> - MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 64` THEN - CONJ_TAC THENL [MP_TAC th THEN ARITH_TAC; REWRITE_TAC[VAL_BOUND_64]]) THEN - REWRITE_TAC[ARITH_RULE `n DIV 2 EXP 63 = (2 * n) DIV 2 EXP 64`] THEN - SUBST1_TAC(SYM(BIGNUM_OF_WORDLIST_DIV_CONV - `bignum_of_wordlist [sum_s22; sum_s24] DIV 2 EXP 64`)) THEN - MATCH_MP_TAC CONG_DIV2 THEN - REWRITE_TAC[REAL_CONGRUENCE] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + SUBGOAL_THEN + `(&r:int == &2 pow 255 + &(38 * h + l) - (&q + &1) * &p_25519) + (mod (&2 pow 256))` + ASSUME_TAC THENL + [SUBGOAL_THEN + `38 * h + l = + bignum_of_wordlist[u0;u1;u2;u3] + + 2 EXP 32 * bignum_of_wordlist[u4;u5;u6;u7]` + SUBST1_TAC THENL + [MAP_EVERY EXPAND_TAC ["h"; "l"] THEN + REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o + check (can (term_match [] `word x = n`) o concl))) THEN + REWRITE_TAC[bignum_of_wordlist; VAL_WORD; DIMINDEX_64] THEN + SIMP_TAC[MOD_LT; VAL_BOUND_64; ARITH_RULE + `m < 2 EXP 64 /\ n < 2 EXP 64 + ==> m DIV 2 EXP 32 + n DIV 2 EXP 32 * 38 < 2 EXP 64`; + ARITH_RULE `m MOD 2 EXP 32 * 38 + n MOD 2 EXP 32 < 2 EXP 64`] THEN + ARITH_TAC; + ALL_TAC] THEN + SUBGOAL_THEN + `2 EXP 32 * bignum_of_wordlist [u4; u5; u6; u7] = + bignum_of_wordlist + [word_shl u4 32; + word_subword ((word_join:int64->int64->int128) u5 u4) (32,64); + word_subword ((word_join:int64->int64->int128) u6 u5) (32,64); + word_subword ((word_join:int64->int64->int128) u7 u6) (32,64); + word_ushr u7 32]` + SUBST1_TAC THENL + [REWRITE_TAC[val_def; DIMINDEX_64; bignum_of_wordlist] THEN + REWRITE_TAC[ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN + REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN + REWRITE_TAC[BIT_WORD_JOIN; BIT_WORD_USHR; BIT_WORD_SUBWORD; + BIT_WORD_SHL; DIMINDEX_64; DIMINDEX_128] THEN + CONV_TAC NUM_REDUCE_CONV THEN + CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN + CONV_TAC NUM_REDUCE_CONV THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN + ONCE_REWRITE_TAC[BIT_GUARD] THEN REWRITE_TAC[DIMINDEX_64] THEN + CONV_TAC NUM_REDUCE_CONV THEN REWRITE_TAC[BITVAL_CLAUSES] THEN + ARITH_TAC; + ALL_TAC] THEN + SIMP_TAC[REAL_INT_CONGRUENCE; INT_POW_EQ_0; INT_OF_NUM_EQ; ARITH_EQ] THEN + REWRITE_TAC[int_of_num_th; int_sub_th; int_add_th; + int_mul_th; int_pow_th] THEN + EXPAND_TAC "r" THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (25--26) THEN - ABBREV_TAC `qm:int64 = word(0 + val(sum_s24:int64) * 19)` THEN - SUBGOAL_THEN `&(val(qm:int64)):real = &19 * &(val(sum_s24:int64))` - ASSUME_TAC THENL - [EXPAND_TAC "qm" THEN REWRITE_TAC[ADD_CLAUSES] THEN - REWRITE_TAC[VAL_WORD; DIMINDEX_64; REAL_OF_NUM_CLAUSES] THEN - REWRITE_TAC[MULT_SYM] THEN MATCH_MP_TAC MOD_LT THEN MAP_EVERY UNDISCH_TAC - [`val(sum_s24:int64) * p_25519 <= ca`; - `ca < 2 EXP 17 * 2 EXP 256`] THEN - REWRITE_TAC[p_25519] THEN ARITH_TAC; - ALL_TAC] THEN - (*** The rest of the computation ***) + (*** The final optional correction ***) - ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (27--30) (27--32) THEN + ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC (154--157) (151--160) THEN ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[GSYM CONG; num_congruent] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(MESON[] - `!q. (ca - q * p == ca) (mod p) /\ ca - q * p < p2 /\ x = ca - q * p - ==> x:int < p2 /\ (x == ca) (mod p)`) THEN - EXISTS_TAC `&(val(sum_s24:int64)):int` THEN - CONJ_TAC THENL [CONV_TAC INTEGER_RULE; ALL_TAC] THEN - MATCH_MP_TAC(TAUT `p /\ (p ==> q) ==> p /\ q`) THEN CONJ_TAC THENL - [REWRITE_TAC[INT_ARITH `x - y:int < z <=> x < y + z`] THEN - ASM_REWRITE_TAC[INT_OF_NUM_CLAUSES]; - DISCH_TAC] THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN - MATCH_MP_TAC INT_CONG_IMP_EQ THEN EXISTS_TAC `(&2:int) pow 256` THEN + REWRITE_TAC[REAL_OF_NUM_CLAUSES] THEN CONV_TAC SYM_CONV THEN + MATCH_MP_TAC EQUAL_FROM_CONGRUENT_MOD_MOD THEN + MAP_EVERY EXISTS_TAC + [`255`; + `(if r < 2 EXP 255 then &r - &19 else &r - &2 pow 255):real`] THEN + CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN + ASM_REWRITE_TAC[] THEN DISCARD_STATE_TAC "s160" THEN + CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN + REPLICATE_TAC 2 + (CONJ_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC]) THEN CONJ_TAC THENL - [FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INT_ARITH - `y:int < p ==> &0 <= y /\ &0 <= p /\ p < e /\ &0 <= x /\ x < e - ==> abs(x - y) < e`)) THEN - ASM_REWRITE_TAC[INT_SUB_LE; INT_OF_NUM_CLAUSES; LE_0] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV THEN - BOUNDER_TAC[]; - ALL_TAC] THEN - REWRITE_TAC[INTEGER_RULE - `(x:int == y - z) (mod p) <=> (x + z == y) (mod p)`] THEN - REWRITE_TAC[INT_OF_NUM_CLAUSES; GSYM num_congruent] THEN - REWRITE_TAC[REAL_CONGRUENCE; p_25519] THEN CONV_TAC NUM_REDUCE_CONV THEN - EXPAND_TAC "ca" THEN - REWRITE_TAC[p_25519; bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN - ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN - DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[SYM(NUM_REDUCE_CONV `2 EXP 63 - 1`)] THEN - REWRITE_TAC[VAL_WORD_AND_MASK_WORD] THEN - UNDISCH_THEN `ca DIV 2 EXP 255 = val(sum_s24:int64)` (SUBST1_TAC o SYM) THEN - EXPAND_TAC "ca" THEN - CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN - REWRITE_TAC[bignum_of_wordlist; ARITH_RULE - `(l + 2 EXP 64 * h) DIV 2 EXP 63 = l DIV 2 EXP 63 + 2 * h`] THEN - REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; REAL_OF_NUM_DIV] THEN - REAL_INTEGER_TAC);; - -(* ------------------------------------------------------------------------- *) -(* Instances of mux_4. *) -(* ------------------------------------------------------------------------- *) - -let LOCAL_MUX_4_TAC = - ARM_MACRO_SIM_ABBREV_TAC curve25519_x25519_byte_mc 10 lvs - `!(t:armstate) pcin pcout p3 n3 p1 n1 p2 n2. - !b. read ZF t = b - ==> - !m. read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) t = m - ==> - !n. read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) t = n - ==> - aligned 16 (read SP t) /\ - nonoverlapping (word pc,0x59e4) (word_add (read p3 t) (word n3),8 * 4) /\ - nonoverlapping (stackpointer:int64,320) (res,32) - ==> ensures arm - (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ - read PC s = pcin /\ - read SP s = read SP t /\ - read X23 s = read X23 t /\ - read ZF s = b /\ - read(memory :> bytes(word_add (read p1 t) (word n1),8 * 4)) s = m /\ - read(memory :> bytes(word_add (read p2 t) (word n2),8 * 4)) s = n) - (\s. read PC s = pcout /\ - read(memory :> bytes(word_add (read p3 t) (word n3),8 * 4)) s = - (if b then n else m)) - (MAYCHANGE [PC; X0; X1; X2; X3] ,, - MAYCHANGE [memory :> bytes(word_add (read p3 t) (word n3),8 * 4)])` - (REWRITE_TAC[C_ARGUMENTS; C_RETURN; SOME_FLAGS; NONOVERLAPPING_CLAUSES] THEN - DISCH_THEN(REPEAT_TCL CONJUNCTS_THEN ASSUME_TAC) THEN - REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "n_" o lhand o concl) THEN - FIRST_ASSUM(BIGNUM_LDIGITIZE_TAC "m_" o lhand o concl) THEN - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (1--10) THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC(LAND_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[COND_SWAP] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[]);; + [REWRITE_TAC[ARITH_RULE `r < 2 EXP 255 <=> r DIV 2 EXP 192 < 2 EXP 63`] THEN + EXPAND_TAC "r" THEN + CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN + REWRITE_TAC[SYM(NUM_REDUCE_CONV `2 EXP 63 - 1`)] THEN + REWRITE_TAC[bignum_of_wordlist; VAL_WORD_AND_MASK_WORD] THEN + ABBREV_TAC `bb <=> val(sum_s150:int64) < 2 EXP 63` THEN + SUBGOAL_THEN + `ival(word_and sum_s150 (word 9223372036854775808):int64) < &0 <=> ~bb` + SUBST_ALL_TAC THENL + [REWRITE_TAC[GSYM MSB_IVAL; BIT_WORD_AND] THEN + REWRITE_TAC[MSB_VAL] THEN REWRITE_TAC[DIMINDEX_64] THEN + CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN + EXPAND_TAC "bb" THEN ARITH_TAC; + RULE_ASSUM_TAC(REWRITE_RULE[]) THEN + REWRITE_TAC[GSYM REAL_OF_NUM_CLAUSES; bignum_of_wordlist] THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + REWRITE_TAC[REAL_OF_NUM_MOD; p_25519] THEN + COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN + CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC]; + FIRST_ASSUM(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ] + endp25519redlemma)) THEN + ANTS_TAC THENL + [REWRITE_TAC[INT_ARITH `--p:int <= x - y <=> y <= x + p`] THEN + REWRITE_TAC[INT_ARITH `x - y:int < p <=> x < y + p`] THEN + ASM_REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN + EXPAND_TAC "r" THEN BOUNDER_TAC[]; + REWRITE_TAC[INT_ARITH `x - q * p:int = --q * p + x`] THEN + REWRITE_TAC[INT_REM_MUL_ADD] THEN + REWRITE_TAC[int_eq; int_of_num_th; INT_OF_NUM_REM] THEN + DISCH_THEN SUBST1_TAC THEN COND_CASES_TAC THEN + ASM_REWRITE_TAC[int_of_num_th; int_sub_th; int_pow_th]]]);; (* ------------------------------------------------------------------------- *) -(* Instances of modular inverse inlining *) +(* Inlined modular inverse proof. *) (* ------------------------------------------------------------------------- *) let LOCAL_MODINV_TAC = ARM_SUBROUTINE_SIM_TAC - (curve25519_x25519_byte_mc,CURVE25519_X25519_BYTE_EXEC,0x45c8, - (GEN_REWRITE_CONV RAND_CONV [bignum_inv_p25519_mc] THENC - TRIM_LIST_CONV) + (curve25519_x25519_byte_mc,CURVE25519_X25519_BYTE_EXEC,0x13f4, + (GEN_REWRITE_CONV RAND_CONV [bignum_inv_p25519_mc] THENC TRIM_LIST_CONV) `TRIM_LIST (12,16) bignum_inv_p25519_mc`, CORE_INV_P25519_CORRECT) [`read X0 s`; `read X1 s`; `read (memory :> bytes(read X1 s,8 * 4)) s`; - `pc + 0x45c8`; `stackpointer:int64`];; + `pc + 0x13f4`; `stackpointer:int64`];; (* ------------------------------------------------------------------------- *) -(* Overall point operation proof. *) +(* The swapping-based Montgomery ladder more abstractly. *) (* ------------------------------------------------------------------------- *) -let nintlemma = prove - (`&(num_of_int(x rem &p_25519)) = x rem &p_25519`, - MATCH_MP_TAC INT_OF_NUM_OF_INT THEN MATCH_MP_TAC INT_REM_POS THEN - REWRITE_TAC[INT_OF_NUM_EQ; p_25519] THEN CONV_TAC NUM_REDUCE_CONV);; - -let lemma = prove - (`X = num_of_int(x rem &p_25519) ==> X < p_25519 /\ &X = x rem &p_25519`, - DISCH_THEN SUBST1_TAC THEN - REWRITE_TAC[GSYM INT_OF_NUM_LT; nintlemma; INT_LT_REM_EQ] THEN - REWRITE_TAC[INT_OF_NUM_LT; p_25519] THEN CONV_TAC NUM_REDUCE_CONV);; - -let lemma_double = prove - (`P IN group_carrier (curve25519x_group(f:(int#int) ring)) /\ - montgomery_xz f (group_pow (curve25519x_group f) P n) (x,y) - ==> field f /\ ring_char f = p_25519 - ==> montgomery_xz f - (group_pow (curve25519x_group f) P (2 * n)) - (montgomery_xzdouble (curve25519x f) (x,y))`, - REWRITE_TAC[curve25519x; curve25519x_group] THEN REPEAT STRIP_TAC THEN - MATCH_MP_TAC MONTGOMERY_XZDOUBLE_GROUP THEN ASM_REWRITE_TAC[] THEN - ASM_SIMP_TAC[GSYM curve25519x; MONTGOMERY_NONSINGULAR_CURVE25519X] THEN - REWRITE_TAC[A_25519; p_25519; RING_OF_NUM] THEN - CONV_TAC NUM_REDUCE_CONV);; - -let lemma_double_base = prove - (`P IN group_carrier (curve25519x_group(f:(int#int) ring)) /\ - montgomery_xz f P (x,y) - ==> field f /\ ring_char f = p_25519 - ==> montgomery_xz f - (group_pow (curve25519x_group f) P 2) - (montgomery_xzdouble (curve25519x f) (x,y))`, - SUBST1_TAC(ARITH_RULE `2 = 2 * 1`) THEN - REWRITE_TAC[curve25519x; curve25519x_group] THEN REPEAT STRIP_TAC THEN - MATCH_MP_TAC MONTGOMERY_XZDOUBLE_GROUP THEN ASM_REWRITE_TAC[] THEN - ASM_SIMP_TAC[GROUP_POW_1] THEN +let flipladder = define + `flipladder x n 0 = ((&1,&0),(&x rem &p_25519,&1)) /\ + flipladder x n (i + 1) = + let (x2,z2),(x3,z3) = flipladder x n i in + montgomery_xzdouble curve25519 + (if ODD(n DIV 2 EXP (255 - (i + 1))) <=> ODD(n DIV 2 EXP (255 - i)) + then (x2,z2) else (x3,z3)), + montgomery_xzdiffadd curve25519 (&x,&1) (x2,z2) (x3,z3)`;; + +let ladder_x2 = define + `ladder_x2 x n i = FST(FST(flipladder x n (255 - i)))`;; + +let ladder_z2 = define + `ladder_z2 x n i = SND(FST(flipladder x n (255 - i)))`;; + +let ladder_x3 = define + `ladder_x3 x n i = FST(SND(flipladder x n (255 - i)))`;; + +let ladder_z3 = define + `ladder_z3 x n i = SND(SND(flipladder x n (255 - i)))`;; + +let deproject = define + `deproject (x,z) = + (x * (if p_25519 divides z then 0 else inverse_mod p_25519 z)) + MOD p_25519`;; + +let curve25519x_represents = define + `curve25519x_represents (f:A ring) P n (X,Z) <=> + P IN group_carrier(montgomery_group (curve25519x f)) /\ + montgomery_xz f (group_pow (montgomery_group (curve25519x f)) P n) + (ring_of_int f X,ring_of_int f Z)`;; + +let CURVE25519X_REPRESENTS_DOUBLE = prove + (`!(f:A ring) P n Q. + field f /\ ring_char f = p_25519 /\ + curve25519x_represents f P n Q + ==> curve25519x_represents f P (2 * n) + (montgomery_xzdouble curve25519 Q)`, + REWRITE_TAC[FORALL_PAIR_THM; curve25519x_represents] THEN + MAP_EVERY X_GEN_TAC + [`f:A ring`; `P:(A#A)option`; `n:num`; `X:int`; `Z:int`] THEN + STRIP_TAC THEN GEN_REWRITE_TAC RAND_CONV [GSYM PAIR] THEN + PURE_REWRITE_TAC[curve25519x_represents] THEN ASM_REWRITE_TAC[] THEN + MP_TAC(ISPECL + [`f:A ring`; `ring_of_num (f:A ring) A_25519`; `ring_of_num (f:A ring) 1`; + `P:(A#A)option`; `n:num`; `ring_of_int f X:A,ring_of_int f Z`] + MONTGOMERY_XZDOUBLE_GROUP) THEN ASM_SIMP_TAC[GSYM curve25519x; MONTGOMERY_NONSINGULAR_CURVE25519X] THEN - REWRITE_TAC[A_25519; p_25519; RING_OF_NUM] THEN - CONV_TAC NUM_REDUCE_CONV);; - -let lemma_diffadd1 = prove - (`field f /\ ring_char f = p_25519 /\ - ~(x:(int#int) = ring_0 f) /\ - P IN group_carrier (curve25519x_group f) /\ - montgomery_xz f P (x,ring_of_num f 1) /\ - montgomery_xz f - (group_pow (curve25519x_group f) P (n + 1)) (xn,zn) /\ - montgomery_xz f - (group_pow (curve25519x_group f) P n) (xm,zm) - ==> montgomery_xz f - (group_pow (curve25519x_group f) P (2 * n + 1)) - (montgomery_xzdiffadd (curve25519x f) (x,ring_of_num f 1) - (xn,zn) (xm,zm))`, - REWRITE_TAC[curve25519x; curve25519x_group] THEN REPEAT STRIP_TAC THEN - MATCH_MP_TAC MONTGOMERY_XZDIFFADD_GROUP THEN ASM_REWRITE_TAC[] THEN + REWRITE_TAC[RING_OF_NUM; p_25519; ARITH_EQ] THEN + MATCH_MP_TAC EQ_IMP THEN AP_TERM_TAC THEN + REWRITE_TAC[montgomery_xzdouble; curve25519x; curve25519] THEN + REWRITE_TAC[INTEGER_MOD_RING_CLAUSES; PAIR_EQ] THEN + CONV_TAC INT_REM_DOWN_CONV THEN + FIRST_X_ASSUM(SUBST1_TAC o SYM) THEN + REWRITE_TAC[RING_OF_INT_REM] THEN + REWRITE_TAC[GSYM RING_OF_INT_CLAUSES] THEN + REWRITE_TAC[RING_OF_INT_OF_NUM]);; + +let CURVE25519X_REPRESENTS_DIFFADD_LEFT = prove + (`!(f:A ring) P n X Qm Qn. + field f /\ ring_char f = p_25519 /\ ~(&p_25519 divides X) /\ + curve25519x_represents f P 1 (X,&1) /\ + curve25519x_represents f P (n + 1) Qm /\ + curve25519x_represents f P n Qn + ==> curve25519x_represents f P (2 * n + 1) + (montgomery_xzdiffadd curve25519 (X,&1) Qm Qn)`, + REWRITE_TAC[FORALL_PAIR_THM; curve25519x_represents] THEN + MAP_EVERY X_GEN_TAC + [`f:A ring`; `P:(A#A)option`; `n:num`; `X:int`; + `Xm:int`; `Zm:int`; `Xn:int`; `Zn:int`] THEN + STRIP_TAC THEN GEN_REWRITE_TAC RAND_CONV [GSYM PAIR] THEN + PURE_REWRITE_TAC[curve25519x_represents] THEN ASM_REWRITE_TAC[] THEN + MP_TAC(ISPECL + [`f:A ring`; `ring_of_num (f:A ring) A_25519`; `ring_of_num (f:A ring) 1`; + `P:(A#A)option`; `n:num`; + `ring_of_int f X:A,ring_of_int f (&1)`; + `ring_of_int f Xm:A,ring_of_int f Zm`; + `ring_of_int f Xn:A,ring_of_int f Zn`] + MONTGOMERY_XZDIFFADD_GROUP) THEN ASM_SIMP_TAC[GSYM curve25519x; MONTGOMERY_NONSINGULAR_CURVE25519X] THEN - REWRITE_TAC[A_25519; p_25519; RING_OF_NUM] THEN - ASM_SIMP_TAC[RING_OF_NUM_1; FIELD_NONTRIVIAL] THEN - CONV_TAC NUM_REDUCE_CONV);; - -let lemma_diffadd2 = prove - (`field f /\ ring_char f = p_25519 /\ - ~(x:(int#int) = ring_0 f) /\ - P IN group_carrier (curve25519x_group f) /\ - montgomery_xz f P (x,ring_of_num f 1) /\ - montgomery_xz f - (group_pow (curve25519x_group f) P (n + 1)) (xm,zm) /\ - montgomery_xz f - (group_pow (curve25519x_group f) P n) (xn,zn) - ==> montgomery_xz f - (group_pow (curve25519x_group f) P (2 * n + 1)) - (montgomery_xzdiffadd (curve25519x f) (x,ring_of_num f 1) - (xn,zn) (xm,zm))`, + ASM_REWRITE_TAC[RING_OF_NUM; p_25519; ARITH_EQ] THEN ANTS_TAC THENL + [ASM_REWRITE_TAC[RING_OF_INT_EQ_0] THEN + REWRITE_TAC[GSYM num_divides; DIVIDES_MOD; p_25519] THEN + CONV_TAC NUM_REDUCE_CONV THEN ASM_MESON_TAC[GROUP_POW_1]; + MATCH_MP_TAC EQ_IMP THEN AP_TERM_TAC] THEN + REWRITE_TAC[montgomery_xzdiffadd; curve25519x; curve25519] THEN + REWRITE_TAC[INTEGER_MOD_RING_CLAUSES; PAIR_EQ] THEN + CONV_TAC INT_REM_DOWN_CONV THEN + FIRST_X_ASSUM(SUBST1_TAC o SYM) THEN + REWRITE_TAC[RING_OF_INT_REM] THEN + REWRITE_TAC[GSYM RING_OF_INT_CLAUSES] THEN + REWRITE_TAC[RING_OF_INT_OF_NUM]);; + +let CURVE25519X_REPRESENTS_DIFFADD_RIGHT = prove + (`!(f:A ring) P n X Qm Qn. + field f /\ ring_char f = p_25519 /\ ~(&p_25519 divides X) /\ + curve25519x_represents f P 1 (X,&1) /\ + curve25519x_represents f P n Qm /\ + curve25519x_represents f P (n + 1) Qn + ==> curve25519x_represents f P (2 * n + 1) + (montgomery_xzdiffadd curve25519 (X,&1) Qm Qn)`, + REWRITE_TAC[FORALL_PAIR_THM] THEN REPEAT GEN_TAC THEN + ONCE_REWRITE_TAC[TAUT + `p /\ q /\ r /\ s /\ t /\ u <=> p /\ q /\ r /\ s /\ u /\ t`] THEN DISCH_TAC THEN - FIRST_ASSUM(MP_TAC o MATCH_MP lemma_diffadd1) THEN + FIRST_ASSUM(MP_TAC o MATCH_MP CURVE25519X_REPRESENTS_DIFFADD_LEFT) THEN MATCH_MP_TAC EQ_IMP THEN AP_TERM_TAC THEN - POP_ASSUM STRIP_ASSUME_TAC THEN - REPEAT(FIRST_X_ASSUM(MP_TAC o MATCH_MP MONTGOMERY_XZ_IN_CARRIER)) THEN - ASM_SIMP_TAC[montgomery_xzdiffadd; curve25519x; RING_MUL_SYM; PAIR_EQ] THEN - RING_TAC);; + REWRITE_TAC[montgomery_xzdiffadd; curve25519] THEN + REWRITE_TAC[PAIR_EQ; INTEGER_MOD_RING_CLAUSES] THEN CONJ_TAC THEN + CONV_TAC INT_REM_DOWN_CONV THEN AP_THM_TAC THEN AP_TERM_TAC THEN + INT_ARITH_TAC);; + +let FLIPLADDER_MAIN = prove + (`!(f:A ring) P x n i. + field f /\ ring_char f = p_25519 /\ ~(p_25519 divides x) /\ + curve25519x_represents f P 1 (&x,&1) /\ n < 2 EXP 255 /\ i <= 255 + ==> curve25519x_represents f P (n DIV 2 EXP (255 - i)) + ((if ODD(n DIV 2 EXP (255 - i)) then SND else FST) + (flipladder x n i)) /\ + curve25519x_represents f P (n DIV 2 EXP (255 - i) + 1) + ((if ODD(n DIV 2 EXP (255 - i)) then FST else SND) + (flipladder x n i))`, + REWRITE_TAC[num_divides] THEN REPLICATE_TAC 4 GEN_TAC THEN + REWRITE_TAC[IMP_CONJ; RIGHT_FORALL_IMP_THM] THEN REPEAT DISCH_TAC THEN + INDUCT_TAC THENL + [DISCH_THEN(K ALL_TAC) THEN REWRITE_TAC[flipladder] THEN + ASM_SIMP_TAC[SUB_0; DIV_LT; ARITH_ODD; ADD_CLAUSES] THEN + FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE I [curve25519x_represents]) THEN + SIMP_TAC[curve25519x_represents; group_pow] THEN DISCH_TAC THEN + FIRST_ASSUM(SUBST1_TAC o SYM) THEN REWRITE_TAC[RING_OF_INT_REM] THEN + STRIP_TAC THEN ASM_SIMP_TAC[CURVE25519X_GROUP; GSYM curve25519x_group] THEN + REWRITE_TAC[montgomery_xz; RING_OF_INT_1; RING_OF_INT_0] THEN + REWRITE_TAC[RING_0; RING_1] THEN ASM_MESON_TAC[field]; + DISCH_TAC THEN FIRST_X_ASSUM(MP_TAC o check (is_imp o concl)) THEN + ANTS_TAC THENL [ASM_ARITH_TAC; ALL_TAC]] THEN + REWRITE_TAC[flipladder; ADD1] THEN + ASM_SIMP_TAC[ARITH_RULE + `SUC i <= 255 ==> 255 - i = SUC(255 - (i + 1))`] THEN + REWRITE_TAC[ONCE_REWRITE_RULE[MULT_SYM] (CONJUNCT2 EXP)] THEN + REWRITE_TAC[GSYM DIV_DIV] THEN + ABBREV_TAC `m = n DIV 2 EXP (255 - (i + 1)) DIV 2` THEN + MP_TAC(SPECL [`n DIV 2 EXP (255 - (i + 1))`; `2`] + (CONJUNCT1 DIVISION_SIMP)) THEN + ASM_REWRITE_TAC[MOD_2_CASES; GSYM NOT_ODD; COND_SWAP] THEN + MAP_EVERY ABBREV_TAC + [`b <=> ODD m`; `c <=> ODD(n DIV 2 EXP (255 - (i + 1)))`] THEN + DISCH_THEN(SUBST1_TAC o SYM) THEN + MAP_EVERY ASM_CASES_TAC [`b:bool`; `c:bool`] THEN + ASM_REWRITE_TAC[] THEN LET_TAC THEN ASM_REWRITE_TAC[] THEN + CONV_TAC(ONCE_DEPTH_CONV let_CONV) THEN ASM_REWRITE_TAC[] THEN + REWRITE_TAC[ADD_CLAUSES; ARITH_RULE `m * 2 = 2 * m`; + ARITH_RULE `(2 * m + 1) + 1 = 2 * (m + 1)`] THEN + ASM_MESON_TAC[CURVE25519X_REPRESENTS_DOUBLE; + CURVE25519X_REPRESENTS_DIFFADD_LEFT; + CURVE25519X_REPRESENTS_DIFFADD_RIGHT]);; + +let FLIPLADDER_DEGENERATE = prove + (`!x n i xm zm xn zn. + p_25519 divides x /\ flipladder x n i = (xm,zm),(xn,zn) + ==> zm = &0 /\ xn = &0`, + GEN_TAC THEN GEN_TAC THEN REWRITE_TAC[IMP_CONJ; RIGHT_FORALL_IMP_THM] THEN + REWRITE_TAC[num_divides; GSYM INT_REM_EQ_0] THEN DISCH_TAC THEN + INDUCT_TAC THEN ASM_SIMP_TAC[flipladder; PAIR_EQ] THENL + [MESON_TAC[]; REWRITE_TAC[flipladder; ADD1]] THEN + REPEAT GEN_TAC THEN LET_TAC THEN + SUBGOAL_THEN `z2:int = &0 /\ x3:int = &0` MP_TAC THENL + [ASM_MESON_TAC[]; REPLICATE_TAC 2 (POP_ASSUM(K ALL_TAC))] THEN + STRIP_TAC THEN COND_CASES_TAC THEN + ASM_REWRITE_TAC[montgomery_xzdouble; curve25519; montgomery_xzdouble; + PAIR_EQ; montgomery_xzdiffadd; INTEGER_MOD_RING_CLAUSES] THEN + CONV_TAC INT_REM_DOWN_CONV THEN + DISCH_THEN(fun th -> REWRITE_TAC[GSYM th]) THEN + REWRITE_TAC[INT_MUL_LZERO; INT_MUL_RZERO; INT_SUB_REFL; INT_POW_ZERO; + ARITH_EQ; INT_REM_ZERO]);; + +let DEPROJECT_LADDER_EVEN = prove + (`!x n x2 z2. + n < 2 EXP 255 /\ EVEN n /\ + (&x2 == ladder_x2 x n 0) (mod &p_25519) /\ + (&z2 == ladder_z2 x n 0) (mod &p_25519) + ==> purex25519(n,x) = deproject(x2,z2)`, + REWRITE_TAC[ladder_x2; ladder_z2; SUB_0] THEN REPEAT STRIP_TAC THEN + MATCH_MP_TAC PUREX25519_UNIQUE_IMP THEN CONJ_TAC THENL + [REWRITE_TAC[deproject; p_25519] THEN ARITH_TAC; ALL_TAC] THEN + MAP_EVERY X_GEN_TAC [`f:(int#int)ring`; `Q:((int#int)#(int#int))option`] THEN + STRIP_TAC THEN ASM_CASES_TAC `p_25519 divides x` THENL + [MP_TAC(ISPECL [`x:num`; `n:num`; `255`] FLIPLADDER_DEGENERATE) THEN + DISCH_THEN(MP_TAC o SPECL + [`ladder_x2 x n 0`; `ladder_z2 x n 0`; + `ladder_x3 x n 0`; `ladder_z3 x n 0`]) THEN + ASM_REWRITE_TAC[ladder_x2; ladder_z2; ladder_x3; ladder_z3] THEN + ASM_REWRITE_TAC[SUB_0] THEN DISCH_THEN(CONJUNCTS_THEN SUBST_ALL_TAC) THEN + ASM_REWRITE_TAC[deproject; num_divides; GSYM INT_CONG_0_DIVIDES] THEN + REWRITE_TAC[MULT_CLAUSES; MOD_0; RING_OF_NUM_0] THEN + REWRITE_TAC[curve25519x_group; curve25519x] THEN + MATCH_MP_TAC MONTGOMERY_XMAP_EQ_0_POW THEN + ASM_REWRITE_TAC[GSYM curve25519x_group; GSYM curve25519x; RING_OF_NUM] THEN + ASM_SIMP_TAC[MONTGOMERY_NONSINGULAR_CURVE25519X; RING_OF_NUM_EQ_0] THEN + REWRITE_TAC[p_25519; ARITH_EQ]; + ALL_TAC] THEN + MP_TAC(ISPECL [`f:(int#int)ring`; `Q:((int#int)#(int#int))option`; + `x:num`; `n:num`; `255`] + FLIPLADDER_MAIN) THEN + ASM_REWRITE_TAC[SUB_REFL; EXP; DIV_1; LE_REFL] THEN ANTS_TAC THENL + [ASM_SIMP_TAC[curve25519x_represents; GROUP_POW_1; + GSYM curve25519x_group; RING_OF_INT_OF_NUM; RING_OF_NUM_1] THEN + ASM_SIMP_TAC[MONTGOMERY_XZ_XMAP; RING_OF_NUM_EQ_0; RING_OF_NUM]; + DISCH_THEN(MP_TAC o CONJUNCT1) THEN ASM_REWRITE_TAC[GSYM NOT_EVEN]] THEN + GEN_REWRITE_TAC (LAND_CONV o RAND_CONV) [GSYM PAIR] THEN + REWRITE_TAC[curve25519x_represents] THEN + ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN + ASM_REWRITE_TAC[GSYM curve25519x_group] THEN + REPEAT(FIRST_X_ASSUM(SUBST1_TAC o SYM o + GEN_REWRITE_RULE I [GSYM INT_REM_EQ])) THEN + SUBST1_TAC(SYM(ASSUME `ring_char(f:(int#int)ring) = p_25519`)) THEN + REWRITE_TAC[RING_OF_INT_REM; RING_OF_INT_OF_NUM] THEN + SPEC_TAC(`group_pow (curve25519x_group(f:(int#int)ring)) Q n`, + `P:((int#int)#(int#int))option`) THEN + MATCH_MP_TAC option_INDUCT THEN + GEN_REWRITE_TAC RAND_CONV [FORALL_PAIR_THM] THEN + ASM_SIMP_TAC[montgomery_xmap; montgomery_xz; deproject; + RING_OF_NUM_EQ_0; MULT_CLAUSES; MOD_0; RING_OF_NUM_0] THEN + X_GEN_TAC `y:int#int` THEN STRIP_TAC THEN + FIRST_X_ASSUM(SUBST1_TAC o SYM) THEN + SUBST1_TAC(SYM(ASSUME `ring_char(f:(int#int)ring) = p_25519`)) THEN + REWRITE_TAC[RING_OF_NUM_MOD; RING_OF_NUM_MUL; ring_div] THEN + AP_TERM_TAC THEN MATCH_MP_TAC RING_LINV_UNIQUE THEN + REWRITE_TAC[RING_OF_NUM; GSYM RING_OF_NUM_1] THEN + ASM_REWRITE_TAC[GSYM RING_OF_NUM_MUL; RING_OF_NUM_EQ] THEN + REWRITE_TAC[INVERSE_MOD_LMUL_EQ] THEN + ASM_SIMP_TAC[PRIME_COPRIME_EQ; PRIME_P25519]);; + +(* ------------------------------------------------------------------------- *) +(* Overall point operation proof. *) +(* ------------------------------------------------------------------------- *) let CURVE25519_X25519_BYTE_CORRECT = time prove (`!res scalar n point X pc stackpointer. aligned 16 stackpointer /\ - ALL (nonoverlapping (stackpointer,320)) - [(word pc,0x59e4); (res,32); (scalar,32); (point,32)] /\ - nonoverlapping (res,32) (word pc,0x59e4) + ALL (nonoverlapping (stackpointer,224)) + [(word pc,0x27f8); (res,32); (scalar,32); (point,32)] /\ + nonoverlapping (res,32) (word pc,0x27f8) ==> ensures arm (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ - read PC s = word(pc + 0x10) /\ + read PC s = word(pc + 0x2c) /\ read SP s = stackpointer /\ C_ARGUMENTS [res; scalar; point] s /\ read (memory :> bytes(scalar,32)) s = n /\ read (memory :> bytes(point,32)) s = X) - (\s. read PC s = word (pc + 0x59d0) /\ + (\s. read PC s = word (pc + 0x27c8) /\ read (memory :> bytes(res,32)) s = rfcx25519(n,X)) (MAYCHANGE [PC; X0; X1; X2; X3; X4; X5; X6; X7; X8; X9; X10; X11; X12; X13; X14; X15; X16; X17; X19; X20; - X21; X22; X23] ,, + X21; X22; X23; X24; X25; X26; X27; X28; X29; X30] ,, + MAYCHANGE [Q0; Q1; Q2; Q3; Q4; Q5; Q6; Q7; Q8; Q9; Q10; + Q11; Q12; Q13; Q14; Q15; Q16; Q17; Q18; Q19; Q20; + Q21; Q22; Q23; Q24; Q25; Q26; Q27; Q28; Q29; Q30; Q31] ,, MAYCHANGE SOME_FLAGS ,, MAYCHANGE [memory :> bytes(res,32); - memory :> bytes(stackpointer,320)])`, + memory :> bytes(stackpointer,224)])`, REWRITE_TAC[FORALL_PAIR_THM] THEN MAP_EVERY X_GEN_TAC [`res:int64`; `scalar:int64`; `n_input:num`; `point:int64`; `X_input:num`; @@ -7638,192 +4318,181 @@ let CURVE25519_X25519_BYTE_CORRECT = time prove (*** Setup of the main loop ***) - ENSURES_WHILE_ADOWN_TAC `254` `3` `pc + 0xcd8` `pc + 0x251c` + ENSURES_WHILE_PDOWN_TAC `255` `pc + 0x308` `pc + 0x12fc` `\i s. - read SP s = stackpointer /\ - read X23 s = res /\ - read X20 s = word_sub (word i) (word 1) /\ - bignum_from_memory (stackpointer,4) s = n_input /\ - bignum_from_memory (word_add stackpointer (word 32),4) s = X /\ - read X21 s = word(bitval(ODD(nn DIV 2 EXP i))) /\ - bignum_from_memory(word_add stackpointer (word 64),4) s < 2 * p_25519 /\ - bignum_from_memory(word_add stackpointer (word 160),4) s < 2 * p_25519 /\ - bignum_from_memory(word_add stackpointer (word 224),4) s < 2 * p_25519 /\ - bignum_from_memory(word_add stackpointer (word 288),4) s < 2 * p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - bignum_from_memory(word_add stackpointer (word 64),4) s - MOD p_25519 <= 1 /\ - bignum_from_memory(word_add stackpointer (word 160),4) s - MOD p_25519 = 0 /\ - bignum_from_memory(word_add stackpointer (word 224),4) s - MOD p_25519 = 0 /\ - bignum_from_memory(word_add stackpointer (word 288),4) s - MOD p_25519 <= 1 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P - (if ODD(nn DIV 2 EXP i) - then nn DIV 2 EXP i + 1 else nn DIV 2 EXP i)) - (bignum_from_memory(word_add stackpointer (word 288),4) s, - bignum_from_memory(word_add stackpointer (word 160),4) s) /\ - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P - (if ODD(nn DIV 2 EXP i) - then nn DIV 2 EXP i else nn DIV 2 EXP i + 1)) - (bignum_from_memory(word_add stackpointer (word 224),4) s, - bignum_from_memory(word_add stackpointer (word 64),4) s)` THEN + (read SP s = stackpointer /\ + read (memory :> bytes64(word_add stackpointer (word 192))) s = res /\ + (bignum_from_memory(stackpointer,4) s == nn) (mod (2 EXP 255)) /\ + read Q31 s = word 0x1300000013 /\ + read Q30 s = word 0x3ffffff0000000003ffffff /\ + read Q29 s = word 0x07fffffe07fffffc /\ + read (memory :> bytes64(word_add stackpointer (word 72))) s = + word 0x07fffffe07fffffc /\ + read Q28 s = word 0x07fffffe07ffffb4 /\ + read (memory :> bytes64(word_add stackpointer (word 80))) s = + word 0x07fffffe07ffffb4 /\ + read X0 s = word_sub (word i) (word 1) /\ + read (memory :> bytes64(word_add stackpointer (word 200))) s = + word_sub (word i) (word 1) /\ + read (memory :> bytes64(word_add stackpointer (word 208))) s = + word(bitval(ODD(nn DIV 2 EXP i))) /\ + normalized_ubignum_preglist + [memory :> bytes64 (word_add stackpointer (word 32)); + memory :> bytes64 (word_add stackpointer (word 40)); + memory :> bytes64 (word_add stackpointer (word 48)); + memory :> bytes64 (word_add stackpointer (word 56)); + memory :> bytes64 (word_add stackpointer (word 64))] (&X) s /\ + normalized_ubignum_qreglist[Q0;Q2;Q4;Q6;Q8] (ladder_x2 X nn i) s /\ + normalized_ubignum_qreglist[Q10;Q12;Q14;Q16;Q18] (ladder_x3 X nn i) s /\ + normalized_ubignum_qreglist'[Q1;Q3;Q5;Q7;Q9] (ladder_z2 X nn i) s /\ + normalized_ubignum_qreglist[Q11;Q13;Q15;Q17;Q19] (ladder_z3 X nn i) s) /\ + (read CF s <=> 0 < i)` THEN REPEAT CONJ_TAC THENL [ARITH_TAC; - (*** Initial setup, modification of the inputs and doubling ***) - + MAP_EVERY (fun n -> GHOST_INTRO_TAC + (mk_var("init_q"^string_of_int n,`:int128`)) + (list_mk_icomb "read" [mk_const("Q"^string_of_int n,[])])) (0--31) THEN REWRITE_TAC(!simulation_precanon_thms) THEN ENSURES_INIT_TAC "s0" THEN BYTES_DIGITIZE_TAC "nb_" `read (memory :> bytes (scalar,32)) s0` THEN BYTES_DIGITIZE_TAC "xb_" `read (memory :> bytes (point,32)) s0` THEN - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (1--131) THEN - SUBGOAL_THEN - `bignum_from_memory (stackpointer,4) s131 = n_input /\ - bignum_from_memory (word_add stackpointer (word 32),4) s131 = X /\ - bignum_from_memory(word_add stackpointer (word 224),4) s131 = X /\ - bignum_from_memory(word_add stackpointer (word 64),4) s131 = 1` - STRIP_ASSUME_TAC THENL + ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (1--183) THEN + ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN + CONJ_TAC THENL [CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN - ASM_REWRITE_TAC[] THEN MAP_EVERY EXPAND_TAC ["X"; "X_input"] THEN - MATCH_MP_TAC(TAUT `r /\ q /\ p ==> p /\ q /\ q /\ r`) THEN CONJ_TAC THENL - [REWRITE_TAC[bignum_of_wordlist] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV); - ALL_TAC] THEN + ASM_REWRITE_TAC[] THEN EXPAND_TAC "nn" THEN REWRITE_TAC[CONG] THEN + SIMP_TAC[MOD_LT; ARITH_RULE + `2 EXP 254 + n_input MOD 2 EXP 254 - n_input MOD 8 < 2 EXP 255`] THEN + MATCH_MP_TAC(ARITH_RULE + `m <= b /\ x + m:num = a + b ==> x = a + b - m`) THEN CONJ_TAC THENL - [REWRITE_TAC[ARITH_RULE - `m = n MOD 2 EXP 255 <=> m + 2 EXP 255 * n DIV 2 EXP 255 = n`] THEN - SUBGOAL_THEN - `X_input DIV 2 EXP 255 = bitval(bit 7 (xb_31:byte))` MP_TAC THEN - EXPAND_TAC "X_input" THENL - [REWRITE_TAC[EXP_ADD; GSYM DIV_DIV; ARITH_RULE `255 = 248 + 7`] THEN - REWRITE_TAC[ADD_ASSOC] THEN - SIMP_TAC[DIV_MULT_ADD; EXP_EQ_0; ARITH_EQ] THEN - W(MP_TAC o PART_MATCH (lhand o rand) DIV_LT o - funpow 3 lhand o snd) THEN - ANTS_TAC THENL - [CONV_TAC NUM_REDUCE_CONV THEN BOUNDER_TAC[]; - DISCH_THEN SUBST1_TAC] THEN - REWRITE_TAC[ADD_CLAUSES; BITVAL_ODD; BIT_VAL] THEN - CONV_TAC SYM_CONV THEN MATCH_MP_TAC MOD_LT THEN - REWRITE_TAC[ARITH_RULE `x DIV 2 EXP 7 < 2 <=> x < 256`] THEN - BOUNDER_TAC[]; - DISCH_THEN SUBST1_TAC]; - EXPAND_TAC "n_input"] THEN - REWRITE_TAC[bignum_of_wordlist; val_def] THEN - REWRITE_TAC[DIMINDEX_8; ARITH_RULE `i < 8 <=> 0 <= i /\ i <= 7`] THEN - REWRITE_TAC[DIMINDEX_64; ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN - REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[BIT_WORD_OR; BIT_WORD_AND; BIT_WORD_SHL; BIT_WORD_ZX] THEN - ONCE_REWRITE_TAC[BIT_GUARD] THEN - REWRITE_TAC[DIMINDEX_8; DIMINDEX_32; DIMINDEX_64] THEN - CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN ARITH_TAC; - RULE_ASSUM_TAC(REWRITE_RULE[BIGNUM_FROM_MEMORY_BYTES])] THEN - LOCAL_SUB_TWICE4_TAC 0 ["d"; "xm"; "zm"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["s"; "xm"; "zm"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["zn"; "p"; "e"] THEN - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC [142] THEN - ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - DISCARD_STATE_TAC "s142" THEN - DISCARD_MATCHING_ASSUMPTIONS [`nonoverlapping_modulo a b c`] THEN - CONV_TAC WORD_REDUCE_CONV THEN - SUBGOAL_THEN `X < 2 * p_25519` ASSUME_TAC THENL - [EXPAND_TAC "X" THEN REWRITE_TAC[p_25519] THEN ARITH_TAC; + [REWRITE_TAC[ARITH_RULE `8 = 2 EXP (MIN 254 3)`] THEN + REWRITE_TAC[GSYM MOD_MOD_EXP_MIN; MOD_LE]; + ALL_TAC] THEN + REWRITE_TAC[ARITH_RULE + `x MOD 2 EXP 255 + n MOD 8 = 2 EXP 254 + n MOD 2 EXP 254 <=> + x + 2 EXP 254 * n DIV 2 EXP 254 + n MOD 8 = + 2 EXP 254 + 2 EXP 255 * x DIV 2 EXP 255 + n`] THEN + SUBGOAL_THEN `n_input MOD 8 = val(nb_0:byte) MOD 8` SUBST1_TAC THENL + [EXPAND_TAC "n_input" THEN REWRITE_TAC[GSYM CONG] THEN + MATCH_MP_TAC(NUMBER_RULE + `n divides y ==> (x + y:num == x) (mod n)`) THEN + REPEAT(MATCH_MP_TAC DIVIDES_ADD THEN CONJ_TAC) THEN + MATCH_MP_TAC DIVIDES_RMUL THEN + REWRITE_TAC[DIVIDES_MOD] THEN ARITH_TAC; + ALL_TAC] THEN + SUBGOAL_THEN `n_input DIV 2 EXP 254 = val(nb_31:byte) DIV 2 EXP 6` + SUBST1_TAC THENL + [EXPAND_TAC "n_input" THEN REWRITE_TAC[ADD_ASSOC] THEN + REWRITE_TAC[ARITH_RULE `2 EXP 254 = 2 EXP 248 * 2 EXP 6`] THEN + SIMP_TAC[GSYM DIV_DIV; DIV_MULT_ADD; EXP_EQ_0; ARITH_EQ] THEN + AP_THM_TAC THEN AP_TERM_TAC THEN + SIMP_TAC[EQ_ADD_RCANCEL_0; DIV_EQ_0; EXP_EQ_0; ARITH_EQ] THEN + BOUNDER_TAC[]; + ALL_TAC] THEN + EXPAND_TAC "n_input" THEN + CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN + REWRITE_TAC[bignum_of_wordlist; WORD_BLAST + `val(word_and x (word 18446744073709551608:int64)) = + 8 * val x DIV 8`] THEN + ONCE_REWRITE_TAC[ARITH_RULE `2 EXP 64 * h = 2 EXP 3 * 2 EXP 61 * h`] THEN + SIMP_TAC[DIV_MULT_ADD; EXP_EQ_0; ARITH_EQ] THEN + REWRITE_TAC[WORD_BLAST + `val(word_or n (word 4611686018427387904:int64)) = + 2 EXP 63 * bitval(bit 63 n) + 2 EXP 62 + val(n) MOD 2 EXP 62`] THEN + SIMP_TAC[DIV_MULT_ADD; EXP_EQ_0; ARITH_EQ; DIV_LT; ARITH_RULE + `2 EXP 62 + n MOD 2 EXP 62 < 2 EXP 63`] THEN + CONV_TAC WORD_BLAST; ALL_TAC] THEN - SUBGOAL_THEN `nn DIV 2 EXP 254 = 1` SUBST1_TAC THENL - [EXPAND_TAC "nn" THEN SIMP_TAC[DIV_ADD; DIVIDES_REFL] THEN - SIMP_TAC[DIV_LT; ARITH_RULE `x:num < n ==> x - k < n`; - MOD_LT_EQ; EXP_EQ_0; ARITH_EQ] THEN - CONV_TAC NUM_REDUCE_CONV; + REPEAT(CONJ_TAC THENL [CONV_TAC WORD_BLAST; ALL_TAC]) THEN + SUBGOAL_THEN `nn DIV 2 EXP 255 = 0` SUBST1_TAC THENL + [REWRITE_TAC[DIV_EQ_0] THEN EXPAND_TAC "nn" THEN ARITH_TAC; CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV)] THEN - ASM_REWRITE_TAC[] THEN - CONJ_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC] THEN - SIMP_TAC[GROUP_POW_1] THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o SYM)) THEN - ASM_REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - REPEAT(FIRST_X_ASSUM(MP_TAC o check (is_imp o concl))) THEN - ASM_REWRITE_TAC[] THEN - REPEAT - (ANTS_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; STRIP_TAC]) THEN - STRIP_TAC THEN - DISCARD_MATCHING_ASSUMPTIONS [`a:num < 2 * b`] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - REPEAT(DISCH_THEN(CONJUNCTS_THEN2 ASSUME_TAC MP_TAC)) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_OF_NUM_CLAUSES] THEN - SIMP_TAC[] THEN CONV_TAC INT_REM_DOWN_CONV THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THENL - [DISCH_THEN(K ALL_TAC) THEN REWRITE_TAC[p_25519] THEN - CONV_TAC INT_REDUCE_CONV; + REWRITE_TAC[BITVAL_CLAUSES; normalized_ubignum_preglist'; + normalized_ubignum_preglist] THEN + ASM_REWRITE_TAC[normalized_ubignum_qreglist; normalized_ubignum_qreglist'; + normalized_ubignum_int32list; normalized_ubignum_int32list'; + normalized_ubignum_list; normalized_ubignum_list'; + MAP; ubignum_of_list; INT_CONG_RREM] THEN + REWRITE_TAC[WORD_BLAST + `word_subword (word_insert (h:int128) (0,64) (l:int64):int128) + (0,32):int32 = word_subword l (0,32) /\ + word_subword (word_insert (h:int128) (0,64) (l:int64):int128) + (32,32):int32 = word_subword l (32,32)`] THEN + CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN + REWRITE_TAC[ladder_x2; ladder_z2; ladder_x3; ladder_z3] THEN + REWRITE_TAC[SUB_REFL; flipladder; INT_CONG_REFL; INT_CONG_RREM] THEN + REWRITE_TAC[WORD_BLAST + `word_subword (word_or x (word_shl y 32):int64) (0,32):int32 = + word_zx x /\ + word_subword (word_or (word_and x (word 67108863)) + (word_shl y 32):int64) (32,32):int32 = + word_zx y /\ + word_subword (word_or (word_ushr x 38) + (word_shl y 32):int64) (32,32):int32 = + word_zx y /\ + word_subword (word_or (word_subword (x:int64) (25,26)) + (word_shl y 32):int64) (32,32):int32 = + word_zx y /\ + word_subword (word_or (word_subword (x:int64) (12,26)) + (word_shl y 32):int64) (32,32):int32 = + word_zx y`] THEN + REPEAT CONJ_TAC THEN + TRY(REWRITE_TAC[VAL_WORD_SUBWORD; VAL_WORD_ADD; VAL_WORD_SHL; + VAL_WORD_ZX_GEN; DIMINDEX_64; DIMINDEX_32] THEN + CONV_TAC NUM_REDUCE_CONV THEN ASM BOUNDER_TAC[]) THEN + MATCH_MP_TAC INT_EQ_IMP_CONG THEN + REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN + EXPAND_TAC "X" THEN + REWRITE_TAC[ARITH_RULE + `x = y MOD 2 EXP 255 <=> x + 2 EXP 255 * y DIV 2 EXP 255 = y`] THEN + SUBGOAL_THEN `X_input DIV 2 EXP 255 = val(xb_31:byte) DIV 2 EXP 7` + SUBST1_TAC THENL + [EXPAND_TAC "X_input" THEN REWRITE_TAC[ADD_ASSOC] THEN + REWRITE_TAC[ARITH_RULE `2 EXP 255 = 2 EXP 248 * 2 EXP 7`] THEN + SIMP_TAC[GSYM DIV_DIV; DIV_MULT_ADD; EXP_EQ_0; ARITH_EQ] THEN + AP_THM_TAC THEN AP_TERM_TAC THEN + SIMP_TAC[EQ_ADD_RCANCEL_0; DIV_EQ_0; EXP_EQ_0; ARITH_EQ] THEN + BOUNDER_TAC[]; ALL_TAC] THEN - DISCH_THEN(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ_ALT] - lemma_double_base)) THEN - ASM_REWRITE_TAC[] THEN - MATCH_MP_TAC EQ_IMP THEN AP_TERM_TAC THEN - ASM_REWRITE_TAC[montgomery_xzdouble; curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; + EXPAND_TAC "X_input" THEN + CONV_TAC(ONCE_DEPTH_CONV BIGNUM_OF_WORDLIST_DIV_CONV) THEN + REWRITE_TAC[bignum_of_wordlist] THEN CONV_TAC WORD_BLAST; (*** The main loop invariant for the Montgomery ladder ***) X_GEN_TAC `i:num` THEN STRIP_TAC THEN - GHOST_INTRO_TAC `xn:num` - `bignum_from_memory (word_add stackpointer (word 288),4)` THEN - GHOST_INTRO_TAC `zn:num` - `bignum_from_memory (word_add stackpointer (word 160),4)` THEN - GHOST_INTRO_TAC `xm:num` - `bignum_from_memory (word_add stackpointer (word 224),4)` THEN - GHOST_INTRO_TAC `zm:num` - `bignum_from_memory(word_add stackpointer (word 64),4)` THEN - REWRITE_TAC[WORD_RULE `word_sub (word (i + 1)) (word 1) = word i`] THEN - REWRITE_TAC(!simulation_precanon_thms) THEN ENSURES_INIT_TAC "s0" THEN - LOCAL_SUB_TWICE4_TAC 0 ["dm"; "xm"; "zm"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["sn"; "xn"; "zn"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["dn"; "xn"; "zn"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["sm"; "xm"; "zm"] THEN - LOCAL_MUL_4_TAC 0 ["dmsn"; "sn"; "dm"] THEN + REWRITE_TAC[normalized_ubignum_qreglist; normalized_ubignum_qreglist'; + normalized_ubignum_int32list; normalized_ubignum_int32list'; + normalized_ubignum_list; normalized_ubignum_list'; + normalized_ubignum_preglist; normalized_ubignum_preglist'; + MAP; ALL] THEN + REWRITE_TAC[WORD_RULE `word_sub (word(i + 1)) (word 1) = word i`] THEN + REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THEN ENSURES_INIT_TAC "s0" THEN + + (*** Introduce zero-state abbreviations ***) + + ABBREVIATE_STATE_COMPONENTS_TAC 0 THEN + + (*** Manually simulate and analyze the scalar bit selection ***) + + ABBREV_TAC `n = read (memory :> bytes (stackpointer,8 * 4)) s0` THEN SUBGOAL_THEN `read(memory :> bytes64(word_add stackpointer - (word(8 * val(word_ushr (word i:int64) 6))))) s5 = - word(n_input DIV (2 EXP (64 * i DIV 64)) MOD 2 EXP (64 * 1))` + (word(8 * val(word_ushr (word i:int64) 6))))) s0 = + word(n DIV (2 EXP (64 * i DIV 64)) MOD 2 EXP (64 * 1))` ASSUME_TAC THENL - [EXPAND_TAC "n_input" THEN REWRITE_TAC[GSYM BIGNUM_FROM_MEMORY_BYTES] THEN + [EXPAND_TAC "n" THEN REWRITE_TAC[GSYM BIGNUM_FROM_MEMORY_BYTES] THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_DIV; BIGNUM_FROM_MEMORY_MOD] THEN - ASM_SIMP_TAC[ARITH_RULE `i < 254 ==> MIN (4 - i DIV 64) 1 = 1`] THEN + ASM_SIMP_TAC[ARITH_RULE `i < 255 ==> MIN (4 - i DIV 64) 1 = 1`] THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_SING; WORD_VAL] THEN VAL_INT64_TAC `i:num` THEN ASM_REWRITE_TAC[VAL_WORD_USHR] THEN CONV_TAC NUM_REDUCE_CONV THEN REFL_TAC; ALL_TAC] THEN - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (6--11) THEN + ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (1--7) THEN SUBGOAL_THEN `word_and - (word_jushr (word((n_input DIV 2 EXP (64 * i DIV 64)) MOD 2 EXP 64)) + (word_jushr (word((n DIV 2 EXP (64 * i DIV 64)) MOD 2 EXP 64)) (word i)) (word 1:int64) = word(bitval(ODD(nn DIV 2 EXP i)))` @@ -7839,576 +4508,462 @@ let CURVE25519_X25519_BYTE_CORRECT = time prove REWRITE_TAC[EXP_ADD; GSYM DIV_MOD; ODD_MOD_POW2] THEN MATCH_MP_TAC(TAUT `p /\ (q <=> q') ==> (p /\ q <=> q')`) THEN CONJ_TAC THENL [ARITH_TAC; ALL_TAC] THEN - REWRITE_TAC[GSYM CONG_MOD_2_ALT] THEN - EXPAND_TAC "nn" THEN - SIMP_TAC[DIV_ADD; DIVIDES_EXP_LE_IMP; LT_IMP_LE; ASSUME `i < 254`; - DIV_EXP; EXP_EQ_0; ARITH_EQ] THEN - MATCH_MP_TAC(NUMBER_RULE - `n divides e /\ (y == z) (mod n) ==> (z:num == e + y) (mod n)`) THEN - ASM_REWRITE_TAC[DIVIDES_2; EVEN_EXP; ARITH_EVEN; SUB_EQ_0; NOT_LE] THEN - REWRITE_TAC[ARITH_RULE `2 EXP 254 = 8 * 2 EXP 251`; MOD_MULT_MOD] THEN - REWRITE_TAC[ADD_SUB] THEN - SUBGOAL_THEN `i = 3 + i - 3` SUBST1_TAC THENL - [UNDISCH_TAC `3 <= i` THEN ARITH_TAC; REWRITE_TAC[EXP_ADD]] THEN - REWRITE_TAC[GSYM DIV_DIV; NUM_REDUCE_CONV `2 EXP 3`] THEN - REWRITE_TAC[ARITH_RULE `(8 * n) DIV 8 = n`] THEN - MATCH_MP_TAC CONG_DIV2 THEN - MATCH_MP_TAC CONG_DIVIDES_MODULUS THEN EXISTS_TAC `2 EXP 251` THEN - REWRITE_TAC[CONG_LMOD; CONG_REFL] THEN + REWRITE_TAC[GSYM CONG_MOD_2_ALT] THEN MATCH_MP_TAC CONG_DIV2 THEN + FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (REWRITE_RULE[IMP_CONJ] + CONG_DIVIDES_MODULUS)) THEN REWRITE_TAC[GSYM(ONCE_REWRITE_RULE[MULT_SYM] (CONJUNCT2 EXP))] THEN MATCH_MP_TAC DIVIDES_EXP_LE_IMP THEN - UNDISCH_TAC `i < 254` THEN ARITH_TAC; + UNDISCH_TAC `i < 255` THEN ARITH_TAC; ALL_TAC] THEN - RULE_ASSUM_TAC(REWRITE_RULE[VAL_EQ_0; WORD_SUB_EQ_0; - MESON[VAL_WORD_BITVAL; VAL_EQ; EQ_BITVAL] - `word(bitval b) = word(bitval c) <=> (b <=> c)`]) THEN - LOCAL_MUX_4_TAC 0 ["d"; "dm"; "dn"] THEN - LOCAL_MUX_4_TAC 0 ["s"; "sm"; "sn"] THEN - LOCAL_MUL_4_TAC 0 ["dnsm"; "sm"; "dn"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["dpro"; "dmsn"; "dnsm"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["spro"; "dmsn"; "dnsm"] THEN - LOCAL_SQR_4_TAC 0 ["dpro"; "dpro"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["xm"; "spro"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["zm"; "dpro"; "x"] THEN - LOCAL_MUL_4_TAC 0 ["zn"; "p"; "e"] THEN - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC [28] THEN - FIRST_X_ASSUM(MP_TAC o - check (can (term_match [] `(MAYCHANGE a ,, b) s s'` o concl))) THEN - POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN - DISCH_THEN(fun th -> DISCH_TAC THEN - ENSURES_FINAL_STATE_TAC THEN MP_TAC th) THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - DISCARD_STATE_TAC "s28" THEN - DISCARD_MATCHING_ASSUMPTIONS - [`aligned a b`; `val(word i) = i`; `nonoverlapping_modulo a b c`] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THENL - [REWRITE_TAC[INT_OF_NUM_CLAUSES; INT_OF_NUM_REM] THEN - REWRITE_TAC[ARITH_RULE `b <= 1 <=> b = 0 \/ b = 1`] THEN - REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - REWRITE_TAC[p_25519] THEN CONV_TAC INT_REDUCE_CONV; + RULE_ASSUM_TAC(REWRITE_RULE + [VAL_WORD_SUB_EQ_0; VAL_WORD_BITVAL; EQ_BITVAL]) THEN + RULE_ASSUM_TAC(PURE_ONCE_REWRITE_RULE + [TAUT `read ZF s = p <=> read ZF s = ~ ~ p`]) THEN + ABBREV_TAC + `flip <=> ~(ODD(nn DIV 2 EXP (i + 1)) <=> ODD(nn DIV 2 EXP i))` THEN + + (*** Now simulate all the rest of the inner loop instructions ***) + + ARM_NAMESTEPS_TAC CURVE25519_X25519_BYTE_EXEC (8--1021) THEN + + (*** Also introduce the full abbreviations ***) + + MAP_EVERY ABBREV_TAC abbreviated_variables THEN + + (*** Finish the simulation and throw away machine states ***) + + ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN + ASM_REWRITE_TAC[SIMD_SPLIT_JOIN_CLAUSES; SIMD_MASK_CLAUSES; + EXTRA_SPLIT_JOIN_CLAUSES] THEN + REWRITE_TAC[WORD_BLAST + `word_subword (word_insert (x:int128) (0,64) (y:int64):int128) + (0,32):int32 = + word_subword y (0,32) /\ + word_subword (word_insert (x:int128) (0,64) (y:int64):int128) + (32,32):int32 = + word_subword y (32,32)`] THEN + DISCARD_STATE_TAC "s1021" THEN + + (*** Apply a few standard simplifications eagerly ***) + + RULE_ASSUM_TAC(REWRITE_RULE[extra; SIMD_SPLIT_JOIN_CLAUSES; + ADD_CLAUSES; WORD_RULE `word_add x x = word_mul (word 2) x`]) THEN + RULE_ASSUM_TAC(REWRITE_RULE + [WORD_BLAST + `(word_zx:int64->int32) ((word_zx:int128->int64) x) = + word_subword x (0,32)`]) THEN + RULE_ASSUM_TAC(REWRITE_RULE + [WORD_BLAST + `(word_zx:int64->int32) (word_ushr ((word_zx:int128->int64) x) 32) = + word_subword x (32,32)`]) THEN + RULE_ASSUM_TAC(REWRITE_RULE + [WORD_BLAST + `(word_zx:int64->int32) ((word_zx:int32->int64) x) = word_zx x`]) THEN + + (*** The initial linear and selection blocks ***) + + SUBGOAL_THEN + `(&b:int == &x2 - &z2) (mod &p_25519) /\ + (&d:int == &x3 - &z3) (mod &p_25519) /\ + (&a:int == &x2 + &z2) (mod &p_25519) /\ + (&c:int == &x3 + &z3) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [REPEAT CONJ_TAC THEN ARITHBLOCK_TAC[]; + ALL_TAC] THEN + + SUBGOAL_THEN + `(&f:int == if flip then &c else &a) (mod &p_25519) /\ + (&g:int == if flip then &d else &b) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [REPEAT CONJ_TAC THEN + W(MAP_EVERY (EXPAND_TAC o name_of) o + filter (not o (=) `:bool` o type_of) o frees o snd) THEN + W(MAP_EVERY (EXPAND_TAC o name_of) o + filter (not o (=) `:bool` o type_of) o frees o lhand o rator o snd) THEN + REWRITE_TAC[COND_SWAP] THEN COND_CASES_TAC THEN + REWRITE_TAC[SIMD_SPLIT_JOIN_CLAUSES; GSYM INT_REM_EQ]; ALL_TAC] THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[TAUT - `(ODD n <=> b) <=> (b <=> ODD n)`]) THEN - ABBREV_TAC `n = nn DIV 2 EXP (i + 1)` THEN - ABBREV_TAC `b = ODD(nn DIV 2 EXP i)` THEN - SUBGOAL_THEN `nn DIV 2 EXP i = 2 * n + bitval b` SUBST1_TAC THENL - [MAP_EVERY EXPAND_TAC ["b"; "n"] THEN - REWRITE_TAC[EXP_ADD; GSYM DIV_DIV; BITVAL_ODD] THEN ARITH_TAC; - SIMP_TAC[BITVAL_CLAUSES; ADD_CLAUSES; COND_ID]] THEN - DISCH_TAC THEN + + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC []) ["a"; "b"; "c"; "d"; "f"; "g"] THEN + + (*** aa = f^2 ***) + + SUBGOAL_THEN + `(&aa:int == &f pow 2) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [ARITHBLOCK_TAC[]; + DEDUCE_DIGITBOUNDS_TAC [] "aa"] THEN + + (*** bb = g^2 ***) + + SUBGOAL_THEN + `(&bb:int == &g pow 2) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [ARITHBLOCK_TAC[]; + DEDUCE_DIGITBOUNDS_TAC [] "bb"] THEN + + (*** Alternative form bbalt of bb, proof a bit ad-hoc ***) + + MAP_EVERY (USE_ABBREV (MP_TAC o ASSUME)) ["bbalt"; "bb"] THEN + W(fun (asl,w) -> + let l1 = dest_list(rand(lhand(lhand w))) + and l2 = dest_list(rand(lhand(lhand(rand w)))) in + SUBGOAL_THEN (list_mk_conj(map2 (curry mk_eq) l1 l2)) MP_TAC) + THENL + [W(MAP_EVERY (EXPAND_TAC o name_of) o frees o snd) THEN + REPEAT + (CONJ_TAC THENL + [CONV_TAC(ONCE_DEPTH_CONV VAL_EXPAND_CONV) THEN + CONV_TAC(TOP_DEPTH_CONV (BIT_WORD_CONV o + check (not o can (term_match [] `bit i (word_add x y)`)))) THEN + REWRITE_TAC[BITVAL_CLAUSES] THEN ARITH_TAC; + ALL_TAC]) THEN + REWRITE_TAC[UBIGNUM_PACK_UNPACK_CLAUSES] THEN + REWRITE_TAC[VAL_WORD; VAL_WORD_ADD; VAL_WORD_USHR] THEN + CONV_TAC(ONCE_DEPTH_CONV(!word_SIZE_CONV)) THEN + REPEAT DEMODULATE_TAC THEN MATCH_MP_TAC MOD_LT THEN ASM BOUNDER_TAC[]; + DISCH_THEN(fun th -> + GEN_REWRITE_TAC (LAND_CONV o ONCE_DEPTH_CONV) [th] THEN + DISCH_THEN SUBST1_TAC THEN MP_TAC th THEN + GEN_REWRITE_TAC I [IMP_IMP]) THEN + DISCH_THEN(fun th -> + REPLICATE_TAC 11 (POP_ASSUM MP_TAC) THEN + REWRITE_TAC[IMP_IMP; GSYM CONJ_ASSOC] THEN MP_TAC th) THEN + DISCH_THEN(fun eth -> DISCH_THEN(fun th -> + STRIP_ASSUME_TAC th THEN STRIP_ASSUME_TAC(SUBS(CONJUNCTS eth) th)))] THEN + + (*** e = aa - bb. This is a bit messy with explicit SWAR ***) + + MAP_EVERY (USE_ABBREV + (MP_TAC o AP_TERM `\x. val((word_subword:int64->num#num->int32) x (0,32))` o + ASSUME)) (map (fun n -> "e_"^string_of_int n) (0--9)) THEN + REWRITE_TAC[IMP_IMP; GSYM CONJ_ASSOC] THEN + REWRITE_TAC[WORD_BLAST + `word_subword (word_ushr (x:int64) 32) (0,32):int32 = + word_subword x (32,32)`] THEN + REWRITE_TAC[WORD_SUBWORD_SWAR_0_32] THEN + MAP_EVERY (fun th -> + let f = PART_MATCH (lhand o rand) th in + REPEAT(W(fun (asl,w) -> MP_TAC(f (find_term (can f) (lhand w)))) THEN + ANTS_TAC THENL + [REWRITE_TAC[WORD_SUBWORD_SWAR_0_32; VAL_WORD_ADD; VAL_WORD; + GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM; DIMINDEX_32] THEN + CONV_TAC WORD_REDUCE_CONV THEN REPEAT DEREMULATE_TAC THEN + ASM BOUNDER_TAC[]; + DISCH_THEN SUBST1_TAC])) (rev(CONJUNCTS WORD_SUBWORD_SWAR_32_32)) THEN + CONV_TAC(LAND_CONV WORD_REDUCE_CONV) THEN + GEN_REWRITE_TAC (LAND_CONV o ONCE_DEPTH_CONV) [VAL_EQ] THEN + DISCH_THEN(fun th -> + MAP_EVERY (BOUND_ABBREV_THEN MP_TAC) (CONJUNCTS th) THEN + REPEAT DISCH_TAC THEN ASSUME_TAC th) THEN SUBGOAL_THEN - `(ring_of_num f xm':(int#int),ring_of_num f zm') = - montgomery_xzdiffadd (curve25519x f) - (ring_of_num f X,ring_of_num f 1) - (ring_of_num f xn,ring_of_num f zn) - (ring_of_num f xm,ring_of_num f zm) /\ - (ring_of_num f xn',ring_of_num f zn') = - montgomery_xzdouble (curve25519x f) - (if b <=> ODD n then (ring_of_num f xn,ring_of_num f zn) - else (ring_of_num f xm,ring_of_num f zm))` + `(&e:int == &aa - &bb) (mod &p_25519)` MP_TAC THENL - [COND_CASES_TAC THEN - ASM_REWRITE_TAC[montgomery_xzdiffadd; montgomery_xzdouble; - curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - ASM_REWRITE_TAC[] THEN CONV_TAC INT_REM_DOWN_CONV THEN - REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; - ASM_REWRITE_TAC[] THEN - SIMP_TAC[curve25519x_halfcanonically_represents] THEN - DISCH_THEN(K ALL_TAC) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - FIRST_X_ASSUM(CONJUNCTS_THEN(MP_TAC o last o CONJUNCTS o - GEN_REWRITE_RULE I [curve25519x_halfcanonically_represents])) THEN - GEN_REWRITE_TAC I [GSYM IMP_CONJ_ALT] THEN - FIRST_X_ASSUM(MP_TAC o GEN_REWRITE_RULE I - [curve25519x_halfcanonically_represents]) THEN - DISCH_THEN(CONJUNCTS_THEN2 ASSUME_TAC (MP_TAC o CONJUNCT2)) THEN - UNDISCH_TAC - `P IN group_carrier(curve25519x_group(f:(int#int) ring))`] THEN - SUBGOAL_THEN `~(ring_of_num (f:(int#int) ring) X = ring_0 f)` MP_TAC THENL - [ASM_REWRITE_TAC[RING_OF_NUM_EQ_0; DIVIDES_MOD] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM]; - MAP_EVERY UNDISCH_TAC - [`ring_char(f:(int#int) ring) = p_25519`; `field(f:(int#int) ring)`] THEN - POP_ASSUM_LIST(K ALL_TAC)] THEN - REPEAT DISCH_TAC THEN CONJ_TAC THENL - [DISJ_CASES_THEN SUBST_ALL_TAC - (TAUT `(b <=> ODD n) \/ (b <=> ~ODD n)`) THEN - REWRITE_TAC[TAUT `~(~p <=> p)`] THENL - [FIRST_X_ASSUM(MP_TAC o CONJUNCT1); - FIRST_X_ASSUM(MP_TAC o CONJUNCT2)] THEN - UNDISCH_TAC `P IN group_carrier(curve25519x_group(f:(int#int) ring))` THEN - REWRITE_TAC[IMP_IMP] THEN DISCH_THEN(MP_TAC o MATCH_MP lemma_double) THEN - ASM_REWRITE_TAC[COND_SWAP] THEN COND_CASES_TAC THEN - REWRITE_TAC[ARITH_RULE `(2 * n + 1) + 1 = 2 * (n + 1)`]; - REPEAT(POP_ASSUM MP_TAC) THEN - REWRITE_TAC[IMP_IMP; GSYM CONJ_ASSOC] THEN - COND_CASES_TAC THEN REWRITE_TAC[lemma_diffadd1] THEN - GEN_REWRITE_TAC (LAND_CONV o funpow 5 RAND_CONV) [CONJ_SYM] THEN - REWRITE_TAC[lemma_diffadd2]]; + [W(MAP_EVERY (EXPAND_TAC o name_of) o frees o snd) THEN + FIRST_X_ASSUM(CONJUNCTS_THEN(fun th -> REWRITE_TAC[GSYM th])) THEN + CONV_TAC WORD_REDUCE_CONV THEN + REWRITE_TAC[ubignum_of_list; GSYM INT_OF_NUM_CLAUSES; DIMINDEX_32; + INT_VAL_WORD_SUB; VAL_WORD_ADD; VAL_WORD; GSYM INT_OF_NUM_REM] THEN + CONV_TAC INT_REM_DOWN_CONV THEN REPEAT DEREMULATE_TAC THEN + REWRITE_TAC[REAL_INT_CONGRUENCE; INT_OF_NUM_EQ; p_25519; ARITH_EQ] THEN + REWRITE_TAC[GSYM REAL_OF_INT_CLAUSES] THEN + REAL_INTEGER_TAC; + POP_ASSUM(K ALL_TAC) THEN DISCH_TAC] THEN + + (*** bce = bb + 121666 * e ***) - (*** The trivial loop-back subgoal ***) + SUBGOAL_THEN + `(&bce:int == &bbalt + &121666 * &e) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [ARITHBLOCK_TAC + (map (C SPEC (WORD_BLAST + `!x. (word_zx:int64->int32) x = word_subword x (0,32)`) o + (fun n -> mk_var("e_"^string_of_int n,`:int64`))) (0--9)); + DEDUCE_DIGITBOUNDS_TAC + (map (C SPEC (WORD_BLAST + `!x. (word_zx:int64->int32) x = word_subword x (0,32)`) o + (fun n -> mk_var("e_"^string_of_int n,`:int64`))) (0--9)) "bce"] THEN - REPEAT STRIP_TAC THEN ARM_SIM_TAC CURVE25519_X25519_BYTE_EXEC (1--2) THEN - REWRITE_TAC[COND_RAND; COND_RATOR] THEN - MATCH_MP_TAC(TAUT `p ==> (if p then T else x)`) THEN - MATCH_MP_TAC(WORD_ARITH - `3 < val x /\ val x < 254 ==> 3 <= val(word_sub x (word 1):int64)`) THEN - VAL_INT64_TAC `i:num` THEN ASM_REWRITE_TAC[]; + (*** z4 = bce * e ***) - ALL_TAC] THEN + SUBGOAL_THEN + `(&z4:int == &bce * &e) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [ARITHBLOCK_TAC + (map (C SPEC (WORD_BLAST + `!x. (word_zx:int64->int32) x = word_subword x (0,32)`) o + (fun n -> mk_var("e_"^string_of_int n,`:int64`))) (0--9)); + DEDUCE_DIGITBOUNDS_TAC + (map (C SPEC (WORD_BLAST + `!x. (word_zx:int64->int32) x = word_subword x (0,32)`) o + (fun n -> mk_var("e_"^string_of_int n,`:int64`))) (0--9)) "z4"] THEN - (*** Multiplexing before last doublings ***) - - GHOST_INTRO_TAC `xn:num` - `bignum_from_memory (word_add stackpointer (word 288),4)` THEN - GHOST_INTRO_TAC `zn:num` - `bignum_from_memory (word_add stackpointer (word 160),4)` THEN - GHOST_INTRO_TAC `xm:num` - `bignum_from_memory (word_add stackpointer (word 224),4)` THEN - GHOST_INTRO_TAC `zm:num` - `bignum_from_memory(word_add stackpointer (word 64),4)` THEN - GLOBALIZE_PRECONDITION_TAC THEN - REWRITE_TAC(!simulation_precanon_thms) THEN ENSURES_INIT_TAC "s0" THEN - LOCAL_MUX_4_TAC 3 ["xn"; "xm"; "xn"] THEN - LOCAL_MUX_4_TAC 0 ["zn"; "zm"; "zn"] THEN + (*** bc = b * c and ad = a * d ***) - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM SUBST_ALL_TAC) - [`xn8 = read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s5`; - `zn8 = - read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s5`] THEN - SUBGOAL_THEN - `xn8 < 2 * p_25519 /\ zn8 < 2 * p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - xn8 MOD p_25519 = 0 /\ zn8 MOD p_25519 <= 1 \/ - xn8 MOD p_25519 <= 1 /\ zn8 MOD p_25519 = 0 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P (nn DIV 8)) (xn8,zn8)` - MP_TAC THENL - [ASM_REWRITE_TAC[VAL_WORD_BITVAL; BITVAL_EQ_0; COND_SWAP] THEN - REPLICATE_TAC 2 - (CONJ_TAC THENL [COND_CASES_TAC THEN ASM_REWRITE_TAC[]; ALL_TAC]) THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - REWRITE_TAC[VAL_EQ_0; WORD_SUB_EQ_0; WORD_BITVAL_EQ_0] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THENL [ARITH_TAC; ALL_TAC] THEN - REWRITE_TAC[NUM_REDUCE_CONV `2 EXP 3`] THEN - COND_CASES_TAC THEN ASM_SIMP_TAC[]; - - FIRST_X_ASSUM(K ALL_TAC o check (is_forall o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o check - (fun th -> intersect (frees (concl th)) - [`xm:num`; `xn:num`; `zm:num`; `zn:num`] <> []))) THEN - STRIP_TAC] THEN - - (*** The first doubling to get from nn/8 to nn/4 ***) - - LOCAL_SUB_TWICE4_TAC 0 ["d"; "xn"; "zn"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["s"; "xn"; "zn"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["zn"; "p"; "e"] THEN - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM SUBST_ALL_TAC) - [`xn4 = read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s15`; - `zn4 = - read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s15`] THEN - SUBGOAL_THEN - `xn4 < 2 * p_25519 /\ zn4 < 2 * p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - xn4 MOD p_25519 = 0 /\ zn4 MOD p_25519 <= 1 \/ - xn4 MOD p_25519 <= 1 /\ zn4 MOD p_25519 = 0 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P (2 * nn DIV 8)) (xn4,zn4)` - MP_TAC THENL - [ASM_REWRITE_TAC[] THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THENL - [REWRITE_TAC[ARITH_RULE `n <= 1 <=> n = 0 \/ n = 1`] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC INT_REDUCE_CONV; - ALL_TAC] THEN - REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - DISCH_THEN(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ_ALT] - lemma_double)) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_EQ] THEN MATCH_MP_TAC EQ_IMP THEN - AP_TERM_TAC THEN REWRITE_TAC[PAIR_EQ] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN - ASM_REWRITE_TAC[] THEN - ASM_REWRITE_TAC[montgomery_xzdouble; curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; + SUBGOAL_THEN + `(&bc:int == &b * &c) (mod &p_25519) /\ + (&ad:int == &a * &d) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [CONJ_TAC THEN ARITHBLOCK_TAC[]; + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC []) ["bc"; "ad"]] THEN - FIRST_X_ASSUM(K ALL_TAC o check (is_forall o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o check - (fun th -> intersect (frees (concl th)) - [`xn8:num`; `zn8:num`; `d:num`; `d':num`; - `s:num`; `s':num`; `p:num`; `e:num`] <> []))) THEN - STRIP_TAC] THEN - - (*** The next doubling to get from nn/4 to nn/2 ***) - - LOCAL_SUB_TWICE4_TAC 0 ["d"; "xn"; "zn"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["s"; "xn"; "zn"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["zn"; "p"; "e"] THEN - MAP_EVERY (fun t -> REABBREV_TAC t THEN POP_ASSUM SUBST_ALL_TAC) - [`xn2 = read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s25`; - `zn2 = - read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s25`] THEN - SUBGOAL_THEN - `xn2 < 2 * p_25519 /\ zn2 < 2 * p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - xn2 MOD p_25519 = 0 /\ zn2 MOD p_25519 <= 1 \/ - xn2 MOD p_25519 <= 1 /\ zn2 MOD p_25519 = 0 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P (2 * 2 * nn DIV 8)) (xn2,zn2)` - MP_TAC THENL - [ASM_REWRITE_TAC[] THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN - RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THENL - [REWRITE_TAC[ARITH_RULE `n <= 1 <=> n = 0 \/ n = 1`] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC INT_REDUCE_CONV; - ALL_TAC] THEN - REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - DISCH_THEN(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ_ALT] - lemma_double)) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_EQ] THEN MATCH_MP_TAC EQ_IMP THEN - AP_TERM_TAC THEN REWRITE_TAC[PAIR_EQ] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN - ASM_REWRITE_TAC[] THEN - ASM_REWRITE_TAC[montgomery_xzdouble; curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN - CONV_TAC INT_REM_DOWN_CONV THEN - REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN - REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; + (*** t1 = ad + bc; t2 = ad - bc ***) - FIRST_X_ASSUM(K ALL_TAC o check (is_forall o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o check - (fun th -> intersect (frees (concl th)) - [`xn4:num`; `zn4:num`; `d:num`; `d':num`; - `s:num`; `s':num`; `p:num`; `e:num`] <> []))) THEN - STRIP_TAC] THEN - - (*** The final doubling to get from nn/2 to nn ***) - - LOCAL_SUB_TWICE4_TAC 0 ["d"; "xn"; "zn"] THEN - LOCAL_ADD_TWICE4_TAC 0 ["s"; "xn"; "zn"] THEN - LOCAL_SQR_4_TAC 0 ["d"; "d"] THEN - LOCAL_SQR_4_TAC 0 ["s"; "s"] THEN - LOCAL_SUB_TWICE4_TAC 0 ["p"; "s"; "d"] THEN - LOCAL_CMADD_4_TAC 2 ["e"; "p"; "d"] THEN - LOCAL_MUL_4_TAC 0 ["xn"; "s"; "d"] THEN - LOCAL_MUL_P25519_TAC 0 ["zn"; "p"; "e"] THEN - SUBGOAL_THEN - `xn < 2 * p_25519 /\ zn < p_25519 /\ - !(f:(int#int) ring) P. - field f /\ ring_char f = p_25519 /\ - P IN group_carrier(curve25519x_group f) /\ - curve25519x_halfcanonically_represents f P (X,1) - ==> - if X MOD p_25519 = 0 then - xn MOD p_25519 = 0 /\ zn MOD p_25519 <= 1 \/ - xn MOD p_25519 <= 1 /\ zn MOD p_25519 = 0 - else - curve25519x_halfcanonically_represents f - (group_pow (curve25519x_group f) P (2 * 2 * 2 * nn DIV 8)) (xn,zn)` - MP_TAC THENL - [ASM_REWRITE_TAC[] THEN CONJ_TAC THENL - [REWRITE_TAC[MOD_LT_EQ; p_25519; ARITH_EQ]; ALL_TAC] THEN - MAP_EVERY X_GEN_TAC - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`] THEN - STRIP_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int) ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - RULE_ASSUM_TAC(REWRITE_RULE[EXP_2]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[num_congruent; GSYM INT_OF_NUM_CLAUSES]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ]) THEN - RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_OF_NUM_CLAUSES]) THEN + SUBGOAL_THEN + `(&t1:int == &ad + &bc) (mod &p_25519) /\ + (&t2:int == &ad - &bc) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + (let ths = + map (C SPEC (WORD_BLAST + `!x:int128. word_subword x (0,32):int32 = + word_zx(word_subword x (0,64):int64)`) o + (fun n -> mk_var("ad_"^string_of_int n,`:int128`))) (0--9) @ + map (C SPEC (WORD_BLAST + `!x:int128. word_subword (word_subword x (64,64):int64) (0,32):int32 = + word_zx(word_subword x (64,64):int64)`) o + (fun n -> mk_var("ad_"^string_of_int n,`:int128`))) (0--9) in + [CONJ_TAC THEN ARITHBLOCK_TAC ths; + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC ths) ["t1"; "t2"]]) THEN + + (*** x5 = t1^2; t3 = t2^2 ***) + + SUBGOAL_THEN + `(&x5:int == &t1 pow 2) (mod &p_25519) /\ + (&t3:int == &t2 pow 2) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + [CONJ_TAC THEN ARITHBLOCK_TAC[]; + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC []) ["x5"; "t3"]] THEN + + (*** x4 = aa * bb and z5 = x * t3 ***) + + SUBGOAL_THEN + `(&x4:int == &aa * &bb) (mod &p_25519) /\ + (&z5:int == &x * &t3) (mod &p_25519)` + STRIP_ASSUME_TAC THENL + (let ths = map (C SPEC (WORD_BLAST + `!x:int128. word_subword x (0,32):int32 = + word_zx(word_subword x (0,64):int64)`) o + (fun n -> mk_var("t3_"^string_of_int n,`:int128`))) (0--9) in + [CONJ_TAC THEN ARITHBLOCK_TAC ths; + MAP_EVERY (DEDUCE_DIGITBOUNDS_TAC ths) ["x4"; "z5"]]) THEN + + (*** The odd goal out, the looping criterion ***) + + REWRITE_TAC[CONJ_ASSOC] THEN CONJ_TAC THENL + [REWRITE_TAC[GSYM CONJ_ASSOC]; + VAL_INT64_TAC `i:num` THEN ASM_REWRITE_TAC[] THEN ARITH_TAC] THEN + + (*** Regularize the form of the digits ***) + + REWRITE_TAC(map (C SPEC (WORD_BLAST + `!x:int128. word_subword x (0,32):int32 = + word_zx(word_subword x (0,64):int64)`) o + (fun n -> mk_var("t3_"^string_of_int n,`:int128`))) (0--9)) THEN + REWRITE_TAC[WORD_BLAST + `!x:int128. word_subword (word_subword x (64,64):int64) (0,32):int32 = + word_zx(word_subword x (64,64):int64)`] THEN + REWRITE_TAC[VAL_WORD_ZX_GEN; DIMINDEX_32; DIMINDEX_64] THEN + REPEAT DEMODULATE_TAC THEN ASM_REWRITE_TAC[] THEN + + (*** Separate the bound properties and prove those first ***) + + W(fun (asl,w) -> + let w1,w2 = partition (can (term_match [] `x:num <= b`)) (conjuncts w) in + GEN_REWRITE_TAC I + [CONJ_ACI_RULE(mk_eq(w,mk_conj(list_mk_conj w1,list_mk_conj w2)))]) THEN + CONJ_TAC THENL [REPEAT CONJ_TAC THEN ASM BOUNDER_TAC[]; ALL_TAC] THEN + + (*** Now the main mathematics ***) + + REWRITE_TAC[ladder_x2; ladder_x3; ladder_z2; ladder_z3] THEN + SUBGOAL_THEN `255 - i = ((255 - (i + 1)) + 1)` SUBST1_TAC THENL + [UNDISCH_TAC `i < 255` THEN ARITH_TAC; ALL_TAC] THEN + REWRITE_TAC[flipladder] THEN + LET_TAC THEN CONV_TAC(TOP_DEPTH_CONV let_CONV) THEN + ASM_SIMP_TAC[ARITH_RULE `i < 255 ==> 255 - (255 - (i + 1) + 1) = i`; + ARITH_RULE `i < 255 ==> 255 - (255 - (i + 1)) = i + 1`] THEN + REPEAT(FIRST_X_ASSUM(MP_TAC o check + (can (term_match [] `(x:int == y) (mod &p)`) o concl))) THEN + FIRST_X_ASSUM(fun th -> + MP_TAC(AP_TERM `(FST o FST):(int#int)#(int#int)->int` th) THEN + MP_TAC(AP_TERM `(SND o FST):(int#int)#(int#int)->int` th) THEN + MP_TAC(AP_TERM `(FST o SND):(int#int)#(int#int)->int` th) THEN + MP_TAC(AP_TERM `(SND o SND):(int#int)#(int#int)->int` th)) THEN + REWRITE_TAC[o_THM; GSYM ladder_x2; GSYM ladder_z2; + GSYM ladder_x3; GSYM ladder_z3] THEN + REPLICATE_TAC 4 (DISCH_THEN SUBST1_TAC) THEN + ONCE_REWRITE_TAC[EQ_SYM_EQ] THEN + ONCE_REWRITE_TAC[GSYM COND_SWAP] THEN ASM_REWRITE_TAC[] THEN + POP_ASSUM_LIST(K ALL_TAC) THEN REWRITE_TAC[COND_SWAP] THEN + COND_CASES_TAC THEN REPEAT DISCH_TAC THEN + REWRITE_TAC[curve25519; montgomery_xzdouble; montgomery_xzdiffadd] THEN + REWRITE_TAC[INTEGER_MOD_RING_CLAUSES; A_25519] THEN + CONV_TAC INT_REM_DOWN_CONV THEN + RULE_ASSUM_TAC(REWRITE_RULE + [num_congruent; GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM]) THEN + RULE_ASSUM_TAC(REWRITE_RULE[GSYM INT_REM_EQ]) THEN RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_SUB_REM; GSYM INT_ADD_REM]) THEN RULE_ASSUM_TAC(ONCE_REWRITE_RULE[GSYM INT_POW_REM; GSYM INT_MUL_REM]) THEN - ONCE_REWRITE_TAC[GSYM MOD_MULT_MOD2] THENL - [REWRITE_TAC[ARITH_RULE `n <= 1 <=> n = 0 \/ n = 1`] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES; GSYM INT_OF_NUM_REM] THEN - STRIP_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC INT_REDUCE_CONV; - ALL_TAC] THEN - REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(TAUT `q /\ (p ==> r) ==> p ==> q /\ r`) THEN - CONJ_TAC THENL - [REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN - MATCH_MP_TAC(ARITH_RULE `x < p ==> x < 2 * p`) THEN - REWRITE_TAC[MOD_LT_EQ; p_25519; ARITH_EQ]; - ALL_TAC] THEN - DISCH_THEN(MP_TAC o MATCH_MP (ONCE_REWRITE_RULE[IMP_CONJ_ALT] - lemma_double)) THEN - ASM_REWRITE_TAC[GSYM INT_OF_NUM_EQ] THEN MATCH_MP_TAC EQ_IMP THEN - AP_TERM_TAC THEN REWRITE_TAC[PAIR_EQ] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_INT_REM] THEN - ASM_REWRITE_TAC[] THEN - ASM_REWRITE_TAC[montgomery_xzdouble; curve25519x; PAIR_EQ] THEN - REWRITE_TAC[GSYM RING_OF_INT_OF_NUM; RING_OF_INT_CLAUSES] THEN - ASM_REWRITE_TAC[RING_OF_INT_EQ] THEN - REWRITE_TAC[GSYM INT_OF_NUM_REM; GSYM INT_REM_EQ; - GSYM INT_OF_NUM_CLAUSES] THEN + ASM_REWRITE_TAC[GSYM INT_REM_EQ] THEN CONV_TAC INT_REM_DOWN_CONV THEN ASM_REWRITE_TAC[] THEN CONV_TAC INT_REM_DOWN_CONV THEN REPEAT CONJ_TAC THEN AP_THM_TAC THEN AP_TERM_TAC THEN REWRITE_TAC[A_25519] THEN INT_ARITH_TAC; - FIRST_X_ASSUM(K ALL_TAC o check (is_forall o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o check - (fun th -> intersect (frees (concl th)) - [`xn2:num`; `zn2:num`; `d:num`; `d':num`; - `s:num`; `s':num`; `p:num`; `e:num`] <> []))) THEN - STRIP_TAC] THEN - - (*** Clean up final goal and observe that we've reached nn ***) - - SUBGOAL_THEN `2 * 2 * 2 * nn DIV 8 = nn` SUBST_ALL_TAC THENL - [REWRITE_TAC[ARITH_RULE `2 * 2 * 2 * nn DIV 8 = nn <=> nn MOD 8 = 0`] THEN - EXPAND_TAC "nn" THEN - REWRITE_TAC[ARITH_RULE `2 EXP 254 = 8 * 2 EXP 251`; MOD_MULT_MOD] THEN - REWRITE_TAC[ADD_SUB; GSYM LEFT_ADD_DISTRIB; MOD_MULT]; - ALL_TAC] THEN - SUBGOAL_THEN `X < 2 * p_25519` ASSUME_TAC THENL - [FIRST_X_ASSUM(MP_TAC o MATCH_MP (ARITH_RULE - `Y MOD 2 EXP 255 = X ==> X < 2 EXP 255`)) THEN - REWRITE_TAC[p_25519] THEN ARITH_TAC; + (*** The trivial loop-back subgoal ***) + + REPEAT STRIP_TAC THEN + REWRITE_TAC[normalized_ubignum_preglist; normalized_ubignum_preglist'; + normalized_ubignum_qreglist; normalized_ubignum_qreglist'; + normalized_ubignum_int32list; normalized_ubignum_int32list'; + normalized_ubignum_list; normalized_ubignum_list'; + MAP; ubignum_of_list] THEN + ARM_SIM_TAC CURVE25519_X25519_BYTE_EXEC [1]; + ALL_TAC] THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o - check (vfree_in `n_input:num`) o concl)) THEN - REPEAT(FIRST_X_ASSUM(K ALL_TAC o - check (vfree_in `X_input:num`) o concl)) THEN + (*** Now the final recoding, inversion and multiplication ***) + + REWRITE_TAC[normalized_ubignum_qreglist; normalized_ubignum_qreglist'; + normalized_ubignum_int32list; normalized_ubignum_int32list'; + normalized_ubignum_list; normalized_ubignum_list'; + LT_REFL; MAP; ubignum_of_list] THEN + GHOST_INTRO_TAC `q0:int128` `read Q0` THEN + GHOST_INTRO_TAC `q1:int128` `read Q1` THEN + GHOST_INTRO_TAC `q2:int128` `read Q2` THEN + GHOST_INTRO_TAC `q3:int128` `read Q3` THEN + GHOST_INTRO_TAC `q4:int128` `read Q4` THEN + GHOST_INTRO_TAC `q5:int128` `read Q5` THEN + GHOST_INTRO_TAC `q6:int128` `read Q6` THEN + GHOST_INTRO_TAC `q7:int128` `read Q7` THEN + GHOST_INTRO_TAC `q8:int128` `read Q8` THEN + GHOST_INTRO_TAC `q9:int128` `read Q9` THEN + REWRITE_TAC(!simulation_precanon_thms) THEN ENSURES_INIT_TAC "s0" THEN - (*** The inlining of modular inverse ***) + (*** Recoding of X2 -> xn ***) - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (36--37) THEN - LOCAL_MODINV_TAC 38 THEN - FIRST_X_ASSUM(ASSUME_TAC o MATCH_MP(MESON[PRIME_COPRIME_EQ; PRIME_P25519] - `(bnx = if p_25519 divides n then 0 else inverse_mod p_25519 n) - ==> coprime(p_25519,n) ==> bnx = inverse_mod p_25519 n`)) THEN + ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC + [12;13;14;15;16;17;18;20;21;23;24;26] (1--28) THEN + SUBGOAL_THEN + `(&(bignum_from_memory(word_add stackpointer (word 128),4) s28):int == + ladder_x2 X nn 0) (mod (&p_25519))` + MP_TAC THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THENL + [CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN + FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INTEGER_RULE + `(x:int == n) (mod p) ==> x' = x ==> (x':int == n) (mod p)`)) THEN + REWRITE_TAC[INT_OF_NUM_CLAUSES] THEN + MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN + CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN + CONJ_TAC THENL [ASM BOUNDER_TAC[]; ALL_TAC] THEN + REWRITE_TAC[REAL_CONGRUENCE; EXP_EQ_0; ARITH_EQ] THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN + REWRITE_TAC[VAL_WORD_SHL; VAL_WORD_ZX_GEN; DIMINDEX_64] THEN + REPEAT DEMODULATE_TAC THEN + REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + REWRITE_TAC[REAL_OF_NUM_MOD; GSYM REAL_OF_NUM_CLAUSES] THEN + STRIP_TAC THEN + ACCUMULATOR_ASSUM_LIST(fun ths -> ASSUM_LIST (fun thc -> + MP_TAC(end_itlist CONJ (GEN_DECARRY_RULE thc ths)))) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; + ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN ABBREV_TAC - `zn' = - read(memory :> bytes(word_add stackpointer (word 224),8 * 4)) s38` THEN - - (*** The tweaking to force xn = 0 whenever zn = 0 ***) + `x2 = + read(memory :> bytes(word_add stackpointer (word 128),8 * 4)) s28` THEN + DISCH_TAC THEN - BIGNUM_LDIGITIZE_TAC "xn_" - `read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s38` THEN - BIGNUM_LDIGITIZE_TAC "zn_" - `read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s38` THEN - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (39--52) THEN + (*** Recoding of Z2 -> zn, similar but slightly more elaborate ***) + ARM_ACCSTEPS_TAC CURVE25519_X25519_BYTE_EXEC + [40;42;44;46;47;48;49;50;52;53;55;56;58] (29--60) THEN SUBGOAL_THEN - `read(memory :> bytes(word_add stackpointer (word 288),8 * 4)) s52 = - if zn = 0 then 0 else xn` - ASSUME_TAC THENL - [CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN - ASM_REWRITE_TAC[] THEN MAP_EVERY EXPAND_TAC ["zn"; "xn"] THEN - REWRITE_TAC[WORD_SUB_0; VAL_EQ_0; WORD_OR_EQ_0] THEN - REWRITE_TAC[BIGNUM_OF_WORDLIST_EQ_0; ALL] THEN - REWRITE_TAC[COND_SWAP; CONJ_ACI] THEN - COND_CASES_TAC THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[bignum_of_wordlist] THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV); - ALL_TAC] THEN + `(&(bignum_from_memory(word_add stackpointer (word 160),4) s60):int == + ladder_z2 X nn 0) (mod (&p_25519))` + MP_TAC THEN REWRITE_TAC[BIGNUM_FROM_MEMORY_BYTES] THENL + [CONV_TAC(ONCE_DEPTH_CONV BIGNUM_LEXPAND_CONV) THEN ASM_REWRITE_TAC[] THEN + FIRST_X_ASSUM(MATCH_MP_TAC o MATCH_MP (INTEGER_RULE + `(x:int == n) (mod p) + ==> (x' == x) (mod p) ==> (x':int == n) (mod p)`)) THEN + REWRITE_TAC[INT_OF_NUM_CLAUSES; GSYM num_congruent] THEN + MP_TAC(SPEC `word_subword (q9:int128) (32,32):int32` (WORD_BLAST + `!x:int32. val x <= 67108863 + ==> val x = 2 EXP 25 * bitval(bit 25 x) + val x MOD 2 EXP 25`)) THEN + ASM_REWRITE_TAC[] THEN DISCH_THEN SUBST1_TAC THEN + MATCH_MP_TAC(NUMBER_RULE `!d:num. x + d * p = y ==> (x == y) (mod p)`) THEN + EXISTS_TAC `bitval(bit 25 (word_subword (q9:int128) (32,32):int32))` THEN + REWRITE_TAC[ADD_ASSOC] THEN MATCH_MP_TAC(ARITH_RULE + `b * 2 EXP 255 = b * p_25519 + b * 19 /\ + x = y + 2 EXP 230 * c + 19 * b + ==> x + b * p_25519 = y + 2 EXP 230 * (2 EXP 25 * b + c)`) THEN + CONJ_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC] THEN + REWRITE_TAC[GSYM ADD_ASSOC] THEN + MATCH_MP_TAC CONG_IMP_EQ THEN EXISTS_TAC `2 EXP 256` THEN + CONJ_TAC THENL [BOUNDER_TAC[]; ALL_TAC] THEN + CONJ_TAC THENL [ASM BOUNDER_TAC[]; ALL_TAC] THEN + REWRITE_TAC[REAL_CONGRUENCE; EXP_EQ_0; ARITH_EQ] THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o rev) THEN + REWRITE_TAC[VAL_WORD_SHL; WORD_BLAST + `val(word_and x (word 33554431):int64) = val x MOD 2 EXP 25`] THEN + REWRITE_TAC[WORD_BLAST + `val(word_and (word_zx (x:int32)) (word 33554432):int64) = + 2 EXP 25 * bitval(bit 25 x)`] THEN + REWRITE_TAC[MULT_EQ_0; EXP_EQ_0; BITVAL_EQ_0; ARITH_EQ] THEN + REWRITE_TAC[VAL_WORD_SHL; VAL_WORD_ZX_GEN; DIMINDEX_64] THEN + REPEAT DEMODULATE_TAC THEN + REWRITE_TAC[bignum_of_wordlist; GSYM REAL_OF_NUM_CLAUSES] THEN + REWRITE_TAC[REAL_OF_NUM_MOD; GSYM REAL_OF_NUM_CLAUSES] THEN + COND_CASES_TAC THEN ASM_REWRITE_TAC[BITVAL_CLAUSES] THEN + CONV_TAC WORD_REDUCE_CONV THEN + STRIP_TAC THEN + ACCUMULATOR_ASSUM_LIST(MP_TAC o end_itlist CONJ o DESUM_RULE) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN + CONV_TAC(RAND_CONV REAL_POLY_CONV) THEN + ACCUMULATOR_POP_ASSUM_LIST(MP_TAC o end_itlist CONJ o DECARRY_RULE) THEN + DISCH_THEN(MP_TAC o end_itlist CONJ o + filter (is_ratconst o rand o concl) o CONJUNCTS) THEN + DISCH_THEN(fun th -> REWRITE_TAC[th]) THEN REAL_INTEGER_TAC; + ACCUMULATOR_POP_ASSUM_LIST(K ALL_TAC)] THEN + ABBREV_TAC + `z2 = + read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s60` THEN + DISCH_TAC THEN + + (*** Inlined modular inverse ***) + + ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (61--62) THEN + LOCAL_MODINV_TAC 63 THEN + ABBREV_TAC + `zn' = + read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s63` THEN - (*** Final multiplication ***) + (*** Inlined final field multiplication ***) - LOCAL_MUL_P25519_TAC 0 ["zn"; "xn"; "xm"] THEN + LOCAL_MUL_P25519_TAC 0 ["zn"; "xn"; "zn"] THEN - (*** Bytewise store and finish of simulation ***) + (*** Bytewise store to the output ***) BIGNUM_LDIGITIZE_TAC "res_" - `read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s53` THEN - ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (54--115) THEN + `read(memory :> bytes(word_add stackpointer (word 160),8 * 4)) s64` THEN + ARM_STEPS_TAC CURVE25519_X25519_BYTE_EXEC (65--127) THEN ENSURES_FINAL_STATE_TAC THEN ASM_REWRITE_TAC[] THEN - TRANS_TAC EQ_TRANS `zn'':num` THEN CONJ_TAC THENL - [CONV_TAC(LAND_CONV BYTES_EXPAND_CONV) THEN EXPAND_TAC "zn''" THEN + TRANS_TAC EQ_TRANS `zn:num` THEN CONJ_TAC THENL + [CONV_TAC(LAND_CONV BYTES_EXPAND_CONV) THEN EXPAND_TAC "zn" THEN REWRITE_TAC[bignum_of_wordlist] THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[bignum_of_wordlist; val_def] THEN - REWRITE_TAC[DIMINDEX_8; ARITH_RULE `i < 8 <=> 0 <= i /\ i <= 7`] THEN - REWRITE_TAC[DIMINDEX_64; ARITH_RULE `i < 64 <=> 0 <= i /\ i <= 63`] THEN - REWRITE_TAC[GSYM IN_NUMSEG; IN_GSPEC] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[BIT_WORD_USHR; BIT_WORD_ZX] THEN - REWRITE_TAC[DIMINDEX_8; DIMINDEX_32; DIMINDEX_64] THEN - CONV_TAC(ONCE_DEPTH_CONV EXPAND_NSUM_CONV) THEN - CONV_TAC(DEPTH_CONV WORD_NUM_RED_CONV) THEN ARITH_TAC; - ASM_REWRITE_TAC[]] THEN - - (*** Completing the mathematics ***) - - CONV_TAC SYM_CONV THEN MATCH_MP_TAC PUREX25519_UNIQUE_IMP THEN - CONJ_TAC THENL [REWRITE_TAC[MOD_LT_EQ; p_25519] THEN ARITH_TAC; ALL_TAC] THEN - MAP_EVERY X_GEN_TAC [`f:(int#int)ring`; `P:((int#int)#(int#int))option`] THEN - - ASM_CASES_TAC `X MOD p_25519 = 0` THEN - ASM_REWRITE_TAC[RING_OF_NUM_0] THEN STRIP_TAC THENL - [MP_TAC(ISPECL - [`f:(int#int)ring`; `ring_of_num f A_25519:int#int`; - `ring_of_num f 1:int#int`; `P:((int#int)#(int#int))option`; - `nn:num`] MONTGOMERY_XMAP_EQ_0_POW) THEN - ASM_REWRITE_TAC[GSYM curve25519x_group; GSYM curve25519x] THEN - ASM_SIMP_TAC[MONTGOMERY_NONSINGULAR_CURVE25519X; RING_OF_NUM] THEN - ANTS_TAC THENL [REWRITE_TAC[p_25519] THEN ARITH_TAC; ALL_TAC] THEN - DISCH_THEN SUBST1_TAC THEN FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int)ring`; `SOME(ring_0 f:int#int,ring_0 f)`]) THEN - ASM_REWRITE_TAC[] THEN ANTS_TAC THENL - [REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - ASM_SIMP_TAC[CURVE25519X_GROUP; montgomery_xz] THEN - GEN_REWRITE_TAC LAND_CONV [IN] THEN - REWRITE_TAC[montgomery_curve; RING_OF_NUM; curve25519x] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_NUM_MOD] THEN ASM_REWRITE_TAC[] THEN - REWRITE_TAC[p_25519; A_25519] THEN CONV_TAC NUM_REDUCE_CONV THEN - ASM_SIMP_TAC[RING_OF_NUM_1; RING_OF_NUM_0; FIELD_NONTRIVIAL; RING_0] THEN - UNDISCH_TAC `field(f:(int#int)ring)` THEN POP_ASSUM_LIST(K ALL_TAC) THEN - REPEAT STRIP_TAC THEN FIELD_TAC; - ASM_SIMP_TAC[MOD_LT]] THEN - COND_CASES_TAC THEN - ASM_REWRITE_TAC[MOD_0; RING_OF_NUM_0; MULT_CLAUSES] THEN - ONCE_REWRITE_TAC[GSYM MOD_MULT_MOD2] THEN - SIMP_TAC[MOD_0; RING_OF_NUM_0; MULT_CLAUSES]; + REWRITE_TAC[bignum_of_wordlist] THEN CONV_TAC WORD_BLAST; ALL_TAC] THEN - FIRST_X_ASSUM(MP_TAC o SPECL - [`f:(int#int)ring`; `P:((int#int)#(int#int))option`]) THEN - ASM_REWRITE_TAC[] THEN ANTS_TAC THENL - [ASM_REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV THEN - REWRITE_TAC[RING_OF_NUM_1] THEN - W(MP_TAC o PART_MATCH (lhand o rand) MONTGOMERY_XZ_XMAP o snd) THEN - ASM_REWRITE_TAC[RING_OF_NUM] THEN - ONCE_REWRITE_TAC[GSYM RING_OF_NUM_MOD] THEN - ASM_REWRITE_TAC[MOD_MOD_REFL] THEN - DISCH_THEN MATCH_MP_TAC THEN - ASM_REWRITE_TAC[RING_OF_NUM_EQ_0; DIVIDES_MOD] THEN - ASM_SIMP_TAC[MOD_LT; MOD_MOD_REFL]; - ALL_TAC] THEN + (*** Completing the mathematics ***) - REWRITE_TAC[curve25519x_halfcanonically_represents] THEN - REPEAT(DISCH_THEN(CONJUNCTS_THEN2 ASSUME_TAC MP_TAC)) THEN - FIRST_X_ASSUM(MP_TAC o SPEC `nn:num` o MATCH_MP GROUP_POW) THEN - SPEC_TAC(`group_pow (curve25519x_group(f:(int#int)ring)) P nn`, - `Q:((int#int)#(int#int))option`) THEN - REWRITE_TAC[FORALL_OPTION_THM] THEN - GEN_REWRITE_TAC RAND_CONV [FORALL_PAIR_THM] THEN - REWRITE_TAC[montgomery_xz; montgomery_xmap] THEN - ASM_SIMP_TAC[RING_OF_NUM_EQ_0; DIVIDES_MOD; MOD_LT] THEN - REWRITE_TAC[RING_OF_NUM] THEN ONCE_REWRITE_TAC[IN] THEN - ASM_SIMP_TAC[CURVE25519X_GROUP] THEN - REWRITE_TAC[montgomery_curve; curve25519x] THEN - SIMP_TAC[MULT_CLAUSES; MOD_0; RING_OF_NUM_0] THEN - MAP_EVERY X_GEN_TAC [`u:int#int`; `v:int#int`] THEN - STRIP_TAC THEN - DISCH_THEN(CONJUNCTS_THEN2 ASSUME_TAC (SUBST1_TAC o SYM)) THEN - MP_TAC(ISPEC `f:(int#int)ring` RING_OF_NUM_MOD) THEN - ASM_SIMP_TAC[RING_OF_NUM_MUL] THEN DISCH_THEN(K ALL_TAC) THEN - REWRITE_TAC[ring_div] THEN AP_TERM_TAC THEN - MATCH_MP_TAC RING_RINV_UNIQUE THEN - REWRITE_TAC[RING_OF_NUM; GSYM RING_OF_NUM_MUL] THEN - REWRITE_TAC[GSYM RING_OF_NUM_1; RING_OF_NUM_EQ] THEN - FIRST_X_ASSUM(MP_TAC o check (is_imp o concl)) THEN - ASM_REWRITE_TAC[] THEN - MATCH_MP_TAC(TAUT `(p /\ q ==> r) /\ p ==> (p ==> q) ==> r`) THEN - CONJ_TAC THENL [MESON_TAC[INVERSE_MOD_RMUL]; ALL_TAC] THEN - SIMP_TAC[PRIME_COPRIME_EQ; PRIME_P25519] THEN - ASM_SIMP_TAC[DIVIDES_MOD; MOD_LT] THEN - REWRITE_TAC[p_25519] THEN CONV_TAC NUM_REDUCE_CONV);; + CONV_TAC SYM_CONV THEN REWRITE_TAC[PUREX25519_MOD] THEN + ASM_REWRITE_TAC[GSYM deproject] THEN MATCH_MP_TAC DEPROJECT_LADDER_EVEN THEN + ASM_REWRITE_TAC[] THEN EXPAND_TAC "nn" THEN + CONJ_TAC THENL [ARITH_TAC; ALL_TAC] THEN + SIMP_TAC[EVEN_ADD; EVEN_SUB; EVEN_EXP; ARITH; EVEN_MOD_EVEN]);; let CURVE25519_X25519_BYTE_SUBROUTINE_CORRECT = time prove (`!res scalar n point X pc stackpointer returnaddress. aligned 16 stackpointer /\ - ALL (nonoverlapping (word_sub stackpointer (word 368),368)) - [(word pc,0x59e4); (res,32); (scalar,32); (point,32)] /\ - nonoverlapping (res,32) (word pc,0x59e4) + ALL (nonoverlapping (word_sub stackpointer (word 384),384)) + [(word pc,0x27f8); (res,32); (scalar,32); (point,32)] /\ + nonoverlapping (res,32) (word pc,0x27f8) ==> ensures arm (\s. aligned_bytes_loaded s (word pc) curve25519_x25519_byte_mc /\ read PC s = word pc /\ @@ -8421,7 +4976,8 @@ let CURVE25519_X25519_BYTE_SUBROUTINE_CORRECT = time prove read (memory :> bytes(res,32)) s = rfcx25519(n,X)) (MAYCHANGE_REGS_AND_FLAGS_PERMITTED_BY_ABI ,, MAYCHANGE [memory :> bytes(res,32); - memory :> bytes(word_sub stackpointer (word 368),368)])`, + memory :> bytes(word_sub stackpointer (word 384),384)])`, ARM_ADD_RETURN_STACK_TAC CURVE25519_X25519_BYTE_EXEC CURVE25519_X25519_BYTE_CORRECT - `[X19; X20; X21; X22; X23; X24]` 368);; + `[D8; D9; D10; D11; D12; D13; D14; D15; + X19; X20; X21; X22; X23; X24; X25; X26; X27; X28; X29; X30]` 384);;