warnings.txt

# Amazon FPGA Hardware Development Kit
#
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WARNING: [Constraints 18-838] Failed to create SRL placer macro for cell SH/SH/MGT_TOP 
CRITICAL WARNING: [Place 30-823] Failed to process clock nets that should have matching clock routes. Reason: Found incompatible user defined or fixed clock roots for related clocks 'CL/SH_DR/ddr_cores.DDR4'
CRITICAL WARNING: [Constraints 18-850] Failed to place register with ASYNC_REG property shape that starts with register SH/SH/MGT_TOP/SH_ILA_0/inst/ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg0_reg.
CRITICAL WARNING: [Constraints 18-850] Failed to place register with ASYNC_REG property shape that starts with register SH/SH/MGT_TOP/SH_ILA_0/inst/ila_core_inst/capture_qual_ctrl_2_reg[0]/
CRITICAL WARNING: [Constraints 18-850] Failed to place register with ASYNC_REG property shape that starts with register SH/SH/MGT_TOP/SH_ILA_0/inst/ila_core_inst/en_adv_trigger_2_reg.
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [DRC RPBF-3] IO port buffering **** no input & output bufferring.
WARNING: [Place 46-14] The placer has determined that this design is highly congested and may have difficulty routing. Run report_design_analysis -congestion for a detailed report.
WARNING: [BD 41-1661] 
WARNING: [Vivado 12-584] No ports matched 'tck'
WARNING: [Vivado 12-830] No fanout objects found