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model_list
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model_list
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#a Copyright
#
# This file 'model_list' copyright Gavin J Stark 2016, 2017
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# @file model_list
# @brief Description of modules/models for CDL building
#
# Standard CDL descriptor file, to enable building/linking of verilog and C sims
# with python simulation library
#
cdl_options ass:on
c_model cmodel/src srams
c_model cmodel/src axi_master inc:cmodel/inc
c_model cmodel/src axi4s32_master_slave inc:cmodel/inc
c_src cmodel/src ef_object inc:cmodel/inc
c_src cmodel/src axi_types inc:cmodel/inc
c_model cmodel/src bbc_display inc:cmodel/inc
c_model cmodel/src bbc_floppy inc:cmodel/inc
c_src cmodel/src bbc_floppy_disk inc:cmodel/inc
c_src cmodel/src image_io inc:cmodel/inc
c_src cmodel/src fb inc:cmodel/inc
c_src cmodel/src vnc_rfb inc:cmodel/inc
#c_src cmodel/src bbc_display_vnc inc:cmodel/inc
c_src cmodel/src bbc_shm inc:cmodel/inc
c_model cmodel/src chk_riscv_ifetch inc:cmodel/inc
c_model cmodel/src chk_riscv_trace inc:cmodel/inc
cdl cdl/technology/src tech_sync_flop inc:cdl/inc
cdl cdl/technology/src tech_sync_bit inc:cdl/inc
cdl cdl/utils/src clock_divider inc:cdl/inc
cdl cdl/utils/src async_reduce2_4_28_r inc:cdl/inc inc:cdl/utils/src dc:input_width=4 dc:output_width=28 dc:shift_right=1 dc:double_sr=1 rmn:generic_async_reduce=async_reduce2_4_28_r
cdl cdl/utils/src async_reduce2_4_28_l inc:cdl/inc inc:cdl/utils/src dc:input_width=4 dc:output_width=28 dc:shift_right=0 dc:double_sr=1 rmn:generic_async_reduce=async_reduce2_4_28_l
cdl cdl/utils/src async_reduce_4_28_r inc:cdl/inc inc:cdl/utils/src dc:input_width=4 dc:output_width=28 dc:shift_right=1 rmn:generic_async_reduce=async_reduce_4_28_r
cdl cdl/utils/src async_reduce_4_28_l inc:cdl/inc inc:cdl/utils/src dc:input_width=4 dc:output_width=28 dc:shift_right=0 rmn:generic_async_reduce=async_reduce_4_28_l
cdl cdl/utils/src async_reduce_4_60_r inc:cdl/inc inc:cdl/utils/src dc:input_width=4 dc:output_width=60 dc:shift_right=1 rmn:generic_async_reduce=async_reduce_4_60_r
cdl cdl/utils/src async_reduce_4_60_l inc:cdl/inc inc:cdl/utils/src dc:input_width=4 dc:output_width=60 dc:shift_right=0 rmn:generic_async_reduce=async_reduce_4_60_l
cdl cdl/utils/src hysteresis_switch inc:cdl/inc
cdl cdl/utils/src dprintf inc:cdl/inc
cdl cdl/utils/tb_src tb_hysteresis_switch inc:cdl/inc
cdl cdl/utils/src dprintf_2_mux inc:cdl/inc inc:cdl/utils/src rmt:gt_generic_valid_req=t_dprintf_req_2 rmn:generic_valid_ack_mux=dprintf_2_mux
cdl cdl/utils/src dprintf_4_mux inc:cdl/inc inc:cdl/utils/src rmt:gt_generic_valid_req=t_dprintf_req_4 rmn:generic_valid_ack_mux=dprintf_4_mux
cdl cdl/utils/src dprintf_2_fifo_4 inc:cdl/inc inc:cdl/utils/src rmt:gt_generic_valid_req=t_dprintf_req_2 rmn:generic_valid_ack_fifo=dprintf_2_fifo_4 dc:fifo_depth=3
cdl cdl/utils/src dprintf_4_fifo_4 inc:cdl/inc inc:cdl/utils/src rmt:gt_generic_valid_req=t_dprintf_req_4 rmn:generic_valid_ack_fifo=dprintf_4_fifo_4 dc:fifo_depth=3
cdl cdl/utils/src dprintf_4_async inc:cdl/inc inc:cdl/utils/src rmt:gt_generic_valid_req=t_dprintf_req_4 rmn:generic_valid_ack_async_slow=dprintf_4_async
cdl cdl/utils/src dprintf_4_fifo_512 inc:cdl/inc inc:cdl/utils/src rmt:gt_generic_valid_req=t_dprintf_req_4 rmn:generic_valid_ack_sram_fifo=dprintf_4_fifo_512 rit:generic_valid_ack_sram_fifo.generic_valid_ack_dpsram=dprintf_4_dp_sram_512 dc:fifo_depth=512
cdl cdl/utils/src dprintf_4_dp_sram_512 inc:cdl/inc inc:cdl/utils/src
cdl cdl/utils/tb_src tb_dprintf inc:cdl/inc
cdl cdl/utils/tb_src tb_dprintf_mux inc:cdl/inc
cdl cdl/analyzer/src analyzer_async_data_slow_to_fast inc:cdl/inc
cdl cdl/analyzer/src analyzer_target inc:cdl/inc
cdl cdl/analyzer/src analyzer_target_stub inc:cdl/inc
cdl cdl/analyzer/src analyzer_mux_2 inc:cdl/inc rit:analyzer_mux_2.analyzer_mux_8=analyzer_mux_8_e2
cdl cdl/analyzer/src analyzer_mux_8_e2 inc:cdl/inc inc:cdl/analyzer/src dc:analyzer_config_num_targets=2 rmn:analyzer_mux_8=analyzer_mux_8_e2
cdl cdl/analyzer/src analyzer_mux_8 inc:cdl/inc
cdl cdl/video/src saa5050 inc:cdl/inc
cdl cdl/video/src crtc6845 inc:cdl/inc
cdl cdl/video/src framebuffer inc:cdl/inc
cdl cdl/video/src framebuffer_timing inc:cdl/inc
cdl cdl/video/src framebuffer_teletext inc:cdl/inc
cdl cdl/video/src teletext inc:cdl/inc
cdl cdl/video/tb_src tb_teletext inc:cdl/inc
cdl cdl/video/tb_src tb_framebuffer_teletext inc:cdl/inc
cdl cdl/cpu/src cpu6502 inc:cdl/inc
cdl cdl/cpu/tb_src tb_6502 inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_jtag_apb_dm inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_debug inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_pipeline_debug inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_fetch_debug inc:cdl/inc
#cdl cdl/cpu/riscv/src riscv_minimal_debug inc:cdl/inc
cdl cdl/cpu/riscv/tb_src tb_riscv_jtag_debug inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_muldiv inc:cdl/inc
cdl cdl/cpu/riscv/tb_src tb_riscv_i32_muldiv inc:cdl/inc
# The decoders are separate for i32 and i32c
# but the e32 and e32c varaints use the same source code and just force enable e32 mode
cdl cdl/cpu/riscv/src riscv_i32_decode inc:cdl/inc dc:rv_cfg_i32_bitmap_enhanced_shift_enable=1
cdl cdl/cpu/riscv/src riscv_i32c_decode inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_e32_decode inc:cdl/inc inc:cdl/cpu/riscv/src dc:rv_cfg_e32_force_enable=1 rmn:riscv_i32_decode=riscv_e32_decode
cdl cdl/cpu/riscv/src riscv_e32c_decode inc:cdl/inc inc:cdl/cpu/riscv/src dc:rv_cfg_e32_force_enable=1 rmn:riscv_i32c_decode=riscv_e32c_decode
cdl cdl/cpu/riscv/src riscv_i32_debug_decode inc:cdl/inc
# These modules are suitable for i/e32[c][m]
cdl cdl/cpu/riscv/src riscv_i32_trace_compression inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_trace_pack inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_trace_decompression inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_trace inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_alu inc:cdl/inc dc:rv_cfg_i32_bitmap_enhanced_shift_enable=1
cdl cdl/cpu/riscv/src riscv_i32_dmem_request inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_dmem_read_data inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_csrs_decode inc:cdl/cpu/riscv/src inc:cdl/inc rmn:riscv_csrs_decode=riscv_csrs_decode dc:rv_cfg_debug_force_disable=1 dc:rv_cfg_supervisor_mode_enable=0 dc:rv_cfg_user_mode_enable=0 dc:rv_cfg_user_irq_mode_enable=0 rmn:riscv_csrs=riscv_csrs_machine_only
cdl cdl/cpu/riscv/src riscv_csrs_machine_only inc:cdl/cpu/riscv/src inc:cdl/inc rmn:riscv_csrs=riscv_csrs_machine_only dc:rv_cfg_debug_force_disable=1 dc:rv_cfg_supervisor_mode_enable=0 dc:rv_cfg_user_mode_enable=0 dc:rv_cfg_user_irq_mode_enable=0 rmn:riscv_csrs=riscv_csrs_machine_only
cdl cdl/cpu/riscv/src riscv_csrs_machine_debug inc:cdl/cpu/riscv/src inc:cdl/inc rmn:riscv_csrs=riscv_csrs_machine_debug dc:rv_cfg_debug_force_disable=0 dc:rv_cfg_supervisor_mode_enable=0 dc:rv_cfg_user_mode_enable=0 dc:rv_cfg_user_irq_mode_enable=0 rmn:riscv_csrs=riscv_csrs_machine_only
cdl cdl/cpu/riscv/src riscv_csrs_machine_debug_user inc:cdl/cpu/riscv/src inc:cdl/inc rmn:riscv_csrs=riscv_csrs_machine_debug_user dc:rv_cfg_debug_force_disable=0 dc:rv_cfg_supervisor_mode_enable=0 dc:rv_cfg_user_mode_enable=1 dc:rv_cfg_user_irq_mode_enable=0 rmn:riscv_csrs=riscv_csrs_machine_only
cdl cdl/cpu/riscv/src riscv_csrs_machine_debug_user_irq inc:cdl/cpu/riscv/src inc:cdl/inc rmn:riscv_csrs=riscv_csrs_machine_debug_user_irq dc:rv_cfg_debug_force_disable=0 dc:rv_cfg_supervisor_mode_enable=0 dc:rv_cfg_user_mode_enable=1 dc:rv_cfg_user_irq_mode_enable=1 rmn:riscv_csrs=riscv_csrs_machine_only
cdl cdl/cpu/riscv/src riscv_i32_pipeline_control inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_pipeline_control_fetch_req inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_pipeline_control_fetch_data inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_pipeline_trap_interposer inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_pipeline_control_flow inc:cdl/inc
# These modules are suitable for i/e32[c][m]
cdl cdl/cpu/riscv/src riscv_i32c_pipeline inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32c_pipeline3 inc:cdl/inc
# These modules are i/e32[c] capable - they tie in the pipelines and no coprocessors, so they cannot support m
cdl cdl/cpu/riscv/src riscv_i32_minimal_apb inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_minimal inc:cdl/inc
cdl cdl/cpu/riscv/src riscv_i32_minimal3 inc:cdl/inc
cdl cdl/cpu/riscv/tb_src tb_riscv_i32_minimal inc:cdl/inc inc:cdl/cpu/riscv/tb_src dc:rv_cfg_i32c_force_disable=1 rmn:tb_riscv_i32_minimal_generic=tb_riscv_i32_minimal rit:tb_riscv_i32_minimal_generic.riscv_i32_minimal_generic=riscv_i32_minimal
cdl cdl/cpu/riscv/tb_src tb_riscv_i32c_minimal inc:cdl/inc inc:cdl/cpu/riscv/tb_src dc:rv_cfg_i32c_force_disable=0 rmn:tb_riscv_i32_minimal_generic=tb_riscv_i32c_minimal rit:tb_riscv_i32_minimal_generic.riscv_i32_minimal_generic=riscv_i32_minimal
cdl cdl/cpu/riscv/tb_src tb_riscv_i32c_minimal3 inc:cdl/inc inc:cdl/cpu/riscv/tb_src dc:rv_cfg_i32c_force_disable=0 rmn:tb_riscv_i32_minimal_generic=tb_riscv_i32c_minimal3 rit:tb_riscv_i32_minimal_generic.riscv_i32_minimal_generic=riscv_i32_minimal3
cdl cdl/cpu/riscv/tb_src tb_riscv_i32c_pipeline3 inc:cdl/inc
cdl cdl/cpu/riscv/tb_src tb_riscv_i32mc_pipeline3 inc:cdl/inc
cdl cdl/cpu/riscv/tb_src tb_riscv_i32mc_system inc:cdl/inc
cdl cdl/cpu/riscv/tb_src tb_riscv_i32mc_minimal3 inc:cdl/inc
#cdl cdl/cpu/clarvi/src clarvi inc:cdl/inc
#cdl cdl/cpu/clarvi/src clarvi_csrs inc:cdl/inc
#cdl cdl/cpu/clarvi/tb_src tb_clarvi inc:cdl/inc
cdl cdl/jtag/src jtag_tap inc:cdl/inc
cdl cdl/jtag/src jtag_apb inc:cdl/inc
cdl cdl/jtag/tb_src tb_jtag_apb_timer inc:cdl/inc
cdl cdl/serial/src via6522 inc:cdl/inc
cdl cdl/serial/src acia6850 inc:cdl/inc
cdl cdl/storage/disk/src fdc8271 inc:cdl/inc
cdl cdl/microcomputers/picoriscv/src picoriscv_clocking inc:cdl/inc
#cdl cdl/microcomputers/picoriscv/src picoriscv inc:cdl/inc
#cdl cdl/microcomputers/picoriscv/tb_src tb_picoriscv inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_vidproc inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_micro_keyboard inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_keyboard_csr inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_keyboard_ps2 inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_display_sram inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_floppy_sram inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_micro_clocking inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_micro_rams inc:cdl/inc
cdl cdl/microcomputers/bbc/src bbc_micro_with_rams inc:cdl/inc
cdl_options mul:on
cdl cdl/microcomputers/bbc/src bbc_micro inc:cdl/inc
cdl_options mul:off
cdl cdl/microcomputers/bbc/tb_src tb_bbc_display_sram inc:cdl/inc
cdl cdl/led/src led_seven_segment inc:cdl/inc
cdl cdl/led/src led_ws2812_chain inc:cdl/inc
cdl cdl/led/tb_src tb_led_ws2812_chain inc:cdl/inc
cdl cdl/input_devices/src uart_minimal inc:cdl/inc
cdl cdl/input_devices/src ps2_host inc:cdl/inc
cdl cdl/input_devices/src ps2_host_keyboard inc:cdl/inc
cdl cdl/input_devices/src i2c_interface inc:cdl/inc
cdl cdl/input_devices/src i2c_slave inc:cdl/inc
cdl cdl/input_devices/src i2c_master inc:cdl/inc
cdl cdl/input_devices/src i2c_slave_apb_master inc:cdl/inc
cdl cdl/input_devices/tb_src tb_input_devices inc:cdl/inc
cdl cdl/input_devices/tb_src tb_i2c inc:cdl/inc
cdl cdl/networking/src decode_8b10b inc:cdl/inc
cdl cdl/networking/src encode_8b10b inc:cdl/inc
cdl cdl/networking/src gbe_axi4s32 inc:cdl/inc
cdl cdl/networking/src sgmii_gmii_gasket inc:cdl/inc
cdl cdl/networking/src sgmii_transceiver inc:cdl/inc
cdl cdl/networking/src gbe_single inc:cdl/inc
cdl cdl/networking/tb_src tb_8b10b inc:cdl/inc
cdl cdl/networking/tb_src tb_sgmii inc:cdl/inc
cdl cdl/networking/tb_src tb_gbe inc:cdl/inc
cdl cdl/axi/src axi4s32_fifo_4 inc:cdl/inc inc:cdl/utils/src rmt:gt_generic_valid_req=t_axi4s32 rmn:generic_valid_ack_fifo=axi4s32_fifo_4 dc:fifo_depth=3
cdl cdl/axi/tb_src tb_axi inc:cdl/inc
cdl cdl/apb/src apb_logging inc:cdl/inc
cdl cdl/apb/src apb_master_mux inc:cdl/inc
cdl cdl/apb/src apb_master_axi inc:cdl/inc
cdl cdl/apb/src apb_target_gpio inc:cdl/inc
cdl cdl/apb/src apb_target_i2c_master inc:cdl/inc
cdl cdl/apb/src apb_target_uart_minimal inc:cdl/inc
cdl cdl/apb/src apb_target_dprintf_uart inc:cdl/inc
cdl cdl/apb/src apb_target_jtag inc:cdl/inc
cdl cdl/apb/src apb_target_timer inc:cdl/inc
cdl cdl/apb/src apb_target_rv_timer inc:cdl/inc
cdl cdl/apb/src apb_target_dprintf inc:cdl/inc
cdl cdl/apb/src apb_target_led_ws2812 inc:cdl/inc
cdl cdl/apb/src apb_target_de1_cl_inputs inc:cdl/inc
cdl cdl/apb/src apb_target_sram_interface inc:cdl/inc
cdl cdl/apb/src apb_target_ps2_host inc:cdl/inc
cdl cdl/apb/src apb_target_axi4s inc:cdl/inc
cdl cdl/apb/src apb_target_analyzer inc:cdl/inc
cdl cdl/apb/src apb_processor inc:cdl/inc
cdl cdl/apb/tb_src tb_apb_processor inc:cdl/inc
cdl cdl/apb/tb_src tb_apb_target_rv_timer inc:cdl/inc
cdl cdl/apb/tb_src tb_apb_target_i2c inc:cdl/inc
cdl cdl/apb/tb_src tb_apb_target_axi4s inc:cdl/inc
cdl cdl/clocking/src clock_timer inc:cdl/inc
cdl cdl/clocking/src clock_timer_async inc:cdl/inc
cdl cdl/clocking/src clock_timer_as_sec_nsec inc:cdl/inc
cdl cdl/clocking/src clocking_eye_tracking inc:cdl/inc
cdl cdl/clocking/src clocking_phase_measure inc:cdl/inc
cdl cdl/clocking/tb_src tb_clock_timer inc:cdl/inc
cdl cdl/clocking/tb_src tb_clocking inc:cdl/inc
cdl cdl/crypt/kasumi/src kasumi_sbox7 inc:cdl/inc
cdl cdl/crypt/kasumi/src kasumi_sbox9 inc:cdl/inc
cdl cdl/crypt/kasumi/src kasumi_fi inc:cdl/inc
cdl cdl/crypt/kasumi/src kasumi_fo_cycles_3 inc:cdl/inc
cdl cdl/crypt/kasumi/src kasumi_cipher_3 inc:cdl/inc
cdl cdl/crypt/kasumi/tb_src tb_kasumi_cipher inc:cdl/inc rit:tb_kasumi_cipher.kasumi_cipher=kasumi_cipher_3
cdl cdl/csrs/src csr_master_apb inc:cdl/inc
cdl cdl/csrs/src csr_target_csr inc:cdl/inc
cdl cdl/csrs/src csr_target_apb inc:cdl/inc
cdl cdl/csrs/src csr_target_timeout inc:cdl/inc
cdl cdl/csrs/tb_src tb_csrs inc:cdl/inc
cdl cdl/subsystem/src subsys_minimal inc:cdl/inc
cdl cdl/boards/de1_cl/src picoriscv_de1_cl inc:cdl/inc
cdl cdl/boards/de1_cl/src bbc_micro_de1_cl_bbc inc:cdl/inc
cdl cdl/boards/de1_cl/src bbc_micro_de1_cl_io inc:cdl/inc
cdl cdl/boards/de1_cl/src bbc_micro_de1_cl inc:cdl/inc
cdl cdl/boards/de1_cl/src de1_cl_controls inc:cdl/inc
cdl cdl/boards/de1_cl/tb_src tb_de1_cl_controls inc:cdl/inc
#cdl cdl/boards/de1_cl/src riscv_adjunct_de1_cl inc:cdl/inc
cdl cdl/boards/de1_cl_hps/src de1_cl_hps_debug inc:cdl/inc
cdl cdl/boards/de1_cl_hps/tb_src tb_de1_cl_hps_debug inc:cdl/boards/de1_cl_hps/tb_src inc:cdl/inc rit:tb_de1_cl_hps_generic.de1_cl_hps_generic=de1_cl_hps_debug rmn:tb_de1_cl_hps_generic=tb_de1_cl_hps_debug
cdl cdl/boards/de1_hps/tb_src tb_de1_hps_generic inc:cdl/boards/de1_hps/tb_src inc:cdl/inc rit:tb_de1_hps_generic.de1_hps_generic=de1_hps_debug rmn:tb_de1_hps_generic=tb_de1_hps_debug
cdl cdl/boards/de1_hps/src de1_hps_debug inc:cdl/inc
cdl cdl/boards/de2/src/ picorisc_de2 inc:cdl/inc
cdl cdl/boards/vcu108/src vcu108_debug inc:cdl/inc
cdl cdl/boards/vcu108/src vcu108_riscv inc:cdl/boards/vcu108/src inc:cdl/inc rit:vcu108_riscv_generic.riscv_i32_minimal_generic=riscv_i32_minimal rmn:vcu108_riscv_generic=vcu108_riscv
cdl cdl/boards/vcu108/src vcu108_riscv_3 inc:cdl/boards/vcu108/src inc:cdl/inc rit:vcu108_riscv_generic.riscv_i32_minimal_generic=riscv_i32_minimal3 rmn:vcu108_riscv_generic=vcu108_riscv_3
cdl cdl/boards/vcu108/tb_src tb_vcu108_debug inc:cdl/boards/vcu108/tb_src inc:cdl/inc rit:tb_vcu108_generic.vcu108_generic=vcu108_debug rmn:tb_vcu108_generic=tb_vcu108_debug
cdl cdl/boards/vcu108/tb_src tb_vcu108_riscv inc:cdl/boards/vcu108/tb_src inc:cdl/inc rit:tb_vcu108_generic.vcu108_generic=vcu108_riscv rmn:tb_vcu108_generic=tb_vcu108_riscv
cdl cdl/boards/vcu108/tb_src tb_vcu108_riscv_3 inc:cdl/boards/vcu108/tb_src inc:cdl/inc rit:tb_vcu108_generic.vcu108_generic=vcu108_riscv_3 rmn:tb_vcu108_generic=tb_vcu108_riscv_3
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