diff --git a/vta/hardware/chisel/Makefile b/vta/hardware/chisel/Makefile
index cf57c0e0fda3..6d89a811c255 100644
--- a/vta/hardware/chisel/Makefile
+++ b/vta/hardware/chisel/Makefile
@@ -38,13 +38,13 @@ TOP_TEST = Test
 BUILD_NAME = build
 USE_TRACE = 0
 VTA_LIBNAME = libvta_hw
+UNITTEST_NAME = all
 
 config_test = $(TOP_TEST)$(CONFIG)
 vta_dir = $(abspath ../../)
 tvm_dir = $(abspath ../../../)
 verilator_build_dir = $(vta_dir)/$(BUILD_NAME)/verilator
 chisel_build_dir = $(vta_dir)/$(BUILD_NAME)/chisel
-test_name = mvm
 
 verilator_opt = --cc
 verilator_opt += +define+RANDOMIZE_GARBAGE_ASSIGN
@@ -112,11 +112,11 @@ verilog_test: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v
 $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v:
 	sbt 'runMain vta.$(config_test) --target-dir $(chisel_build_dir) --top-name $(TOP_TEST).$(CONFIG)'
 
-test:
-	sbt 'test:runMain unittest.Launcher $(test_name)'
+unittest:
+	sbt 'test:runMain unittest.Launcher $(UNITTEST_NAME)'
 
 clean:
-	-rm -rf target project/target project/project
+	-rm -rf target project/target project/project test_run_dir
 
 cleanall:
 	-rm -rf $(vta_dir)/$(BUILD_NAME)