From b93b985e8a2cdd86faa4c4d2f54d3c32e6c4ed5a Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Mon, 10 Jun 2019 22:51:55 +0000
Subject: [PATCH 01/15] add initial support to cycle counter to accelerator

---
 vta/apps/tsim_example/Makefile                |  2 +-
 .../tsim_example/hardware/verilog/Accel.v     | 83 +++++++++++--------
 .../tsim_example/hardware/verilog/Compute.v   | 35 ++++++--
 .../tsim_example/hardware/verilog/RegFile.v   | 73 +++++++++++-----
 vta/apps/tsim_example/python/tsim/driver.py   |  6 +-
 vta/apps/tsim_example/src/driver.cc           | 36 ++++----
 .../tsim_example/tests/python/add_by_one.py   | 19 ++---
 7 files changed, 165 insertions(+), 89 deletions(-)

diff --git a/vta/apps/tsim_example/Makefile b/vta/apps/tsim_example/Makefile
index 2d7629ce12b2..2d5a6180de40 100644
--- a/vta/apps/tsim_example/Makefile
+++ b/vta/apps/tsim_example/Makefile
@@ -30,7 +30,7 @@ $(BUILD_DIR):
 	mkdir -p $@
 
 run:
-	python3 tests/python/add_by_one.py | grep PASS
+	python3 tests/python/add_by_one.py
 
 clean:
 	-rm -rf $(BUILD_DIR)
diff --git a/vta/apps/tsim_example/hardware/verilog/Accel.v b/vta/apps/tsim_example/hardware/verilog/Accel.v
index b025aad22ab7..34d7d957a858 100644
--- a/vta/apps/tsim_example/hardware/verilog/Accel.v
+++ b/vta/apps/tsim_example/hardware/verilog/Accel.v
@@ -62,6 +62,11 @@ module Accel #
 
   logic                      launch;
   logic                      finish;
+
+  logic                      event_counter_valid;
+  logic [HOST_DATA_BITS-1:0] event_counter_value;
+
+  logic [HOST_DATA_BITS-1:0] constant;
   logic [HOST_DATA_BITS-1:0] length;
   logic  [MEM_ADDR_BITS-1:0] inp_baddr;
   logic  [MEM_ADDR_BITS-1:0] out_baddr;
@@ -74,22 +79,27 @@ module Accel #
   )
   rf
   (
-    .clock           (clock),
-    .reset           (reset),
-
-    .host_req_valid  (host_req_valid),
-    .host_req_opcode (host_req_opcode),
-    .host_req_addr   (host_req_addr),
-    .host_req_value  (host_req_value),
-    .host_req_deq    (host_req_deq),
-    .host_resp_valid (host_resp_valid),
-    .host_resp_bits  (host_resp_bits),
-
-    .launch          (launch),
-    .finish          (finish),
-    .length          (length),
-    .inp_baddr       (inp_baddr),
-    .out_baddr       (out_baddr)
+    .clock               (clock),
+    .reset               (reset),
+
+    .host_req_valid      (host_req_valid),
+    .host_req_opcode     (host_req_opcode),
+    .host_req_addr       (host_req_addr),
+    .host_req_value      (host_req_value),
+    .host_req_deq        (host_req_deq),
+    .host_resp_valid     (host_resp_valid),
+    .host_resp_bits      (host_resp_bits),
+
+    .launch              (launch),
+    .finish              (finish),
+
+    .event_counter_valid (event_counter_valid),
+    .event_counter_value (event_counter_value),
+
+    .constant            (constant),
+    .length              (length),
+    .inp_baddr           (inp_baddr),
+    .out_baddr           (out_baddr)
   );
 
   Compute #
@@ -101,24 +111,29 @@ module Accel #
   )
   comp
   (
-    .clock           (clock),
-    .reset           (reset),
-
-    .mem_req_valid   (mem_req_valid),
-    .mem_req_opcode  (mem_req_opcode),
-    .mem_req_len     (mem_req_len),
-    .mem_req_addr    (mem_req_addr),
-    .mem_wr_valid    (mem_wr_valid),
-    .mem_wr_bits     (mem_wr_bits),
-    .mem_rd_valid    (mem_rd_valid),
-    .mem_rd_bits     (mem_rd_bits),
-    .mem_rd_ready    (mem_rd_ready),
-
-    .launch          (launch),
-    .finish          (finish),
-    .length          (length),
-    .inp_baddr       (inp_baddr),
-    .out_baddr       (out_baddr)
+    .clock               (clock),
+    .reset               (reset),
+
+    .mem_req_valid       (mem_req_valid),
+    .mem_req_opcode      (mem_req_opcode),
+    .mem_req_len         (mem_req_len),
+    .mem_req_addr        (mem_req_addr),
+    .mem_wr_valid        (mem_wr_valid),
+    .mem_wr_bits         (mem_wr_bits),
+    .mem_rd_valid        (mem_rd_valid),
+    .mem_rd_bits         (mem_rd_bits),
+    .mem_rd_ready        (mem_rd_ready),
+
+    .launch              (launch),
+    .finish              (finish),
+
+    .event_counter_valid (event_counter_valid),
+    .event_counter_value (event_counter_value),
+
+    .constant            (constant),
+    .length              (length),
+    .inp_baddr           (inp_baddr),
+    .out_baddr           (out_baddr)
   );
 
 endmodule
diff --git a/vta/apps/tsim_example/hardware/verilog/Compute.v b/vta/apps/tsim_example/hardware/verilog/Compute.v
index a5660ac8bc7d..4360b1ca20dd 100644
--- a/vta/apps/tsim_example/hardware/verilog/Compute.v
+++ b/vta/apps/tsim_example/hardware/verilog/Compute.v
@@ -52,6 +52,11 @@ module Compute #
 
   input                         launch,
   output                        finish,
+
+  output                        event_counter_valid,
+  output   [HOST_DATA_BITS-1:0] event_counter_value,
+
+  input    [HOST_DATA_BITS-1:0] constant,
   input    [HOST_DATA_BITS-1:0] length,
   input     [MEM_ADDR_BITS-1:0] inp_baddr,
   input     [MEM_ADDR_BITS-1:0] out_baddr
@@ -84,7 +89,7 @@ module Compute #
       IDLE: begin
         if (launch) begin
           state_n = READ_REQ;
-	end
+        end
       end
 
       READ_REQ: begin
@@ -94,9 +99,9 @@ module Compute #
       READ_DATA: begin
         if (mem_rd_valid) begin
           state_n = WRITE_REQ;
-	end else begin
+        end else begin
           state_n = READ_DATA;
-	end
+        end
       end
 
       WRITE_REQ: begin
@@ -106,9 +111,9 @@ module Compute #
       WRITE_DATA: begin
         if (cnt == (length - 1'b1)) begin
           state_n = IDLE;
-	end else begin
+        end else begin
           state_n = READ_REQ;
-	end
+        end
       end
 
       default: begin
@@ -116,6 +121,22 @@ module Compute #
     endcase
   end
 
+  logic last;
+  assign last = (state_r == WRITE_DATA) & (cnt == (length - 1'b1));
+
+  // cycle counter
+  logic [HOST_DATA_BITS-1:0] cycle_counter;
+  always_ff @(posedge clock) begin
+    if (reset | state_r == IDLE) begin
+      cycle_counter <= '0;
+    end else begin
+      cycle_counter <= cycle_counter + 1'b1;
+    end
+  end
+
+  assign event_counter_valid = last;
+  assign event_counter_value = cycle_counter;
+
   // calculate next address
   always_ff @(posedge clock) begin
     if (reset | state_r == IDLE) begin
@@ -136,7 +157,7 @@ module Compute #
   // read
   always_ff @(posedge clock) begin
     if ((state_r == READ_DATA) & mem_rd_valid) begin
-      data <= mem_rd_bits + 1'b1;
+      data <= mem_rd_bits + {32'd0, constant};
     end
   end
   assign mem_rd_ready = state_r == READ_DATA;
@@ -155,5 +176,5 @@ module Compute #
   end
 
   // done when read/write are equal to length
-  assign finish = (state_r == WRITE_DATA) & (cnt == (length - 1'b1));
+  assign finish = last;
 endmodule
diff --git a/vta/apps/tsim_example/hardware/verilog/RegFile.v b/vta/apps/tsim_example/hardware/verilog/RegFile.v
index 28edf9672f48..7174682dc8a2 100644
--- a/vta/apps/tsim_example/hardware/verilog/RegFile.v
+++ b/vta/apps/tsim_example/hardware/verilog/RegFile.v
@@ -25,11 +25,13 @@
   *  Register description    | addr
   * -------------------------|-----
   *  Control status register | 0x00
-  *  Length value register   | 0x04
-  *  Input pointer lsb       | 0x08
-  *  Input pointer msb       | 0x0c
-  *  Output pointer lsb      | 0x10
-  *  Output pointer msb      | 0x14
+  *  Cycle counter           | 0x04
+  *  Constant value          | 0x08
+  *  Vector length           | 0x0c
+  *  Input pointer lsb       | 0x10
+  *  Input pointer msb       | 0x14
+  *  Output pointer lsb      | 0x18
+  *  Output pointer msb      | 0x1c
   * -------------------------------
 
   * ------------------------------
@@ -58,11 +60,18 @@ module RegFile #
 
   output                        launch,
   input                         finish,
+
+  input                         event_counter_valid,
+  input    [HOST_DATA_BITS-1:0] event_counter_value,
+
+  output   [HOST_DATA_BITS-1:0] constant,
   output   [HOST_DATA_BITS-1:0] length,
   output    [MEM_ADDR_BITS-1:0] inp_baddr,
   output    [MEM_ADDR_BITS-1:0] out_baddr
 );
 
+  localparam NUM_REG = 8;
+
   typedef enum logic {IDLE, READ} state_t;
   state_t state_n, state_r;
 
@@ -80,7 +89,7 @@ module RegFile #
       IDLE: begin
         if (host_req_valid & ~host_req_opcode) begin
           state_n = READ;
-	end
+        end
       end
 
       READ: begin
@@ -91,28 +100,49 @@ module RegFile #
 
   assign host_req_deq = (state_r == IDLE) ? host_req_valid : 1'b0;
 
-  logic [HOST_DATA_BITS-1:0] rf [5:0];
+  logic [HOST_DATA_BITS-1:0] rf [NUM_REG-1:0];
 
   genvar i;
-  for (i = 0; i < 6; i++) begin
+  for (i = 0; i < NUM_REG; i++) begin
+
     logic wen = (state_r == IDLE)? host_req_valid & host_req_opcode & i*4 == host_req_addr : 1'b0;
+
     if (i == 0) begin
+
       always_ff @(posedge clock) begin
         if (reset) begin
-	end else if (finish) begin
-	  rf[i] <= 'd2;
-	end else if (wen) begin
-	  rf[i] <= host_req_value;
-	end
+          rf[i] <= 'd0;
+        end else if (finish) begin
+          rf[i] <= 'd2;
+        end else if (wen) begin
+          rf[i] <= host_req_value;
+        end
       end
+
+    end else if (i == 1) begin
+
+      always_ff @(posedge clock) begin
+        if (reset) begin
+          rf[i] <= 'd0;
+        end else if (event_counter_valid) begin
+          rf[i] <= event_counter_value;
+        end else if (wen) begin
+          rf[i] <= host_req_value;
+        end
+      end
+
     end else begin
+
       always_ff @(posedge clock) begin
         if (reset) begin
-	end else if (wen) begin
-	  rf[i] <= host_req_value;
-	end
+          rf[i] <= 'd0;
+        end else if (wen) begin
+          rf[i] <= host_req_value;
+        end
       end
+
     end
+
   end
 
   logic [HOST_DATA_BITS-1:0] rdata;
@@ -132,6 +162,10 @@ module RegFile #
         rdata <= rf[4];
       end else if (host_req_addr == 'h14) begin
         rdata <= rf[5];
+      end else if (host_req_addr == 'h18) begin
+        rdata <= rf[6];
+      end else if (host_req_addr == 'h1c) begin
+        rdata <= rf[7];
       end else begin
         rdata <= 'd0;
       end
@@ -142,8 +176,9 @@ module RegFile #
   assign host_resp_bits = rdata;
 
   assign launch = rf[0][0];
-  assign length = rf[1];
-  assign inp_baddr = {rf[3], rf[2]};
-  assign out_baddr = {rf[5], rf[4]};
+  assign constant = rf[2];
+  assign length = rf[3];
+  assign inp_baddr = {rf[5], rf[4]};
+  assign out_baddr = {rf[7], rf[6]};
 
 endmodule
diff --git a/vta/apps/tsim_example/python/tsim/driver.py b/vta/apps/tsim_example/python/tsim/driver.py
index c388b99cbec9..16aaa5c3a501 100644
--- a/vta/apps/tsim_example/python/tsim/driver.py
+++ b/vta/apps/tsim_example/python/tsim/driver.py
@@ -49,9 +49,11 @@ def load_dll(dll):
         except OSError:
             return []
 
-    def run(a, b):
+    def run(a, b, c):
         load_dll(_sw_lib)
         f = tvm.get_global_func("tvm.vta.driver")
         m = tvm.module.load(_hw_lib, "vta-tsim")
-        f(m, a, b)
+        return f(m, a, b, c)
+        #cycles = f(m, a, b, c)
+        #print("cycles: ", cycles)
     return run
diff --git a/vta/apps/tsim_example/src/driver.cc b/vta/apps/tsim_example/src/driver.cc
index c11a8f8a3ee7..c1dc61f8bee1 100644
--- a/vta/apps/tsim_example/src/driver.cc
+++ b/vta/apps/tsim_example/src/driver.cc
@@ -43,34 +43,37 @@ class Device {
         module.operator->());
   }
 
-  int Run(uint32_t length, void* inp, void* out) {
-    uint32_t wait_cycles = 100000000;
-    this->Launch(wait_cycles, length, inp, out);
-    this->WaitForCompletion(wait_cycles);
+  uint32_t Run(uint32_t c, uint32_t length, void* inp, void* out) {
+    uint32_t cycles;
+    this->Launch(c, length, inp, out);
+    cycles = this->WaitForCompletion();
     dpi_->Finish();
-    return 0;
+    return cycles;
   }
 
  private:
-  void Launch(uint32_t wait_cycles, uint32_t length, void* inp, void* out) {
-    dpi_->Launch(wait_cycles);
-    // write registers
-    dpi_->WriteReg(0x04, length);
-    dpi_->WriteReg(0x08, get_half_addr(inp, false));
-    dpi_->WriteReg(0x0c, get_half_addr(inp, true));
-    dpi_->WriteReg(0x10, get_half_addr(out, false));
-    dpi_->WriteReg(0x14, get_half_addr(out, true));
+  void Launch(uint32_t c, uint32_t length, void* inp, void* out) {
+    dpi_->Launch(wait_cycles_);
+    dpi_->WriteReg(0x08, c);
+    dpi_->WriteReg(0x0c, length);
+    dpi_->WriteReg(0x10, get_half_addr(inp, false));
+    dpi_->WriteReg(0x14, get_half_addr(inp, true));
+    dpi_->WriteReg(0x18, get_half_addr(out, false));
+    dpi_->WriteReg(0x1c, get_half_addr(out, true));
     dpi_->WriteReg(0x00, 0x1); // launch
   }
 
-  void WaitForCompletion(uint32_t wait_cycles) {
+  uint32_t WaitForCompletion() {
     uint32_t i, val;
-    for (i = 0; i < wait_cycles; i++) {
+    for (i = 0; i < wait_cycles_; i++) {
       val = dpi_->ReadReg(0x00);
       if (val == 2) break; // finish
     }
+    val = dpi_->ReadReg(0x04);
+    return val;
   }
 
+  uint32_t wait_cycles_{100000000};
   DPIModuleNode* dpi_;
   Module module_;
 };
@@ -84,7 +87,8 @@ TVM_REGISTER_GLOBAL("tvm.vta.driver")
     DLTensor* A = args[1];
     DLTensor* B = args[2];
     Device dev_(dev_mod);
-    dev_.Run(A->shape[0], A->data, B->data);
+    uint32_t cycles = dev_.Run(static_cast<int>(args[3]), A->shape[0], A->data, B->data);
+    *rv = static_cast<int>(cycles);
   });
 
 }  // namespace driver
diff --git a/vta/apps/tsim_example/tests/python/add_by_one.py b/vta/apps/tsim_example/tests/python/add_by_one.py
index 6e0d094367b5..7940a4b2968f 100644
--- a/vta/apps/tsim_example/tests/python/add_by_one.py
+++ b/vta/apps/tsim_example/tests/python/add_by_one.py
@@ -20,20 +20,19 @@
 
 from tsim.driver import driver
 
-def test_tsim(i):
-    rmin = 1 # min vector size of 1
+def test_tsim():
     rmax = 64
-    n = np.random.randint(rmin, rmax)
+    n = np.random.randint(1, rmax)
+    c = np.random.randint(0, rmax)
     ctx = tvm.cpu(0)
     a = tvm.nd.array(np.random.randint(rmax, size=n).astype("uint64"), ctx)
     b = tvm.nd.array(np.zeros(n).astype("uint64"), ctx)
     f = driver("libhw", "libsw")
-    f(a, b)
-    emsg = "[FAIL] test number:{} n:{}".format(i, n)
-    np.testing.assert_equal(b.asnumpy(), a.asnumpy() + 1, err_msg=emsg)
-    print("[PASS] test number:{} n:{}".format(i, n))
+    cycles = f(a, b, c)
+    emsg = "[FAIL] n:{} cycles:{}".format(n, cycles)
+    np.testing.assert_equal(b.asnumpy(), a.asnumpy() + c, err_msg=emsg)
+    print("[PASS] n:{} cycles:{}".format(n, cycles))
 
 if __name__ == "__main__":
-    times = 10
-    for i in range(times):
-        test_tsim(i)
+    for i in range(10):
+        test_tsim()

From 17e5f78fd9dbb43ec41d902199d623c03f70aa6d Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Mon, 10 Jun 2019 23:36:43 +0000
Subject: [PATCH 02/15] remove prints from c

---
 vta/apps/tsim_example/Makefile                         |  2 +-
 .../tests/python/{add_by_one.py => accel.py}           | 10 +++++-----
 .../chisel/src/main/resources/verilog/VTAHostDPI.v     |  1 -
 vta/hardware/dpi/tsim_device.cc                        |  1 -
 4 files changed, 6 insertions(+), 8 deletions(-)
 rename vta/apps/tsim_example/tests/python/{add_by_one.py => accel.py} (89%)

diff --git a/vta/apps/tsim_example/Makefile b/vta/apps/tsim_example/Makefile
index 2d5a6180de40..d775a34e7f9f 100644
--- a/vta/apps/tsim_example/Makefile
+++ b/vta/apps/tsim_example/Makefile
@@ -30,7 +30,7 @@ $(BUILD_DIR):
 	mkdir -p $@
 
 run:
-	python3 tests/python/add_by_one.py
+	python3 tests/python/accel.py
 
 clean:
 	-rm -rf $(BUILD_DIR)
diff --git a/vta/apps/tsim_example/tests/python/add_by_one.py b/vta/apps/tsim_example/tests/python/accel.py
similarity index 89%
rename from vta/apps/tsim_example/tests/python/add_by_one.py
rename to vta/apps/tsim_example/tests/python/accel.py
index 7940a4b2968f..23c25c8c1b46 100644
--- a/vta/apps/tsim_example/tests/python/add_by_one.py
+++ b/vta/apps/tsim_example/tests/python/accel.py
@@ -20,7 +20,7 @@
 
 from tsim.driver import driver
 
-def test_tsim():
+def test_accel():
     rmax = 64
     n = np.random.randint(1, rmax)
     c = np.random.randint(0, rmax)
@@ -29,10 +29,10 @@ def test_tsim():
     b = tvm.nd.array(np.zeros(n).astype("uint64"), ctx)
     f = driver("libhw", "libsw")
     cycles = f(a, b, c)
-    emsg = "[FAIL] n:{} cycles:{}".format(n, cycles)
-    np.testing.assert_equal(b.asnumpy(), a.asnumpy() + c, err_msg=emsg)
-    print("[PASS] n:{} cycles:{}".format(n, cycles))
+    msg = "cycles:{0:4} n:{1:2} c:{2:2}".format(cycles, n, c)
+    np.testing.assert_equal(b.asnumpy(), a.asnumpy() + c, err_msg = "[FAIL] " + msg)
+    print("[PASS] " + msg)
 
 if __name__ == "__main__":
     for i in range(10):
-        test_tsim()
+        test_accel()
diff --git a/vta/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v b/vta/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v
index 8ab85f6b752c..b466c79d4555 100644
--- a/vta/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v
+++ b/vta/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v
@@ -112,7 +112,6 @@ module VTAHostDPI #
 
   always_ff @(posedge clock) begin
     if (__exit == 'd1) begin
-      $display("[TSIM] Verilog $finish called at cycle:%016d", cycles);
       $finish;
     end
   end
diff --git a/vta/hardware/dpi/tsim_device.cc b/vta/hardware/dpi/tsim_device.cc
index 0b315e4cb541..aa05c8c2663c 100644
--- a/vta/hardware/dpi/tsim_device.cc
+++ b/vta/hardware/dpi/tsim_device.cc
@@ -75,7 +75,6 @@ void VTADPIInit(VTAContextHandle handle,
 // VL_USER_FINISH needs to be defined when compiling Verilator code
 void vl_finish(const char* filename, int linenum, const char* hier) {
   Verilated::gotFinish(true);
-  VL_PRINTF("[TSIM] exiting simulation\n");
 }
 
 int VTADPISim(uint64_t max_cycles) {

From 0345bb7e2244238d3b5581471323caa4d65cb245 Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 06:27:42 +0000
Subject: [PATCH 03/15] add event counter support to chisel tsim example

---
 vta/apps/tsim_example/config/config.json      |  2 +-
 .../chisel/src/main/scala/accel/Accel.scala   |  6 +--
 .../chisel/src/main/scala/accel/Compute.scala | 41 +++++++++++-----
 .../chisel/src/main/scala/accel/RegFile.scala | 47 ++++++++++++++-----
 4 files changed, 68 insertions(+), 28 deletions(-)

diff --git a/vta/apps/tsim_example/config/config.json b/vta/apps/tsim_example/config/config.json
index 887eaac67d74..b1d0a1b7f3fe 100644
--- a/vta/apps/tsim_example/config/config.json
+++ b/vta/apps/tsim_example/config/config.json
@@ -1,5 +1,5 @@
 {
-  "TARGET" : "verilog",
+  "TARGET" : "chisel",
   "TOP_NAME" : "TestAccel",
   "BUILD_NAME" : "build",
   "USE_TRACE" : "off",
diff --git a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala
index 9225f83b0821..ba61009835ab 100644
--- a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala
+++ b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala
@@ -46,7 +46,7 @@ class Accel extends Module {
   io.mem <> ce.io.mem
   ce.io.launch := rf.io.launch
   rf.io.finish := ce.io.finish
-  ce.io.length := rf.io.length
-  ce.io.inp_baddr := rf.io.inp_baddr
-  ce.io.out_baddr := rf.io.out_baddr
+  rf.io.ecnt <> ce.io.ecnt
+  ce.io.vals <> rf.io.vals
+  ce.io.ptrs <> rf.io.ptrs
 }
diff --git a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala
index fb7a2f396cb0..91cbe36e211c 100644
--- a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala
+++ b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala
@@ -36,20 +36,27 @@ import vta.dpi._
   *    otherwise go to step 2.
   */
 class Compute extends Module {
+  val nCtrl = 1
+  val nECnt = 1
+  val nVals = 2
+  val nPtrs = 2
   val io = IO(new Bundle {
     val launch = Input(Bool())
     val finish = Output(Bool())
-    val length = Input(UInt(32.W))
-    val inp_baddr = Input(UInt(64.W))
-    val out_baddr = Input(UInt(64.W))
+    val ecnt = Vec(nECnt, ValidIO(UInt(32.W)))
+    val vals = Input(Vec(nVals, UInt(32.W)))
+    val ptrs = Input(Vec(nPtrs, UInt(64.W)))
     val mem = new VTAMemDPIMaster
   })
   val sIdle :: sReadReq :: sReadData :: sWriteReq :: sWriteData :: Nil = Enum(5)
   val state = RegInit(sIdle)
+  val const = io.vals(0)
+  val length = io.vals(1)
+  val cycles = RegInit(0.U(32.W))
   val reg = Reg(chiselTypeOf(io.mem.rd.bits))
-  val cnt = Reg(chiselTypeOf(io.length))
-  val raddr = Reg(chiselTypeOf(io.inp_baddr))
-  val waddr = Reg(chiselTypeOf(io.out_baddr))
+  val cnt = Reg(UInt(32.W))
+  val raddr = Reg(UInt(64.W))
+  val waddr = Reg(UInt(64.W))
 
   switch (state) {
     is (sIdle) {
@@ -69,7 +76,7 @@ class Compute extends Module {
       state := sWriteData
     }
     is (sWriteData) {
-      when (cnt === (io.length - 1.U)) {
+      when (cnt === (length - 1.U)) {
         state := sIdle
       } .otherwise {
         state := sReadReq
@@ -77,10 +84,22 @@ class Compute extends Module {
     }
   }
 
+  val last = state === sWriteData && cnt === (length - 1.U)
+
+  // cycle counter
+  when (state === sIdle) {
+    cycles := 0.U
+  } .otherwise {
+    cycles := cycles + 1.U
+  }
+
+  io.ecnt(0).valid := last
+  io.ecnt(0).bits := cycles
+
   // calculate next address
   when (state === sIdle) {
-    raddr := io.inp_baddr
-    waddr := io.out_baddr
+    raddr := io.ptrs(0)
+    waddr := io.ptrs(1)
   } .elsewhen (state === sWriteData) { // increment by 8-bytes
     raddr := raddr + 8.U
     waddr := waddr + 8.U
@@ -94,7 +113,7 @@ class Compute extends Module {
 
   // read
   when (state === sReadData && io.mem.rd.valid) {
-    reg := io.mem.rd.bits + 1.U
+    reg := io.mem.rd.bits + const
   }
   io.mem.rd.ready := state === sReadData
 
@@ -110,5 +129,5 @@ class Compute extends Module {
   }
 
   // done when read/write are equal to length
-  io.finish := state === sWriteData && cnt === (io.length - 1.U)
+  io.finish := last
 }
diff --git a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
index e636afdfb2e1..0b53a4ad97d9 100644
--- a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
+++ b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
@@ -31,11 +31,13 @@ import vta.dpi._
   *  Register description    | addr
   * -------------------------|-----
   *  Control status register | 0x00
-  *  Length value register   | 0x04
-  *  Input pointer lsb       | 0x08
-  *  Input pointer msb       | 0x0c
-  *  Output pointer lsb      | 0x10
-  *  Output pointer msb      | 0x14
+  *  Cycle counter           | 0x04
+  *  Constant value          | 0x08
+  *  Vector length           | 0x0c
+  *  Input pointer lsb       | 0x10
+  *  Input pointer msb       | 0x14
+  *  Output pointer lsb      | 0x18
+  *  Output pointer msb      | 0x1c
   * -------------------------------
 
   * ------------------------------
@@ -46,12 +48,17 @@ import vta.dpi._
   * ------------------------------
   */
 class RegFile extends Module {
+  val nCtrl = 1
+  val nECnt = 1
+  val nVals = 2
+  val nPtrs = 2
+  val nTotal = nCtrl + nECnt + nVals + (2*nPtrs)
   val io = IO(new Bundle {
     val launch = Output(Bool())
     val finish = Input(Bool())
-    val length = Output(UInt(32.W))
-    val inp_baddr = Output(UInt(64.W))
-    val out_baddr = Output(UInt(64.W))
+    val ecnt = Vec(nECnt, Flipped(ValidIO(UInt(32.W))))
+    val vals = Output(Vec(nVals, UInt(32.W)))
+    val ptrs = Output(Vec(nPtrs, UInt(64.W)))
     val host = new VTAHostDPIClient
   })
   val sIdle :: sRead :: Nil = Enum(2)
@@ -70,8 +77,8 @@ class RegFile extends Module {
 
   io.host.req.deq := state === sIdle & io.host.req.valid
 
-  val reg = Seq.fill(6)(RegInit(0.U.asTypeOf(chiselTypeOf(io.host.req.value))))
-  val addr = Seq.tabulate(6)(_ * 4)
+  val reg = Seq.fill(nTotal)(RegInit(0.U.asTypeOf(chiselTypeOf(io.host.req.value))))
+  val addr = Seq.tabulate(nTotal)(_ * 4)
   val reg_map = (addr zip reg)  map { case (a, r) => a.U -> r }
 
   (reg zip addr).foreach { case(r, a) =>
@@ -82,6 +89,13 @@ class RegFile extends Module {
             io.host.req.opcode && a.U === io.host.req.addr) {
         r := io.host.req.value
       }
+    } else if (a == 4) {
+      when (io.ecnt(0).valid) {
+        r := io.ecnt(0).bits
+      } .elsewhen (state === sIdle && io.host.req.valid &&
+            io.host.req.opcode && a.U === io.host.req.addr) {
+        r := io.host.req.value
+      }
     } else {
       when (state === sIdle && io.host.req.valid &&
             io.host.req.opcode && a.U === io.host.req.addr) {
@@ -99,7 +113,14 @@ class RegFile extends Module {
   io.host.resp.bits := rdata
 
   io.launch := reg(0)(0)
-  io.length := reg(1)
-  io.inp_baddr := Cat(reg(3), reg(2))
-  io.out_baddr := Cat(reg(5), reg(4))
+
+  val vo = nCtrl + nECnt
+  for (i <- 0 until nVals) {
+    io.vals(i) := reg(vo + i)
+  }
+
+  val po = nCtrl + nECnt + nVals
+  for (i <- 0 until nPtrs) {
+    io.ptrs(i) := Cat(reg(po + 2*i + 1), reg(po + 2*i))
+  }
 }

From c6204a5b8b3b532979f36937a46b872fdf5c520f Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 06:46:01 +0000
Subject: [PATCH 04/15] make it more readable

---
 .../chisel/src/main/scala/accel/RegFile.scala | 45 ++++++++++---------
 vta/config/vta_config.json                    |  2 +-
 2 files changed, 24 insertions(+), 23 deletions(-)

diff --git a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
index 0b53a4ad97d9..3cb1e21abef2 100644
--- a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
+++ b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
@@ -80,27 +80,30 @@ class RegFile extends Module {
   val reg = Seq.fill(nTotal)(RegInit(0.U.asTypeOf(chiselTypeOf(io.host.req.value))))
   val addr = Seq.tabulate(nTotal)(_ * 4)
   val reg_map = (addr zip reg)  map { case (a, r) => a.U -> r }
+  val eo = nCtrl
+  val vo = eo + nECnt
+  val po = vo + nVals
 
-  (reg zip addr).foreach { case(r, a) =>
-    if (a == 0) { // control status register
-      when (io.finish) {
-        r := "b_10".U
-      } .elsewhen (state === sIdle && io.host.req.valid &&
-            io.host.req.opcode && a.U === io.host.req.addr) {
-        r := io.host.req.value
-      }
-    } else if (a == 4) {
-      when (io.ecnt(0).valid) {
-        r := io.ecnt(0).bits
-      } .elsewhen (state === sIdle && io.host.req.valid &&
-            io.host.req.opcode && a.U === io.host.req.addr) {
-        r := io.host.req.value
-      }
-    } else {
-      when (state === sIdle && io.host.req.valid &&
-            io.host.req.opcode && a.U === io.host.req.addr) {
-        r := io.host.req.value
-      }
+  when (io.finish) {
+    reg(0) := "b_10".U
+  } .elsewhen (state === sIdle && io.host.req.valid &&
+        io.host.req.opcode && addr(0).U === io.host.req.addr) {
+    reg(0) := io.host.req.value
+  }
+
+  for (i <- 0 until nECnt) {
+    when (io.ecnt(i).valid) {
+      reg(eo + i) := io.ecnt(i).bits
+    } .elsewhen (state === sIdle && io.host.req.valid &&
+          io.host.req.opcode && addr(eo + i).U === io.host.req.addr) {
+      reg(eo + i) := io.host.req.value
+    }
+  }
+
+  for (i <- 0 until (nVals + (2*nPtrs))) {
+    when (state === sIdle && io.host.req.valid &&
+          io.host.req.opcode && addr(vo + i).U === io.host.req.addr) {
+      reg(vo + i) := io.host.req.value
     }
   }
 
@@ -114,12 +117,10 @@ class RegFile extends Module {
 
   io.launch := reg(0)(0)
 
-  val vo = nCtrl + nECnt
   for (i <- 0 until nVals) {
     io.vals(i) := reg(vo + i)
   }
 
-  val po = nCtrl + nECnt + nVals
   for (i <- 0 until nPtrs) {
     io.ptrs(i) := Cat(reg(po + 2*i + 1), reg(po + 2*i))
   }
diff --git a/vta/config/vta_config.json b/vta/config/vta_config.json
index 602af0126816..3f49ecd01da0 100644
--- a/vta/config/vta_config.json
+++ b/vta/config/vta_config.json
@@ -1,5 +1,5 @@
 {
-  "TARGET" : "sim",
+  "TARGET" : "tsim",
   "HW_FREQ" : 100,
   "HW_CLK_TARGET" : 7,
   "HW_VER" : "0.0.0",

From 45f12bb339b20824a34483e231da9ccbe8bb4529 Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 07:05:58 +0000
Subject: [PATCH 05/15] use a config class

---
 .../chisel/src/main/scala/accel/Accel.scala   | 10 +++++++
 .../chisel/src/main/scala/accel/Compute.scala | 20 ++++++-------
 .../chisel/src/main/scala/accel/RegFile.scala | 28 ++++++++-----------
 3 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala
index ba61009835ab..d654a7fdd41a 100644
--- a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala
+++ b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala
@@ -35,11 +35,21 @@ import vta.dpi._
   * |_________|      |_________|
   *
   */
+case class AccelConfig() {
+  val nCtrl = 1
+  val nECnt = 1
+  val nVals = 2
+  val nPtrs = 2
+  val regBits = 32
+  val ptrBits = 2*regBits
+}
+
 class Accel extends Module {
   val io = IO(new Bundle {
     val host = new VTAHostDPIClient
     val mem = new VTAMemDPIMaster
   })
+  implicit val config = AccelConfig()
   val rf = Module(new RegFile)
   val ce = Module(new Compute)
   rf.io.host <> io.host
diff --git a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala
index 91cbe36e211c..f24cbdd8bdb7 100644
--- a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala
+++ b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala
@@ -35,28 +35,24 @@ import vta.dpi._
   * 6. Check if counter (cnt) is equal to length to assert finish,
   *    otherwise go to step 2.
   */
-class Compute extends Module {
-  val nCtrl = 1
-  val nECnt = 1
-  val nVals = 2
-  val nPtrs = 2
+class Compute(implicit config: AccelConfig) extends Module {
   val io = IO(new Bundle {
     val launch = Input(Bool())
     val finish = Output(Bool())
-    val ecnt = Vec(nECnt, ValidIO(UInt(32.W)))
-    val vals = Input(Vec(nVals, UInt(32.W)))
-    val ptrs = Input(Vec(nPtrs, UInt(64.W)))
+    val ecnt = Vec(config.nECnt, ValidIO(UInt(config.regBits.W)))
+    val vals = Input(Vec(config.nVals, UInt(config.regBits.W)))
+    val ptrs = Input(Vec(config.nPtrs, UInt(config.ptrBits.W)))
     val mem = new VTAMemDPIMaster
   })
   val sIdle :: sReadReq :: sReadData :: sWriteReq :: sWriteData :: Nil = Enum(5)
   val state = RegInit(sIdle)
   val const = io.vals(0)
   val length = io.vals(1)
-  val cycles = RegInit(0.U(32.W))
+  val cycles = RegInit(0.U(config.regBits.W))
   val reg = Reg(chiselTypeOf(io.mem.rd.bits))
-  val cnt = Reg(UInt(32.W))
-  val raddr = Reg(UInt(64.W))
-  val waddr = Reg(UInt(64.W))
+  val cnt = Reg(UInt(config.regBits.W))
+  val raddr = Reg(UInt(config.ptrBits.W))
+  val waddr = Reg(UInt(config.ptrBits.W))
 
   switch (state) {
     is (sIdle) {
diff --git a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
index 3cb1e21abef2..5fdb3529573c 100644
--- a/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
+++ b/vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
@@ -47,18 +47,13 @@ import vta.dpi._
   *  Finish                  | 1
   * ------------------------------
   */
-class RegFile extends Module {
-  val nCtrl = 1
-  val nECnt = 1
-  val nVals = 2
-  val nPtrs = 2
-  val nTotal = nCtrl + nECnt + nVals + (2*nPtrs)
+class RegFile(implicit config: AccelConfig) extends Module {
   val io = IO(new Bundle {
     val launch = Output(Bool())
     val finish = Input(Bool())
-    val ecnt = Vec(nECnt, Flipped(ValidIO(UInt(32.W))))
-    val vals = Output(Vec(nVals, UInt(32.W)))
-    val ptrs = Output(Vec(nPtrs, UInt(64.W)))
+    val ecnt = Vec(config.nECnt, Flipped(ValidIO(UInt(config.regBits.W))))
+    val vals = Output(Vec(config.nVals, UInt(config.regBits.W)))
+    val ptrs = Output(Vec(config.nPtrs, UInt(config.regBits.W)))
     val host = new VTAHostDPIClient
   })
   val sIdle :: sRead :: Nil = Enum(2)
@@ -77,12 +72,13 @@ class RegFile extends Module {
 
   io.host.req.deq := state === sIdle & io.host.req.valid
 
+  val nTotal = config.nCtrl + config.nECnt + config.nVals + (2*config.nPtrs)
   val reg = Seq.fill(nTotal)(RegInit(0.U.asTypeOf(chiselTypeOf(io.host.req.value))))
   val addr = Seq.tabulate(nTotal)(_ * 4)
   val reg_map = (addr zip reg)  map { case (a, r) => a.U -> r }
-  val eo = nCtrl
-  val vo = eo + nECnt
-  val po = vo + nVals
+  val eo = config.nCtrl
+  val vo = eo + config.nECnt
+  val po = vo + config.nVals
 
   when (io.finish) {
     reg(0) := "b_10".U
@@ -91,7 +87,7 @@ class RegFile extends Module {
     reg(0) := io.host.req.value
   }
 
-  for (i <- 0 until nECnt) {
+  for (i <- 0 until config.nECnt) {
     when (io.ecnt(i).valid) {
       reg(eo + i) := io.ecnt(i).bits
     } .elsewhen (state === sIdle && io.host.req.valid &&
@@ -100,7 +96,7 @@ class RegFile extends Module {
     }
   }
 
-  for (i <- 0 until (nVals + (2*nPtrs))) {
+  for (i <- 0 until (config.nVals + (2*config.nPtrs))) {
     when (state === sIdle && io.host.req.valid &&
           io.host.req.opcode && addr(vo + i).U === io.host.req.addr) {
       reg(vo + i) := io.host.req.value
@@ -117,11 +113,11 @@ class RegFile extends Module {
 
   io.launch := reg(0)(0)
 
-  for (i <- 0 until nVals) {
+  for (i <- 0 until config.nVals) {
     io.vals(i) := reg(vo + i)
   }
 
-  for (i <- 0 until nPtrs) {
+  for (i <- 0 until config.nPtrs) {
     io.ptrs(i) := Cat(reg(po + 2*i + 1), reg(po + 2*i))
   }
 }

From 1639689d557a559da56e9fdf884b4f8ca6675522 Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 15:53:51 +0000
Subject: [PATCH 06/15] update driver

---
 vta/apps/tsim_example/python/tsim/driver.py | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/vta/apps/tsim_example/python/tsim/driver.py b/vta/apps/tsim_example/python/tsim/driver.py
index 16aaa5c3a501..0571cff7eb2e 100644
--- a/vta/apps/tsim_example/python/tsim/driver.py
+++ b/vta/apps/tsim_example/python/tsim/driver.py
@@ -22,7 +22,7 @@
 from sys import platform
 
 def driver(hw_lib, sw_lib):
-    """Init hardware and software shared library for add-by-one accelerator
+    """Init hardware and software shared library for accelerator
 
      Parameters
      ------------
@@ -54,6 +54,4 @@ def run(a, b, c):
         f = tvm.get_global_func("tvm.vta.driver")
         m = tvm.module.load(_hw_lib, "vta-tsim")
         return f(m, a, b, c)
-        #cycles = f(m, a, b, c)
-        #print("cycles: ", cycles)
     return run

From 8bbd48347e640d3f1306a385823ef136806fb9d1 Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 16:10:49 +0000
Subject: [PATCH 07/15] add individual Makefile to chisel

---
 .../tsim_example/hardware/chisel/Makefile     | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/vta/apps/tsim_example/hardware/chisel/Makefile b/vta/apps/tsim_example/hardware/chisel/Makefile
index 65a9ed13c989..92c13e70c9b4 100644
--- a/vta/apps/tsim_example/hardware/chisel/Makefile
+++ b/vta/apps/tsim_example/hardware/chisel/Makefile
@@ -15,5 +15,91 @@
 # specific language governing permissions and limitations
 # under the License.
 
+ifeq (, $(shell which verilator))
+ $(error "No Verilator in $(PATH), consider doing apt-get install verilator")
+endif
+
+# Change VERILATOR_INC_DIR if Verilator is installed on a different location
+ifeq (, $(VERILATOR_INC_DIR))
+  ifeq (, $(wildcard /usr/local/share/verilator/include/*))
+    ifeq (, $(wildcard /usr/share/verilator/include/*))
+      $(error "Verilator include directory is not set properly")
+    else
+      VERILATOR_INC_DIR := /usr/share/verilator/include
+    endif
+  else
+      VERILATOR_INC_DIR := /usr/local/share/verilator/include
+  endif
+endif
+
+TOP = TestAccel
+BUILD_NAME = build
+USE_TRACE = 0
+LIBNAME = libhw
+
+vta_dir = $(abspath ../../../../)
+tvm_dir = $(abspath ../../../../../)
+build_dir = $(abspath .)/$(BUILD_NAME)
+verilator_build_dir = $(build_dir)//verilator
+chisel_build_dir = $(build_dir)/chisel
+
+verilator_opt = --cc
+verilator_opt += +define+RANDOMIZE_GARBAGE_ASSIGN
+verilator_opt += +define+RANDOMIZE_REG_INIT
+verilator_opt += +define+RANDOMIZE_MEM_INIT
+verilator_opt += --x-assign unique
+verilator_opt += --output-split 20000
+verilator_opt += --output-split-cfuncs 20000
+verilator_opt += --top-module ${TOP}
+verilator_opt += -Mdir ${verilator_build_dir}
+verilator_opt += -I$(chisel_build_dir)
+
+cxx_flags = -O2 -Wall -fPIC -shared
+cxx_flags += -fvisibility=hidden -std=c++11
+cxx_flags += -DVL_TSIM_NAME=V$(TOP)
+cxx_flags += -DVL_PRINTF=printf
+cxx_flags += -DVL_USER_FINISH
+cxx_flags += -DVM_COVERAGE=0
+cxx_flags += -DVM_SC=0
+cxx_flags += -Wno-sign-compare
+cxx_flags += -include V$(TOP).h
+cxx_flags += -I$(verilator_build_dir)
+cxx_flags += -I$(VERILATOR_INC_DIR)
+cxx_flags += -I$(VERILATOR_INC_DIR)/vltstd
+cxx_flags += -I$(vta_dir)/include
+cxx_flags += -I$(tvm_dir)/include
+cxx_flags += -I$(tvm_dir)/3rdparty/dlpack/include
+
+cxx_files = $(VERILATOR_INC_DIR)/verilated.cpp
+cxx_files += $(VERILATOR_INC_DIR)/verilated_dpi.cpp
+cxx_files += $(wildcard $(verilator_build_dir)/*.cpp)
+cxx_files += $(vta_dir)/hardware/dpi/tsim_device.cc
+
+ifneq ($(USE_TRACE), 0)
+  verilator_opt += --trace
+  cxx_flags += -DVM_TRACE=1
+  cxx_flags += -DTSIM_TRACE_FILE=$(verilator_build_dir)/$(TOP).vcd
+  cxx_files += $(VERILATOR_INC_DIR)/verilated_vcd_c.cpp
+else
+  cxx_flags += -DVM_TRACE=0
+endif
+
+default: lib
+
+lib: $(build_dir)/$(LIBNAME).so
+$(build_dir)/$(LIBNAME).so: $(verilator_build_dir)/V$(TOP).cpp
+	g++ $(cxx_flags) $(cxx_files) -o $@
+
+verilator: $(verilator_build_dir)/V$(TOP).cpp
+$(verilator_build_dir)/V$(TOP).cpp: $(chisel_build_dir)/$(TOP).v
+	verilator $(verilator_opt) $<
+
+verilog: $(chisel_build_dir)/$(TOP).v
+$(chisel_build_dir)/$(TOP).v:
+	sbt 'test:runMain test.Elaborate --target-dir $(chisel_build_dir) --top-name $(TOP)'
+
 clean:
 	-rm -rf target project/target project/project
+
+cleanall:
+	-rm -rf $(build_dir)

From b241d8ddf9c3cf1a3ffac0394d32eb54977719ff Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 16:23:39 +0000
Subject: [PATCH 08/15] add rule for installing vta package

---
 vta/apps/tsim_example/hardware/chisel/Makefile | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/vta/apps/tsim_example/hardware/chisel/Makefile b/vta/apps/tsim_example/hardware/chisel/Makefile
index 92c13e70c9b4..d5d629136c0e 100644
--- a/vta/apps/tsim_example/hardware/chisel/Makefile
+++ b/vta/apps/tsim_example/hardware/chisel/Makefile
@@ -95,11 +95,14 @@ $(verilator_build_dir)/V$(TOP).cpp: $(chisel_build_dir)/$(TOP).v
 	verilator $(verilator_opt) $<
 
 verilog: $(chisel_build_dir)/$(TOP).v
-$(chisel_build_dir)/$(TOP).v:
+$(chisel_build_dir)/$(TOP).v: install_vta_package
 	sbt 'test:runMain test.Elaborate --target-dir $(chisel_build_dir) --top-name $(TOP)'
 
-clean:
-	-rm -rf target project/target project/project
+install_vta_package:
+	cd $(vta_dir)/hardware/chisel && sbt publishLocal
 
-cleanall:
+cleanall: clean
 	-rm -rf $(build_dir)
+
+clean:
+	-rm -rf target project/target project/project

From 4bcb87a3d99dfe2845975917bbcb4c892d5e9e01 Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 18:19:17 +0000
Subject: [PATCH 09/15] add makefile for verilog backend

---
 .../tsim_example/hardware/chisel/Makefile     |   8 +-
 .../tsim_example/hardware/verilog/Makefile    | 100 ++++++++++++++++++
 .../hardware/verilog/{ => src}/Accel.v        |   0
 .../hardware/verilog/{ => src}/Compute.v      |   0
 .../hardware/verilog/{ => src}/RegFile.v      |   0
 .../hardware/verilog/{ => src}/TestAccel.v    |   0
 6 files changed, 103 insertions(+), 5 deletions(-)
 create mode 100644 vta/apps/tsim_example/hardware/verilog/Makefile
 rename vta/apps/tsim_example/hardware/verilog/{ => src}/Accel.v (100%)
 rename vta/apps/tsim_example/hardware/verilog/{ => src}/Compute.v (100%)
 rename vta/apps/tsim_example/hardware/verilog/{ => src}/RegFile.v (100%)
 rename vta/apps/tsim_example/hardware/verilog/{ => src}/TestAccel.v (100%)

diff --git a/vta/apps/tsim_example/hardware/chisel/Makefile b/vta/apps/tsim_example/hardware/chisel/Makefile
index d5d629136c0e..463786a9a806 100644
--- a/vta/apps/tsim_example/hardware/chisel/Makefile
+++ b/vta/apps/tsim_example/hardware/chisel/Makefile
@@ -40,7 +40,7 @@ LIBNAME = libhw
 vta_dir = $(abspath ../../../../)
 tvm_dir = $(abspath ../../../../../)
 build_dir = $(abspath .)/$(BUILD_NAME)
-verilator_build_dir = $(build_dir)//verilator
+verilator_build_dir = $(build_dir)/verilator
 chisel_build_dir = $(build_dir)/chisel
 
 verilator_opt = --cc
@@ -88,6 +88,7 @@ default: lib
 
 lib: $(build_dir)/$(LIBNAME).so
 $(build_dir)/$(LIBNAME).so: $(verilator_build_dir)/V$(TOP).cpp
+	echo $(cxx_files)
 	g++ $(cxx_flags) $(cxx_files) -o $@
 
 verilator: $(verilator_build_dir)/V$(TOP).cpp
@@ -101,8 +102,5 @@ $(chisel_build_dir)/$(TOP).v: install_vta_package
 install_vta_package:
 	cd $(vta_dir)/hardware/chisel && sbt publishLocal
 
-cleanall: clean
-	-rm -rf $(build_dir)
-
 clean:
-	-rm -rf target project/target project/project
+	-rm -rf $(build_dir) target project/target project/project
diff --git a/vta/apps/tsim_example/hardware/verilog/Makefile b/vta/apps/tsim_example/hardware/verilog/Makefile
new file mode 100644
index 000000000000..8a4369aa8075
--- /dev/null
+++ b/vta/apps/tsim_example/hardware/verilog/Makefile
@@ -0,0 +1,100 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+ifeq (, $(shell which verilator))
+ $(error "No Verilator in $(PATH), consider doing apt-get install verilator")
+endif
+
+# Change VERILATOR_INC_DIR if Verilator is installed on a different location
+ifeq (, $(VERILATOR_INC_DIR))
+  ifeq (, $(wildcard /usr/local/share/verilator/include/*))
+    ifeq (, $(wildcard /usr/share/verilator/include/*))
+      $(error "Verilator include directory is not set properly")
+    else
+      VERILATOR_INC_DIR := /usr/share/verilator/include
+    endif
+  else
+      VERILATOR_INC_DIR := /usr/local/share/verilator/include
+  endif
+endif
+
+TOP = TestAccel
+BUILD_NAME = build
+USE_TRACE = 0
+LIBNAME = libhw
+
+vta_dir = $(abspath ../../../../)
+tvm_dir = $(abspath ../../../../../)
+build_dir = $(abspath .)/$(BUILD_NAME)
+
+verilator_opt = --cc
+verilator_opt += +define+RANDOMIZE_GARBAGE_ASSIGN
+verilator_opt += +define+RANDOMIZE_REG_INIT
+verilator_opt += +define+RANDOMIZE_MEM_INIT
+verilator_opt += --x-assign unique
+verilator_opt += --output-split 20000
+verilator_opt += --output-split-cfuncs 20000
+verilator_opt += --top-module ${TOP}
+verilator_opt += -Mdir ${build_dir}
+
+cxx_flags = -O2 -Wall -fPIC -shared
+cxx_flags += -fvisibility=hidden -std=c++11
+cxx_flags += -DVL_TSIM_NAME=V$(TOP)
+cxx_flags += -DVL_PRINTF=printf
+cxx_flags += -DVL_USER_FINISH
+cxx_flags += -DVM_COVERAGE=0
+cxx_flags += -DVM_SC=0
+cxx_flags += -Wno-sign-compare
+cxx_flags += -include V$(TOP).h
+cxx_flags += -I$(build_dir)
+cxx_flags += -I$(VERILATOR_INC_DIR)
+cxx_flags += -I$(VERILATOR_INC_DIR)/vltstd
+cxx_flags += -I$(vta_dir)/include
+cxx_flags += -I$(tvm_dir)/include
+cxx_flags += -I$(tvm_dir)/3rdparty/dlpack/include
+
+cxx_files = $(VERILATOR_INC_DIR)/verilated.cpp
+cxx_files += $(VERILATOR_INC_DIR)/verilated_dpi.cpp
+cxx_files += $(wildcard $(build_dir)/*.cpp)
+cxx_files += $(vta_dir)/hardware/dpi/tsim_device.cc
+
+v_files = $(wildcard $(abspath .)/src/*.v $(vta_dir)/hardware/chisel/src/main/resources/verilog/*.v)
+
+ifneq ($(USE_TRACE), 0)
+  verilator_opt += --trace
+  cxx_flags += -DVM_TRACE=1
+  cxx_flags += -DTSIM_TRACE_FILE=$(build_dir)/$(TOP).vcd
+  cxx_files += $(VERILATOR_INC_DIR)/verilated_vcd_c.cpp
+else
+  cxx_flags += -DVM_TRACE=0
+endif
+
+default: lib
+
+lib: $(build_dir)/$(LIBNAME).so
+$(build_dir)/$(LIBNAME).so: $(build_dir)/V$(TOP).cpp
+	g++ $(cxx_flags) $(cxx_files) -o $@
+
+verilator: $(build_dir)/V$(TOP).cpp
+$(build_dir)/V$(TOP).cpp: $(v_files) | $(build_dir)
+	verilator $(verilator_opt) $(v_files)
+
+$(build_dir):
+	mkdir -p $@
+
+clean:
+	-rm -rf $(build_dir)
diff --git a/vta/apps/tsim_example/hardware/verilog/Accel.v b/vta/apps/tsim_example/hardware/verilog/src/Accel.v
similarity index 100%
rename from vta/apps/tsim_example/hardware/verilog/Accel.v
rename to vta/apps/tsim_example/hardware/verilog/src/Accel.v
diff --git a/vta/apps/tsim_example/hardware/verilog/Compute.v b/vta/apps/tsim_example/hardware/verilog/src/Compute.v
similarity index 100%
rename from vta/apps/tsim_example/hardware/verilog/Compute.v
rename to vta/apps/tsim_example/hardware/verilog/src/Compute.v
diff --git a/vta/apps/tsim_example/hardware/verilog/RegFile.v b/vta/apps/tsim_example/hardware/verilog/src/RegFile.v
similarity index 100%
rename from vta/apps/tsim_example/hardware/verilog/RegFile.v
rename to vta/apps/tsim_example/hardware/verilog/src/RegFile.v
diff --git a/vta/apps/tsim_example/hardware/verilog/TestAccel.v b/vta/apps/tsim_example/hardware/verilog/src/TestAccel.v
similarity index 100%
rename from vta/apps/tsim_example/hardware/verilog/TestAccel.v
rename to vta/apps/tsim_example/hardware/verilog/src/TestAccel.v

From 3ea53a656d1fba1d82e3b6bf0bfedfbee92e1a3d Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 18:47:39 +0000
Subject: [PATCH 10/15] update drivers

---
 vta/apps/tsim_example/CMakeLists.txt         |  10 +-
 vta/apps/tsim_example/Makefile               |  21 ++-
 vta/apps/tsim_example/cmake/modules/hw.cmake | 152 -------------------
 vta/apps/tsim_example/cmake/modules/sw.cmake |  24 ---
 vta/apps/tsim_example/config/config.json     |   7 -
 vta/apps/tsim_example/config/config.py       |  61 --------
 vta/apps/tsim_example/python/tsim/driver.py  |  24 ++-
 vta/apps/tsim_example/tests/python/accel.py  |   2 +-
 8 files changed, 32 insertions(+), 269 deletions(-)
 delete mode 100644 vta/apps/tsim_example/cmake/modules/hw.cmake
 delete mode 100644 vta/apps/tsim_example/cmake/modules/sw.cmake
 delete mode 100644 vta/apps/tsim_example/config/config.json
 delete mode 100644 vta/apps/tsim_example/config/config.py

diff --git a/vta/apps/tsim_example/CMakeLists.txt b/vta/apps/tsim_example/CMakeLists.txt
index 28cfded75823..56a5b9a3b228 100644
--- a/vta/apps/tsim_example/CMakeLists.txt
+++ b/vta/apps/tsim_example/CMakeLists.txt
@@ -34,6 +34,10 @@ if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" AND
   set(CMAKE_CXX_FLAGS "-faligned-new ${CMAKE_CXX_FLAGS}")
 endif()
 
-# Module rules
-include(cmake/modules/hw.cmake)
-include(cmake/modules/sw.cmake)
+file(GLOB TSIM_SW_SRC src/driver.cc)
+add_library(sw SHARED ${TSIM_SW_SRC})
+target_include_directories(sw PRIVATE ${VTA_DIR}/include)
+
+if(APPLE)
+  set_target_properties(sw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
+endif(APPLE)
diff --git a/vta/apps/tsim_example/Makefile b/vta/apps/tsim_example/Makefile
index d775a34e7f9f..5e70c53a2687 100644
--- a/vta/apps/tsim_example/Makefile
+++ b/vta/apps/tsim_example/Makefile
@@ -17,20 +17,29 @@
 
 export PYTHONPATH:=$(PWD)/python:$(PYTHONPATH)
 
-BUILD_DIR = $(shell python3 config/config.py --get-build-name)
+BUILD_NAME = build
+build_dir = $(abspath .)/$(BUILD_NAME)
 
-default: cmake run
+default: verilog driver run
 
 .PHONY: cmake
 
-cmake: | $(BUILD_DIR)
-	cd $(BUILD_DIR) && cmake .. && make
+driver: | $(build_dir)
+	cd $(build_dir) && cmake .. && make
 
-$(BUILD_DIR):
+$(build_dir):
 	mkdir -p $@
 
+verilog:
+	make -C hardware/verilog
+
+chisel:
+	make -C hardware/chisel
+
 run:
 	python3 tests/python/accel.py
 
 clean:
-	-rm -rf $(BUILD_DIR)
+	-rm -rf $(build_dir)
+	make -C hardware/chisel clean
+	make -C hardware/verilog clean
diff --git a/vta/apps/tsim_example/cmake/modules/hw.cmake b/vta/apps/tsim_example/cmake/modules/hw.cmake
deleted file mode 100644
index 102df9987752..000000000000
--- a/vta/apps/tsim_example/cmake/modules/hw.cmake
+++ /dev/null
@@ -1,152 +0,0 @@
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements.  See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership.  The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License.  You may obtain a copy of the License at
-#
-#   http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied.  See the License for the
-# specific language governing permissions and limitations
-# under the License.
-
-if(MSVC)
-  message(STATUS "[TSIM_HW] build is skipped in Windows..")
-else()
-  find_program(PYTHON NAMES python python3 python3.6)
-  find_program(VERILATOR NAMES verilator)
-
-  if (VERILATOR AND PYTHON)
-
-    if (TSIM_TOP_NAME STREQUAL "")
-      message(FATAL_ERROR "[TSIM_HW] TSIM_TOP_NAME should be defined")
-    endif()
-
-    if (TSIM_BUILD_NAME STREQUAL "")
-      message(FATAL_ERROR "[TSIM_HW] TSIM_BUILD_NAME should be defined")
-    endif()
-
-    set(TSIM_CONFIG ${PYTHON} ${CMAKE_CURRENT_SOURCE_DIR}/config/config.py)
-
-    execute_process(COMMAND ${TSIM_CONFIG} --get-target OUTPUT_VARIABLE TSIM_TARGET OUTPUT_STRIP_TRAILING_WHITESPACE)
-    execute_process(COMMAND ${TSIM_CONFIG} --get-top-name OUTPUT_VARIABLE TSIM_TOP_NAME OUTPUT_STRIP_TRAILING_WHITESPACE)
-    execute_process(COMMAND ${TSIM_CONFIG} --get-build-name OUTPUT_VARIABLE TSIM_BUILD_NAME OUTPUT_STRIP_TRAILING_WHITESPACE)
-    execute_process(COMMAND ${TSIM_CONFIG} --get-use-trace OUTPUT_VARIABLE TSIM_USE_TRACE OUTPUT_STRIP_TRAILING_WHITESPACE)
-    execute_process(COMMAND ${TSIM_CONFIG} --get-trace-name OUTPUT_VARIABLE TSIM_TRACE_NAME OUTPUT_STRIP_TRAILING_WHITESPACE)
-
-    set(TSIM_BUILD_DIR ${CMAKE_CURRENT_SOURCE_DIR}/${TSIM_BUILD_NAME})
-
-    if (TSIM_TARGET STREQUAL "chisel")
-
-      find_program(SBT NAMES sbt)
-
-      if (SBT)
-
-        # Install Chisel VTA package for DPI modules
-        set(VTA_CHISEL_DIR ${VTA_DIR}/hardware/chisel)
-
-        execute_process(WORKING_DIRECTORY ${VTA_CHISEL_DIR}
-          COMMAND ${SBT} publishLocal RESULT_VARIABLE RETCODE)
-
-        if (NOT RETCODE STREQUAL "0")
-          message(FATAL_ERROR "[TSIM_HW] sbt failed to install VTA scala package")
-        endif()
-
-        # Chisel - Scala to Verilog compilation
-        set(TSIM_CHISEL_DIR ${CMAKE_CURRENT_SOURCE_DIR}/hardware/chisel)
-        set(CHISEL_BUILD_DIR ${TSIM_BUILD_DIR}/chisel)
-        set(CHISEL_OPT "test:runMain test.Elaborate --target-dir ${CHISEL_BUILD_DIR} --top-name ${TSIM_TOP_NAME}")
-
-        execute_process(WORKING_DIRECTORY ${TSIM_CHISEL_DIR} COMMAND ${SBT} ${CHISEL_OPT} RESULT_VARIABLE RETCODE)
-
-        if (NOT RETCODE STREQUAL "0")
-          message(FATAL_ERROR "[TSIM_HW] sbt failed to compile from Chisel to Verilog.")
-        endif()
-
-        file(GLOB VERILATOR_RTL_SRC ${CHISEL_BUILD_DIR}/*.v)
-
-      else()
-        message(FATAL_ERROR "[TSIM_HW] sbt should be installed for Chisel")
-      endif() # sbt
-
-    elseif (TSIM_TARGET STREQUAL "verilog")
-
-      set(VTA_VERILOG_DIR ${VTA_DIR}/hardware/chisel/src/main/resources/verilog)
-      set(TSIM_VERILOG_DIR ${CMAKE_CURRENT_SOURCE_DIR}/hardware/verilog)
-      file(GLOB VERILATOR_RTL_SRC ${VTA_VERILOG_DIR}/*.v ${TSIM_VERILOG_DIR}/*.v)
-
-    else()
-      message(FATAL_ERROR "[TSIM_HW] target language can be only verilog or chisel...")
-    endif() # TSIM_TARGET
-
-    if (TSIM_TARGET STREQUAL "chisel" OR TSIM_TARGET STREQUAL "verilog")
-
-      # Check if tracing can be enabled
-      if (NOT TSIM_USE_TRACE STREQUAL "off")
-        message(STATUS "[TSIM_HW] Verilog enable tracing")
-      else()
-        message(STATUS "[TSIM_HW] Verilator disable tracing")
-      endif()
-
-      # Verilator - Verilog to C++ compilation
-      set(VERILATOR_BUILD_DIR ${TSIM_BUILD_DIR}/verilator)
-      set(VERILATOR_OPT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_REG_INIT)
-      list(APPEND VERILATOR_OPT +define+RANDOMIZE_MEM_INIT --x-assign unique)
-      list(APPEND VERILATOR_OPT --output-split 20000 --output-split-cfuncs 20000)
-      list(APPEND VERILATOR_OPT --top-module ${TSIM_TOP_NAME} -Mdir ${VERILATOR_BUILD_DIR})
-      list(APPEND VERILATOR_OPT --cc ${VERILATOR_RTL_SRC})
-
-      if (NOT TSIM_USE_TRACE STREQUAL "off")
-        list(APPEND VERILATOR_OPT --trace)
-      endif()
-
-      execute_process(COMMAND ${VERILATOR} ${VERILATOR_OPT} RESULT_VARIABLE RETCODE)
-
-      if (NOT RETCODE STREQUAL "0")
-        message(FATAL_ERROR "[TSIM_HW] Verilator failed to compile Verilog to C++...")
-      endif()
-
-      # Build shared library (.so)
-      set(VTA_HW_DPI_DIR ${VTA_DIR}/hardware/dpi)
-      if (EXISTS /usr/local/share/verilator/include)
-        set(VERILATOR_INC_DIR /usr/local/share/verilator/include)
-      elseif (EXISTS /usr/share/verilator/include)
-        set(VERILATOR_INC_DIR /usr/share/verilator/include)
-      else()
-        message(FATAL_ERROR "[TSIM_HW] Verilator include directory not found")
-      endif()
-      set(VERILATOR_LIB_SRC ${VERILATOR_INC_DIR}/verilated.cpp ${VERILATOR_INC_DIR}/verilated_dpi.cpp)
-
-      if (NOT TSIM_USE_TRACE STREQUAL "off")
-        list(APPEND VERILATOR_LIB_SRC ${VERILATOR_INC_DIR}/verilated_vcd_c.cpp)
-      endif()
-
-      file(GLOB VERILATOR_GEN_SRC ${VERILATOR_BUILD_DIR}/*.cpp)
-      file(GLOB VERILATOR_SRC ${VTA_HW_DPI_DIR}/tsim_device.cc)
-      add_library(hw SHARED ${VERILATOR_LIB_SRC} ${VERILATOR_GEN_SRC} ${VERILATOR_SRC})
-
-      set(VERILATOR_DEF VL_USER_FINISH VL_TSIM_NAME=V${TSIM_TOP_NAME} VL_PRINTF=printf VM_COVERAGE=0 VM_SC=0)
-      if (NOT TSIM_USE_TRACE STREQUAL "off")
-        list(APPEND VERILATOR_DEF VM_TRACE=1 TSIM_TRACE_FILE=${TSIM_BUILD_DIR}/${TSIM_TRACE_NAME}.vcd)
-      else()
-        list(APPEND VERILATOR_DEF VM_TRACE=0)
-      endif()
-      target_compile_definitions(hw PRIVATE ${VERILATOR_DEF})
-      target_compile_options(hw PRIVATE -Wno-sign-compare -include V${TSIM_TOP_NAME}.h)
-      target_include_directories(hw PRIVATE ${VERILATOR_BUILD_DIR} ${VERILATOR_INC_DIR} ${VERILATOR_INC_DIR}/vltstd ${VTA_DIR}/include)
-
-      if(APPLE)
-        set_target_properties(hw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
-      endif(APPLE)
-
-    endif() # TSIM_TARGET STREQUAL "chisel" OR TSIM_TARGET STREQUAL "verilog"
-
-  else()
-    message(STATUS "[TSIM_HW] could not find Python or Verilator, build is skipped...")
-  endif() # VERILATOR
-endif() # MSVC
diff --git a/vta/apps/tsim_example/cmake/modules/sw.cmake b/vta/apps/tsim_example/cmake/modules/sw.cmake
deleted file mode 100644
index d0368c3edc75..000000000000
--- a/vta/apps/tsim_example/cmake/modules/sw.cmake
+++ /dev/null
@@ -1,24 +0,0 @@
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements.  See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership.  The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License.  You may obtain a copy of the License at
-#
-#   http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied.  See the License for the
-# specific language governing permissions and limitations
-# under the License.
-
-file(GLOB TSIM_SW_SRC src/driver.cc)
-add_library(sw SHARED ${TSIM_SW_SRC})
-target_include_directories(sw PRIVATE ${VTA_DIR}/include)
-
-if(APPLE)
-  set_target_properties(sw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
-endif(APPLE)
diff --git a/vta/apps/tsim_example/config/config.json b/vta/apps/tsim_example/config/config.json
deleted file mode 100644
index b1d0a1b7f3fe..000000000000
--- a/vta/apps/tsim_example/config/config.json
+++ /dev/null
@@ -1,7 +0,0 @@
-{
-  "TARGET" : "chisel",
-  "TOP_NAME" : "TestAccel",
-  "BUILD_NAME" : "build",
-  "USE_TRACE" : "off",
-  "TRACE_NAME" : "trace"
-}
diff --git a/vta/apps/tsim_example/config/config.py b/vta/apps/tsim_example/config/config.py
deleted file mode 100644
index 6ff4f4234cf0..000000000000
--- a/vta/apps/tsim_example/config/config.py
+++ /dev/null
@@ -1,61 +0,0 @@
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements.  See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership.  The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License.  You may obtain a copy of the License at
-#
-#   http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied.  See the License for the
-# specific language governing permissions and limitations
-# under the License.
-
-import os.path as osp
-import sys
-import json
-import argparse
-
-cur = osp.abspath(osp.dirname(__file__))
-cfg = json.load(open(osp.join(cur, 'config.json')))
-
-def main():
-    """Main function"""
-    parser = argparse.ArgumentParser()
-    parser.add_argument("--get-target", action="store_true",
-                        help="Get target language, i.e. verilog or chisel")
-    parser.add_argument("--get-top-name", action="store_true",
-                        help="Get hardware design top name")
-    parser.add_argument("--get-build-name", action="store_true",
-                        help="Get build folder name")
-    parser.add_argument("--get-use-trace", action="store_true",
-                        help="Get use trace")
-    parser.add_argument("--get-trace-name", action="store_true",
-                        help="Get trace filename")
-    args = parser.parse_args()
-
-    if len(sys.argv) == 1:
-        parser.print_help()
-        return
-
-    if args.get_target:
-        print(cfg['TARGET'])
-
-    if args.get_top_name:
-        print(cfg['TOP_NAME'])
-
-    if args.get_build_name:
-        print(cfg['BUILD_NAME'])
-
-    if args.get_use_trace:
-        print(cfg['USE_TRACE'])
-
-    if args.get_trace_name:
-        print(cfg['TRACE_NAME'])
-
-if __name__ == "__main__":
-    main()
diff --git a/vta/apps/tsim_example/python/tsim/driver.py b/vta/apps/tsim_example/python/tsim/driver.py
index 0571cff7eb2e..6d8e7181b707 100644
--- a/vta/apps/tsim_example/python/tsim/driver.py
+++ b/vta/apps/tsim_example/python/tsim/driver.py
@@ -17,31 +17,25 @@
 
 import tvm
 import ctypes
-import json
 import os.path as osp
 from sys import platform
 
-def driver(hw_lib, sw_lib):
+def driver(hw_backend):
     """Init hardware and software shared library for accelerator
 
      Parameters
      ------------
-     hw_lib : str
-        Name of hardware shared library
+     hw_backend : str
+        Hardware backend can be verilog or chisel
 
-     sw_lib : str
-        Name of software shared library
     """
+    _ext = ".dylib" if platform == "darwin" else ".so"
+    _hw_libname = "libhw" + _ext
+    _sw_libname = "libsw" + _ext
     _cur_path = osp.dirname(osp.abspath(osp.expanduser(__file__)))
-    _root_path = osp.join(_cur_path, "..", "..")
-    _cfg_file = osp.join(_root_path, "config", "config.json")
-    _cfg = json.load(open(_cfg_file))
-    if not hw_lib.endswith(("dylib", "so")):
-        hw_lib += ".dylib" if platform == "darwin" else ".so"
-    if not sw_lib.endswith(("dylib", "so")):
-        sw_lib += ".dylib" if platform == "darwin" else ".so"
-    _hw_lib = osp.join(_root_path, _cfg['BUILD_NAME'], hw_lib)
-    _sw_lib = osp.join(_root_path, _cfg['BUILD_NAME'], sw_lib)
+    if hw_backend in ("verilog", "chisel"):
+        _hw_lib = osp.join(_cur_path, "..", "..", "hardware", hw_backend, "build", _hw_libname)
+    _sw_lib = osp.join(_cur_path, "..", "..", "build", _sw_libname)
 
     def load_dll(dll):
         try:
diff --git a/vta/apps/tsim_example/tests/python/accel.py b/vta/apps/tsim_example/tests/python/accel.py
index 23c25c8c1b46..81f52356f274 100644
--- a/vta/apps/tsim_example/tests/python/accel.py
+++ b/vta/apps/tsim_example/tests/python/accel.py
@@ -27,7 +27,7 @@ def test_accel():
     ctx = tvm.cpu(0)
     a = tvm.nd.array(np.random.randint(rmax, size=n).astype("uint64"), ctx)
     b = tvm.nd.array(np.zeros(n).astype("uint64"), ctx)
-    f = driver("libhw", "libsw")
+    f = driver("verilog")
     cycles = f(a, b, c)
     msg = "cycles:{0:4} n:{1:2} c:{2:2}".format(cycles, n, c)
     np.testing.assert_equal(b.asnumpy(), a.asnumpy() + c, err_msg = "[FAIL] " + msg)

From 6d6d0bab25a1c9d1309720249431ef138b601cb9 Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 18:58:32 +0000
Subject: [PATCH 11/15] update

---
 vta/apps/tsim_example/Makefile                |  9 +++--
 vta/apps/tsim_example/README.md               | 25 +++++-------
 .../tsim_example/tests/python/chisel_accel.py | 38 +++++++++++++++++++
 .../python/{accel.py => verilog_accel.py}     |  0
 4 files changed, 54 insertions(+), 18 deletions(-)
 create mode 100644 vta/apps/tsim_example/tests/python/chisel_accel.py
 rename vta/apps/tsim_example/tests/python/{accel.py => verilog_accel.py} (100%)

diff --git a/vta/apps/tsim_example/Makefile b/vta/apps/tsim_example/Makefile
index 5e70c53a2687..ea8358b3dfe3 100644
--- a/vta/apps/tsim_example/Makefile
+++ b/vta/apps/tsim_example/Makefile
@@ -20,8 +20,11 @@ export PYTHONPATH:=$(PWD)/python:$(PYTHONPATH)
 BUILD_NAME = build
 build_dir = $(abspath .)/$(BUILD_NAME)
 
-default: verilog driver run
+default: verilog driver run_verilog
 
+run_chisel: chisel driver 
+	python3 tests/python/chisel_accel.py
+	
 .PHONY: cmake
 
 driver: | $(build_dir)
@@ -36,8 +39,8 @@ verilog:
 chisel:
 	make -C hardware/chisel
 
-run:
-	python3 tests/python/accel.py
+run_verilog:
+	python3 tests/python/verilog_accel.py
 
 clean:
 	-rm -rf $(build_dir)
diff --git a/vta/apps/tsim_example/README.md b/vta/apps/tsim_example/README.md
index 8f1230e9ba7e..1145c28c74ff 100644
--- a/vta/apps/tsim_example/README.md
+++ b/vta/apps/tsim_example/README.md
@@ -49,29 +49,24 @@ sudo apt install verilator sbt
 ## Setup in TVM
 
 1. Install `verilator` and `sbt` as described above
-2. Change `TARGET` to `tsim` in `<tvm-root>/tvm/vta/config/vta_config.json`
-3. Build [tvm](https://docs.tvm.ai/install/from_source.html#build-the-shared-library)
+2. Build [tvm](https://docs.tvm.ai/install/from_source.html#build-the-shared-library)
 
 ## How to run VTA TSIM examples
 
-There are two sample VTA accelerators (add-by-one) designed in Chisel3 and Verilog to show how *TSIM* works.
+There are two sample VTA accelerators, add-a-constant, designed in Chisel3 and Verilog to show how *TSIM* works.
 The default `TARGET` language for these two implementations is Verilog. The following instructions show
 how to run both of them:
 
-* Verilog add-by-one
+* Test Verilog backend
     * Go to `<tvm-root>/vta/apps/tsim_example`
-    * Run `make` to build and run add-by-one test
+    * Run `make`
 
-* Chisel3 add-by-one
-    * Open `<tvm-root>/vta/apps/tsim_example/python/tsim/config.json`
-    * Change `TARGET` from `verilog` to `chisel`
-    * Go to `tvm/vta/apps/tsim_example`
-    * Run `make` to build and run add-by-one test
+* Test Chisel3 backend
+    * Open `<tvm-root>/vta/apps/tsim_example`
+    * Run `make run_chisel`
 
 * Some pointers
-    * Add-by-one test `<tvm-root>/vta/apps/tsim_example/tests/python/add_by_one.py`
-    * Add-by-one accelerator in Verilog `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
-    * Add-by-one accelerator in Chisel3 `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
+    * Verilog and Chisel3 tests in `<tvm-root>/vta/apps/tsim_example/tests/python`
+    * Verilog accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
+    * Chisel3 accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
     * Software driver that handles the accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
-    * Build cmake script for software library`<tvm-root>/vta/apps/tsim_example/cmake/modules/sw.cmake`
-    * Build cmake script for hardware library`<tvm-root>/vta/apps/tsim_example/cmake/modules/hw.cmake`
diff --git a/vta/apps/tsim_example/tests/python/chisel_accel.py b/vta/apps/tsim_example/tests/python/chisel_accel.py
new file mode 100644
index 000000000000..1115cb335a3c
--- /dev/null
+++ b/vta/apps/tsim_example/tests/python/chisel_accel.py
@@ -0,0 +1,38 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+import tvm
+import numpy as np
+
+from tsim.driver import driver
+
+def test_accel():
+    rmax = 64
+    n = np.random.randint(1, rmax)
+    c = np.random.randint(0, rmax)
+    ctx = tvm.cpu(0)
+    a = tvm.nd.array(np.random.randint(rmax, size=n).astype("uint64"), ctx)
+    b = tvm.nd.array(np.zeros(n).astype("uint64"), ctx)
+    f = driver("chisel")
+    cycles = f(a, b, c)
+    msg = "cycles:{0:4} n:{1:2} c:{2:2}".format(cycles, n, c)
+    np.testing.assert_equal(b.asnumpy(), a.asnumpy() + c, err_msg = "[FAIL] " + msg)
+    print("[PASS] " + msg)
+
+if __name__ == "__main__":
+    for i in range(10):
+        test_accel()
diff --git a/vta/apps/tsim_example/tests/python/accel.py b/vta/apps/tsim_example/tests/python/verilog_accel.py
similarity index 100%
rename from vta/apps/tsim_example/tests/python/accel.py
rename to vta/apps/tsim_example/tests/python/verilog_accel.py

From f560d98c613149f494ce6cb12c5bfbb7d20e4a2c Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 20:49:42 +0000
Subject: [PATCH 12/15] rename

---
 vta/apps/tsim_example/README.md                          | 3 ++-
 vta/apps/tsim_example/python/{tsim => accel}/__init__.py | 0
 vta/apps/tsim_example/python/{tsim => accel}/driver.py   | 0
 vta/apps/tsim_example/tests/python/chisel_accel.py       | 2 +-
 vta/apps/tsim_example/tests/python/verilog_accel.py      | 2 +-
 5 files changed, 4 insertions(+), 3 deletions(-)
 rename vta/apps/tsim_example/python/{tsim => accel}/__init__.py (100%)
 rename vta/apps/tsim_example/python/{tsim => accel}/driver.py (100%)

diff --git a/vta/apps/tsim_example/README.md b/vta/apps/tsim_example/README.md
index 1145c28c74ff..25eddad1dcc7 100644
--- a/vta/apps/tsim_example/README.md
+++ b/vta/apps/tsim_example/README.md
@@ -69,4 +69,5 @@ how to run both of them:
     * Verilog and Chisel3 tests in `<tvm-root>/vta/apps/tsim_example/tests/python`
     * Verilog accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
     * Chisel3 accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
-    * Software driver that handles the accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
+    * Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
+    * Software Python driver (frontend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/python/tsim`
diff --git a/vta/apps/tsim_example/python/tsim/__init__.py b/vta/apps/tsim_example/python/accel/__init__.py
similarity index 100%
rename from vta/apps/tsim_example/python/tsim/__init__.py
rename to vta/apps/tsim_example/python/accel/__init__.py
diff --git a/vta/apps/tsim_example/python/tsim/driver.py b/vta/apps/tsim_example/python/accel/driver.py
similarity index 100%
rename from vta/apps/tsim_example/python/tsim/driver.py
rename to vta/apps/tsim_example/python/accel/driver.py
diff --git a/vta/apps/tsim_example/tests/python/chisel_accel.py b/vta/apps/tsim_example/tests/python/chisel_accel.py
index 1115cb335a3c..6ab0bf5a36eb 100644
--- a/vta/apps/tsim_example/tests/python/chisel_accel.py
+++ b/vta/apps/tsim_example/tests/python/chisel_accel.py
@@ -18,7 +18,7 @@
 import tvm
 import numpy as np
 
-from tsim.driver import driver
+from accel.driver import driver
 
 def test_accel():
     rmax = 64
diff --git a/vta/apps/tsim_example/tests/python/verilog_accel.py b/vta/apps/tsim_example/tests/python/verilog_accel.py
index 81f52356f274..97f636cbfde1 100644
--- a/vta/apps/tsim_example/tests/python/verilog_accel.py
+++ b/vta/apps/tsim_example/tests/python/verilog_accel.py
@@ -18,7 +18,7 @@
 import tvm
 import numpy as np
 
-from tsim.driver import driver
+from accel.driver import driver
 
 def test_accel():
     rmax = 64

From 6dabb1ec0aa0c611fc015b825179c6cd98021f48 Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 20:50:49 +0000
Subject: [PATCH 13/15] update README

---
 vta/apps/tsim_example/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/vta/apps/tsim_example/README.md b/vta/apps/tsim_example/README.md
index 25eddad1dcc7..56696fe533fc 100644
--- a/vta/apps/tsim_example/README.md
+++ b/vta/apps/tsim_example/README.md
@@ -70,4 +70,4 @@ how to run both of them:
     * Verilog accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
     * Chisel3 accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
     * Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
-    * Software Python driver (frontend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/python/tsim`
+    * Software Python driver (frontend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/python/accel`

From d1e3ea754b1af1a4541044a3bfa4f743539a17af Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 20:51:17 +0000
Subject: [PATCH 14/15] put default sim back

---
 vta/config/vta_config.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/vta/config/vta_config.json b/vta/config/vta_config.json
index 3f49ecd01da0..602af0126816 100644
--- a/vta/config/vta_config.json
+++ b/vta/config/vta_config.json
@@ -1,5 +1,5 @@
 {
-  "TARGET" : "tsim",
+  "TARGET" : "sim",
   "HW_FREQ" : 100,
   "HW_CLK_TARGET" : 7,
   "HW_VER" : "0.0.0",

From b8c616bcda063c9988b315381cd82412b15d3ded Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@gmail.com>
Date: Tue, 11 Jun 2019 22:45:12 +0000
Subject: [PATCH 15/15] set counter to zero

---
 vta/apps/tsim_example/src/driver.cc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/vta/apps/tsim_example/src/driver.cc b/vta/apps/tsim_example/src/driver.cc
index c1dc61f8bee1..ad9d6ddf2620 100644
--- a/vta/apps/tsim_example/src/driver.cc
+++ b/vta/apps/tsim_example/src/driver.cc
@@ -54,20 +54,23 @@ class Device {
  private:
   void Launch(uint32_t c, uint32_t length, void* inp, void* out) {
     dpi_->Launch(wait_cycles_);
+    // set counter to zero
+    dpi_->WriteReg(0x04, 0);
     dpi_->WriteReg(0x08, c);
     dpi_->WriteReg(0x0c, length);
     dpi_->WriteReg(0x10, get_half_addr(inp, false));
     dpi_->WriteReg(0x14, get_half_addr(inp, true));
     dpi_->WriteReg(0x18, get_half_addr(out, false));
     dpi_->WriteReg(0x1c, get_half_addr(out, true));
-    dpi_->WriteReg(0x00, 0x1); // launch
+    // launch
+    dpi_->WriteReg(0x00, 0x1);
   }
 
   uint32_t WaitForCompletion() {
     uint32_t i, val;
     for (i = 0; i < wait_cycles_; i++) {
       val = dpi_->ReadReg(0x00);
-      if (val == 2) break; // finish
+      if (val == 2) break;  // finish
     }
     val = dpi_->ReadReg(0x04);
     return val;