From ffd7ca0b71a0d7d4503dc2da33839cdc75745b9a Mon Sep 17 00:00:00 2001 From: Yizhi Liu Date: Mon, 30 Sep 2019 12:19:24 -0700 Subject: [PATCH] add ic_bn % 4 checker --- topi/python/topi/arm_cpu/tensor_intrin.py | 2 +- topi/python/topi/generic/conv2d.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/topi/python/topi/arm_cpu/tensor_intrin.py b/topi/python/topi/arm_cpu/tensor_intrin.py index 5b14ea7d9d76c..2f300a18e117b 100644 --- a/topi/python/topi/arm_cpu/tensor_intrin.py +++ b/topi/python/topi/arm_cpu/tensor_intrin.py @@ -55,7 +55,7 @@ def dot_int8_int8_int32(int32_lanes, dtype='uint'): intrin : TensorIntrin The ARM uint8 TensorIntrin that can be used in tensorizing schedule """ - num_int8_elements = 4 # 4 uint8 elements in int32 + num_int8_elements = 4 # 4 int8 elements in int32 data = tvm.placeholder((num_int8_elements,), dtype='%s8' % dtype, name='data') kernel = tvm.placeholder((int32_lanes, num_int8_elements), dtype='%s8' % dtype, name='kernel') diff --git a/topi/python/topi/generic/conv2d.py b/topi/python/topi/generic/conv2d.py index e1382d183c530..332c2fdad4595 100644 --- a/topi/python/topi/generic/conv2d.py +++ b/topi/python/topi/generic/conv2d.py @@ -144,8 +144,8 @@ def schedule_conv_NCHWc_cpu_common_int8(s, cfg, data, conv_out, last, int32_lane ow_chunk, ow_block = s[CC].split(ow, factor=reg_n) - # Skylake and future processors have 16 vector lanes assert oc_bn % int32_lanes == 0 + assert ic_bn % 4 == 0 # 4 (u)int8 elements in (u)int32 oc_f_inner, oc_s_inner = s[CC].split(oc_block, factor=int32_lanes) @@ -209,6 +209,7 @@ def schedule_conv_NCHWc_cpu_1x1_int8(s, cfg, data, conv_out, last, int32_lanes=1 kh, kw, ic_outer, ic_f_inner, ic_s_inner = s[CC].op.reduce_axis assert oc_bn % int32_lanes == 0 + assert ic_bn % 4 == 0 # 4 (u)int8 elements in (u)int32 oc_f_inner, oc_s_inner = s[CC].split(oc_block, factor=int32_lanes)