diff --git a/docs/vta/install.md b/docs/vta/install.md index 6c87b4edd288a..7ef4cecda7f8b 100644 --- a/docs/vta/install.md +++ b/docs/vta/install.md @@ -187,28 +187,28 @@ This third and last guide allows users to generate custom VTA bitstreams using f ### Xilinx Toolchain Installation -We recommend using `Vivado 2018.2` since our scripts have been tested to work on this version of the Xilinx toolchains. +We recommend using `Vivado 2018.3` since our scripts have been tested to work on this version of the Xilinx toolchains. Our guide is written for Linux (Ubuntu) installation. -You’ll need to install Xilinx’ FPGA compilation toolchain, [Vivado HL WebPACK 2018.2](https://www.xilinx.com/products/design-tools/vivado.html), which a license-free version of the Vivado HLx toolchain. +You’ll need to install Xilinx’ FPGA compilation toolchain, [Vivado HL WebPACK 2018.3](https://www.xilinx.com/products/design-tools/vivado.html), which a license-free version of the Vivado HLx toolchain. #### Obtaining and Launching the Vivado GUI Installer -1. Go to the [download webpage](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2018-2.html), and download the Linux Self Extracting Web Installer for Vivado HLx 2018.2: WebPACK and Editions. +1. Go to the [download webpage](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2018-3.html), and download the Linux Self Extracting Web Installer for Vivado HLx 2018.3: WebPACK and Editions. 2. You’ll have to sign in with a Xilinx account. This requires a Xilinx account creation that will take 2 minutes. -3. Complete the Name and Address Verification by clicking “Next”, and you will get the opportunity to download a binary file, called `Xilinx_Vivado_SDK_Web_2018.2_0614_1954_Lin64.bin`. +3. Complete the Name and Address Verification by clicking “Next”, and you will get the opportunity to download a binary file, called `Xilinx_Vivado_SDK_Web_2018.3_1207_2324_Lin64.bin`. 4. Now that the file is downloaded, go to your `Downloads` directory, and change the file permissions so it can be executed: ```bash -chmod u+x Xilinx_Vivado_SDK_Web_2018.2_0614_1954_Lin64.bin +chmod u+x Xilinx_Vivado_SDK_Web_2018.3_1207_2324_Lin64.bin ``` 5. Now you can execute the binary: ```bash -./Xilinx_Vivado_SDK_Web_2018.2_0614_1954_Lin64.bin +./Xilinx_Vivado_SDK_Web_2018.3_1207_2324_Lin64.bin ``` #### Xilinx Vivado GUI Installer Steps -At this point you've launched the Vivado 2018.2 Installer GUI program. +At this point you've launched the Vivado 2018.3 Installer GUI program. 1. Click “Next” on the *Welcome* screen. 2. On the *Select Install Type* screen, enter your Xilinx user credentials under the “User Authentication” box and select the “Download and Install Now” option before clicking “Next” . @@ -230,8 +230,8 @@ At this point you've launched the Vivado 2018.2 Installer GUI program. The last step is to update your `~/.bashrc` with the following lines. This will include all of the Xilinx binary paths so you can launch compilation scripts from the command line. ```bash -# Xilinx Vivado 2018.2 environment -export XILINX_VIVADO=${XILINX_PATH}/Vivado/2018.2 +# Xilinx Vivado 2018.3 environment +export XILINX_VIVADO=${XILINX_PATH}/Vivado/2018.3 export PATH=${XILINX_VIVADO}/bin:${PATH} ``` diff --git a/vta/config/pynq_sample.json b/vta/config/pynq_sample.json index 5c37108e6b12f..247d255c34382 100644 --- a/vta/config/pynq_sample.json +++ b/vta/config/pynq_sample.json @@ -1,8 +1,12 @@ { "TARGET" : "pynq", - "HW_FREQ" : 100, - "HW_CLK_TARGET" : 8, "HW_VER" : "0.0.0", + "HW_FREQ" : 100, + "HW_CLK_TARGET" : 7, + "ALU_EN" : true, + "MUL_EN" : false, + "GEMM_II" : 1, + "TALU_II" : 2, "LOG_INP_WIDTH" : 3, "LOG_WGT_WIDTH" : 3, "LOG_ACC_WIDTH" : 5, @@ -10,6 +14,7 @@ "LOG_BATCH" : 0, "LOG_BLOCK_IN" : 4, "LOG_BLOCK_OUT" : 4, + "LOG_BUS_WIDTH" : 6, "LOG_UOP_BUFF_SIZE" : 15, "LOG_INP_BUFF_SIZE" : 15, "LOG_WGT_BUFF_SIZE" : 18, diff --git a/vta/config/vta_config.json b/vta/config/vta_config.json index 602af01268165..2a1f3aad600cc 100644 --- a/vta/config/vta_config.json +++ b/vta/config/vta_config.json @@ -1,8 +1,12 @@ { "TARGET" : "sim", + "HW_VER" : "0.0.0", "HW_FREQ" : 100, "HW_CLK_TARGET" : 7, - "HW_VER" : "0.0.0", + "ALU_EN" : true, + "MUL_EN" : false, + "GEMM_II" : 1, + "TALU_II" : 2, "LOG_INP_WIDTH" : 3, "LOG_WGT_WIDTH" : 3, "LOG_ACC_WIDTH" : 5, @@ -10,6 +14,7 @@ "LOG_BATCH" : 0, "LOG_BLOCK_IN" : 4, "LOG_BLOCK_OUT" : 4, + "LOG_BUS_WIDTH" : 6, "LOG_UOP_BUFF_SIZE" : 15, "LOG_INP_BUFF_SIZE" : 15, "LOG_WGT_BUFF_SIZE" : 18, diff --git a/vta/config/vta_config.py b/vta/config/vta_config.py index ea07e5a7770c6..808a07b6d14d8 100644 --- a/vta/config/vta_config.py +++ b/vta/config/vta_config.py @@ -54,6 +54,14 @@ def main(): help="print the target") parser.add_argument("--cfg-str", action="store_true", help="print the configuration string") + parser.add_argument("--get-aluen", action="store_true", + help="returns whether ALU is enabled") + parser.add_argument("--get-mulen", action="store_true", + help="returns whether mul in ALU is enabled") + parser.add_argument("--get-gemmii", action="store_true", + help="returns the GEMM core II") + parser.add_argument("--get-taluii", action="store_true", + help="returns the tensor ALU core II") parser.add_argument("--get-inpwidth", action="store_true", help="returns log of input bitwidth") parser.add_argument("--get-wgtwidth", action="store_true", @@ -68,6 +76,8 @@ def main(): help="returns log of tensor block in dimension") parser.add_argument("--get-blockout", action="store_true", help="returns log of tensor block out dimension") + parser.add_argument("--get-buswidth", action="store_true", + help="returns log of bus width in b") parser.add_argument("--get-uopbuffsize", action="store_true", help="returns log of micro-op buffer size in B") parser.add_argument("--get-inpbuffsize", action="store_true", @@ -103,9 +113,31 @@ def main(): raise RuntimeError("Cannot find config in %s" % str(path_list)) cfg = json.load(open(ok_path_list[0])) cfg["LOG_OUT_BUFF_SIZE"] = ( - cfg["LOG_ACC_BUFF_SIZE"] + - cfg["LOG_OUT_WIDTH"] - - cfg["LOG_ACC_WIDTH"]) + cfg["LOG_ACC_BUFF_SIZE"] + + cfg["LOG_OUT_WIDTH"] + - cfg["LOG_ACC_WIDTH"]) + # Generate bitstream config string. + # Needs to match the BITSTREAM string in python/vta/environment.py + cfg["BITSTREAM"] = "{}_{}x{}x{}_a{}w{}o{}s{}_{}_{}_{}_{}_{}MHz_{}ns_gii{}".format( + cfg["TARGET"], + (1 << cfg["LOG_BATCH"]), + (1 << cfg["LOG_BLOCK_IN"]), + (1 << cfg["LOG_BLOCK_OUT"]), + (1 << cfg["LOG_INP_WIDTH"]), + (1 << cfg["LOG_WGT_WIDTH"]), + (1 << cfg["LOG_OUT_WIDTH"]), + (1 << cfg["LOG_ACC_WIDTH"]), + cfg["LOG_UOP_BUFF_SIZE"], + cfg["LOG_INP_BUFF_SIZE"], + cfg["LOG_WGT_BUFF_SIZE"], + cfg["LOG_ACC_BUFF_SIZE"], + cfg["HW_FREQ"], + cfg["HW_CLK_TARGET"], + cfg["GEMM_II"]) + if cfg["ALU_EN"]: + cfg["BITSTREAM"] += "_aii{}".format(cfg["TALU_II"]) + if cfg["MUL_EN"] and cfg["ALU_EN"]: + cfg["BITSTREAM"] += "_mul" pkg = get_pkg_config(cfg) if args.target: @@ -121,6 +153,8 @@ def main(): cflags_str = " ".join(pkg.cflags) if cfg["TARGET"] == "pynq": cflags_str += " -DVTA_TARGET_PYNQ" + if cfg["TARGET"] == "ultra96": + cflags_str += " -DVTA_TARGET_ULTRA96" print(cflags_str) if args.ldflags: @@ -134,21 +168,19 @@ def main(): fo.write(pkg.cfg_json) if args.cfg_str: - # Needs to match the BITSTREAM string in python/vta/environment.py - cfg_str = "{}x{}x{}_{}bx{}b_{}_{}_{}_{}_{}MHz_{}ns_v{}".format( - (1 << cfg["LOG_BATCH"]), - (1 << cfg["LOG_BLOCK_IN"]), - (1 << cfg["LOG_BLOCK_OUT"]), - (1 << cfg["LOG_INP_WIDTH"]), - (1 << cfg["LOG_WGT_WIDTH"]), - cfg["LOG_UOP_BUFF_SIZE"], - cfg["LOG_INP_BUFF_SIZE"], - cfg["LOG_WGT_BUFF_SIZE"], - cfg["LOG_ACC_BUFF_SIZE"], - cfg["HW_FREQ"], - cfg["HW_CLK_TARGET"], - cfg["HW_VER"].replace('.', '_')) - print(cfg_str) + print(cfg["BITSTREAM"]) + + if args.get_aluen: + print(cfg["ALU_EN"]) + + if args.get_mulen: + print(cfg["MUL_EN"]) + + if args.get_gemmii: + print(cfg["GEMM_II"]) + + if args.get_taluii: + print(cfg["TALU_II"]) if args.get_inpwidth: print(cfg["LOG_INP_WIDTH"]) @@ -171,6 +203,9 @@ def main(): if args.get_blockout: print(cfg["LOG_BLOCK_OUT"]) + if args.get_buswidth: + print(cfg["LOG_BUS_WIDTH"]) + if args.get_uopbuffsize: print(cfg["LOG_UOP_BUFF_SIZE"]) diff --git a/vta/hardware/xilinx/Makefile b/vta/hardware/xilinx/Makefile index af13cdc166f80..79082036f535f 100644 --- a/vta/hardware/xilinx/Makefile +++ b/vta/hardware/xilinx/Makefile @@ -31,18 +31,14 @@ VIVADO = vivado HSI = hsi # HLS mode -MODE = skip_sim +MODE = all # Debug flag -DEBUG = false +DEBUG = False # SLURM -SLURM = false -# Prevent generation of DSP -NO_DSP = false -# Prevent generation of ALU -NO_ALU = false +SLURM = False # Process VTA JSON config -VTA_CONFIG = python $(CURDIR)/../../config/vta_config.py +VTA_CONFIG := python $(CURDIR)/../../config/vta_config.py CFLAGS := $(shell ${VTA_CONFIG} --cflags) VTA_TARGET := $(shell ${VTA_CONFIG} --target) @@ -56,17 +52,22 @@ VTA_OUT_WIDTH := $(shell ${VTA_CONFIG} --get-outwidth) VTA_BATCH := $(shell ${VTA_CONFIG} --get-batch) VTA_IN_BLOCK := $(shell ${VTA_CONFIG} --get-blockin) VTA_OUT_BLOCK := $(shell ${VTA_CONFIG} --get-blockout) +VTA_BUS_WIDTH := $(shell ${VTA_CONFIG} --get-buswidth) VTA_UOP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-uopbuffsize) VTA_INP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-inpbuffsize) VTA_WGT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-wgtbuffsize) VTA_ACC_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-accbuffsize) VTA_OUT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-outbuffsize) +VTA_ALU_EN := $(shell ${VTA_CONFIG} --get-aluen) +VTA_MUL_EN := $(shell ${VTA_CONFIG} --get-mulen) #--------------------- # FPGA Parameters #-------------------- -VTA_CLOCK_FREQ = $(shell ${VTA_CONFIG} --get-fpgafreq) -VTA_TARGET_PER = $(shell ${VTA_CONFIG} --get-fpgaper) +VTA_CLOCK_FREQ := $(shell ${VTA_CONFIG} --get-fpgafreq) +VTA_TARGET_PER := $(shell ${VTA_CONFIG} --get-fpgaper) +VTA_GEMM_II := $(shell ${VTA_CONFIG} --get-gemmii) +VTA_TALU_II := $(shell ${VTA_CONFIG} --get-taluii) #--------------------- # Compilation parameters @@ -76,20 +77,21 @@ VTA_TARGET_PER = $(shell ${VTA_CONFIG} --get-fpgaper) VTA_HW_COMP_THREADS = 8 # Derive config name -CONF = $(shell ${VTA_CONFIG} --cfg-str) -IP_BUILD_PATH = $(BUILD_DIR)/hls/$(CONF) -HW_BUILD_PATH = $(BUILD_DIR)/vivado/$(CONF) +CONF := $(shell ${VTA_CONFIG} --cfg-str) +IP_BUILD_PATH := $(BUILD_DIR)/hls/$(CONF) +HW_BUILD_PATH := $(BUILD_DIR)/vivado/$(CONF) -ifeq ($(SLURM), true) +# Build on local scratch drive when using cluster +ifeq ($(SLURM), True) IP_BUILD_PATH = /scratch/hls/$(CONF) HW_BUILD_PATH = /scratch/vivado/$(CONF) endif # IP file path -IP_PATH = $(BUILD_DIR)/hls/$(CONF)/solution0/impl/ip/xilinx_com_hls_vta_1_0.zip +IP_PATH := $(BUILD_DIR)/hls/$(CONF)/vta_compute/solution0/impl/ip/xilinx_com_hls_compute_1_0.zip # Bitstream file path -BIT_PATH = $(BUILD_DIR)/vivado/$(CONF)/export/$(CONF).bit +BIT_PATH := $(BUILD_DIR)/vivado/$(CONF)/export/$(CONF).bit .PHONY: all ip bit bsp clean clean_all @@ -101,13 +103,15 @@ $(IP_PATH): $(SRC_DIR)/* mkdir -p $(IP_BUILD_PATH) cd $(IP_BUILD_PATH) && \ $(VIVADO_HLS) -f $(SCRIPT_DIR)/hls.tcl \ - -tclargs $(SRC_DIR) $(SIM_DIR) $(TEST_DIR) $(INCLUDE_DIR) \ - $(MODE) $(DEBUG) $(NO_DSP) $(NO_ALU) $(VTA_TARGET_PER) \ + -tclargs $(VTA_TARGET) \ + $(SRC_DIR) $(SIM_DIR) $(TEST_DIR) $(INCLUDE_DIR) \ + $(MODE) $(DEBUG) $(VTA_ALU_EN) $(VTA_MUL_EN) \ + $(VTA_TARGET_PER) $(VTA_GEMM_II) $(VTA_TALU_II) \ $(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_ACC_WIDTH) $(VTA_OUT_WIDTH) \ - $(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \ + $(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) $(VTA_BUS_WIDTH) \ $(VTA_UOP_BUFF_SIZE) $(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) \ $(VTA_ACC_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE) -ifeq ($(SLURM), true) +ifeq ($(SLURM), True) mkdir -p $(BUILD_DIR)/hls mv $(IP_BUILD_PATH) $(BUILD_DIR)/hls/. endif @@ -116,11 +120,12 @@ $(BIT_PATH): $(IP_PATH) mkdir -p $(HW_BUILD_PATH) cd $(HW_BUILD_PATH) && \ $(VIVADO) -mode tcl -source $(SCRIPT_DIR)/vivado.tcl \ - -tclargs $(BUILD_DIR)/hls/$(CONF) $(VTA_HW_COMP_THREADS) $(VTA_CLOCK_FREQ) \ + -tclargs $(VTA_TARGET) $(BUILD_DIR)/hls/$(CONF) $(VTA_HW_COMP_THREADS) \ + $(VTA_CLOCK_FREQ) $(VTA_GEMM_II) \ $(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_OUT_WIDTH) \ $(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \ $(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE) -ifeq ($(SLURM), true) +ifeq ($(SLURM), True) mkdir -p $(BUILD_DIR)/vivado mv $(HW_BUILD_PATH) $(BUILD_DIR)/vivado/. endif diff --git a/vta/hardware/xilinx/scripts/hls.tcl b/vta/hardware/xilinx/scripts/hls.tcl index 3d308bc58d257..75979c8c3af84 100644 --- a/vta/hardware/xilinx/scripts/hls.tcl +++ b/vta/hardware/xilinx/scripts/hls.tcl @@ -14,132 +14,147 @@ # KIND, either express or implied. See the License for the # specific language governing permissions and limitations # under the License. -# -# Copyright (c) 2018 by Contributors -# file: hls.tcl -# brief: HLS generation script. -# # Command line arguments: -# Arg 1: path to design sources -# Arg 2: path to sim sources -# Arg 3: path to test sources -# Arg 4: path to include sources -# Arg 5: mode -# Arg 6: debug -# Arg 7: no_dsp -# Arg 8: no_alu -# Arg 9: target clock period -# Arg 10: input type width (log) -# Arg 11: weight type width (log) -# Arg 12: accum type width (log) -# Arg 13: output type width (log) -# Arg 14: batch size (log) -# Arg 15: in block size (log) -# Arg 16: out block size (log) -# Arg 17: uop buffer size in B (log) -# Arg 18: inp buffer size in B (log) -# Arg 19: wgt buffer size in B (log) -# Arg 20: acc buffer size in B (log) -# Arg 21: out buffer size in B (log) - -if { [llength $argv] eq 23 } { - set src_dir [lindex $argv 2] - set sim_dir [lindex $argv 3] - set test_dir [lindex $argv 4] - set include_dir [lindex $argv 5] - set mode [lindex $argv 6] - set debug [lindex $argv 7] - set no_dsp [lindex $argv 8] - set no_alu [lindex $argv 9] - set target_period [lindex $argv 10] - set inp_width [lindex $argv 11] - set wgt_width [lindex $argv 12] - set acc_width [lindex $argv 13] - set out_width [lindex $argv 14] - set batch [lindex $argv 15] - set block_in [lindex $argv 16] - set block_out [lindex $argv 17] - set uop_buff_size [lindex $argv 18] - set inp_buff_size [lindex $argv 19] - set wgt_buff_size [lindex $argv 20] - set acc_buff_size [lindex $argv 21] - set out_buff_size [lindex $argv 22] +# Arg 1: target (FPGA) +# Arg 2: path to design sources +# Arg 3: path to sim sources +# Arg 4: path to test sources +# Arg 5: path to include sources +# Arg 6: mode +# Arg 7: debug +# Arg 8: alu_ena +# Arg 9: mul_ena +# Arg 10: target clock period +# Arg 11: target II for GEMM +# Arg 12: target II for tensor ALU +# Arg 13: input type width (log) +# Arg 14: weight type width (log) +# Arg 15: accum type width (log) +# Arg 16: output type width (log) +# Arg 17: batch size (log) +# Arg 18: in block size (log) +# Arg 19: out block size (log) +# Arg 20: bus width in b (log) +# Arg 21: uop buffer size in B (log) +# Arg 22: inp buffer size in B (log) +# Arg 23: wgt buffer size in B (log) +# Arg 24: acc buffer size in B (log) +# Arg 25: out buffer size in B (log) + +if { [llength $argv] eq 27 } { + set target [lindex $argv 2] + set src_dir [lindex $argv 3] + set sim_dir [lindex $argv 4] + set test_dir [lindex $argv 5] + set include_dir [lindex $argv 6] + set mode [lindex $argv 7] + set debug [lindex $argv 8] + set alu_ena [lindex $argv 9] + set mul_ena [lindex $argv 10] + set target_period [lindex $argv 11] + set target_gemm_ii [lindex $argv 12] + set target_alu_ii [lindex $argv 13] + set inp_width [lindex $argv 14] + set wgt_width [lindex $argv 15] + set acc_width [lindex $argv 16] + set out_width [lindex $argv 17] + set batch [lindex $argv 18] + set block_in [lindex $argv 19] + set block_out [lindex $argv 20] + set bus_width [lindex $argv 21] + set uop_buff_size [lindex $argv 22] + set inp_buff_size [lindex $argv 23] + set wgt_buff_size [lindex $argv 24] + set acc_buff_size [lindex $argv 25] + set out_buff_size [lindex $argv 26] } else { - set src_dir "../src" - set sim_dir "../sim" - set test_dir "../../src/test" - set include_dir "../../include" - set mode "all" - set debug "false" - set no_dsp "true" - set no_alu "false" - set target_period 10 - set inp_width 3 - set wgt_width 3 - set acc_width 5 - set out_width 3 - set batch 1 - set block_in 4 - set block_out 4 - set uop_buff_size 15 - set inp_buff_size 15 - set wgt_buff_size 15 - set acc_buff_size 17 - set out_buff_size 15 + puts "Not enough arguments provided!" exit } +puts "about to start doing some stuff" + + # Initializes the HLS design and sets HLS pragmas for memory partitioning. # This is necessary because of a Vivado restriction that doesn't allow for # buses wider than 1024 bits. -proc init_design {per inp_width wgt_width out_width batch block_in block_out} { +proc init_design {target per g_ii a_ii bus_width inp_width wgt_width out_width acc_width batch block_in block_out alu_ena} { # Set device number - set_part {xc7z020clg484-1} + if {$target=="pynq"} { + set_part {xc7z020clg484-1} + } elseif {$target=="ultra96"} { + set_part {xczu3eg-sbva484-1-e} + } elseif {$target=="zcu102"} { + set_part {xczu9eg-ffvb1156-2-e} + } elseif {$target=="f1"} { + set_part {xcvu9p-flgb2104-2-i} + # config_interface -m_axi_addr64 + } + + # Max bus width (supported by Vivado) + set max_width 1024 + + # Set axi width + set axi_width [expr {1 << $bus_width}] # Set the clock frequency create_clock -period $per -name default - # Set input partition factor to (INP_VECTOR_WIDTH*BATCH/1024) - set inp_partition_factor [expr {(1 << ($inp_width + $block_in + $batch)) / 1024}] + # Set pipeline directive + set_directive_pipeline -II $g_ii "gemm/READ_GEMM_UOP" + + if {$alu_ena=="True"} { + set_directive_pipeline -II $a_ii "alu/READ_ALU_UOP" + } + + # Set input partition factor to (INP_VECTOR_WIDTH*BATCH/(1024*g_ii) + set inp_bus_width [expr {(1 << ($inp_width + $block_in + $batch)) / $g_ii}] + set inp_partition_factor [expr {$inp_bus_width / $max_width}] if {$inp_partition_factor == 0} { - set_directive_array_reshape -type complete -dim 2 "load" inp_mem - set_directive_array_reshape -type complete -dim 2 "compute" inp_mem + set inp_reshape_factor [expr {$inp_bus_width / $axi_width}] + set_directive_array_reshape -type block -factor $inp_reshape_factor -dim 2 "load" inp_mem + set_directive_array_reshape -type block -factor $inp_reshape_factor -dim 2 "compute" inp_mem } else { - # Set input reshaping factor below to (1024/INP_VECTOR_WIDTH) - set inp_reshape_factor [expr {1024 / (1 << ($inp_width + $block_in))}] + set inp_reshape_factor [expr {$max_width / $axi_width}] set_directive_array_partition -type block -factor $inp_partition_factor -dim 2 "load" inp_mem set_directive_array_partition -type block -factor $inp_partition_factor -dim 2 "compute" inp_mem set_directive_array_reshape -type block -factor $inp_reshape_factor -dim 2 "load" inp_mem set_directive_array_reshape -type block -factor $inp_reshape_factor -dim 2 "compute" inp_mem } - # Set weight partition factor to (WGT_VECTOR_WIDTH*BLOCK_OUT/1024) - set wgt_partition_factor [expr {(1 << ($wgt_width + $block_in + $block_out)) / 1024}] + # Set weight partition factor to (WGT_VECTOR_WIDTH*BLOCK_OUT/(1024*g_ii)) + set wgt_bus_width [expr {(1 << ($wgt_width + $block_in + $block_out)) / $g_ii}] + set wgt_partition_factor [expr {$wgt_bus_width / $max_width}] if {$wgt_partition_factor == 0} { - set_directive_array_reshape -type complete -dim 2 "load" wgt_mem - set_directive_array_reshape -type complete -dim 2 "compute" wgt_mem + set wgt_reshape_factor [expr {$wgt_bus_width / $axi_width}] + set_directive_array_reshape -type block -factor $wgt_reshape_factor -dim 2 "load" wgt_mem + set_directive_array_reshape -type block -factor $wgt_reshape_factor -dim 2 "compute" wgt_mem } else { - # Set weight reshaping factor below to (1024/WGT_VECTOR_WIDTH) - set wgt_reshape_factor [expr {1024 / (1 << ($wgt_width + $block_in))}] + set wgt_reshape_factor [expr {$max_width / $axi_width}] set_directive_array_partition -type block -factor $wgt_partition_factor -dim 2 "load" wgt_mem set_directive_array_partition -type block -factor $wgt_partition_factor -dim 2 "compute" wgt_mem set_directive_array_reshape -type block -factor $wgt_reshape_factor -dim 2 "load" wgt_mem set_directive_array_reshape -type block -factor $wgt_reshape_factor -dim 2 "compute" wgt_mem } - # Set output partition factor to (OUT_VECTOR_WIDTH*BATCH/1024) - set out_partition_factor [expr {(1 << ($out_width + $block_out + $batch)) / 1024}] + # Set output partition factor to (OUT_VECTOR_WIDTH*BATCH/(1024*g_ii)) + set out_bus_width [expr {(1 << ($out_width + $block_out + $batch)) / $g_ii}] + set out_partition_factor [expr {$out_bus_width / $max_width}] if {$out_partition_factor == 0} { - set_directive_array_reshape -type complete -dim 2 "compute" out_mem - set_directive_array_reshape -type complete -dim 2 "store" out_mem + set out_reshape_factor [expr {$out_bus_width / $axi_width}] + set_directive_array_reshape -type block -factor $out_reshape_factor -dim 2 "compute" out_mem + set_directive_array_reshape -type block -factor $out_reshape_factor -dim 2 "store" out_mem } else { - # Set output reshaping factor below to (1024/OUT_VECTOR_WIDTH) - set out_reshape_factor [expr {1024 / (1 << ($out_width + $block_out))}] + set out_reshape_factor [expr {$max_width / $axi_width}] set_directive_array_partition -type block -factor $out_partition_factor -dim 2 "compute" out_mem set_directive_array_partition -type block -factor $out_partition_factor -dim 2 "store" out_mem set_directive_array_reshape -type block -factor $out_reshape_factor -dim 2 "compute" out_mem set_directive_array_reshape -type block -factor $out_reshape_factor -dim 2 "store" out_mem } + # Set accumulator partition factor + # set acc_bus_width [expr {(1 << ($acc_width + $block_out + $batch)) / $g_ii}] + # set acc_reshape_factor [expr {$acc_bus_width / $axi_width}] + # set_directive_array_partition -type block -factor $acc_reshape_factor -dim 2 "compute" acc_mem } # C define flags to pass to compiler @@ -149,17 +164,19 @@ set cflags "-I $include_dir -I $src_dir -I $test_dir \ -DVTA_LOG_BATCH=$batch -DVTA_LOG_BLOCK_OUT=$block_out -DVTA_LOG_BLOCK_IN=$block_in \ -DVTA_LOG_UOP_BUFF_SIZE=$uop_buff_size -DVTA_LOG_INP_BUFF_SIZE=$inp_buff_size \ -DVTA_LOG_WGT_BUFF_SIZE=$wgt_buff_size -DVTA_LOG_ACC_BUFF_SIZE=$acc_buff_size \ - -DVTA_LOG_OUT_BUFF_SIZE=$out_buff_size" -if {$debug=="true"} { + -DVTA_LOG_OUT_BUFF_SIZE=$out_buff_size -DVTA_LOG_BUS_WIDTH=$bus_width \ + -DVTA_GEMM_II=$target_gemm_ii" +if {$debug=="True"} { append cflags " -DVTA_DEBUG=1" } -if {$no_dsp=="true"} { - append cflags " -DNO_DSP" +if {$alu_ena=="True"} { + append cflags " -DALU_EN" } -if {$no_alu=="true"} { - append cflags " -DNO_ALU" +if {$mul_ena=="True"} { + append cflags " -DMUL_EN" } + # HLS behavioral sim if {$mode=="all" || $mode=="sim"} { open_project vta_sim @@ -168,7 +185,7 @@ if {$mode=="all" || $mode=="sim"} { add_files -tb $sim_dir/vta_test.cc -cflags $cflags add_files -tb $test_dir/test_lib.cc -cflags $cflags open_solution "solution0" - init_design $target_period $inp_width $wgt_width $out_width $batch $block_in $block_out + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csim_design -clean close_project } @@ -179,7 +196,7 @@ if {$mode=="all" || $mode=="skip_sim" || $mode=="fetch"} { set_top fetch add_files $src_dir/vta.cc -cflags $cflags open_solution "solution0" - init_design $target_period $inp_width $wgt_width $out_width $batch $block_in $block_out + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csynth_design if {$mode=="all" || $mode=="skip_sim"} { export_design -format ip_catalog @@ -193,7 +210,7 @@ if {$mode=="all" || $mode=="skip_sim" || $mode=="load"} { set_top load add_files $src_dir/vta.cc -cflags $cflags open_solution "solution0" - init_design $target_period $inp_width $wgt_width $out_width $batch $block_in $block_out + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csynth_design if {$mode=="all" || $mode=="skip_sim"} { export_design -format ip_catalog @@ -207,7 +224,7 @@ if {$mode=="all" || $mode=="skip_sim" || $mode=="compute"} { set_top compute add_files $src_dir/vta.cc -cflags $cflags open_solution "solution0" - init_design $target_period $inp_width $wgt_width $out_width $batch $block_in $block_out + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csynth_design if {$mode=="all" || $mode=="skip_sim"} { export_design -format ip_catalog @@ -221,7 +238,7 @@ if {$mode=="all" || $mode=="skip_sim" || $mode=="store"} { set_top store add_files $src_dir/vta.cc -cflags $cflags open_solution "solution0" - init_design $target_period $inp_width $wgt_width $out_width $batch $block_in $block_out + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csynth_design if {$mode=="all" || $mode=="skip_sim"} { export_design -format ip_catalog diff --git a/vta/hardware/xilinx/scripts/vivado.tcl b/vta/hardware/xilinx/scripts/vivado.tcl index 9cfa10ea74826..3a2e1d3cb0b7c 100644 --- a/vta/hardware/xilinx/scripts/vivado.tcl +++ b/vta/hardware/xilinx/scripts/vivado.tcl @@ -14,69 +14,47 @@ # KIND, either express or implied. See the License for the # specific language governing permissions and limitations # under the License. -# -# Copyright (c) 2018 by Xilinx, Contributors -# file: vivado.tcl -# brief: Vivado compilation script. Partially automatically generated -# by Vivado. -# # Check if script is running in correct Vivado version. -set scripts_vivado_version 2018.2 +set scripts_vivado_version 2018.3 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado \ - <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. \ - Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado \ - <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP \ - Status...\", then run write_bd_tcl to create an updated script."} - + <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado."} return 1 } # Parse argument list, derive the clock to utilize -set clock_id 0 -if { [llength $argv] eq 12 } { - set ip_path [lindex $argv 0] - set num_threads [lindex $argv 1] - set clock_freq [lindex $argv 2] - set inp_width [expr 1 << [lindex $argv 3]] - set wgt_width [expr 1 << [lindex $argv 4]] - set out_width [expr 1 << [lindex $argv 5]] - set batch [expr 1 << [lindex $argv 6]] - set out_block [expr 1 << [lindex $argv 7]] - set in_block [expr 1 << [lindex $argv 8]] - set inp_mem_size [expr 1 << [lindex $argv 9]] - set wgt_mem_size [expr 1 << [lindex $argv 10]] - set out_mem_size [expr 1 << [lindex $argv 11]] - if {$clock_freq eq 100} { - set clock_id 0 - puts "Setting clock frequency to 100MHz" - } elseif {$clock_freq eq 142} { - set clock_id 1 - puts "Setting clock frequency to 142MHz" - } elseif {$clock_freq eq 167} { - set clock_id 3 - puts "Setting clock frequency to 167MHz" - } elseif {$clock_freq eq 200} { - set clock_id 2 - puts "Setting clock frequency to 200MHz" - } else { - set clock_id 0 - puts "Unrecognized clock frequency, setting clock to 100MHz" - } +if { [llength $argv] eq 14 } { + set target [lindex $argv 0] + set ip_path [lindex $argv 1] + set num_threads [lindex $argv 2] + set clock_freq [lindex $argv 3] + set gemm_ii [lindex $argv 4] + set inp_width [expr 1 << [lindex $argv 5]] + set wgt_width [expr 1 << [lindex $argv 6]] + set out_width [expr 1 << [lindex $argv 7]] + set batch [expr 1 << [lindex $argv 8]] + set out_block [expr 1 << [lindex $argv 9]] + set in_block [expr 1 << [lindex $argv 10]] + set inp_mem_size [expr 1 << [lindex $argv 11]] + set wgt_mem_size [expr 1 << [lindex $argv 12]] + set out_mem_size [expr 1 << [lindex $argv 13]] } else { - puts "Arg list incomplete: \ - \ + \ " return 1 } +# Max bus width supported by Vivado +set max_bus_width 1024 + # Derive input mem parameters -set inp_mem_width [expr $inp_width * $batch * $in_block] -set inp_bus_width 1024 +set inp_mem_width [expr $inp_width * $batch * $in_block / $gemm_ii] +set inp_bus_width $max_bus_width set inp_part [expr $inp_mem_width / $inp_bus_width] if {[expr $inp_part == 0]} { set inp_part 1 @@ -85,8 +63,8 @@ if {[expr $inp_part == 0]} { set inp_mem_depth [expr $inp_mem_size * 8 / ($inp_mem_width * $inp_part)] # Derive weight mem parameters -set wgt_mem_width [expr $wgt_width * $out_block * $in_block] -set wgt_bus_width 1024 +set wgt_mem_width [expr $wgt_width * $out_block * $in_block / $gemm_ii] +set wgt_bus_width $max_bus_width set wgt_part [expr $wgt_mem_width / $wgt_bus_width] if {[expr $wgt_part == 0]} { set wgt_part 1 @@ -95,8 +73,8 @@ if {[expr $wgt_part == 0]} { set wgt_mem_depth [expr $wgt_mem_size * 8 / ($wgt_mem_width * $wgt_part)] # Derive output mem parameters -set out_mem_width [expr $out_width * $batch * $out_block] -set out_bus_width 1024 +set out_mem_width [expr $out_width * $batch * $out_block / $gemm_ii] +set out_bus_width $max_bus_width set out_part [expr $out_mem_width / $out_bus_width] if {[expr $out_part == 0]} { set out_part 1 @@ -104,8 +82,9 @@ if {[expr $out_part == 0]} { } set out_mem_depth [expr $out_mem_size * 8 / ($out_mem_width * $out_part)] -# User defined paths +# Paths to IP library of VTA modules set proj_name vta +set design_name $proj_name set proj_path "." set ip_lib "ip_lib" set fetch_ip "${ip_path}/vta_fetch/solution0/impl/ip/xilinx_com_hls_fetch_1_0.zip" @@ -114,7 +93,15 @@ set compute_ip "${ip_path}/vta_compute/solution0/impl/ip/xilinx_com_hls_compute_ set store_ip "${ip_path}/vta_store/solution0/impl/ip/xilinx_com_hls_store_1_0.zip" # Create custom project -create_project -force $proj_name $proj_path -part xc7z020clg484-1 +if { ${target} eq "pynq" } { + create_project -force $proj_name $proj_path -part xc7z020clg484-1 +} elseif { ${target} eq "ultra96" } { + create_project -force $proj_name $proj_path -part xczu3eg-sbva484-1-e + set_property BOARD_PART em.avnet.com:ultra96:part0:1.0 [current_project] +} elseif { ${target} eq "zcu102" } { + create_project -force $proj_name $proj_path -part xczu9eg-ffvb1156-2-e + set_property BOARD_PART xilinx.com:zcu102:part0:3.2 [current_project] +} # Update IP repository with generated IP file mkdir $ip_lib @@ -125,84 +112,13 @@ update_ip_catalog -add_ip $load_ip -repo_path $ip_lib update_ip_catalog -add_ip $compute_ip -repo_path $ip_lib update_ip_catalog -add_ip $store_ip -repo_path $ip_lib -# CHANGE DESIGN NAME HERE -set design_name $proj_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> \ - to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable \ - to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable \ - to another value." - set nRet 2 +# Create bd design +create_bd_design $design_name +current_bd_design $design_name -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in \ - project, so creating one..." - - create_bd_design $design_name - - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal \ - to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} - return $nRet -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell clk inp_part wgt_part out_part inp_bus_width inp_mem_depth wgt_bus_width wgt_mem_depth out_bus_width out_mem_depth} { +# Procedure to create entire design. +# Mostly auto-generated by Vivado. +proc create_root_design { parentCell target clk inp_part wgt_part out_part inp_bus_width inp_mem_depth wgt_bus_width wgt_mem_depth out_bus_width out_mem_depth } { variable script_folder @@ -233,253 +149,145 @@ proc create_root_design { parentCell clk inp_part wgt_part out_part inp_bus_widt # Create interface ports - set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] - set FIXED_IO [ create_bd_intf_port -mode Master \ - -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] - - # Create ports + if { ${target} eq "pynq" } { + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master \ + -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + } - # Create instance: axi_interconnect_1, and set properties - set axi_interconnect_1 \ - [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ] - set_property -dict [ list \ - CONFIG.NUM_MI {5} \ - ] $axi_interconnect_1 + # Create instance: proc_sys_reset, and set properties + set proc_sys_reset \ + [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset ] - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + # Create instance: pll_clk, and set properties + set pll_clk [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 pll_clk ] set_property -dict [ list \ - CONFIG.NUM_SI {5} \ - ] $axi_smc - - # Create instance: axi_timer_1, and set properties - set axi_timer_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1 ] + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $clk \ + CONFIG.RESET_PORT {resetn} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + CONFIG.USE_LOCKED {false} \ + ] $pll_clk + + # Create as many SMCs as there are memory channels + if { ${target} eq "pynq" } { + # Create instance: axi_smc0, and set properties + set axi_smc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {5} \ + ] $axi_smc0 + } elseif { ${target} eq "ultra96" || ${target} eq "zcu102" } { + # Create instance: axi_smc0, and set properties + set axi_smc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {4} \ + ] $axi_smc0 + # Create instance: axi_smc1, and set properties + set axi_smc1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc1 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_smc1 + } - # Create instance: compute_0, and set properties - set compute_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:compute:1.0 compute_0 ] + # Create instance: axi_xbar, and set properties + set axi_xbar \ + [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_xbar ] set_property -dict [ list \ - CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE {"1111"} \ - CONFIG.C_M_AXI_DATA_PORT_DATA_WIDTH {64} \ - CONFIG.C_M_AXI_UOP_PORT_CACHE_VALUE {"1111"} \ - ] $compute_0 + CONFIG.NUM_MI {4} \ + CONFIG.NUM_SI {1} \ + ] $axi_xbar + + # Set appropriate cache, prot signals + if { ${target} eq "pynq" } { + set axi_cache "1111" + set axi_prot "000" + } elseif { ${target} eq "ultra96" || ${target} eq "zcu102" } { + set axi_cache "1111" + set axi_prot "010" + } # Create instance: fetch_0, and set properties set fetch_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:fetch:1.0 fetch_0 ] set_property -dict [ list \ - CONFIG.C_M_AXI_INS_PORT_CACHE_VALUE {"1111"} \ - CONFIG.C_M_AXI_INS_PORT_DATA_WIDTH {64} \ + CONFIG.C_M_AXI_INS_PORT_CACHE_VALUE $axi_cache \ + CONFIG.C_M_AXI_INS_PORT_PROT_VALUE $axi_prot \ ] $fetch_0 - # Create instance: g2l_queue, and set properties - set g2l_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 g2l_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {1} \ - CONFIG.Full_Threshold_Assert_Value_axis {1023} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {1024} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TUSER_WIDTH {0} \ - ] $g2l_queue - - # Create instance: g2s_queue, and set properties - set g2s_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 g2s_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {1} \ - CONFIG.Full_Threshold_Assert_Value_axis {1023} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {1024} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TUSER_WIDTH {0} \ - ] $g2s_queue - - # Create instance: gemm_queue, and set properties - set gemm_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 gemm_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {510} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {1} \ - CONFIG.Full_Threshold_Assert_Value_axis {511} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {512} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TDATA_NUM_BYTES {16} \ - CONFIG.TKEEP_WIDTH {16} \ - CONFIG.TSTRB_WIDTH {16} \ - CONFIG.TUSER_WIDTH {0} \ - ] $gemm_queue - - # Create instance: l2g_queue, and set properties - set l2g_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 l2g_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {1} \ - CONFIG.Full_Threshold_Assert_Value_axis {1023} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {1024} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TUSER_WIDTH {0} \ - ] $l2g_queue - # Create instance: load_0, and set properties set load_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:load:1.0 load_0 ] set_property -dict [ list \ - CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE {"1111"} \ + CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE $axi_cache \ + CONFIG.C_M_AXI_DATA_PORT_PROT_VALUE $axi_prot \ ] $load_0 - # Create instance: load_queue, and set properties - set load_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 load_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {510} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {1} \ - CONFIG.Full_Threshold_Assert_Value_axis {511} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {512} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TDATA_NUM_BYTES {16} \ - CONFIG.TKEEP_WIDTH {16} \ - CONFIG.TSTRB_WIDTH {16} \ - CONFIG.TUSER_WIDTH {0} \ - ] $load_queue - - # Create instance: proc_sys_reset, and set properties - set proc_sys_reset \ - [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset ] - - # Create instance: processing_system7_1, and set properties - set processing_system7_1 \ - [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_1 ] - set_property -dict [ list \ - CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ - CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \ - CONFIG.PCW_EN_CLK0_PORT {1} \ - CONFIG.PCW_EN_CLK1_PORT {1} \ - CONFIG.PCW_EN_CLK2_PORT {1} \ - CONFIG.PCW_EN_CLK3_PORT {1} \ - CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ - CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {142.86} \ - CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200} \ - CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {167} \ - CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \ - CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \ - CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ - CONFIG.PCW_IRQ_F2P_INTR {1} \ - CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \ - CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {0} \ - CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \ - CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \ - CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {1} \ - CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ - CONFIG.PCW_USE_HIGH_OCM {1} \ - CONFIG.PCW_USE_S_AXI_ACP {1} \ - CONFIG.PCW_USE_S_AXI_HP0 {0} \ - CONFIG.PCW_USE_S_AXI_HP1 {0} \ - CONFIG.PCW_USE_S_AXI_HP2 {0} \ - CONFIG.PCW_USE_S_AXI_HP3 {0} \ - CONFIG.preset {ZC702} \ - ] $processing_system7_1 - - # Create instance: s2g_queue, and set properties - set s2g_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 s2g_queue ] + # Create instance: compute_0, and set properties + set compute_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:compute:1.0 compute_0 ] set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {1} \ - CONFIG.Full_Threshold_Assert_Value_axis {1023} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {1024} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TUSER_WIDTH {0} \ - ] $s2g_queue + CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE $axi_cache \ + CONFIG.C_M_AXI_DATA_PORT_PROT_VALUE $axi_prot \ + CONFIG.C_M_AXI_UOP_PORT_CACHE_VALUE $axi_cache \ + CONFIG.C_M_AXI_UOP_PORT_PROT_VALUE $axi_prot \ + ] $compute_0 # Create instance: store_0, and set properties set store_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:store:1.0 store_0 ] set_property -dict [ list \ -CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE {"1111"} \ + CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE $axi_cache \ + CONFIG.C_M_AXI_DATA_PORT_PROT_VALUE $axi_prot \ ] $store_0 - # Create instance: store_queue, and set properties - set store_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 store_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {510} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {1} \ - CONFIG.Full_Threshold_Assert_Value_axis {511} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {512} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TDATA_NUM_BYTES {16} \ - CONFIG.TKEEP_WIDTH {16} \ - CONFIG.TSTRB_WIDTH {16} \ - CONFIG.TUSER_WIDTH {0} \ - ] $store_queue - - # Create instance: xlconcat_1, and set properties - set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] - set_property -dict [ list \ -CONFIG.NUM_PORTS {5} \ - ] $xlconcat_1 + # Create command queues and set properties + set cmd_queue_list {load_queue gemm_queue store_queue} + foreach cmd_queue $cmd_queue_list { + set tmp_cmd_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 $cmd_queue ] + set_property -dict [ list \ + CONFIG.Empty_Threshold_Assert_Value_axis {510} \ + CONFIG.Empty_Threshold_Assert_Value_rach {14} \ + CONFIG.Empty_Threshold_Assert_Value_wach {14} \ + CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ + CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ + CONFIG.Full_Flags_Reset_Value {1} \ + CONFIG.Full_Threshold_Assert_Value_axis {511} \ + CONFIG.Full_Threshold_Assert_Value_rach {15} \ + CONFIG.Full_Threshold_Assert_Value_wach {15} \ + CONFIG.Full_Threshold_Assert_Value_wrch {15} \ + CONFIG.INTERFACE_TYPE {AXI_STREAM} \ + CONFIG.Input_Depth_axis {512} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.TDATA_NUM_BYTES {16} \ + CONFIG.TKEEP_WIDTH {16} \ + CONFIG.TSTRB_WIDTH {16} \ + CONFIG.TUSER_WIDTH {0} \ + ] $tmp_cmd_queue + } + + # Create dependence queues and set properties + set dep_queue_list {l2g_queue g2l_queue g2s_queue s2g_queue} + foreach dep_queue $dep_queue_list { + set tmp_dep_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 $dep_queue ] + set_property -dict [ list \ + CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ + CONFIG.Empty_Threshold_Assert_Value_rach {14} \ + CONFIG.Empty_Threshold_Assert_Value_wach {14} \ + CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ + CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ + CONFIG.Full_Flags_Reset_Value {1} \ + CONFIG.Full_Threshold_Assert_Value_axis {1023} \ + CONFIG.Full_Threshold_Assert_Value_rach {15} \ + CONFIG.Full_Threshold_Assert_Value_wach {15} \ + CONFIG.Full_Threshold_Assert_Value_wrch {15} \ + CONFIG.INTERFACE_TYPE {AXI_STREAM} \ + CONFIG.Input_Depth_axis {1024} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.TUSER_WIDTH {0} \ + ] $tmp_dep_queue + } # Create and connect inp_mem partitions if {${inp_part} > 1} { @@ -487,6 +295,7 @@ CONFIG.NUM_PORTS {5} \ # Create instance: inp_mem, and set properties set inp_mem [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 inp_mem_${i} ] set_property -dict [ list \ + CONFIG.Assume_Synchronous_Clk {true} \ CONFIG.Byte_Size {8} \ CONFIG.Enable_32bit_Address {true} \ CONFIG.Enable_B {Use_ENB_Pin} \ @@ -501,7 +310,6 @@ CONFIG.NUM_PORTS {5} \ CONFIG.Write_Depth_A $inp_mem_depth \ CONFIG.Write_Width_A $inp_bus_width \ CONFIG.Write_Width_B $inp_bus_width \ - CONFIG.use_bram_block {BRAM_Controller} \ ] $inp_mem # Create interface connections connect_bd_intf_net -intf_net load_0_inp_mem_${i}_V_PORTA \ @@ -515,6 +323,7 @@ CONFIG.NUM_PORTS {5} \ # Create instance: inp_mem, and set properties set inp_mem [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 inp_mem ] set_property -dict [ list \ + CONFIG.Assume_Synchronous_Clk {true} \ CONFIG.Byte_Size {8} \ CONFIG.Enable_32bit_Address {true} \ CONFIG.Enable_B {Use_ENB_Pin} \ @@ -529,7 +338,6 @@ CONFIG.NUM_PORTS {5} \ CONFIG.Write_Depth_A $inp_mem_depth \ CONFIG.Write_Width_A $inp_bus_width \ CONFIG.Write_Width_B $inp_bus_width \ - CONFIG.use_bram_block {BRAM_Controller} \ ] $inp_mem # Create interface connections connect_bd_intf_net -intf_net load_0_inp_mem_V_PORTA \ @@ -605,6 +413,7 @@ CONFIG.NUM_PORTS {5} \ # Create instance: out_mem, and set properties set out_mem [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 out_mem_${i} ] set_property -dict [ list \ + CONFIG.Assume_Synchronous_Clk {true} \ CONFIG.Byte_Size {8} \ CONFIG.Enable_32bit_Address {true} \ CONFIG.Enable_B {Use_ENB_Pin} \ @@ -619,7 +428,6 @@ CONFIG.NUM_PORTS {5} \ CONFIG.Write_Depth_A $out_mem_depth \ CONFIG.Write_Width_A $out_bus_width \ CONFIG.Write_Width_B $out_bus_width \ - CONFIG.use_bram_block {BRAM_Controller} \ ] $out_mem # Create interface connections connect_bd_intf_net -intf_net compute_0_out_mem_${i}_V_PORTA \ @@ -633,6 +441,7 @@ CONFIG.NUM_PORTS {5} \ # Create instance: out_mem, and set properties set out_mem [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 out_mem ] set_property -dict [ list \ + CONFIG.Assume_Synchronous_Clk {true} \ CONFIG.Byte_Size {8} \ CONFIG.Enable_32bit_Address {true} \ CONFIG.Enable_B {Use_ENB_Pin} \ @@ -647,7 +456,6 @@ CONFIG.NUM_PORTS {5} \ CONFIG.Write_Depth_A $out_mem_depth \ CONFIG.Write_Width_A $out_bus_width \ CONFIG.Write_Width_B $out_bus_width \ - CONFIG.use_bram_block {BRAM_Controller} \ ] $out_mem # Create interface connections connect_bd_intf_net -intf_net compute_0_out_mem_V_PORTA \ @@ -658,261 +466,1648 @@ CONFIG.NUM_PORTS {5} \ [get_bd_intf_pins store_0/out_mem_V_PORTA] } + # Create instance: processing_system, and set properties + if { ${target} eq "pynq" } { + set processing_system7_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_1 ] + set_property -dict [ list \ + CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_EN_CLK0_PORT {1} \ + CONFIG.PCW_EN_CLK1_PORT {0} \ + CONFIG.PCW_EN_CLK2_PORT {0} \ + CONFIG.PCW_EN_CLK3_PORT {0} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ + CONFIG.PCW_IRQ_F2P_INTR {0} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \ + CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {1} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ + CONFIG.PCW_USE_HIGH_OCM {1} \ + CONFIG.PCW_USE_S_AXI_ACP {1} \ + CONFIG.PCW_USE_S_AXI_HP0 {0} \ + CONFIG.PCW_USE_S_AXI_HP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP2 {0} \ + CONFIG.PCW_USE_S_AXI_HP3 {0} \ + CONFIG.preset {ZC702} \ + ] $processing_system7_1 + } elseif { ${target} eq "ultra96" || ${target} eq "zcu102" } { + set ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 ps_e_0 ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {slow} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {slow} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {slow} \ + CONFIG.PSU_MIO_12_DIRECTION {inout} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {slow} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {slow} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {slow} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {slow} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {slow} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {slow} \ + CONFIG.PSU_MIO_18_DIRECTION {inout} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {slow} \ + CONFIG.PSU_MIO_19_DIRECTION {inout} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {slow} \ + CONFIG.PSU_MIO_1_DIRECTION {in} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {slow} \ + CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {slow} \ + CONFIG.PSU_MIO_21_DIRECTION {inout} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {slow} \ + CONFIG.PSU_MIO_22_DIRECTION {out} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {slow} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {slow} \ + CONFIG.PSU_MIO_24_DIRECTION {in} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {slow} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {slow} \ + CONFIG.PSU_MIO_26_DIRECTION {in} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {slow} \ + CONFIG.PSU_MIO_27_DIRECTION {out} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {slow} \ + CONFIG.PSU_MIO_28_DIRECTION {in} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {slow} \ + CONFIG.PSU_MIO_29_DIRECTION {out} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {slow} \ + CONFIG.PSU_MIO_2_DIRECTION {in} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {slow} \ + CONFIG.PSU_MIO_30_DIRECTION {in} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {slow} \ + CONFIG.PSU_MIO_31_DIRECTION {inout} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {slow} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {slow} \ + CONFIG.PSU_MIO_33_DIRECTION {out} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {slow} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {slow} \ + CONFIG.PSU_MIO_35_DIRECTION {inout} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {slow} \ + CONFIG.PSU_MIO_36_DIRECTION {inout} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {slow} \ + CONFIG.PSU_MIO_37_DIRECTION {inout} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {slow} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {slow} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {slow} \ + CONFIG.PSU_MIO_3_DIRECTION {out} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {slow} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {slow} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {slow} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {slow} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {slow} \ + CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_SLEW {slow} \ + CONFIG.PSU_MIO_45_DIRECTION {inout} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {slow} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {slow} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {slow} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {slow} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {slow} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {slow} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {slow} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {slow} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {slow} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {slow} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {slow} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {slow} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {slow} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {slow} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {slow} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {slow} \ + CONFIG.PSU_MIO_5_DIRECTION {inout} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {slow} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {slow} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {slow} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {slow} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {slow} \ + CONFIG.PSU_MIO_64_DIRECTION {in} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {slow} \ + CONFIG.PSU_MIO_65_DIRECTION {in} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {slow} \ + CONFIG.PSU_MIO_66_DIRECTION {inout} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {slow} \ + CONFIG.PSU_MIO_67_DIRECTION {in} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {slow} \ + CONFIG.PSU_MIO_68_DIRECTION {inout} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {slow} \ + CONFIG.PSU_MIO_69_DIRECTION {inout} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {slow} \ + CONFIG.PSU_MIO_6_DIRECTION {inout} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {slow} \ + CONFIG.PSU_MIO_70_DIRECTION {out} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {slow} \ + CONFIG.PSU_MIO_71_DIRECTION {inout} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {slow} \ + CONFIG.PSU_MIO_72_DIRECTION {inout} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {slow} \ + CONFIG.PSU_MIO_73_DIRECTION {inout} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {slow} \ + CONFIG.PSU_MIO_74_DIRECTION {inout} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {slow} \ + CONFIG.PSU_MIO_75_DIRECTION {inout} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {slow} \ + CONFIG.PSU_MIO_76_DIRECTION {inout} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {slow} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {slow} \ + CONFIG.PSU_MIO_7_DIRECTION {inout} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {slow} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {slow} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {slow} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ + CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {525.000000} \ + CONFIG.PSU__AFI0_COHERENCY {1} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000024} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000005} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000005} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {262.500005} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000012} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000006} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000012} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000010} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000011} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000010} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000001} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000010} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000005} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999985} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000005} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000010} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500004} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500004} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500004} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500004} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500004} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000002} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000005} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000005} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU_COHERENCY {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {1} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \ + CONFIG.PSU__DDRC__CL {NA} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__COMPONENTS {Components} \ + CONFIG.PSU__DDRC__CWL {NA} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {NA} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LP_ASR {NA} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SB_TARGET {NA} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \ + CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {40.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {42} \ + CONFIG.PSU__DDRC__T_RC {63} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {0} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \ + CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \ + CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \ + CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \ + CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \ + CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \ + CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \ + CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \ + CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \ + CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \ + CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \ + CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \ + CONFIG.PSU__DEVICE_TYPE {EG} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET0__PTP__ENABLE {0} \ + CONFIG.PSU__ENET0__TSU__ENABLE {0} \ + CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PTP__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PTP__ENABLE {0} \ + CONFIG.PSU__ENET2__TSU__ENABLE {0} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {1} \ + CONFIG.PSU__FPGA_PL3_ENABLE {1} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM0_COHERENCY {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM2_COHERENCY {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI__TRUSTZONE {