From 6947e1b979c1262cba27bca509038585dc33345e Mon Sep 17 00:00:00 2001 From: Thierry Moreau Date: Sun, 21 Jul 2019 17:36:48 -0700 Subject: [PATCH] streamlining address mapping --- vta/config/vta_config.py | 5 +++++ vta/hardware/xilinx/scripts/vivado.tcl | 9 +++++---- vta/python/vta/pkg_config.py | 22 +++++++++++++--------- vta/src/zynq/zynq_driver.cc | 24 ++++++++++++------------ vta/src/zynq/zynq_driver.h | 6 ++---- vta/tests/hardware/common/test_lib.cc | 16 ++++++++-------- 6 files changed, 45 insertions(+), 37 deletions(-) diff --git a/vta/config/vta_config.py b/vta/config/vta_config.py index a5bc61536f1ed..66b922d0d6f63 100644 --- a/vta/config/vta_config.py +++ b/vta/config/vta_config.py @@ -107,6 +107,8 @@ def main(): help="returns AXI system ARCACHE/AWCACHE hardcoded bit value") parser.add_argument("--get-axi-prot-bits", action="store_true", help="returns AXI system ARPROT/AWPROT hardcoded bit value") + parser.add_argument("--get-ip-reg-map-range", action="store_true", + help="returns ip register map address range") parser.add_argument("--get-fetch-base-addr", action="store_true", help="returns fetch module base address") parser.add_argument("--get-load-base-addr", action="store_true", @@ -262,6 +264,9 @@ def main(): if args.get_axi_prot_bits: print(pkg.axi_prot_bits) + if args.get_ip_reg_map_range: + print(pkg.ip_reg_map_range) + if args.get_fetch_base_addr: print(pkg.fetch_base_addr) diff --git a/vta/hardware/xilinx/scripts/vivado.tcl b/vta/hardware/xilinx/scripts/vivado.tcl index 6245337bceac1..3be575749c27a 100644 --- a/vta/hardware/xilinx/scripts/vivado.tcl +++ b/vta/hardware/xilinx/scripts/vivado.tcl @@ -56,6 +56,7 @@ set axi_cache [exec python $vta_config --get-axi-cache-bits] set axi_prot [exec python $vta_config --get-axi-prot-bits] # Address map +set ip_reg_map_range [exec python $vta_config --get-ip-reg-map-range] set fetch_base_addr [exec python $vta_config --get-fetch-base-addr] set load_base_addr [exec python $vta_config --get-load-base-addr] set compute_base_addr [exec python $vta_config --get-compute-base-addr] @@ -387,10 +388,10 @@ connect_bd_net -net processing_system_clk \ $saxi_clk # Create address segments -create_bd_addr_seg -range 0x00001000 -offset $fetch_base_addr [get_bd_addr_spaces processing_system/Data] [get_bd_addr_segs fetch_0/s_axi_CONTROL_BUS/Reg] SEG_fetch_0_Reg -create_bd_addr_seg -range 0x00001000 -offset $load_base_addr [get_bd_addr_spaces processing_system/Data] [get_bd_addr_segs load_0/s_axi_CONTROL_BUS/Reg] SEG_load_0_Reg -create_bd_addr_seg -range 0x00001000 -offset $compute_base_addr [get_bd_addr_spaces processing_system/Data] [get_bd_addr_segs compute_0/s_axi_CONTROL_BUS/Reg] SEG_compute_0_Reg -create_bd_addr_seg -range 0x00001000 -offset $store_base_addr [get_bd_addr_spaces processing_system/Data] [get_bd_addr_segs store_0/s_axi_CONTROL_BUS/Reg] SEG_store_0_Reg +create_bd_addr_seg -range $ip_reg_map_range -offset $fetch_base_addr [get_bd_addr_spaces processing_system/Data] [get_bd_addr_segs fetch_0/s_axi_CONTROL_BUS/Reg] SEG_fetch_0_Reg +create_bd_addr_seg -range $ip_reg_map_range -offset $load_base_addr [get_bd_addr_spaces processing_system/Data] [get_bd_addr_segs load_0/s_axi_CONTROL_BUS/Reg] SEG_load_0_Reg +create_bd_addr_seg -range $ip_reg_map_range -offset $compute_base_addr [get_bd_addr_spaces processing_system/Data] [get_bd_addr_segs compute_0/s_axi_CONTROL_BUS/Reg] SEG_compute_0_Reg +create_bd_addr_seg -range $ip_reg_map_range -offset $store_base_addr [get_bd_addr_spaces processing_system/Data] [get_bd_addr_segs store_0/s_axi_CONTROL_BUS/Reg] SEG_store_0_Reg if { $device_family eq "zynq-7000" } { create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] [get_bd_addr_segs processing_system/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system_ACP_DDR_LOWOCM create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces compute_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system_ACP_DDR_LOWOCM diff --git a/vta/python/vta/pkg_config.py b/vta/python/vta/pkg_config.py index 98e261f4fc89e..5b120f994f3f4 100644 --- a/vta/python/vta/pkg_config.py +++ b/vta/python/vta/pkg_config.py @@ -118,10 +118,11 @@ def __init__(self, cfg, proj_root): self.axi_cache_bits = '1111' self.axi_prot_bits = '010' # IP register address map - self.fetch_base_addr = "0xA0001000" - self.load_base_addr = "0xA0002000" - self.compute_base_addr = "0xA0003000" - self.store_base_addr = "0xA0004000" + self.ip_reg_map_range = "0x1000" + self.fetch_base_addr = "0xA0000000" + self.load_base_addr = "0xA0001000" + self.compute_base_addr = "0xA0002000" + self.store_base_addr = "0xA0003000" else: # By default, we use the pynq parameters self.fpga_device = "xc7z020clg484-1" @@ -130,12 +131,13 @@ def __init__(self, cfg, proj_root): self.fpga_per = 7 self.fpga_log_axi_bus_width = 6 self.axi_cache_bits = '1111' - self.axi_prot_bits = '000' + self.axi_prot_bits = '010' # IP register address map - self.fetch_base_addr = "0x43C00000" - self.load_base_addr = "0x43C10000" - self.compute_base_addr = "0x43C20000" - self.store_base_addr = "0x43C30000" + self.ip_reg_map_range = "0x1000" + self.fetch_base_addr = "0x43C00000" + self.load_base_addr = "0x43C01000" + self.compute_base_addr = "0x43C02000" + self.store_base_addr = "0x43C03000" # Derive SRAM parameters # The goal here is to determine how many memory banks are needed, @@ -191,6 +193,8 @@ def __init__(self, cfg, proj_root): self.macro_defs.append("-DVTA_%s=%s" % (key, str(cfg[key]))) self.cfg_dict[key] = cfg[key] self.macro_defs.append("-DVTA_LOG_BUS_WIDTH=%s" % (self.fpga_log_axi_bus_width)) + # Macros used by the VTA driver + self.macro_defs.append("-DVTA_IP_REG_MAP_RANGE=%s" % (self.ip_reg_map_range)) self.macro_defs.append("-DVTA_FETCH_ADDR=%s" % (self.fetch_base_addr)) self.macro_defs.append("-DVTA_LOAD_ADDR=%s" % (self.load_base_addr)) self.macro_defs.append("-DVTA_COMPUTE_ADDR=%s" % (self.compute_base_addr)) diff --git a/vta/src/zynq/zynq_driver.cc b/vta/src/zynq/zynq_driver.cc index c1f0c3ccdd110..d76f77ef6fc77 100644 --- a/vta/src/zynq/zynq_driver.cc +++ b/vta/src/zynq/zynq_driver.cc @@ -62,7 +62,7 @@ void VTAInvalidateCache(vta_phy_addr_t buf, int size) { xlnkInvalidateCache(reinterpret_cast(buf), size); } -void *VTAMapRegister(uint32_t addr, size_t length) { +void *VTAMapRegister(uint32_t addr) { // Align the base address with the pages uint32_t virt_base = addr & ~(getpagesize() - 1); // Calculate base address offset w.r.t the base address @@ -70,16 +70,16 @@ void *VTAMapRegister(uint32_t addr, size_t length) { // Open file and mmap uint32_t mmap_file = open("/dev/mem", O_RDWR|O_SYNC); return mmap(NULL, - (length+virt_offset), + (VTA_IP_REG_MAP_RANGE + virt_offset), PROT_READ|PROT_WRITE, MAP_SHARED, mmap_file, virt_base); } -void VTAUnmapRegister(void *vta, size_t length) { +void VTAUnmapRegister(void *vta) { // Unmap memory - int status = munmap(vta, length); + int status = munmap(vta, VTA_IP_REG_MAP_RANGE); assert(status == 0); } @@ -95,18 +95,18 @@ class VTADevice { public: VTADevice() { // VTA stage handles - vta_fetch_handle_ = VTAMapRegister(VTA_FETCH_ADDR, VTA_RANGE); - vta_load_handle_ = VTAMapRegister(VTA_LOAD_ADDR, VTA_RANGE); - vta_compute_handle_ = VTAMapRegister(VTA_COMPUTE_ADDR, VTA_RANGE); - vta_store_handle_ = VTAMapRegister(VTA_STORE_ADDR, VTA_RANGE); + vta_fetch_handle_ = VTAMapRegister(VTA_FETCH_ADDR); + vta_load_handle_ = VTAMapRegister(VTA_LOAD_ADDR); + vta_compute_handle_ = VTAMapRegister(VTA_COMPUTE_ADDR); + vta_store_handle_ = VTAMapRegister(VTA_STORE_ADDR); } ~VTADevice() { // Close VTA stage handle - VTAUnmapRegister(vta_fetch_handle_, VTA_RANGE); - VTAUnmapRegister(vta_load_handle_, VTA_RANGE); - VTAUnmapRegister(vta_compute_handle_, VTA_RANGE); - VTAUnmapRegister(vta_store_handle_, VTA_RANGE); + VTAUnmapRegister(vta_fetch_handle_); + VTAUnmapRegister(vta_load_handle_); + VTAUnmapRegister(vta_compute_handle_); + VTAUnmapRegister(vta_store_handle_); } int Run(vta_phy_addr_t insn_phy_addr, diff --git a/vta/src/zynq/zynq_driver.h b/vta/src/zynq/zynq_driver.h index 48712f08d0268..a2c774026c7c1 100644 --- a/vta/src/zynq/zynq_driver.h +++ b/vta/src/zynq/zynq_driver.h @@ -48,13 +48,11 @@ uint32_t cma_get_phy_addr(void* buf); void xlnkFlushCache(void* buf, int size); void xlnkInvalidateCache(void* buf, int size); -void *VTAMapRegister(uint32_t addr, size_t length); -void VTAUnmapRegister(void *vta, size_t length); +void *VTAMapRegister(uint32_t addr); +void VTAUnmapRegister(void *vta); void VTAWriteMappedReg(void* base_addr, uint32_t offset, uint32_t val); uint32_t VTAReadMappedReg(void* base_addr, uint32_t offset); -/*! \brief VTA configuration register address range */ -#define VTA_RANGE 0x100 /*! \brief VTA configuration register start value */ #define VTA_START 0x1 /*! \brief VTA configuration register auto-restart value */ diff --git a/vta/tests/hardware/common/test_lib.cc b/vta/tests/hardware/common/test_lib.cc index 943bb0172894b..26d87efb5e0d1 100644 --- a/vta/tests/hardware/common/test_lib.cc +++ b/vta/tests/hardware/common/test_lib.cc @@ -52,10 +52,10 @@ uint64_t vta( snprintf(bitstream, sizeof(bitstream), "%s", "vta.bit"); // Get VTA handles - void* vta_fetch_handle = VTAMapRegister(VTA_FETCH_ADDR, VTA_RANGE); - void* vta_load_handle = VTAMapRegister(VTA_LOAD_ADDR, VTA_RANGE); - void* vta_compute_handle = VTAMapRegister(VTA_COMPUTE_ADDR, VTA_RANGE); - void* vta_store_handle = VTAMapRegister(VTA_STORE_ADDR, VTA_RANGE); + void* vta_fetch_handle = VTAMapRegister(VTA_FETCH_ADDR); + void* vta_load_handle = VTAMapRegister(VTA_LOAD_ADDR); + void* vta_compute_handle = VTAMapRegister(VTA_COMPUTE_ADDR); + void* vta_store_handle = VTAMapRegister(VTA_STORE_ADDR); // Physical address pointers uint32_t insn_phy = insns ? cma_get_phy_addr(insns) : 0; @@ -110,10 +110,10 @@ uint64_t vta( t_fpga = 1000000000ULL * (stop.tv_sec - start.tv_sec) + (stop.tv_nsec - start.tv_nsec); // Unmap VTA register - VTAUnmapRegister(vta_fetch_handle, VTA_RANGE); - VTAUnmapRegister(vta_load_handle, VTA_RANGE); - VTAUnmapRegister(vta_compute_handle, VTA_RANGE); - VTAUnmapRegister(vta_store_handle, VTA_RANGE); + VTAUnmapRegister(vta_fetch_handle); + VTAUnmapRegister(vta_load_handle); + VTAUnmapRegister(vta_compute_handle); + VTAUnmapRegister(vta_store_handle); return t_fpga; }