From 3e5f99db0b6d7ce32dab71ead3e9cbffd33f8f6c Mon Sep 17 00:00:00 2001 From: Chris Sidebottom Date: Fri, 5 Aug 2022 15:55:36 +0000 Subject: [PATCH] [Target] Replace IsaAnalyzer with Target Features This is clean up to use the new `target.features` instead of `IsaAnalyzer`. --- python/MANIFEST.in | 0 python/tvm/relay/op/strategy/arm_cpu.py | 17 ++++------- python/tvm/target/arm_isa.py | 39 ------------------------- tests/micro/zephyr/test_zephyr.py | 4 +-- 4 files changed, 6 insertions(+), 54 deletions(-) create mode 100644 python/MANIFEST.in delete mode 100644 python/tvm/target/arm_isa.py diff --git a/python/MANIFEST.in b/python/MANIFEST.in new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/python/tvm/relay/op/strategy/arm_cpu.py b/python/tvm/relay/op/strategy/arm_cpu.py index 54e1c871f5049..ba28b6c7c31c4 100644 --- a/python/tvm/relay/op/strategy/arm_cpu.py +++ b/python/tvm/relay/op/strategy/arm_cpu.py @@ -24,7 +24,6 @@ from ....auto_scheduler import is_auto_scheduler_enabled from ....meta_schedule import is_meta_schedule_enabled -from ....target import arm_isa from ....topi.generic import conv2d as conv2d_generic from .. import op as _op from .generic import * @@ -57,15 +56,14 @@ def schedule_concatenate_arm_cpu(_, outs, target): def schedule_pool_arm_cpu(attrs, outs, target): """schedule pooling ops arm cpu""" layout = attrs.layout - isa = arm_isa.IsaAnalyzer(target) avg_pool = isinstance(attrs, relay.op.op_attrs.AvgPool2DAttrs) with target: if ( avg_pool - and isa.has_dsp_support + and target.features.has_dsp and layout in ("NCW", "NCHW") or not avg_pool - and isa.has_dsp_support + and target.features.has_dsp and layout in ("NWC", "NHWC") ): return topi.arm_cpu.schedule_pool(outs, layout) @@ -87,8 +85,6 @@ def conv2d_strategy_arm_cpu(attrs, inputs, out_type, target): if dilation_h < 1 or dilation_w < 1: raise ValueError("dilation should be positive value") - isa = arm_isa.IsaAnalyzer(target) - if groups == 1: if layout == "NCHW": if kernel_layout == "OIHW": @@ -163,7 +159,7 @@ def conv2d_strategy_arm_cpu(attrs, inputs, out_type, target): name="conv2d_hwcn.generic", ) elif layout == "NHWC": - if isa.has_dsp_support and kernel_layout == "HWOI": + if target.features.has_dsp and kernel_layout == "HWOI": strategy.add_implementation( wrap_compute_conv2d(topi.arm_cpu.conv2d_nhwc_dsp), wrap_topi_schedule(topi.arm_cpu.schedule_conv2d_nhwc_dsp), @@ -473,10 +469,9 @@ def schedule_bitserial_dense_arm_cpu(attrs, inputs, out_type, target): def schedule_dense_arm_cpu(attrs, inputs, out_type, target): """dense arm cpu strategy""" strategy = _op.OpStrategy() - isa = arm_isa.IsaAnalyzer(target) data, _ = inputs - if isa.has_dsp_support and data.dtype in ["int8", "int16"]: + if target.features.has_dsp and data.dtype in ["int8", "int16"]: strategy.add_implementation( wrap_compute_dense(topi.arm_cpu.dense_dsp), wrap_topi_schedule(topi.arm_cpu.schedule_dense_dsp), @@ -506,10 +501,8 @@ def conv1d_strategy_arm_cpu(attrs, inputs, out_type, target): if dilation[0] < 1: raise ValueError("dilation should be a positive value") - isa = arm_isa.IsaAnalyzer(target) - if kernel_layout == "WOI": - if layout == "NWC" and isa.has_dsp_support: + if layout == "NWC" and target.features.has_dsp: strategy.add_implementation( wrap_compute_conv1d(topi.arm_cpu.conv1d_nwc_dsp), wrap_topi_schedule(topi.arm_cpu.schedule_conv1d_nwc_dsp), diff --git a/python/tvm/target/arm_isa.py b/python/tvm/target/arm_isa.py deleted file mode 100644 index a5ac9b1563a5c..0000000000000 --- a/python/tvm/target/arm_isa.py +++ /dev/null @@ -1,39 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -"""Defines functions to analyze available opcodes in the ARM ISA.""" - -import tvm.target - - -ARM_MPROFILE_DSP_SUPPORT_LIST = [ - "cortex-m7", - "cortex-m4", - "cortex-m33", - "cortex-m35p", - "cortex-m55", -] - - -class IsaAnalyzer(object): - """Checks ISA support for given target""" - - def __init__(self, target): - self.target = tvm.target.Target(target) - - @property - def has_dsp_support(self): - return self.target.mcpu is not None and self.target.mcpu in ARM_MPROFILE_DSP_SUPPORT_LIST diff --git a/tests/micro/zephyr/test_zephyr.py b/tests/micro/zephyr/test_zephyr.py index 1f53e4baa8c3f..8916510ce9465 100644 --- a/tests/micro/zephyr/test_zephyr.py +++ b/tests/micro/zephyr/test_zephyr.py @@ -32,7 +32,6 @@ from tvm.relay.testing import byoc from tvm.contrib import utils from tvm.micro.testing.utils import check_tune_log -from tvm.target import arm_isa import test_utils @@ -525,8 +524,7 @@ def test_schedule_build_with_cmsis_dependency(workspace_dir, board, west_cmd, mi build_config = {"debug": microtvm_debug} target = tvm.target.target.micro(model, options=["-keys=arm_cpu,cpu"]) - isa = arm_isa.IsaAnalyzer(target) - if not isa.has_dsp_support: + if not target.features.has_dsp: pytest.skip(f"ISA does not support DSP. target: {target}") # Create a Relay conv2d