[BACKPORT-0.6][VTA] End-to-end Inference with Chisel VTA (#5896)

* [BACKPORT-0.6][VTA][Chisel] End-to-end Inference with Chisel VTA (#4574) * [BACKPORT-0.6][VTA] Added declare of aluBits for TensorAlu (#4624) Co-authored-by: Kevin Yuan <[email protected]> * retrigger ci * retrigger ci Co-authored-by: Kevin Yuan <[email protected]>
apache · Jun 25, 2020 · 26807ba · 26807ba
1 parent c03d97c
commit 26807ba
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
@@ -108,6 +108,7 @@ class AluVector(implicit p: Parameters) extends Module {
   * acc-scratchpad.
   */
 class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
+  val aluBits = p(CoreKey).accBits
   val io = IO(new Bundle {
     val start = Input(Bool())
     val done = Output(Bool())
@@ -230,7 +231,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
   tensorImm.data.valid := state === sReadTensorB
   tensorImm.data.bits.foreach { b =>
     b.foreach { c =>
-      c := dec.alu_imm
+      c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1),
+               Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm), dec.alu_imm)
     }
   }