From 951914da7eb1964b59a1058fadc20691259a879a Mon Sep 17 00:00:00 2001 From: Lucas Date: Wed, 27 Nov 2024 17:55:11 -0300 Subject: [PATCH] Implement store imm instructions --- llvm/lib/Target/SBF/BTFDebug.cpp | 10 +- llvm/lib/Target/SBF/SBFInstrInfo.td | 77 +++++++-- .../lib/Target/SBF/SBFMISimplifyPatchable.cpp | 45 +++-- llvm/lib/Target/SBF/SBFSubtarget.cpp | 1 + llvm/lib/Target/SBF/SBFSubtarget.h | 4 + llvm/lib/Target/SBF/SBFTargetFeatures.td | 3 + .../CodeGen/SBF/CORE/field-reloc-st-imm.ll | 154 ++++++++++++++++++ llvm/test/CodeGen/SBF/store-imm.ll | 75 +++++++++ llvm/test/MC/Disassembler/SBF/sbf-ldst.txt | 9 + llvm/test/MC/SBF/sbf-ldst.s | 14 ++ 10 files changed, 364 insertions(+), 28 deletions(-) create mode 100644 llvm/test/CodeGen/SBF/CORE/field-reloc-st-imm.ll create mode 100644 llvm/test/CodeGen/SBF/store-imm.ll diff --git a/llvm/lib/Target/SBF/BTFDebug.cpp b/llvm/lib/Target/SBF/BTFDebug.cpp index c6726d2f8a030f..474307284de661 100644 --- a/llvm/lib/Target/SBF/BTFDebug.cpp +++ b/llvm/lib/Target/SBF/BTFDebug.cpp @@ -1345,8 +1345,9 @@ void BTFDebug::beginInstruction(const MachineInstr *MI) { // If the insn is "r2 = LD_imm64 @", // The LD_imm64 result will be replaced with a btf type id. processGlobalValue(MI->getOperand(1)); - } else if (MI->getOpcode() == SBF::CORE_MEM || - MI->getOpcode() == SBF::CORE_ALU32_MEM || + } else if (MI->getOpcode() == SBF::CORE_LD64 || + MI->getOpcode() == SBF::CORE_LD32 || + MI->getOpcode() == SBF::CORE_ST || MI->getOpcode() == SBF::CORE_SHIFT) { // relocation insn is a load, store or shift insn. processGlobalValue(MI->getOperand(3)); @@ -1524,8 +1525,9 @@ bool BTFDebug::InstLower(const MachineInstr *MI, MCInst &OutMI) { return true; } } - } else if (MI->getOpcode() == SBF::CORE_MEM || - MI->getOpcode() == SBF::CORE_ALU32_MEM || + } else if (MI->getOpcode() == SBF::CORE_LD64 || + MI->getOpcode() == SBF::CORE_LD32 || + MI->getOpcode() == SBF::CORE_ST || MI->getOpcode() == SBF::CORE_SHIFT) { const MachineOperand &MO = MI->getOperand(3); if (MO.isGlobal()) { diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td index e61f7ff70515fe..bfce5db3197423 100644 --- a/llvm/lib/Target/SBF/SBFInstrInfo.td +++ b/llvm/lib/Target/SBF/SBFInstrInfo.td @@ -64,6 +64,7 @@ def SBFCallxSrc : Predicate<"Subtarget->getCallXRegSrc()">, AssemblerPredicate<( def SBFNoCallxSrc : Predicate<"!Subtarget->getCallXRegSrc()">; def SBFPqrInstr : Predicate<"Subtarget->getHasPqrClass()">; def SBFNoPqrInstr : Predicate<"!Subtarget->getHasPqrClass()">; +def SBFHasStoreImm : Predicate<"Subtarget->getHasStoreImm()">; def brtarget : Operand { let PrintMethod = "printBrTargetOperand"; @@ -74,10 +75,18 @@ def u64imm : Operand { let PrintMethod = "printImm64Operand"; } +def gpr_or_imm : Operand; + def i64immSExt32 : PatLeaf<(i64 imm), [{return isInt<32>(N->getSExtValue()); }]>; def i32immSExt32 : PatLeaf<(i32 imm), [{return isInt<32>(N->getSExtValue()); }]>; +def i64immZExt32 : PatLeaf<(i64 imm), + [{return isUInt<32>(N->getZExtValue()); }]>; + +def imm_to_i64 : SDNodeXFormgetTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i64); +}]>; // Fetch the upper 32-bits of a 64-bit integer. def Upper32 : SDNodeXForm Pattern> } class STOREi64 - : STORE; + : STORE; let Predicates = [SBFNoALU32] in { def STW : STOREi64; @@ -478,6 +487,49 @@ let Predicates = [SBFNoALU32] in { } def STD : STOREi64; +class STORE_imm + : TYPE_LD_ST { + bits<20> addr; + bits<32> imm; + let Inst{51-48} = addr{19-16}; // base reg + let Inst{47-32} = addr{15-0}; // offset + let Inst{31-0} = imm; + let SBFClass = SBF_ST; +} + +// Opcode (SBF_ST | SBF_MEM | SBF_DW) implies sign extension for +// value stored to memory: +// - it is fine to generate such write when immediate is -1 +// - it is incorrect to generate such write when immediate is +// +0xffff_ffff. +// +// In the latter case two instructions would be generated instead of +// one BPF_ST: +// lddw rA, 0xffffffff +// stx [rb], rA +// +// For SBF_{B,H,W} the size of value stored matches size of the immediate. +let Predicates = [SBFHasStoreImm] in { + def STD_imm : STORE_imm; + def STW_imm : STORE_imm; + def STH_imm : STORE_imm; + def STB_imm : STORE_imm; +} + +let Predicates = [SBFHasALU32, SBFHasStoreImm] in { + def : Pat<(store (i32 imm:$src), ADDRri:$dst), + (STW_imm (imm_to_i64 $src), ADDRri:$dst)>; + def : Pat<(truncstorei16 (i32 imm:$src), ADDRri:$dst), + (STH_imm (imm_to_i64 imm:$src), ADDRri:$dst)>; + def : Pat<(truncstorei8 (i32 imm:$src), ADDRri:$dst), + (STB_imm (imm_to_i64 imm:$src), ADDRri:$dst)>; +} + // LOAD instructions class LOAD Pattern> : TYPE_LD_ST : LOAD; let isCodeGenOnly = 1 in { - def CORE_MEM : TYPE_LD_ST + : TYPE_LD_ST; - def CORE_ALU32_MEM : TYPE_LD_ST; + + def CORE_LD64 : CORE_LD; + def CORE_LD32 : CORE_LD; + + def CORE_ST : TYPE_LD_ST; let Constraints = "$dst = $src" in { def CORE_SHIFT : MATH_RR Pattern> } class STOREi32 - : STORE32; + : STORE32; let Predicates = [SBFHasALU32], DecoderNamespace = "SBFALU32" in { def STW32 : STOREi32; diff --git a/llvm/lib/Target/SBF/SBFMISimplifyPatchable.cpp b/llvm/lib/Target/SBF/SBFMISimplifyPatchable.cpp index 1a5bef5e149d68..358b7c2e4e013c 100644 --- a/llvm/lib/Target/SBF/SBFMISimplifyPatchable.cpp +++ b/llvm/lib/Target/SBF/SBFMISimplifyPatchable.cpp @@ -92,10 +92,31 @@ void SBFMISimplifyPatchable::initialize(MachineFunction &MFParm) { LLVM_DEBUG(dbgs() << "*** SBF simplify patchable insts pass ***\n\n"); } +static bool isST(unsigned Opcode) { + return Opcode == SBF::STB_imm || Opcode == SBF::STH_imm || + Opcode == SBF::STW_imm || Opcode == SBF::STD_imm; +} + +static bool isSTX32(unsigned Opcode) { + return Opcode == SBF::STB32 || Opcode == SBF::STH32 || Opcode == SBF::STW32; +} + +static bool isSTX64(unsigned Opcode) { + return Opcode == SBF::STB || Opcode == SBF::STH || Opcode == SBF::STW || + Opcode == SBF::STD; +} + +static bool isLDX32(unsigned Opcode) { + return Opcode == SBF::LDB32 || Opcode == SBF::LDH32 || Opcode == SBF::LDW32; +} + +static bool isLDX64(unsigned Opcode) { + return Opcode == SBF::LDB || Opcode == SBF::LDH || Opcode == SBF::LDW || + Opcode == SBF::LDD; +} + bool SBFMISimplifyPatchable::isLoadInst(unsigned Opcode) { - return Opcode == SBF::LDD || Opcode == SBF::LDW || Opcode == SBF::LDH || - Opcode == SBF::LDB || Opcode == SBF::LDW32 || Opcode == SBF::LDH32 || - Opcode == SBF::LDB32; + return isLDX32(Opcode) || isLDX64(Opcode); } void SBFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, @@ -116,14 +137,12 @@ void SBFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, MachineInstr *DefInst = MO.getParent(); unsigned Opcode = DefInst->getOpcode(); unsigned COREOp; - if (Opcode == SBF::LDB || Opcode == SBF::LDH || Opcode == SBF::LDW || - Opcode == SBF::LDD || Opcode == SBF::STB || Opcode == SBF::STH || - Opcode == SBF::STW || Opcode == SBF::STD) - COREOp = SBF::CORE_MEM; - else if (Opcode == SBF::LDB32 || Opcode == SBF::LDH32 || - Opcode == SBF::LDW32 || Opcode == SBF::STB32 || - Opcode == SBF::STH32 || Opcode == SBF::STW32) - COREOp = SBF::CORE_ALU32_MEM; + if (isLDX64(Opcode)) + COREOp = SBF::CORE_LD64; + else if (isLDX32(Opcode)) + COREOp = SBF::CORE_LD32; + else if (isSTX64(Opcode) || isSTX32(Opcode) || isST(Opcode)) + COREOp = SBF::CORE_ST; else continue; @@ -135,9 +154,7 @@ void SBFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, // Reject the form: // %1 = ADD_rr %2, %3 // *(type *)(%2 + 0) = %1 - if (Opcode == SBF::STB || Opcode == SBF::STH || Opcode == SBF::STW || - Opcode == SBF::STD || Opcode == SBF::STB32 || Opcode == SBF::STH32 || - Opcode == SBF::STW32) { + if (isSTX64(Opcode) || isSTX32(Opcode)) { const MachineOperand &Opnd = DefInst->getOperand(0); if (Opnd.isReg() && Opnd.getReg() == MO.getReg()) continue; diff --git a/llvm/lib/Target/SBF/SBFSubtarget.cpp b/llvm/lib/Target/SBF/SBFSubtarget.cpp index 5b915a382e2bd8..e3098cae86bf6e 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.cpp +++ b/llvm/lib/Target/SBF/SBFSubtarget.cpp @@ -47,6 +47,7 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) { CallxRegSrc = false; HasPqrClass = false; NewCallConvention = false; + HasStoreImm = false; } void SBFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { diff --git a/llvm/lib/Target/SBF/SBFSubtarget.h b/llvm/lib/Target/SBF/SBFSubtarget.h index 2421403962700c..c32a76d2e4368a 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.h +++ b/llvm/lib/Target/SBF/SBFSubtarget.h @@ -77,6 +77,9 @@ class SBFSubtarget : public SBFGenSubtargetInfo { // Whether to use the new call convention in SBFv2 bool NewCallConvention; + // Whether we have store imm instructions + bool HasStoreImm; + public: // This constructor initializes the data members to match that // of the specified triple. @@ -101,6 +104,7 @@ class SBFSubtarget : public SBFGenSubtargetInfo { bool getEnableNewCallConvention() const { return HasDynamicFrames && NewCallConvention; } + bool getHasStoreImm() const { return HasStoreImm; } const SBFInstrInfo *getInstrInfo() const override { return &InstrInfo; } const SBFFrameLowering *getFrameLowering() const override { return &FrameLowering; diff --git a/llvm/lib/Target/SBF/SBFTargetFeatures.td b/llvm/lib/Target/SBF/SBFTargetFeatures.td index 91c8d2eb616c4e..753c8d04988dc1 100644 --- a/llvm/lib/Target/SBF/SBFTargetFeatures.td +++ b/llvm/lib/Target/SBF/SBFTargetFeatures.td @@ -43,6 +43,9 @@ def FeaturePqrInstr : SubtargetFeature<"pqr-instr", "HasPqrClass", "true", def FeatureCallConv : SubtargetFeature<"new-call-conv", "NewCallConvention", "true", "Enable new call convetion for SBFv2">; +def FeatureStoreImm : SubtargetFeature<"store-imm", "HasStoreImm", "true", + "Enable store imm instructions">; + class Proc Features> : Processor; diff --git a/llvm/test/CodeGen/SBF/CORE/field-reloc-st-imm.ll b/llvm/test/CodeGen/SBF/CORE/field-reloc-st-imm.ll new file mode 100644 index 00000000000000..ab5a6a68f2b229 --- /dev/null +++ b/llvm/test/CodeGen/SBF/CORE/field-reloc-st-imm.ll @@ -0,0 +1,154 @@ +; RUN: llc -march=sbf -mattr=+store-imm -sbf-enable-btf-emission < %s | FileCheck %s + +; Make sure that CO-RE relocations had been generated correctly for +; BPF_ST (store immediate) instructions and that +; BPFMISimplifyPatchable optimizations had been applied. +; +; Generated from the following source code: +; +; #define __pai __attribute__((preserve_access_index)) +; +; struct foo { +; unsigned char b; +; unsigned short h; +; unsigned int w; +; unsigned long d; +; } __pai; +; +; void bar(volatile struct foo *p) { +; p->b = 1; +; p->h = 2; +; p->w = 3; +; p->d = 4; +; } +; +; Using the following command: +; +; clang -g -O2 -S -emit-llvm --target=sbf test.c + +@"llvm.foo:0:0$0:0" = external global i64, !llvm.preserve.access.index !0 #0 +@"llvm.foo:0:2$0:1" = external global i64, !llvm.preserve.access.index !0 #0 +@"llvm.foo:0:4$0:2" = external global i64, !llvm.preserve.access.index !0 #0 +@"llvm.foo:0:8$0:3" = external global i64, !llvm.preserve.access.index !0 #0 + +; Function Attrs: nofree nounwind +define dso_local void @bar(ptr noundef %p) local_unnamed_addr #1 !dbg !18 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !24, metadata !DIExpression()), !dbg !25 + %0 = load i64, ptr @"llvm.foo:0:0$0:0", align 8 + %1 = getelementptr i8, ptr %p, i64 %0 + %2 = tail call ptr @llvm.bpf.passthrough.p0.p0(i32 0, ptr %1) + store volatile i8 1, ptr %2, align 8, !dbg !26, !tbaa !27 + %3 = load i64, ptr @"llvm.foo:0:2$0:1", align 8 + %4 = getelementptr i8, ptr %p, i64 %3 + %5 = tail call ptr @llvm.bpf.passthrough.p0.p0(i32 1, ptr %4) + store volatile i16 2, ptr %5, align 2, !dbg !34, !tbaa !35 + %6 = load i64, ptr @"llvm.foo:0:4$0:2", align 8 + %7 = getelementptr i8, ptr %p, i64 %6 + %8 = tail call ptr @llvm.bpf.passthrough.p0.p0(i32 2, ptr %7) + store volatile i32 3, ptr %8, align 4, !dbg !36, !tbaa !37 + %9 = load i64, ptr @"llvm.foo:0:8$0:3", align 8 + %10 = getelementptr i8, ptr %p, i64 %9 + %11 = tail call ptr @llvm.bpf.passthrough.p0.p0(i32 3, ptr %10) + store volatile i64 4, ptr %11, align 8, !dbg !38, !tbaa !39 + ret void, !dbg !40 +} + +; CHECK: [[L0:.Ltmp.*]]: +; CHECK: stb [r1 + 0], 1 +; CHECK: [[L2:.Ltmp.*]]: +; CHECK: sth [r1 + 2], 2 +; CHECK: [[L4:.Ltmp.*]]: +; CHECK: stw [r1 + 4], 3 +; CHECK: [[L6:.Ltmp.*]]: +; CHECK: stdw [r1 + 8], 4 + +; CHECK: .section .BTF +; ... +; CHECK: .long [[FOO:.*]] # BTF_KIND_STRUCT(id = [[FOO_ID:.*]]) +; ... +; CHECK: .ascii "foo" # string offset=[[FOO]] +; CHECK: .ascii ".text" # string offset=[[TEXT:.*]] +; CHECK: .ascii "0:0" # string offset=[[S1:.*]] +; CHECK: .ascii "0:1" # string offset=[[S2:.*]] +; CHECK: .ascii "0:2" # string offset=[[S3:.*]] +; CHECK: .ascii "0:3" # string offset=[[S4:.*]] + +; CHECK: .section .BTF.ext +; ... +; CHECK: .long [[#]] # FieldReloc +; CHECK-NEXT: .long [[TEXT]] # Field reloc section string offset=[[TEXT]] +; CHECK-NEXT: .long [[#]] +; CHECK-NEXT: .long [[L0]] +; CHECK-NEXT: .long [[FOO_ID]] +; CHECK-NEXT: .long [[S1]] +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .long [[L2]] +; CHECK-NEXT: .long [[FOO_ID]] +; CHECK-NEXT: .long [[S2]] +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .long [[L4]] +; CHECK-NEXT: .long [[FOO_ID]] +; CHECK-NEXT: .long [[S3]] +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .long [[L6]] +; CHECK-NEXT: .long [[FOO_ID]] +; CHECK-NEXT: .long [[S4]] +; CHECK-NEXT: .long 0 + +; Function Attrs: nofree nosync nounwind memory(none) +declare ptr @llvm.bpf.passthrough.p0.p0(i32, ptr) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #3 + +attributes #0 = { "btf_ama" } +attributes #1 = { nofree nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="v4" } +attributes #2 = { nofree nosync nounwind memory(none) } +attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.dbg.cu = !{!11} +!llvm.module.flags = !{!12, !13, !14, !15, !16} +!llvm.ident = !{!17} + +!0 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 3, size: 128, elements: !2) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir", checksumkind: CSK_MD5, checksum: "e5d03b4d39dfffadc6c607e956c37996") +!2 = !{!3, !5, !7, !9} +!3 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !0, file: !1, line: 4, baseType: !4, size: 8) +!4 = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char) +!5 = !DIDerivedType(tag: DW_TAG_member, name: "h", scope: !0, file: !1, line: 5, baseType: !6, size: 16, offset: 16) +!6 = !DIBasicType(name: "unsigned short", size: 16, encoding: DW_ATE_unsigned) +!7 = !DIDerivedType(tag: DW_TAG_member, name: "w", scope: !0, file: !1, line: 6, baseType: !8, size: 32, offset: 32) +!8 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) +!9 = !DIDerivedType(tag: DW_TAG_member, name: "d", scope: !0, file: !1, line: 7, baseType: !10, size: 64, offset: 64) +!10 = !DIBasicType(name: "unsigned long", size: 64, encoding: DW_ATE_unsigned) +!11 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang version 18.0.0 ...", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!12 = !{i32 7, !"Dwarf Version", i32 5} +!13 = !{i32 2, !"Debug Info Version", i32 3} +!14 = !{i32 1, !"wchar_size", i32 4} +!15 = !{i32 7, !"frame-pointer", i32 2} +!16 = !{i32 7, !"debug-info-assignment-tracking", i1 true} +!17 = !{!"clang version 18.0.0 ..."} +!18 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 10, type: !19, scopeLine: 10, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !11, retainedNodes: !23) +!19 = !DISubroutineType(types: !20) +!20 = !{null, !21} +!21 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !22, size: 64) +!22 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !0) +!23 = !{!24} +!24 = !DILocalVariable(name: "p", arg: 1, scope: !18, file: !1, line: 10, type: !21) +!25 = !DILocation(line: 0, scope: !18) +!26 = !DILocation(line: 11, column: 8, scope: !18) +!27 = !{!28, !29, i64 0} +!28 = !{!"foo", !29, i64 0, !31, i64 2, !32, i64 4, !33, i64 8} +!29 = !{!"omnipotent char", !30, i64 0} +!30 = !{!"Simple C/C++ TBAA"} +!31 = !{!"short", !29, i64 0} +!32 = !{!"int", !29, i64 0} +!33 = !{!"long", !29, i64 0} +!34 = !DILocation(line: 12, column: 8, scope: !18) +!35 = !{!28, !31, i64 2} +!36 = !DILocation(line: 13, column: 8, scope: !18) +!37 = !{!28, !32, i64 4} +!38 = !DILocation(line: 14, column: 8, scope: !18) +!39 = !{!28, !33, i64 8} +!40 = !DILocation(line: 15, column: 1, scope: !18) \ No newline at end of file diff --git a/llvm/test/CodeGen/SBF/store-imm.ll b/llvm/test/CodeGen/SBF/store-imm.ll new file mode 100644 index 00000000000000..37b0bb1a32edb4 --- /dev/null +++ b/llvm/test/CodeGen/SBF/store-imm.ll @@ -0,0 +1,75 @@ +; RUN: llc < %s -march=sbf -mattr=+store-imm -show-mc-encoding | FileCheck %s +; RUN: llc < %s -march=sbf -mattr=+store-imm,+alu32 -show-mc-encoding | FileCheck %s + +define void @byte(ptr %p0) { +; CHECK-LABEL: byte: +; CHECK: # %bb.0: +; CHECK-NEXT: stb [r1 + 0], 1 # encoding: [0x72,0x01,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK-NEXT: stb [r1 + 1], 255 # encoding: [0x72,0x01,0x01,0x00,0xff,0x00,0x00,0x00] + %p1 = getelementptr i8, ptr %p0, i32 1 + store volatile i8 1, ptr %p0, align 1 + store volatile i8 -1, ptr %p1, align 1 + unreachable +} +define void @half(ptr, ptr %p0) { +; CHECK-LABEL: half: +; CHECK: # %bb.0: +; CHECK-NEXT: sth [r2 + 0], 1 # encoding: [0x6a,0x02,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK-NEXT: sth [r2 + 2], 65535 # encoding: [0x6a,0x02,0x02,0x00,0xff,0xff,0x00,0x00] + %p1 = getelementptr i8, ptr %p0, i32 2 + store volatile i16 1, ptr %p0, align 2 + store volatile i16 -1, ptr %p1, align 2 + unreachable +} +define void @word(ptr, ptr, ptr %p0) { +; CHECK-LABEL: word: +; CHECK: # %bb.0: +; CHECK-NEXT: stw [r3 + 0], 1 # encoding: [0x62,0x03,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK-NEXT: stw [r3 + 4], -1 # encoding: [0x62,0x03,0x04,0x00,0xff,0xff,0xff,0xff] +; CHECK-NEXT: stw [r3 + 8], -2000000000 # encoding: [0x62,0x03,0x08,0x00,0x00,0x6c,0xca,0x88] +; CHECK-NEXT: stw [r3 + 12], -1 # encoding: [0x62,0x03,0x0c,0x00,0xff,0xff,0xff,0xff] +; CHECK-NEXT: stw [r3 + 12], 0 # encoding: [0x62,0x03,0x0c,0x00,0x00,0x00,0x00,0x00] + %p1 = getelementptr i8, ptr %p0, i32 4 + %p2 = getelementptr i8, ptr %p0, i32 8 + %p3 = getelementptr i8, ptr %p0, i32 12 + store volatile i32 1, ptr %p0, align 4 + store volatile i32 -1, ptr %p1, align 4 + store volatile i32 -2000000000, ptr %p2, align 4 + store volatile i32 4294967295, ptr %p3, align 4 + store volatile i32 4294967296, ptr %p3, align 4 + unreachable +} +define void @dword(ptr, ptr, ptr, ptr %p0) { +; CHECK-LABEL: dword: +; CHECK: # %bb.0: +; CHECK-NEXT: stdw [r4 + 0], 1 # encoding: [0x7a,0x04,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK-NEXT: stdw [r4 + 8], -1 # encoding: [0x7a,0x04,0x08,0x00,0xff,0xff,0xff,0xff] +; CHECK-NEXT: stdw [r4 + 16], 2000000000 # encoding: [0x7a,0x04,0x10,0x00,0x00,0x94,0x35,0x77] +; CHECK-NEXT: stdw [r4 + 16], -2000000000 # encoding: [0x7a,0x04,0x10,0x00,0x00,0x6c,0xca,0x88] +; CHECK-NEXT: lddw r1, 4294967295 # encoding: [0x18,0x01,0x00,0x00,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK-NEXT: stxdw [r4 + 24], r1 # encoding: [0x7b,0x14,0x18,0x00,0x00,0x00,0x00,0x00] + %p1 = getelementptr i8, ptr %p0, i32 8 + %p2 = getelementptr i8, ptr %p0, i32 16 + %p3 = getelementptr i8, ptr %p0, i32 24 + store volatile i64 1, ptr %p0, align 8 + store volatile i64 -1, ptr %p1, align 8 + store volatile i64 2000000000, ptr %p2, align 8 + store volatile i64 -2000000000, ptr %p2, align 8 + store volatile i64 4294967295, ptr %p3, align 8 + unreachable +} + +define void @unaligned(ptr %p0) { +; SBF allows misaligned memory accesses +; CHECK-LABEL: unaligned: +; CHECK: # %bb.0: +; CHECK-NEXT: sth [r1 + 0], 65534 # encoding: [0x6a,0x01,0x00,0x00,0xfe,0xff,0x00,0x00] +; CHECK-NEXT: stw [r1 + 8], -2 # encoding: [0x62,0x01,0x08,0x00,0xfe,0xff,0xff,0xff] +; CHECK-NEXT: stdw [r1 + 16], -2 # encoding: [0x7a,0x01,0x10,0x00,0xfe,0xff,0xff,0xff] + %p1 = getelementptr i8, ptr %p0, i32 8 + %p2 = getelementptr i8, ptr %p0, i32 16 + store volatile i16 -2, ptr %p0, align 1 + store volatile i32 -2, ptr %p1, align 2 + store volatile i64 -2, ptr %p2, align 4 + unreachable +} \ No newline at end of file diff --git a/llvm/test/MC/Disassembler/SBF/sbf-ldst.txt b/llvm/test/MC/Disassembler/SBF/sbf-ldst.txt index 00541d55cc4047..de26039d03f694 100644 --- a/llvm/test/MC/Disassembler/SBF/sbf-ldst.txt +++ b/llvm/test/MC/Disassembler/SBF/sbf-ldst.txt @@ -130,3 +130,12 @@ 0xc3,0x58,0xf0,0xff,0xf1,0x00,0x00,0x00 + +# CHECK-NEW: stb [r10 - 8], 2 +# CHECK-NEW: sth [r9 + 4], -20 +# CHECK-NEW: stw [r4 - 16], 34 +# CHECK-NEW: stdw [r1 + 24], 65534 +0x72,0x0a,0xf8,0xff,0x02,0x00,0x00,0x00 +0x6a,0x09,0x04,0x00,0xec,0xff,0xff,0xff +0x62,0x04,0xf0,0xff,0x22,0x00,0x00,0x00 +0x7a,0x01,0x18,0x00,0xfe,0xff,0x00,0x00 \ No newline at end of file diff --git a/llvm/test/MC/SBF/sbf-ldst.s b/llvm/test/MC/SBF/sbf-ldst.s index 001b9f8d518389..0f05cfc62b96d8 100644 --- a/llvm/test/MC/SBF/sbf-ldst.s +++ b/llvm/test/MC/SBF/sbf-ldst.s @@ -183,3 +183,17 @@ stxxchgw [r8 - 16], w0 stxcmpxchgdw [r8 - 16], r5 stxcmpxchgw [r8 - 16], w5 + + +# CHECK-OBJ-NEW: stb [r10 - 0x8], 0x2 +# CHECK-OBJ-NEW: sth [r9 + 0x4], -0x14 +# CHECK-OBJ-NEW: stw [r4 - 0x10], 0x22 +# CHECK-OBJ-NEW: stdw [r1 + 0x18], 0xfffe +# CHECK-ASM-NEW: encoding: [0x72,0x0a,0xf8,0xff,0x02,0x00,0x00,0x00] +# CHECK-ASM-NEW: encoding: [0x6a,0x09,0x04,0x00,0xec,0xff,0xff,0xff] +# CHECK-ASM-NEW: encoding: [0x62,0x04,0xf0,0xff,0x22,0x00,0x00,0x00] +# CHECK-ASM-NEW: encoding: [0x7a,0x01,0x18,0x00,0xfe,0xff,0x00,0x00] +stb [r10 - 8], 2 +sth [r9 + 4], -20 +stw [r4 - 16], 34 +stdw [r1 + 24], 65534 \ No newline at end of file