diff --git a/.github/workflows/ci_cd.yml b/.github/workflows/ci_cd.yml index 0e6a2fa8..6e9d1b45 100644 --- a/.github/workflows/ci_cd.yml +++ b/.github/workflows/ci_cd.yml @@ -30,7 +30,7 @@ jobs: name: Documentation style runs-on: ubuntu-latest steps: - - uses: ansys/actions/doc-style@v4 + - uses: ansys/actions/doc-style@v7 with: token: ${{ secrets.GITHUB_TOKEN }} @@ -42,68 +42,16 @@ jobs: name: Build documentation runs-on: [self-hosted, Windows, pyaedt-examples] steps: - - uses: actions/checkout@v4 - - - name: Set up Python ${{ env.MAIN_PYTHON_VERSION }} - uses: actions/setup-python@v4 - with: - python-version: ${{ env.MAIN_PYTHON_VERSION }} - - - name: Create virtual environment - run: | - python -m venv .venv - .venv\Scripts\Activate.ps1 - python -m pip install pip -U - python -m pip install wheel setuptools -U - python -c "import sys; print(sys.executable)" - - - name: Install project and documentation dependencies - run: | - .venv\Scripts\Activate.ps1 - pip install --no-cache-dir -r requirements/requirements_doc.txt - - # Use environment variable speed up build for PDF pages - - name: Create HTML documentation - env: - SPHINXBUILD_HTML_AND_PDF_WORKFLOW: "1" - run: | - .venv\Scripts\Activate.ps1 - . .\doc\make.bat html --color - - # NOTE: Ugly HTML checking but redirecting errors with our docs either leads - # to errors in powershell or workflows getting stuck in Github CICD. - - name: Check HTML doc creation - run : | - if (Test-Path "doc\_build\html\index.html" ) { - Write-Output "File index.html found, HTML build successful." - } else { - Write-Error "Sphinx build failed, check if there is no cell execution error." - exit 1 - } - - - name: Upload HTML documentation artifact - uses: actions/upload-artifact@v4 - with: - name: documentation-html - path: doc/_build/html - retention-days: 7 - - # Use environment variable to remove the doctree after the build of PDF pages - # Keeping doctree could cause an issue, see https://github.com/ansys/pyaedt/pull/3844/files - - name: Create PDF documentation + - name: Build documentation + uses: ansys/actions/doc-build@fix/inconsistent-behavior env: SPHINXBUILD_HTML_AND_PDF_WORKFLOW: "1" - run: | - .venv\Scripts\Activate.ps1 - . .\doc\make.bat pdf - - - name: Upload PDF documentation artifact - uses: actions/upload-artifact@v4 with: - name: documentation-pdf - path: doc/_build/latex - retention-days: 7 - + python-version: ${{ env.MAIN_PYTHON_VERSION }} + check-links: false + use-python-cache: false + skip-install: true + deploy-doc: name: Upload documentation if: contains(github.ref, 'refs/heads/main') @@ -111,8 +59,7 @@ jobs: needs: [doc-build] steps: - name: Deploy the documentation - uses: ansys/actions/doc-deploy-dev@v5 + uses: ansys/actions/doc-deploy-dev@v7 with: cname: ${{ env.DOCUMENTATION_CNAME }} token: ${{ secrets.GITHUB_TOKEN }} - doc-artifact-name: 'documentation-html' diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 7c7a4016..c2661e34 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -32,7 +32,7 @@ repos: rev: v2.2.6 hooks: - id: codespell - args: ["--ignore-words", "doc/styles/Vocab/ANSYS/accept.txt", "-w"] + args: ["--ignore-words=doc/styles/config/vocabularies/ANSYS/accept.txt", "-w"] exclude: > (?x)^( .*\.css diff --git a/doc/.vale.ini b/doc/.vale.ini index 344c6c4a..7cf74d77 100644 --- a/doc/.vale.ini +++ b/doc/.vale.ini @@ -27,6 +27,9 @@ Vocab = ANSYS # Apply the following styles BasedOnStyles = Vale, Google +# Remove vale terms +Vale.Terms = NO + # Removing Google-specific rule - Not applicable under some circumstances Google.WordList = NO Google.Colons = NO \ No newline at end of file diff --git a/doc/source/Resources/3dlayout.png b/doc/source/Resources/3dlayout.png deleted file mode 100644 index 565d941c..00000000 Binary files a/doc/source/Resources/3dlayout.png and /dev/null differ diff --git a/doc/source/Resources/3dlayout_1.png b/doc/source/Resources/3dlayout_1.png deleted file mode 100644 index d616a530..00000000 Binary files a/doc/source/Resources/3dlayout_1.png and /dev/null differ diff --git a/doc/source/Resources/5gantenna.png b/doc/source/Resources/5gantenna.png deleted file mode 100644 index a8fe70a5..00000000 Binary files a/doc/source/Resources/5gantenna.png and /dev/null differ diff --git a/doc/source/Resources/BlankDiagram3DLayout.png b/doc/source/Resources/BlankDiagram3DLayout.png deleted file mode 100644 index b57d3b06..00000000 Binary files a/doc/source/Resources/BlankDiagram3DLayout.png and /dev/null differ diff --git a/doc/source/Resources/BlankDiagram3DModeler.png b/doc/source/Resources/BlankDiagram3DModeler.png deleted file mode 100644 index 058c9d38..00000000 Binary files a/doc/source/Resources/BlankDiagram3DModeler.png and /dev/null differ diff --git a/doc/source/Resources/BlankDiagramCircuit.png b/doc/source/Resources/BlankDiagramCircuit.png deleted file mode 100644 index d2c08c87..00000000 Binary files a/doc/source/Resources/BlankDiagramCircuit.png and /dev/null differ diff --git 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mode 100644 index f4009cbc..00000000 Binary files a/doc/source/Resources/aedt_3.png and /dev/null differ diff --git a/doc/source/Resources/aedt_box.png b/doc/source/Resources/aedt_box.png deleted file mode 100644 index 26a179e9..00000000 Binary files a/doc/source/Resources/aedt_box.png and /dev/null differ diff --git a/doc/source/Resources/aedt_first_page.png b/doc/source/Resources/aedt_first_page.png deleted file mode 100644 index 00bbdade..00000000 Binary files a/doc/source/Resources/aedt_first_page.png and /dev/null differ diff --git a/doc/source/Resources/aedt_setup.png b/doc/source/Resources/aedt_setup.png deleted file mode 100644 index 7a6e210d..00000000 Binary files a/doc/source/Resources/aedt_setup.png and /dev/null differ diff --git a/doc/source/Resources/aedt_variables.png b/doc/source/Resources/aedt_variables.png deleted file mode 100644 index caa87868..00000000 Binary files a/doc/source/Resources/aedt_variables.png and /dev/null differ diff --git a/doc/source/Resources/array.png b/doc/source/Resources/array.png deleted file mode 100644 index 591463c2..00000000 Binary files a/doc/source/Resources/array.png and /dev/null differ diff --git a/doc/source/Resources/array_example.json b/doc/source/Resources/array_example.json deleted file mode 100644 index a64330c5..00000000 --- a/doc/source/Resources/array_example.json +++ /dev/null @@ -1,44 +0,0 @@ -{ - "primarylattice": "Circ_Patch_5GHz_232_1_Primary1", - "secondarylattice": "Circ_Patch_5GHz_232_1_Primary2", - "useairobjects": true, - "rowdimension": 3, - "columndimension": 3, - "visible": false, - "showcellnumber": false, - "paddingcells": 0, - "referencecsid": 1, - "cells": { - "(1,1)": { - "name": "Circ_Patch_5GHz_232_1", - "color": "(255,0,20)", - "active": true, - "postprocessing": true, - "rotation": 0.0 - }, - "(1,2)": { - "name": "Circ_Patch_5GHz_232_1" - }, - "(1,3)": { - "name": "Circ_Patch_5GHz_232_1" - }, - "(2,1)": { - "name": "Circ_Patch_5GHz_232_1" - }, - "(2,2)": { - "name": "Circ_Patch_5GHz_232_1" - }, - "(2,3)": { - "name": "Circ_Patch_5GHz_232_1" - }, - "(3,1)": { - "name": "Circ_Patch_5GHz_232_1" - }, - "(3,2)": { - "name": "Circ_Patch_5GHz_232_1" - }, - "(3,3)": { - "name": "Circ_Patch_5GHz_232_1" - } - } -} \ No newline at end of file diff --git a/doc/source/Resources/busbar.png b/doc/source/Resources/busbar.png deleted file mode 100644 index 891820e3..00000000 Binary files a/doc/source/Resources/busbar.png and /dev/null differ diff --git a/doc/source/Resources/cable_example.json b/doc/source/Resources/cable_example.json deleted file mode 100644 index ffe0db20..00000000 --- a/doc/source/Resources/cable_example.json +++ /dev/null @@ -1,170 +0,0 @@ -{ - "Add_Cable": "True", - "Update_Cable": "False", - "Remove_Cable": "False", - "Add_CablesToBundle": "False", - "Add_Source": "False", - "Update_Source": "False", - "Remove_Source": "False", - "Add_CableHarness": "False", - "Cable_prop": { - "CableType":"bundle", - "IsJacketTypeInsulation": "True", - "IsJacketTypeBraidShield": "False", - "IsJacketTypeNoJacket": "False", - "UpdatedName": "", - "CablesToRemove": "" - }, - "CablesToBundle_prop": { - "CablesToAdd": "", - "BundleCable": "", - "NumberOfCableToAdd": 1 - }, - "Source_prop": { - "AddClockSource": "False", - "UpdateClockSource": "False", - "AddPwlSource": "False", - "AddPwlSourceFromFile": "", - "UpdatePwlSource": "False", - "UpdatedSourceName": "update_pwl_source", - "SourcesToRemove": "" - }, - "CableHarness_prop": { - "Name": "cable_harness_test", - "Bundle": "bundle1", - "TwistAngleAlongRoute": "20deg", - "Polyline": "polyline1", - "AutoOrient": "False", - "XAxis": "Undefined", - "XAxisOrigin": ["0mm", "0mm", "0mm"], - "XAxisEnd": ["0mm", "0mm", "0mm"], - "ReverseYAxisDirection": "True", - "CableTerminationsToInclude": [ - { - "CableName": "stwire1", - "Assignment": "Reference Conductor", - "AssignmentType": "Impedance", - "Impedance": "40ohm", - "Source": { - "Type": "Single Value", - "Signal": "10V", - "ImpedanceValue": "23ohm" - } - }, - { - "CableName": "stwire2", - "Assignment": "Input Terminations", - "AssignmentType": "Source", - "Impedance": "40ohm", - "Source": { - "Type": "Single Value", - "Signal": "4V", - "ImpedanceValue": "23ohm" - } - }, - { - "CableName": "stwire3", - "Assignment": "Output Terminations", - "AssignmentType": "Source", - "Impedance": "40ohm", - "Source": { - "Type": "Transient", - "Signal": "clock1", - "ImpedanceValue": "23ohm" - } - } - ] - }, - "CableManager": { - "TDSources": { - "ClockSourceDef": { - "ClockSignalParams": { - "Period": "40us", - "LowPulseVal": "0.1V", - "HighPulseVal": "2V", - "Risetime": "5us", - "Falltime": "10us", - "PulseWidth": "23us" - }, - "TDSourceAttribs": { - "Name": "clock_test" - } - }, - "PWLSourceDef": { - "PWLSignalParams": { - "SignalValues": [ - "0V", - "0.5V", - "0V", - "3V", - "4V", - "0V" - ], - "TimeValues": [ - "0ns", - "1ns", - "2ns", - "3ns", - "4ns", - "5ns" - ] - }, - "TDSourceAttribs": { - "Name": "pwl4" - } - } - }, - "Definitions": { - "CableBundle":{ - "BundleParams": { - "AutoPack": "True", - "InsulationJacketParams": { - "InsThickness": "3.66mm", - "JacketMaterial": "pec", - "InnerDiameter": "2.88mm" - }, - "BraidShieldJacketParams": { - "JacketMaterial": "pec", - "InnerDiameter": "6mm", - "NumCarriers": "36", - "NumWiresInCarrier": "52", - "WireDiameter": "0.242424mm", - "WeaveAngle": "33deg" - }, - "VirtualJacketParams": { - "JacketMaterial": "copper", - "InnerDiameter": "2.5mm" - } - }, - "BundleAttribs": { - "Name": "Bundle_Cable_Insulation" - } - }, - "StWireCable": { - "StWireParams": { - "WireStandard": "ISO", - "WireGauge": "2.5", - "CondDiameter": "10mm", - "CondMaterial": "pec", - "InsThickness": "0.9mm", - "InsMaterial": "copper", - "InsType": "Thin Wall" - }, - "StWireAttribs": { - "Name": "stwire_Test_ISO_70" - } - }, - "TwistedPairCable": { - "TwistedPairParams": { - "StraightWireCableID": 1003, - "IsLayLengthSpecified": "False", - "LayLength": "34mm", - "TurnsPerMeter": "99" - }, - "TwistedPairAttribs": { - "Name": "twisted_pair_test_1003_1" - } - } - } - } -} \ No newline at end of file diff --git a/doc/source/Resources/choke_example.json b/doc/source/Resources/choke_example.json deleted file mode 100644 index f841c236..00000000 --- a/doc/source/Resources/choke_example.json +++ /dev/null @@ -1,70 +0,0 @@ -{ - "Number of Windings": - { - "1": true, - "2": false, - "3": false, - "4": false - }, - "Layer": - { - "Simple": true, - "Double": false, - "Triple": false - }, - "Layer Type": - { - "Separate": true, - "Linked": false - }, - "Similar Layer": - { - "Similar": true, - "Different": false - }, - "Mode": - { - "Differential": true, - "Common": false - }, - "Wire Section": - { - "None": false, - "Hexagon": false, - "Octagon": false, - "Circle": true - }, - "Core": - { - "Name": "Core", - "Material": "ferrite", - "Inner Radius": 20, - "Outer Radius": 50, - "Height": 20, - "Chamfer": 0.8 - }, - "Outer Winding": - { - "Name": "Winding", - "Material": "copper", - "Inner Radius": 19.45, - "Outer Radius": 50.55, - "Height": 21.1, - "Wire Diameter": 1, - "Turns": 111, - "Coil Pit(deg)": 1.621, - "Occupation(%)": 99.96166666666666 - }, - "Mid Winding": - { - "Turns": 111, - "Coil Pit(deg)": 1.621, - "Occupation(%)": 99.96166666666666 - }, - "Inner Winding": - { - "Turns": 111, - "Coil Pit(deg)": 1.621, - "Occupation(%)": 99.96166666666666 - } -} \ No newline at end of file diff --git a/doc/source/Resources/coordinate_system.png b/doc/source/Resources/coordinate_system.png deleted file mode 100644 index 4f303114..00000000 Binary files a/doc/source/Resources/coordinate_system.png and /dev/null differ diff --git a/doc/source/Resources/edb.png b/doc/source/Resources/edb.png deleted file mode 100644 index b257222a..00000000 Binary files a/doc/source/Resources/edb.png and /dev/null differ diff --git a/doc/source/Resources/edb2.png b/doc/source/Resources/edb2.png deleted file mode 100644 index edef3694..00000000 Binary files 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b/doc/source/Resources/field_plot.png deleted file mode 100644 index df5d89c2..00000000 Binary files a/doc/source/Resources/field_plot.png and /dev/null differ diff --git a/doc/source/Resources/hfss3dlayout_project_example.json b/doc/source/Resources/hfss3dlayout_project_example.json deleted file mode 100644 index f6a5168a..00000000 --- a/doc/source/Resources/hfss3dlayout_project_example.json +++ /dev/null @@ -1,281 +0,0 @@ -{ - "general": { - "pyaedt_version": "0.8.dev0", - "model_units": "mm", - "design_name": "HFSS 3D Layout Design_JLN", - "date": "09/01/2024 09:36:47", - "object_mapping": {}, - "output_variables": {}, - "variables": {}, - "postprocessing_variables": {} - }, - "setups": { - "My_HFSS_Setup_2": { - "Properties": { - "Enable": "true" - }, - "CustomSetup": false, - "AutoSetup": false, - "SliderType": "Balanced", - "SolveSetupType": "HFSS", - "PercentRefinementPerPass": 30, - "MinNumberOfPasses": 1, - "MinNumberOfConvergedPasses": 1, - "UseDefaultLambda": true, - "UseMaxRefinement": false, - "MaxRefinement": 1000000, - "SaveAdaptiveCurrents": false, - "SaveLastAdaptiveRadFields": false, - "UseConvergenceMatrix": false, - "AllEntries": false, - "AllDiagEntries": false, - "AllOffDiagEntries": false, - "MagMinThreshold": 0.01, - "ProdMajVerID": -1, - "ProjDesignSetup": "", - "ProdMinVerID": -1, - "Refine": false, - "Frequency": "10GHz", - "LambdaRefine": true, - "MeshSizeFactor": 1.5, - "QualityRefine": true, - "MinAngle": "15deg", - "UniformityRefine": false, - "MaxRatio": 2, - "Smooth": false, - "SmoothingPasses": 5, - "UseEdgeMesh": false, - "UseEdgeMeshAbsLength": false, - "EdgeMeshRatio": 0.1, - "EdgeMeshAbsLength": "1000mm", - "LayerProjectThickness": "0meter", - "UseDefeature": true, - "UseDefeatureAbsLength": false, - "DefeatureRatio": 1e-06, - "DefeatureAbsLength": "0mm", - "InfArrayDimX": 0, - "InfArrayDimY": 0, - "InfArrayOrigX": 0, - "InfArrayOrigY": 0, - "InfArraySkew": 0, - "ViaNumSides": 6, - "ViaMaterial": "copper", - "Style25DVia": "Mesh", - "Replace3DTriangles": true, - "LayerSnapTol": "1e-05", - "ViaDensity": 0, - "HfssMesh": true, - "Q3dPostProc": false, - "UnitFactor": 1000, - "Verbose": false, - "NumberOfProcessors": 0, - "SmallVoidArea": -2e-09, - "RemoveFloatingGeometry": false, - "HealingOption": 1, - "InclBBoxOption": 1, - "ModelType": 0, - "ICModeAuto": 1, - "ICModeLength": "50nm", - "AuxBlock": {}, - "DoAdaptive": true, - "Color": [ - "R:=", - 0, - "G:=", - 0, - "B:=", - 0 - ], - "AdvancedSettings": { - "AccuracyLevel": 2, - "GapPortCalibration": true, - "ReferenceLengthRatio": 0.25, - "RefineAreaRatio": 4, - "DRCOn": false, - "FastSolverOn": false, - "StartFastSolverAt": 3000, - "LoopTreeOn": true, - "SingularElementsOn": false, - "UseStaticPortSolver": false, - "UseThinMetalPortSolver": false, - "ComputeBothEvenAndOddCPWModes": false, - "ZeroMetalLayerThickness": 0, - "ThinDielectric": 0, - "UseShellElements": false, - "SVDHighCompression": false, - "NumProcessors": 1, - "SolverType": "Direct Solver", - "UseHfssIterativeSolver": false, - "UseHfssMUMPSSolver": true, - "RelativeResidual": 1e-06, - "EnhancedLowFreqAccuracy": false, - "OrderBasis": -1, - "MaxDeltaZo": 2, - "UseRadBoundaryOnPorts": false, - "SetTrianglesForWavePort": false, - "MinTrianglesForWavePort": 100, - "MaxTrianglesForWavePort": 500, - "numprocessorsdistrib": 1, - "CausalMaterials": true, - "enabledsoforopti": true, - "usehfsssolvelicense": false, - "ExportAfterSolve": false, - "ExportDir": "", - "CircuitSparamDefinition": false, - "CircuitIntegrationType": "FFT", - "DesignType": "generic", - "MeshingMethod": "Phi", - "EnableDesignIntersectionCheck": true, - "UseAlternativeMeshMethodsAsFallBack": true, - "ModeOption": "General mode", - "BroadbandFreqOption": "AutoMaxFreq", - "BroadbandMaxNumFreq": 5, - "SaveADP": true, - "UseAdvancedDCExtrap": false, - "PhiMesherDeltaZRatio": 100000 - }, - "CurveApproximation": { - "ArcAngle": "30deg", - "StartAzimuth": "0deg", - "UseError": false, - "Error": "0meter", - "MaxPoints": 8, - "UnionPolys": true, - "Replace3DTriangles": true - }, - "Q3D_DCSettings": { - "SolveResOnly": true, - "Cond": { - "MaxPass": 10, - "MinPass": 1, - "MinConvPass": 1, - "PerError": 1, - "PerRefine": 30 - }, - "Mult": { - "MaxPass": 1, - "MinPass": 1, - "MinConvPass": 1, - "PerError": 1, - "PerRefine": 30 - }, - "Solution Order": "Normal" - }, - "AdaptiveSettings": { - "DoAdaptive": true, - "SaveFields": false, - "SaveRadFieldsOnly": false, - "MaxRefinePerPass": 30, - "MinPasses": 1, - "MinConvergedPasses": 1, - "AdaptType": "kSingle", - "Basic": true, - "SingleFrequencyDataList": { - "AdaptiveFrequencyData": { - "AdaptiveFrequency": "5GHz", - "MaxDelta": "0.02", - "MaxPasses": 10, - "Expressions": [] - } - }, - "BroadbandFrequencyDataList": { - "AdaptiveFrequencyData": [ - { - "AdaptiveFrequency": "5GHz", - "MaxDelta": "0.02", - "MaxPasses": 10, - "Expressions": [] - }, - { - "AdaptiveFrequency": "10GHz", - "MaxDelta": "0.02", - "MaxPasses": 10, - "Expressions": [] - } - ] - }, - "MultiFrequencyDataList": { - "AdaptiveFrequencyData": [ - { - "AdaptiveFrequency": "2.5GHz", - "MaxDelta": "0.02", - "MaxPasses": 10, - "Expressions": [] - }, - { - "AdaptiveFrequency": "5GHz", - "MaxDelta": "0.02", - "MaxPasses": 10, - "Expressions": [] - }, - { - "AdaptiveFrequency": "10GHz", - "MaxDelta": "0.02", - "MaxPasses": 10, - "Expressions": [] - } - ] - } - }, - "Data": {}, - "MeshOps": {}, - "SetupType": 29 - } - }, - "materials": { - "copper": { - "CoordinateSystemType": "Cartesian", - "BulkOrSurfaceType": 1, - "PhysicsTypes": { - "set": [ - "Electromagnetic", - "Thermal", - "Structural" - ] - }, - "AttachedData": { - "MatAppearanceData": { - "property_data": "appearance_data", - "Red": 242, - "Green": 140, - "Blue": 102 - } - }, - "permeability": "0.999991", - "conductivity": "58000000", - "thermal_conductivity": "400", - "mass_density": "8933", - "specific_heat": "385", - "youngs_modulus": "120000000000", - "poissons_ratio": "0.38", - "thermal_expansion_coefficient": "1.77e-05" - }, - "FR4_epoxy": { - "CoordinateSystemType": "Cartesian", - "BulkOrSurfaceType": 1, - "PhysicsTypes": { - "set": [ - "Electromagnetic", - "Thermal", - "Structural" - ] - }, - "AttachedData": { - "MatAppearanceData": { - "property_data": "appearance_data", - "Red": 27, - "Green": 110, - "Blue": 76 - } - }, - "permittivity": "4.4", - "dielectric_loss_tangent": "0.02", - "thermal_conductivity": "0.294", - "mass_density": "1900", - "specific_heat": "1150", - "youngs_modulus": "11000000000", - "poissons_ratio": "0.28", - "thermal_expansion_coefficient": "1.5e-05" - } - } -} \ No newline at end of file diff --git a/doc/source/Resources/hfss_report_example.json b/doc/source/Resources/hfss_report_example.json deleted file mode 100644 index 694517b5..00000000 --- a/doc/source/Resources/hfss_report_example.json +++ /dev/null @@ -1,218 +0,0 @@ -{ - "Help": "Report Template", - "report_category": "Standard", - "report_type": "Rectangular Plot", - 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a/doc/source/Resources/material_example.json +++ /dev/null @@ -1,23 +0,0 @@ -{ - "materials": { - "new_material": { - "CoordinateSystemType": "Cartesian", - "BulkOrSurfaceType": 1, - "PhysicsTypes": { - "set": [ - "Electromagnetic" - ] - }, - "AttachedData": { - "MatAppearanceData": { - "property_data": "appearance_data", - "Red": 230, - "Green": 230, - "Blue": 230, - "Transparency": 0.949999988079071 - } - }, - "permittivity": "1" - } - } -} \ No newline at end of file diff --git a/doc/source/Resources/maxwell_losses.png b/doc/source/Resources/maxwell_losses.png deleted file mode 100644 index be3b9670..00000000 Binary files a/doc/source/Resources/maxwell_losses.png and /dev/null differ diff --git a/doc/source/Resources/mechanical.png b/doc/source/Resources/mechanical.png deleted file mode 100644 index 8bef2dc2..00000000 Binary files a/doc/source/Resources/mechanical.png and /dev/null differ diff --git a/doc/source/Resources/merge_utility.png b/doc/source/Resources/merge_utility.png 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files a/doc/source/Resources/variables_advanced.png and /dev/null differ diff --git a/doc/source/Resources/viawizard.png b/doc/source/Resources/viawizard.png deleted file mode 100644 index 5baa89a8..00000000 Binary files a/doc/source/Resources/viawizard.png and /dev/null differ diff --git a/doc/source/conf.py b/doc/source/conf.py index f155218b..6be1f030 100644 --- a/doc/source/conf.py +++ b/doc/source/conf.py @@ -126,15 +126,15 @@ def copy_script_examples(app: Sphinx, config: Config): Configuration file abstraction. """ destination_dir = Path(app.outdir, "examples").resolve() - logger.info(f"Copying script examples into out directory {destination_dir}.") - - EXAMPLES = EXAMPLES_DIRECTORY.glob("**/*.py") - for example in EXAMPLES: - example_path = str(example).split("examples" + os.sep)[-1] - shutil.copyfile(example, str(destination_dir / example_path)) - - logger.info(f"Copy performed.") + if os.path.exists(destination_dir): + logger.info(f"Copying script examples into out directory {destination_dir}.") + + EXAMPLES = EXAMPLES_DIRECTORY.glob("**/*.py") + for example in EXAMPLES: + example_path = str(example).split("examples" + os.sep)[-1] + shutil.copyfile(example, str(destination_dir / example_path)) + logger.info(f"Copy performed.") def adjust_image_path(app: Sphinx, docname, source): """Adjust the HTML label used to insert images in the examples. diff --git a/doc/styles/.gitignore b/doc/styles/.gitignore index 080f12aa..62d72f2c 100644 --- a/doc/styles/.gitignore +++ b/doc/styles/.gitignore @@ -1,4 +1,4 @@ * -!Vocab -!Vocab/** +!config +!config/** !.gitignore \ No newline at end of file diff --git a/doc/styles/Vocab/ANSYS/accept.txt b/doc/styles/config/vocabularies/ANSYS/accept.txt similarity index 100% rename from doc/styles/Vocab/ANSYS/accept.txt rename to doc/styles/config/vocabularies/ANSYS/accept.txt diff --git a/doc/styles/Vocab/ANSYS/reject.txt b/doc/styles/config/vocabularies/ANSYS/reject.txt similarity index 100% rename from doc/styles/Vocab/ANSYS/reject.txt rename to doc/styles/config/vocabularies/ANSYS/reject.txt