From 4eb9da6bc00b4c5fa201295d896f052dc1acc271 Mon Sep 17 00:00:00 2001
From: AMAN MOGAL <81488924+amanmogal@users.noreply.github.com>
Date: Fri, 29 Nov 2024 12:14:12 +0530
Subject: [PATCH] Issue #27715

---
 .vscode/settings.json                         |  2 ++
 .../plugin/aarch64/debug_capabilities.hpp     | 25 +++++++++++++++++++
 .../aarch64/jit_uni_eltwise_generic.cpp       |  5 ++++
 3 files changed, 32 insertions(+)
 create mode 100644 .vscode/settings.json
 create mode 100644 src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp

diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 00000000000000..e02aef276ea851
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,2 @@
+{
+}
\ No newline at end of file
diff --git a/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp b/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp
new file mode 100644
index 00000000000000..7f16aef752e0b6
--- /dev/null
+++ b/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp
@@ -0,0 +1,25 @@
+#ifndef DEBUG_CAPABILITIES_HPP
+#define DEBUG_CAPABILITIES_HPP
+
+#include <iostream>
+#include <cstdint>
+#include <arm_neon.h> // For SIMD support
+
+class RegPrints {
+public:
+    // Print general-purpose registers
+    static void print_gpr(const uint64_t& reg_value, const char* reg_name) {
+        std::cout << "Register " << reg_name << ": " << std::hex << reg_value << std::endl;
+    }
+
+    // Print vector registers (SIMD)
+    static void print_simd(const float32x4_t& reg_value, const char* reg_name) {
+        float values[4];
+        vst1q_f32(values, reg_value); // Store SIMD register into an array
+        std::cout << "SIMD Register " << reg_name << ": ["
+                  << values[0] << ", " << values[1] << ", "
+                  << values[2] << ", " << values[3] << "]" << std::endl;
+    }
+};
+
+#endif // DEBUG_CAPABILITIES_HPP
diff --git a/src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp b/src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp
index 7ac3b603353541..90d72a7edd4633 100644
--- a/src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp
+++ b/src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp
@@ -50,13 +50,18 @@ void jit_uni_eltwise_generic<isa>::generate() {
     if (jep.use_runtime_ptrs) {
         for (size_t i = 0; i < jep.inputs_number; i++) {
             ldr(start_to_offsets, ptr(reg_const_params, static_cast<int32_t>(offsetof(node::jit_eltwise_call_args_ptrs, src_offsets) + i * sizeof(size_t))));
+            RegPrints::print_gpr(start_to_offsets.getIdx(), "start_to_offsets");
             ldr(get_src_reg(i), ptr(reg_const_params, static_cast<int32_t>(offsetof(node::jit_eltwise_call_args_ptrs, src_ptr[0]) + i * sizeof(size_t))));
+            RegPrints::print_gpr(get_src_reg(i).getIdx(), "src_ptr");
             XReg offset_reg = get_aux_gpr(0); // X_TMP_0;
             XReg index_reg = get_aux_gpr(1);  // X_TMP_1;
             for (int j = 0; j < offset_count; j++) {
                 ldr(offset_reg, ptr(start_to_offsets, static_cast<int32_t>(j * sizeof(size_t))));
+                RegPrints::print_gpr(offset_reg.getIdx(), "offset_reg");
                 ldr(index_reg, ptr(reg_indexes, static_cast<int32_t>(j * sizeof(size_t))));
+                RegPrints::print_gpr(index_reg.getIdx(), "index_reg");
                 madd(get_src_reg(i), offset_reg, index_reg, get_src_reg(i));
+                RegPrints::print_gpr(get_src_reg(i).getIdx(), "effective_address");
             }
         }